drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/debugfs.h>
  34 #include <linux/highmem.h>
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/errno.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #if defined(CONFIG_X86)
  42 #include <asm/pat.h>
  43 #endif
  44 #include <linux/sched.h>
  45 #include <linux/sched/mm.h>
  46 #include <linux/sched/task.h>
  47 #include <linux/delay.h>
  48 #include <rdma/ib_user_verbs.h>
  49 #include <rdma/ib_addr.h>
  50 #include <rdma/ib_cache.h>
  51 #include <linux/mlx5/port.h>
  52 #include <linux/mlx5/vport.h>
  53 #include <linux/mlx5/fs.h>
  54 #include <linux/list.h>
  55 #include <rdma/ib_smi.h>
  56 #include <rdma/ib_umem.h>
  57 #include <linux/in.h>
  58 #include <linux/etherdevice.h>
  59 #include "mlx5_ib.h"
  60 #include "cmd.h"
  61
  62 #define DRIVER_NAME "mlx5_ib"
  63 #define DRIVER_VERSION "5.0-0"
  64
  65 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  66 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  67 MODULE_LICENSE("Dual BSD/GPL");
  68
  69 static char mlx5_version[] =
  70         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  71         DRIVER_VERSION "\n";
  72
  73 enum {
  74         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  75 };
  76
  77 static enum rdma_link_layer
  78 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  79 {
  80         switch (port_type_cap) {
  81         case MLX5_CAP_PORT_TYPE_IB:
  82                 return IB_LINK_LAYER_INFINIBAND;
  83         case MLX5_CAP_PORT_TYPE_ETH:
  84                 return IB_LINK_LAYER_ETHERNET;
  85         default:
  86                 return IB_LINK_LAYER_UNSPECIFIED;
  87         }
  88 }
  89
  90 static enum rdma_link_layer
  91 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  92 {
  93         struct mlx5_ib_dev *dev = to_mdev(device);
  94         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  95
  96         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  97 }
  98
  99 static int get_port_state(struct ib_device *ibdev,
 100                           u8 port_num,
 101                           enum ib_port_state *state)
 102 {
 103         struct ib_port_attr attr;
 104         int ret;
 105
 106         memset(&attr, 0, sizeof(attr));
 107         ret = mlx5_ib_query_port(ibdev, port_num, &attr);
 108         if (!ret)
 109                 *state = attr.state;
 110         return ret;
 111 }
 112
 113 static int mlx5_netdev_event(struct notifier_block *this,
 114                              unsigned long event, void *ptr)
 115 {
 116         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 117         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 118                                                  roce.nb);
 119
 120         switch (event) {
 121         case NETDEV_REGISTER:
 122         case NETDEV_UNREGISTER:
 123                 write_lock(&ibdev->roce.netdev_lock);
 124                 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 125                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
 126                                              NULL : ndev;
 127                 write_unlock(&ibdev->roce.netdev_lock);
 128                 break;
 129
 130         case NETDEV_CHANGE:
 131         case NETDEV_UP:
 132         case NETDEV_DOWN: {
 133                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 134                 struct net_device *upper = NULL;
 135
 136                 if (lag_ndev) {
 137                         upper = netdev_master_upper_dev_get(lag_ndev);
 138                         dev_put(lag_ndev);
 139                 }
 140
 141                 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
 142                     && ibdev->ib_active) {
 143                         struct ib_event ibev = { };
 144                         enum ib_port_state port_state;
 145
 146                         if (get_port_state(&ibdev->ib_dev, 1, &port_state))
 147                                 return NOTIFY_DONE;
 148
 149                         if (ibdev->roce.last_port_state == port_state)
 150                                 return NOTIFY_DONE;
 151
 152                         ibdev->roce.last_port_state = port_state;
 153                         ibev.device = &ibdev->ib_dev;
 154                         if (port_state == IB_PORT_DOWN)
 155                                 ibev.event = IB_EVENT_PORT_ERR;
 156                         else if (port_state == IB_PORT_ACTIVE)
 157                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 158                         else
 159                                 return NOTIFY_DONE;
 160
 161                         ibev.element.port_num = 1;
 162                         ib_dispatch_event(&ibev);
 163                 }
 164                 break;
 165         }
 166
 167         default:
 168                 break;
 169         }
 170
 171         return NOTIFY_DONE;
 172 }
 173
 174 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 175                                              u8 port_num)
 176 {
 177         struct mlx5_ib_dev *ibdev = to_mdev(device);
 178         struct net_device *ndev;
 179
 180         ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 181         if (ndev)
 182                 return ndev;
 183
 184         /* Ensure ndev does not disappear before we invoke dev_hold()
 185          */
 186         read_lock(&ibdev->roce.netdev_lock);
 187         ndev = ibdev->roce.netdev;
 188         if (ndev)
 189                 dev_hold(ndev);
 190         read_unlock(&ibdev->roce.netdev_lock);
 191
 192         return ndev;
 193 }
 194
 195 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 196                                     u8 *active_width)
 197 {
 198         switch (eth_proto_oper) {
 199         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 200         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 201         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 202         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 203                 *active_width = IB_WIDTH_1X;
 204                 *active_speed = IB_SPEED_SDR;
 205                 break;
 206         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 207         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 208         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 209         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 210         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 211         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 212         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 213                 *active_width = IB_WIDTH_1X;
 214                 *active_speed = IB_SPEED_QDR;
 215                 break;
 216         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 217         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 218         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 219                 *active_width = IB_WIDTH_1X;
 220                 *active_speed = IB_SPEED_EDR;
 221                 break;
 222         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 223         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 224         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 225         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 226                 *active_width = IB_WIDTH_4X;
 227                 *active_speed = IB_SPEED_QDR;
 228                 break;
 229         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 230         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 231         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 232                 *active_width = IB_WIDTH_1X;
 233                 *active_speed = IB_SPEED_HDR;
 234                 break;
 235         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 236                 *active_width = IB_WIDTH_4X;
 237                 *active_speed = IB_SPEED_FDR;
 238                 break;
 239         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 240         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 241         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 242         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 243                 *active_width = IB_WIDTH_4X;
 244                 *active_speed = IB_SPEED_EDR;
 245                 break;
 246         default:
 247                 return -EINVAL;
 248         }
 249
 250         return 0;
 251 }
 252
 253 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 254                                 struct ib_port_attr *props)
 255 {
 256         struct mlx5_ib_dev *dev = to_mdev(device);
 257         struct mlx5_core_dev *mdev = dev->mdev;
 258         struct net_device *ndev, *upper;
 259         enum ib_mtu ndev_ib_mtu;
 260         u16 qkey_viol_cntr;
 261         u32 eth_prot_oper;
 262         int err;
 263
 264         /* Possible bad flows are checked before filling out props so in case
 265          * of an error it will still be zeroed out.
 266          */
 267         err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
 268         if (err)
 269                 return err;
 270
 271         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 272                                  &props->active_width);
 273
 274         props->port_cap_flags  |= IB_PORT_CM_SUP;
 275         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 276
 277         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 278                                                 roce_address_table_size);
 279         props->max_mtu          = IB_MTU_4096;
 280         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 281         props->pkey_tbl_len     = 1;
 282         props->state            = IB_PORT_DOWN;
 283         props->phys_state       = 3;
 284
 285         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 286         props->qkey_viol_cntr = qkey_viol_cntr;
 287
 288         ndev = mlx5_ib_get_netdev(device, port_num);
 289         if (!ndev)
 290                 return 0;
 291
 292         if (mlx5_lag_is_active(dev->mdev)) {
 293                 rcu_read_lock();
 294                 upper = netdev_master_upper_dev_get_rcu(ndev);
 295                 if (upper) {
 296                         dev_put(ndev);
 297                         ndev = upper;
 298                         dev_hold(ndev);
 299                 }
 300                 rcu_read_unlock();
 301         }
 302
 303         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 304                 props->state      = IB_PORT_ACTIVE;
 305                 props->phys_state = 5;
 306         }
 307
 308         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 309
 310         dev_put(ndev);
 311
 312         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 313         return 0;
 314 }
 315
 316 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 317                          unsigned int index, const union ib_gid *gid,
 318                          const struct ib_gid_attr *attr)
 319 {
 320         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 321         u8 roce_version = 0;
 322         u8 roce_l3_type = 0;
 323         bool vlan = false;
 324         u8 mac[ETH_ALEN];
 325         u16 vlan_id = 0;
 326
 327         if (gid) {
 328                 gid_type = attr->gid_type;
 329                 ether_addr_copy(mac, attr->ndev->dev_addr);
 330
 331                 if (is_vlan_dev(attr->ndev)) {
 332                         vlan = true;
 333                         vlan_id = vlan_dev_vlan_id(attr->ndev);
 334                 }
 335         }
 336
 337         switch (gid_type) {
 338         case IB_GID_TYPE_IB:
 339                 roce_version = MLX5_ROCE_VERSION_1;
 340                 break;
 341         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 342                 roce_version = MLX5_ROCE_VERSION_2;
 343                 if (ipv6_addr_v4mapped((void *)gid))
 344                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 345                 else
 346                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 347                 break;
 348
 349         default:
 350                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 351         }
 352
 353         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 354                                       roce_l3_type, gid->raw, mac, vlan,
 355                                       vlan_id);
 356 }
 357
 358 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 359                            unsigned int index, const union ib_gid *gid,
 360                            const struct ib_gid_attr *attr,
 361                            __always_unused void **context)
 362 {
 363         return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
 364 }
 365
 366 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 367                            unsigned int index, __always_unused void **context)
 368 {
 369         return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
 370 }
 371
 372 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 373                                int index)
 374 {
 375         struct ib_gid_attr attr;
 376         union ib_gid gid;
 377
 378         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 379                 return 0;
 380
 381         if (!attr.ndev)
 382                 return 0;
 383
 384         dev_put(attr.ndev);
 385
 386         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 387                 return 0;
 388
 389         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 390 }
 391
 392 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
 393                            int index, enum ib_gid_type *gid_type)
 394 {
 395         struct ib_gid_attr attr;
 396         union ib_gid gid;
 397         int ret;
 398
 399         ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
 400         if (ret)
 401                 return ret;
 402
 403         if (!attr.ndev)
 404                 return -ENODEV;
 405
 406         dev_put(attr.ndev);
 407
 408         *gid_type = attr.gid_type;
 409
 410         return 0;
 411 }
 412
 413 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 414 {
 415         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 416                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 417         return 0;
 418 }
 419
 420 enum {
 421         MLX5_VPORT_ACCESS_METHOD_MAD,
 422         MLX5_VPORT_ACCESS_METHOD_HCA,
 423         MLX5_VPORT_ACCESS_METHOD_NIC,
 424 };
 425
 426 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 427 {
 428         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 429                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 430
 431         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 432             IB_LINK_LAYER_ETHERNET)
 433                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 434
 435         return MLX5_VPORT_ACCESS_METHOD_HCA;
 436 }
 437
 438 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 439                             struct ib_device_attr *props)
 440 {
 441         u8 tmp;
 442         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 443         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 444         u8 atomic_req_8B_endianness_mode =
 445                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 446
 447         /* Check if HW supports 8 bytes standard atomic operations and capable
 448          * of host endianness respond
 449          */
 450         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 451         if (((atomic_operations & tmp) == tmp) &&
 452             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 453             (atomic_req_8B_endianness_mode)) {
 454                 props->atomic_cap = IB_ATOMIC_HCA;
 455         } else {
 456                 props->atomic_cap = IB_ATOMIC_NONE;
 457         }
 458 }
 459
 460 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 461                                         __be64 *sys_image_guid)
 462 {
 463         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 464         struct mlx5_core_dev *mdev = dev->mdev;
 465         u64 tmp;
 466         int err;
 467
 468         switch (mlx5_get_vport_access_method(ibdev)) {
 469         case MLX5_VPORT_ACCESS_METHOD_MAD:
 470                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 471                                                             sys_image_guid);
 472
 473         case MLX5_VPORT_ACCESS_METHOD_HCA:
 474                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 475                 break;
 476
 477         case MLX5_VPORT_ACCESS_METHOD_NIC:
 478                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 479                 break;
 480
 481         default:
 482                 return -EINVAL;
 483         }
 484
 485         if (!err)
 486                 *sys_image_guid = cpu_to_be64(tmp);
 487
 488         return err;
 489
 490 }
 491
 492 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 493                                 u16 *max_pkeys)
 494 {
 495         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 496         struct mlx5_core_dev *mdev = dev->mdev;
 497
 498         switch (mlx5_get_vport_access_method(ibdev)) {
 499         case MLX5_VPORT_ACCESS_METHOD_MAD:
 500                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 501
 502         case MLX5_VPORT_ACCESS_METHOD_HCA:
 503         case MLX5_VPORT_ACCESS_METHOD_NIC:
 504                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 505                                                 pkey_table_size));
 506                 return 0;
 507
 508         default:
 509                 return -EINVAL;
 510         }
 511 }
 512
 513 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 514                                 u32 *vendor_id)
 515 {
 516         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 517
 518         switch (mlx5_get_vport_access_method(ibdev)) {
 519         case MLX5_VPORT_ACCESS_METHOD_MAD:
 520                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 521
 522         case MLX5_VPORT_ACCESS_METHOD_HCA:
 523         case MLX5_VPORT_ACCESS_METHOD_NIC:
 524                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 525
 526         default:
 527                 return -EINVAL;
 528         }
 529 }
 530
 531 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 532                                 __be64 *node_guid)
 533 {
 534         u64 tmp;
 535         int err;
 536
 537         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 538         case MLX5_VPORT_ACCESS_METHOD_MAD:
 539                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 540
 541         case MLX5_VPORT_ACCESS_METHOD_HCA:
 542                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 543                 break;
 544
 545         case MLX5_VPORT_ACCESS_METHOD_NIC:
 546                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 547                 break;
 548
 549         default:
 550                 return -EINVAL;
 551         }
 552
 553         if (!err)
 554                 *node_guid = cpu_to_be64(tmp);
 555
 556         return err;
 557 }
 558
 559 struct mlx5_reg_node_desc {
 560         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 561 };
 562
 563 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 564 {
 565         struct mlx5_reg_node_desc in;
 566
 567         if (mlx5_use_mad_ifc(dev))
 568                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 569
 570         memset(&in, 0, sizeof(in));
 571
 572         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 573                                     sizeof(struct mlx5_reg_node_desc),
 574                                     MLX5_REG_NODE_DESC, 0, 0);
 575 }
 576
 577 static int mlx5_ib_query_device(struct ib_device *ibdev,
 578                                 struct ib_device_attr *props,
 579                                 struct ib_udata *uhw)
 580 {
 581         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 582         struct mlx5_core_dev *mdev = dev->mdev;
 583         int err = -ENOMEM;
 584         int max_sq_desc;
 585         int max_rq_sg;
 586         int max_sq_sg;
 587         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 588         struct mlx5_ib_query_device_resp resp = {};
 589         size_t resp_len;
 590         u64 max_tso;
 591
 592         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 593         if (uhw->outlen && uhw->outlen < resp_len)
 594                 return -EINVAL;
 595         else
 596                 resp.response_length = resp_len;
 597
 598         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 599                 return -EINVAL;
 600
 601         memset(props, 0, sizeof(*props));
 602         err = mlx5_query_system_image_guid(ibdev,
 603                                            &props->sys_image_guid);
 604         if (err)
 605                 return err;
 606
 607         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 608         if (err)
 609                 return err;
 610
 611         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 612         if (err)
 613                 return err;
 614
 615         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 616                 (fw_rev_min(dev->mdev) << 16) |
 617                 fw_rev_sub(dev->mdev);
 618         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 619                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 620                 IB_DEVICE_SYS_IMAGE_GUID                |
 621                 IB_DEVICE_RC_RNR_NAK_GEN;
 622
 623         if (MLX5_CAP_GEN(mdev, pkv))
 624                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 625         if (MLX5_CAP_GEN(mdev, qkv))
 626                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 627         if (MLX5_CAP_GEN(mdev, apm))
 628                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 629         if (MLX5_CAP_GEN(mdev, xrc))
 630                 props->device_cap_flags |= IB_DEVICE_XRC;
 631         if (MLX5_CAP_GEN(mdev, imaicl)) {
 632                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 633                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 634                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 635                 /* We support 'Gappy' memory registration too */
 636                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 637         }
 638         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 639         if (MLX5_CAP_GEN(mdev, sho)) {
 640                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 641                 /* At this stage no support for signature handover */
 642                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 643                                       IB_PROT_T10DIF_TYPE_2 |
 644                                       IB_PROT_T10DIF_TYPE_3;
 645                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 646                                        IB_GUARD_T10DIF_CSUM;
 647         }
 648         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 649                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 650
 651         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
 652                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 653                         /* Legacy bit to support old userspace libraries */
 654                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 655                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 656                 }
 657
 658                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 659                         props->raw_packet_caps |=
 660                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 661
 662                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 663                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 664                         if (max_tso) {
 665                                 resp.tso_caps.max_tso = 1 << max_tso;
 666                                 resp.tso_caps.supported_qpts |=
 667                                         1 << IB_QPT_RAW_PACKET;
 668                                 resp.response_length += sizeof(resp.tso_caps);
 669                         }
 670                 }
 671
 672                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 673                         resp.rss_caps.rx_hash_function =
 674                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 675                         resp.rss_caps.rx_hash_fields_mask =
 676                                                 MLX5_RX_HASH_SRC_IPV4 |
 677                                                 MLX5_RX_HASH_DST_IPV4 |
 678                                                 MLX5_RX_HASH_SRC_IPV6 |
 679                                                 MLX5_RX_HASH_DST_IPV6 |
 680                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 681                                                 MLX5_RX_HASH_DST_PORT_TCP |
 682                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 683                                                 MLX5_RX_HASH_DST_PORT_UDP |
 684                                                 MLX5_RX_HASH_INNER;
 685                         resp.response_length += sizeof(resp.rss_caps);
 686                 }
 687         } else {
 688                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 689                         resp.response_length += sizeof(resp.tso_caps);
 690                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 691                         resp.response_length += sizeof(resp.rss_caps);
 692         }
 693
 694         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 695                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 696                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 697         }
 698
 699         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 700             MLX5_CAP_GEN(dev->mdev, general_notification_event))
 701                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 702
 703         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 704             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 705                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 706
 707         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 708             MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
 709                 /* Legacy bit to support old userspace libraries */
 710                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 711                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 712         }
 713
 714         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 715                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 716
 717         if (MLX5_CAP_GEN(mdev, end_pad))
 718                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 719
 720         props->vendor_part_id      = mdev->pdev->device;
 721         props->hw_ver              = mdev->pdev->revision;
 722
 723         props->max_mr_size         = ~0ull;
 724         props->page_size_cap       = ~(min_page_size - 1);
 725         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 726         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 727         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 728                      sizeof(struct mlx5_wqe_data_seg);
 729         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 730         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 731                      sizeof(struct mlx5_wqe_raddr_seg)) /
 732                 sizeof(struct mlx5_wqe_data_seg);
 733         props->max_sge = min(max_rq_sg, max_sq_sg);
 734         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 735         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 736         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 737         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 738         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 739         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 740         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 741         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 742         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 743         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 744         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 745         props->max_srq_sge         = max_rq_sg - 1;
 746         props->max_fast_reg_page_list_len =
 747                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 748         get_atomic_caps(dev, props);
 749         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 750         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 751         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 752         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 753                                            props->max_mcast_grp;
 754         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 755         props->max_ah = INT_MAX;
 756         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 757         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 758
 759 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 760         if (MLX5_CAP_GEN(mdev, pg))
 761                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 762         props->odp_caps = dev->odp_caps;
 763 #endif
 764
 765         if (MLX5_CAP_GEN(mdev, cd))
 766                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 767
 768         if (!mlx5_core_is_pf(mdev))
 769                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 770
 771         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 772             IB_LINK_LAYER_ETHERNET) {
 773                 props->rss_caps.max_rwq_indirection_tables =
 774                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 775                 props->rss_caps.max_rwq_indirection_table_size =
 776                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 777                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 778                 props->max_wq_type_rq =
 779                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 780         }
 781
 782         if (MLX5_CAP_GEN(mdev, tag_matching)) {
 783                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
 784                 props->tm_caps.max_num_tags =
 785                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
 786                 props->tm_caps.flags = IB_TM_CAP_RC;
 787                 props->tm_caps.max_ops =
 788                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 789                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
 790         }
 791
 792         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
 793                 props->cq_caps.max_cq_moderation_count =
 794                                                 MLX5_MAX_CQ_COUNT;
 795                 props->cq_caps.max_cq_moderation_period =
 796                                                 MLX5_MAX_CQ_PERIOD;
 797         }
 798
 799         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 800                 resp.cqe_comp_caps.max_num =
 801                         MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
 802                         MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
 803                 resp.cqe_comp_caps.supported_format =
 804                         MLX5_IB_CQE_RES_FORMAT_HASH |
 805                         MLX5_IB_CQE_RES_FORMAT_CSUM;
 806                 resp.response_length += sizeof(resp.cqe_comp_caps);
 807         }
 808
 809         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
 810                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
 811                     MLX5_CAP_GEN(mdev, qos)) {
 812                         resp.packet_pacing_caps.qp_rate_limit_max =
 813                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
 814                         resp.packet_pacing_caps.qp_rate_limit_min =
 815                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
 816                         resp.packet_pacing_caps.supported_qpts |=
 817                                 1 << IB_QPT_RAW_PACKET;
 818                 }
 819                 resp.response_length += sizeof(resp.packet_pacing_caps);
 820         }
 821
 822         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
 823                         uhw->outlen)) {
 824                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
 825                         resp.mlx5_ib_support_multi_pkt_send_wqes =
 826                                 MLX5_IB_ALLOW_MPW;
 827
 828                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
 829                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
 830                                 MLX5_IB_SUPPORT_EMPW;
 831
 832                 resp.response_length +=
 833                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
 834         }
 835
 836         if (field_avail(typeof(resp), flags, uhw->outlen)) {
 837                 resp.response_length += sizeof(resp.flags);
 838
 839                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
 840                         resp.flags |=
 841                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
 842
 843                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
 844                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
 845         }
 846
 847         if (field_avail(typeof(resp), sw_parsing_caps,
 848                         uhw->outlen)) {
 849                 resp.response_length += sizeof(resp.sw_parsing_caps);
 850                 if (MLX5_CAP_ETH(mdev, swp)) {
 851                         resp.sw_parsing_caps.sw_parsing_offloads |=
 852                                 MLX5_IB_SW_PARSING;
 853
 854                         if (MLX5_CAP_ETH(mdev, swp_csum))
 855                                 resp.sw_parsing_caps.sw_parsing_offloads |=
 856                                         MLX5_IB_SW_PARSING_CSUM;
 857
 858                         if (MLX5_CAP_ETH(mdev, swp_lso))
 859                                 resp.sw_parsing_caps.sw_parsing_offloads |=
 860                                         MLX5_IB_SW_PARSING_LSO;
 861
 862                         if (resp.sw_parsing_caps.sw_parsing_offloads)
 863                                 resp.sw_parsing_caps.supported_qpts =
 864                                         BIT(IB_QPT_RAW_PACKET);
 865                 }
 866         }
 867
 868         if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen)) {
 869                 resp.response_length += sizeof(resp.striding_rq_caps);
 870                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
 871                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
 872                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
 873                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
 874                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
 875                         resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
 876                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
 877                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
 878                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
 879                         resp.striding_rq_caps.supported_qpts =
 880                                 BIT(IB_QPT_RAW_PACKET);
 881                 }
 882         }
 883
 884         if (field_avail(typeof(resp), tunnel_offloads_caps,
 885                         uhw->outlen)) {
 886                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
 887                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
 888                         resp.tunnel_offloads_caps |=
 889                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
 890                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
 891                         resp.tunnel_offloads_caps |=
 892                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
 893                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
 894                         resp.tunnel_offloads_caps |=
 895                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
 896         }
 897
 898         if (uhw->outlen) {
 899                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
 900
 901                 if (err)
 902                         return err;
 903         }
 904
 905         return 0;
 906 }
 907
 908 enum mlx5_ib_width {
 909         MLX5_IB_WIDTH_1X        = 1 << 0,
 910         MLX5_IB_WIDTH_2X        = 1 << 1,
 911         MLX5_IB_WIDTH_4X        = 1 << 2,
 912         MLX5_IB_WIDTH_8X        = 1 << 3,
 913         MLX5_IB_WIDTH_12X       = 1 << 4
 914 };
 915
 916 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 917                                   u8 *ib_width)
 918 {
 919         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 920         int err = 0;
 921
 922         if (active_width & MLX5_IB_WIDTH_1X) {
 923                 *ib_width = IB_WIDTH_1X;
 924         } else if (active_width & MLX5_IB_WIDTH_2X) {
 925                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 926                             (int)active_width);
 927                 err = -EINVAL;
 928         } else if (active_width & MLX5_IB_WIDTH_4X) {
 929                 *ib_width = IB_WIDTH_4X;
 930         } else if (active_width & MLX5_IB_WIDTH_8X) {
 931                 *ib_width = IB_WIDTH_8X;
 932         } else if (active_width & MLX5_IB_WIDTH_12X) {
 933                 *ib_width = IB_WIDTH_12X;
 934         } else {
 935                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 936                             (int)active_width);
 937                 err = -EINVAL;
 938         }
 939
 940         return err;
 941 }
 942
 943 static int mlx5_mtu_to_ib_mtu(int mtu)
 944 {
 945         switch (mtu) {
 946         case 256: return 1;
 947         case 512: return 2;
 948         case 1024: return 3;
 949         case 2048: return 4;
 950         case 4096: return 5;
 951         default:
 952                 pr_warn("invalid mtu\n");
 953                 return -1;
 954         }
 955 }
 956
 957 enum ib_max_vl_num {
 958         __IB_MAX_VL_0           = 1,
 959         __IB_MAX_VL_0_1         = 2,
 960         __IB_MAX_VL_0_3         = 3,
 961         __IB_MAX_VL_0_7         = 4,
 962         __IB_MAX_VL_0_14        = 5,
 963 };
 964
 965 enum mlx5_vl_hw_cap {
 966         MLX5_VL_HW_0    = 1,
 967         MLX5_VL_HW_0_1  = 2,
 968         MLX5_VL_HW_0_2  = 3,
 969         MLX5_VL_HW_0_3  = 4,
 970         MLX5_VL_HW_0_4  = 5,
 971         MLX5_VL_HW_0_5  = 6,
 972         MLX5_VL_HW_0_6  = 7,
 973         MLX5_VL_HW_0_7  = 8,
 974         MLX5_VL_HW_0_14 = 15
 975 };
 976
 977 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 978                                 u8 *max_vl_num)
 979 {
 980         switch (vl_hw_cap) {
 981         case MLX5_VL_HW_0:
 982                 *max_vl_num = __IB_MAX_VL_0;
 983                 break;
 984         case MLX5_VL_HW_0_1:
 985                 *max_vl_num = __IB_MAX_VL_0_1;
 986                 break;
 987         case MLX5_VL_HW_0_3:
 988                 *max_vl_num = __IB_MAX_VL_0_3;
 989                 break;
 990         case MLX5_VL_HW_0_7:
 991                 *max_vl_num = __IB_MAX_VL_0_7;
 992                 break;
 993         case MLX5_VL_HW_0_14:
 994                 *max_vl_num = __IB_MAX_VL_0_14;
 995                 break;
 996
 997         default:
 998                 return -EINVAL;
 999         }
1000
1001         return 0;
1002 }
1003
1004 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1005                                struct ib_port_attr *props)
1006 {
1007         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1008         struct mlx5_core_dev *mdev = dev->mdev;
1009         struct mlx5_hca_vport_context *rep;
1010         u16 max_mtu;
1011         u16 oper_mtu;
1012         int err;
1013         u8 ib_link_width_oper;
1014         u8 vl_hw_cap;
1015
1016         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1017         if (!rep) {
1018                 err = -ENOMEM;
1019                 goto out;
1020         }
1021
1022         /* props being zeroed by the caller, avoid zeroing it here */
1023
1024         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1025         if (err)
1026                 goto out;
1027
1028         props->lid              = rep->lid;
1029         props->lmc              = rep->lmc;
1030         props->sm_lid           = rep->sm_lid;
1031         props->sm_sl            = rep->sm_sl;
1032         props->state            = rep->vport_state;
1033         props->phys_state       = rep->port_physical_state;
1034         props->port_cap_flags   = rep->cap_mask1;
1035         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1036         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1037         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1038         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1039         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1040         props->subnet_timeout   = rep->subnet_timeout;
1041         props->init_type_reply  = rep->init_type_reply;
1042         props->grh_required     = rep->grh_required;
1043
1044         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1045         if (err)
1046                 goto out;
1047
1048         err = translate_active_width(ibdev, ib_link_width_oper,
1049                                      &props->active_width);
1050         if (err)
1051                 goto out;
1052         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1053         if (err)
1054                 goto out;
1055
1056         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1057
1058         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1059
1060         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1061
1062         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1063
1064         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1065         if (err)
1066                 goto out;
1067
1068         err = translate_max_vl_num(ibdev, vl_hw_cap,
1069                                    &props->max_vl_num);
1070 out:
1071         kfree(rep);
1072         return err;
1073 }
1074
1075 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1076                        struct ib_port_attr *props)
1077 {
1078         unsigned int count;
1079         int ret;
1080
1081         switch (mlx5_get_vport_access_method(ibdev)) {
1082         case MLX5_VPORT_ACCESS_METHOD_MAD:
1083                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1084                 break;
1085
1086         case MLX5_VPORT_ACCESS_METHOD_HCA:
1087                 ret = mlx5_query_hca_port(ibdev, port, props);
1088                 break;
1089
1090         case MLX5_VPORT_ACCESS_METHOD_NIC:
1091                 ret = mlx5_query_port_roce(ibdev, port, props);
1092                 break;
1093
1094         default:
1095                 ret = -EINVAL;
1096         }
1097
1098         if (!ret && props) {
1099                 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
1100                 props->gid_tbl_len -= count;
1101         }
1102         return ret;
1103 }
1104
1105 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1106                              union ib_gid *gid)
1107 {
1108         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1109         struct mlx5_core_dev *mdev = dev->mdev;
1110
1111         switch (mlx5_get_vport_access_method(ibdev)) {
1112         case MLX5_VPORT_ACCESS_METHOD_MAD:
1113                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1114
1115         case MLX5_VPORT_ACCESS_METHOD_HCA:
1116                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1117
1118         default:
1119                 return -EINVAL;
1120         }
1121
1122 }
1123
1124 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1125                               u16 *pkey)
1126 {
1127         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1128         struct mlx5_core_dev *mdev = dev->mdev;
1129
1130         switch (mlx5_get_vport_access_method(ibdev)) {
1131         case MLX5_VPORT_ACCESS_METHOD_MAD:
1132                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1133
1134         case MLX5_VPORT_ACCESS_METHOD_HCA:
1135         case MLX5_VPORT_ACCESS_METHOD_NIC:
1136                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
1137                                                  pkey);
1138         default:
1139                 return -EINVAL;
1140         }
1141 }
1142
1143 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1144                                  struct ib_device_modify *props)
1145 {
1146         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1147         struct mlx5_reg_node_desc in;
1148         struct mlx5_reg_node_desc out;
1149         int err;
1150
1151         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1152                 return -EOPNOTSUPP;
1153
1154         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1155                 return 0;
1156
1157         /*
1158          * If possible, pass node desc to FW, so it can generate
1159          * a 144 trap.  If cmd fails, just ignore.
1160          */
1161         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1162         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1163                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1164         if (err)
1165                 return err;
1166
1167         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1168
1169         return err;
1170 }
1171
1172 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1173                                 u32 value)
1174 {
1175         struct mlx5_hca_vport_context ctx = {};
1176         int err;
1177
1178         err = mlx5_query_hca_vport_context(dev->mdev, 0,
1179                                            port_num, 0, &ctx);
1180         if (err)
1181                 return err;
1182
1183         if (~ctx.cap_mask1_perm & mask) {
1184                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1185                              mask, ctx.cap_mask1_perm);
1186                 return -EINVAL;
1187         }
1188
1189         ctx.cap_mask1 = value;
1190         ctx.cap_mask1_perm = mask;
1191         err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1192                                                  port_num, 0, &ctx);
1193
1194         return err;
1195 }
1196
1197 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1198                                struct ib_port_modify *props)
1199 {
1200         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1201         struct ib_port_attr attr;
1202         u32 tmp;
1203         int err;
1204         u32 change_mask;
1205         u32 value;
1206         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1207                       IB_LINK_LAYER_INFINIBAND);
1208
1209         /* CM layer calls ib_modify_port() regardless of the link layer. For
1210          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1211          */
1212         if (!is_ib)
1213                 return 0;
1214
1215         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1216                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1217                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1218                 return set_port_caps_atomic(dev, port, change_mask, value);
1219         }
1220
1221         mutex_lock(&dev->cap_mask_mutex);
1222
1223         err = ib_query_port(ibdev, port, &attr);
1224         if (err)
1225                 goto out;
1226
1227         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1228                 ~props->clr_port_cap_mask;
1229
1230         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1231
1232 out:
1233         mutex_unlock(&dev->cap_mask_mutex);
1234         return err;
1235 }
1236
1237 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1238 {
1239         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1240                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1241 }
1242
1243 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1244 {
1245         /* Large page with non 4k uar support might limit the dynamic size */
1246         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1247                 return MLX5_MIN_DYN_BFREGS;
1248
1249         return MLX5_MAX_DYN_BFREGS;
1250 }
1251
1252 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1253                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1254                              struct mlx5_bfreg_info *bfregi)
1255 {
1256         int uars_per_sys_page;
1257         int bfregs_per_sys_page;
1258         int ref_bfregs = req->total_num_bfregs;
1259
1260         if (req->total_num_bfregs == 0)
1261                 return -EINVAL;
1262
1263         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1264         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1265
1266         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1267                 return -ENOMEM;
1268
1269         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1270         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1271         /* This holds the required static allocation asked by the user */
1272         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1273         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1274                 return -EINVAL;
1275
1276         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1277         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1278         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1279         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1280
1281         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1282                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1283                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1284                     req->total_num_bfregs, bfregi->total_num_bfregs,
1285                     bfregi->num_sys_pages);
1286
1287         return 0;
1288 }
1289
1290 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1291 {
1292         struct mlx5_bfreg_info *bfregi;
1293         int err;
1294         int i;
1295
1296         bfregi = &context->bfregi;
1297         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1298                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1299                 if (err)
1300                         goto error;
1301
1302                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1303         }
1304         return 0;
1305
1306 error:
1307         for (--i; i >= 0; i--)
1308                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1309                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1310
1311         return err;
1312 }
1313
1314 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1315 {
1316         struct mlx5_bfreg_info *bfregi;
1317         int err;
1318         int i;
1319
1320         bfregi = &context->bfregi;
1321         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1322                 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1323                 if (err) {
1324                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1325                         return err;
1326                 }
1327         }
1328         return 0;
1329 }
1330
1331 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1332 {
1333         int err;
1334
1335         err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1336         if (err)
1337                 return err;
1338
1339         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1340             !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1341                 return err;
1342
1343         mutex_lock(&dev->lb_mutex);
1344         dev->user_td++;
1345
1346         if (dev->user_td == 2)
1347                 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1348
1349         mutex_unlock(&dev->lb_mutex);
1350         return err;
1351 }
1352
1353 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1354 {
1355         mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1356
1357         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1358             !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1359                 return;
1360
1361         mutex_lock(&dev->lb_mutex);
1362         dev->user_td--;
1363
1364         if (dev->user_td < 2)
1365                 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1366
1367         mutex_unlock(&dev->lb_mutex);
1368 }
1369
1370 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1371                                                   struct ib_udata *udata)
1372 {
1373         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1374         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1375         struct mlx5_ib_alloc_ucontext_resp resp = {};
1376         struct mlx5_ib_ucontext *context;
1377         struct mlx5_bfreg_info *bfregi;
1378         int ver;
1379         int err;
1380         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1381                                      max_cqe_version);
1382         bool lib_uar_4k;
1383
1384         if (!dev->ib_active)
1385                 return ERR_PTR(-EAGAIN);
1386
1387         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1388                 ver = 0;
1389         else if (udata->inlen >= min_req_v2)
1390                 ver = 2;
1391         else
1392                 return ERR_PTR(-EINVAL);
1393
1394         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1395         if (err)
1396                 return ERR_PTR(err);
1397
1398         if (req.flags)
1399                 return ERR_PTR(-EINVAL);
1400
1401         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1402                 return ERR_PTR(-EOPNOTSUPP);
1403
1404         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1405                                     MLX5_NON_FP_BFREGS_PER_UAR);
1406         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1407                 return ERR_PTR(-EINVAL);
1408
1409         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1410         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1411                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1412         resp.cache_line_size = cache_line_size();
1413         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1414         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1415         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1416         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1417         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1418         resp.cqe_version = min_t(__u8,
1419                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1420                                  req.max_cqe_version);
1421         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1422                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1423         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1424                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1425         resp.response_length = min(offsetof(typeof(resp), response_length) +
1426                                    sizeof(resp.response_length), udata->outlen);
1427
1428         context = kzalloc(sizeof(*context), GFP_KERNEL);
1429         if (!context)
1430                 return ERR_PTR(-ENOMEM);
1431
1432         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1433         bfregi = &context->bfregi;
1434
1435         /* updates req->total_num_bfregs */
1436         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1437         if (err)
1438                 goto out_ctx;
1439
1440         mutex_init(&bfregi->lock);
1441         bfregi->lib_uar_4k = lib_uar_4k;
1442         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1443                                 GFP_KERNEL);
1444         if (!bfregi->count) {
1445                 err = -ENOMEM;
1446                 goto out_ctx;
1447         }
1448
1449         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1450                                     sizeof(*bfregi->sys_pages),
1451                                     GFP_KERNEL);
1452         if (!bfregi->sys_pages) {
1453                 err = -ENOMEM;
1454                 goto out_count;
1455         }
1456
1457         err = allocate_uars(dev, context);
1458         if (err)
1459                 goto out_sys_pages;
1460
1461 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1462         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1463 #endif
1464
1465         context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1466         if (!context->upd_xlt_page) {
1467                 err = -ENOMEM;
1468                 goto out_uars;
1469         }
1470         mutex_init(&context->upd_xlt_page_mutex);
1471
1472         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1473                 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1474                 if (err)
1475                         goto out_page;
1476         }
1477
1478         INIT_LIST_HEAD(&context->vma_private_list);
1479         mutex_init(&context->vma_private_list_mutex);
1480         INIT_LIST_HEAD(&context->db_page_list);
1481         mutex_init(&context->db_page_mutex);
1482
1483         resp.tot_bfregs = req.total_num_bfregs;
1484         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1485
1486         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1487                 resp.response_length += sizeof(resp.cqe_version);
1488
1489         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1490                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1491                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1492                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1493         }
1494
1495         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1496                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1497                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1498                         resp.eth_min_inline++;
1499                 }
1500                 resp.response_length += sizeof(resp.eth_min_inline);
1501         }
1502
1503         /*
1504          * We don't want to expose information from the PCI bar that is located
1505          * after 4096 bytes, so if the arch only supports larger pages, let's
1506          * pretend we don't support reading the HCA's core clock. This is also
1507          * forced by mmap function.
1508          */
1509         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1510                 if (PAGE_SIZE <= 4096) {
1511                         resp.comp_mask |=
1512                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1513                         resp.hca_core_clock_offset =
1514                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1515                 }
1516                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1517                                         sizeof(resp.reserved2);
1518         }
1519
1520         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1521                 resp.response_length += sizeof(resp.log_uar_size);
1522
1523         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1524                 resp.response_length += sizeof(resp.num_uars_per_page);
1525
1526         if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1527                 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1528                 resp.response_length += sizeof(resp.num_dyn_bfregs);
1529         }
1530
1531         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1532         if (err)
1533                 goto out_td;
1534
1535         bfregi->ver = ver;
1536         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1537         context->cqe_version = resp.cqe_version;
1538         context->lib_caps = req.lib_caps;
1539         print_lib_caps(dev, context->lib_caps);
1540
1541         return &context->ibucontext;
1542
1543 out_td:
1544         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1545                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1546
1547 out_page:
1548         free_page(context->upd_xlt_page);
1549
1550 out_uars:
1551         deallocate_uars(dev, context);
1552
1553 out_sys_pages:
1554         kfree(bfregi->sys_pages);
1555
1556 out_count:
1557         kfree(bfregi->count);
1558
1559 out_ctx:
1560         kfree(context);
1561
1562         return ERR_PTR(err);
1563 }
1564
1565 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1566 {
1567         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1568         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1569         struct mlx5_bfreg_info *bfregi;
1570
1571         bfregi = &context->bfregi;
1572         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1573                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1574
1575         free_page(context->upd_xlt_page);
1576         deallocate_uars(dev, context);
1577         kfree(bfregi->sys_pages);
1578         kfree(bfregi->count);
1579         kfree(context);
1580
1581         return 0;
1582 }
1583
1584 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1585                                  struct mlx5_bfreg_info *bfregi,
1586                                  int idx)
1587 {
1588         int fw_uars_per_page;
1589
1590         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1591
1592         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1593                         bfregi->sys_pages[idx] / fw_uars_per_page;
1594 }
1595
1596 static int get_command(unsigned long offset)
1597 {
1598         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1599 }
1600
1601 static int get_arg(unsigned long offset)
1602 {
1603         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1604 }
1605
1606 static int get_index(unsigned long offset)
1607 {
1608         return get_arg(offset);
1609 }
1610
1611 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1612 {
1613         /* vma_open is called when a new VMA is created on top of our VMA.  This
1614          * is done through either mremap flow or split_vma (usually due to
1615          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1616          * as this VMA is strongly hardware related.  Therefore we set the
1617          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1618          * calling us again and trying to do incorrect actions.  We assume that
1619          * the original VMA size is exactly a single page, and therefore all
1620          * "splitting" operation will not happen to it.
1621          */
1622         area->vm_ops = NULL;
1623 }
1624
1625 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1626 {
1627         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1628
1629         /* It's guaranteed that all VMAs opened on a FD are closed before the
1630          * file itself is closed, therefore no sync is needed with the regular
1631          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1632          * However need a sync with accessing the vma as part of
1633          * mlx5_ib_disassociate_ucontext.
1634          * The close operation is usually called under mm->mmap_sem except when
1635          * process is exiting.
1636          * The exiting case is handled explicitly as part of
1637          * mlx5_ib_disassociate_ucontext.
1638          */
1639         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1640
1641         /* setting the vma context pointer to null in the mlx5_ib driver's
1642          * private data, to protect a race condition in
1643          * mlx5_ib_disassociate_ucontext().
1644          */
1645         mlx5_ib_vma_priv_data->vma = NULL;
1646         mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1647         list_del(&mlx5_ib_vma_priv_data->list);
1648         mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1649         kfree(mlx5_ib_vma_priv_data);
1650 }
1651
1652 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1653         .open = mlx5_ib_vma_open,
1654         .close = mlx5_ib_vma_close
1655 };
1656
1657 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1658                                 struct mlx5_ib_ucontext *ctx)
1659 {
1660         struct mlx5_ib_vma_private_data *vma_prv;
1661         struct list_head *vma_head = &ctx->vma_private_list;
1662
1663         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1664         if (!vma_prv)
1665                 return -ENOMEM;
1666
1667         vma_prv->vma = vma;
1668         vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1669         vma->vm_private_data = vma_prv;
1670         vma->vm_ops =  &mlx5_ib_vm_ops;
1671
1672         mutex_lock(&ctx->vma_private_list_mutex);
1673         list_add(&vma_prv->list, vma_head);
1674         mutex_unlock(&ctx->vma_private_list_mutex);
1675
1676         return 0;
1677 }
1678
1679 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1680 {
1681         int ret;
1682         struct vm_area_struct *vma;
1683         struct mlx5_ib_vma_private_data *vma_private, *n;
1684         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1685         struct task_struct *owning_process  = NULL;
1686         struct mm_struct   *owning_mm       = NULL;
1687
1688         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1689         if (!owning_process)
1690                 return;
1691
1692         owning_mm = get_task_mm(owning_process);
1693         if (!owning_mm) {
1694                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1695                 while (1) {
1696                         put_task_struct(owning_process);
1697                         usleep_range(1000, 2000);
1698                         owning_process = get_pid_task(ibcontext->tgid,
1699                                                       PIDTYPE_PID);
1700                         if (!owning_process ||
1701                             owning_process->state == TASK_DEAD) {
1702                                 pr_info("disassociate ucontext done, task was terminated\n");
1703                                 /* in case task was dead need to release the
1704                                  * task struct.
1705                                  */
1706                                 if (owning_process)
1707                                         put_task_struct(owning_process);
1708                                 return;
1709                         }
1710                 }
1711         }
1712
1713         /* need to protect from a race on closing the vma as part of
1714          * mlx5_ib_vma_close.
1715          */
1716         down_write(&owning_mm->mmap_sem);
1717         mutex_lock(&context->vma_private_list_mutex);
1718         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1719                                  list) {
1720                 vma = vma_private->vma;
1721                 ret = zap_vma_ptes(vma, vma->vm_start,
1722                                    PAGE_SIZE);
1723                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1724                 /* context going to be destroyed, should
1725                  * not access ops any more.
1726                  */
1727                 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1728                 vma->vm_ops = NULL;
1729                 list_del(&vma_private->list);
1730                 kfree(vma_private);
1731         }
1732         mutex_unlock(&context->vma_private_list_mutex);
1733         up_write(&owning_mm->mmap_sem);
1734         mmput(owning_mm);
1735         put_task_struct(owning_process);
1736 }
1737
1738 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1739 {
1740         switch (cmd) {
1741         case MLX5_IB_MMAP_WC_PAGE:
1742                 return "WC";
1743         case MLX5_IB_MMAP_REGULAR_PAGE:
1744                 return "best effort WC";
1745         case MLX5_IB_MMAP_NC_PAGE:
1746                 return "NC";
1747         default:
1748                 return NULL;
1749         }
1750 }
1751
1752 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1753                     struct vm_area_struct *vma,
1754                     struct mlx5_ib_ucontext *context)
1755 {
1756         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1757         int err;
1758         unsigned long idx;
1759         phys_addr_t pfn, pa;
1760         pgprot_t prot;
1761         int uars_per_page;
1762
1763         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1764                 return -EINVAL;
1765
1766         uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1767         idx = get_index(vma->vm_pgoff);
1768         if (idx % uars_per_page ||
1769             idx * uars_per_page >= bfregi->num_sys_pages) {
1770                 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1771                 return -EINVAL;
1772         }
1773
1774         switch (cmd) {
1775         case MLX5_IB_MMAP_WC_PAGE:
1776 /* Some architectures don't support WC memory */
1777 #if defined(CONFIG_X86)
1778                 if (!pat_enabled())
1779                         return -EPERM;
1780 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1781                         return -EPERM;
1782 #endif
1783         /* fall through */
1784         case MLX5_IB_MMAP_REGULAR_PAGE:
1785                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1786                 prot = pgprot_writecombine(vma->vm_page_prot);
1787                 break;
1788         case MLX5_IB_MMAP_NC_PAGE:
1789                 prot = pgprot_noncached(vma->vm_page_prot);
1790                 break;
1791         default:
1792                 return -EINVAL;
1793         }
1794
1795         pfn = uar_index2pfn(dev, bfregi, idx);
1796         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1797
1798         vma->vm_page_prot = prot;
1799         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1800                                  PAGE_SIZE, vma->vm_page_prot);
1801         if (err) {
1802                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1803                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1804                 return -EAGAIN;
1805         }
1806
1807         pa = pfn << PAGE_SHIFT;
1808         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1809                     vma->vm_start, &pa);
1810
1811         return mlx5_ib_set_vma_data(vma, context);
1812 }
1813
1814 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1815 {
1816         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1817         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1818         unsigned long command;
1819         phys_addr_t pfn;
1820
1821         command = get_command(vma->vm_pgoff);
1822         switch (command) {
1823         case MLX5_IB_MMAP_WC_PAGE:
1824         case MLX5_IB_MMAP_NC_PAGE:
1825         case MLX5_IB_MMAP_REGULAR_PAGE:
1826                 return uar_mmap(dev, command, vma, context);
1827
1828         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1829                 return -ENOSYS;
1830
1831         case MLX5_IB_MMAP_CORE_CLOCK:
1832                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1833                         return -EINVAL;
1834
1835                 if (vma->vm_flags & VM_WRITE)
1836                         return -EPERM;
1837
1838                 /* Don't expose to user-space information it shouldn't have */
1839                 if (PAGE_SIZE > 4096)
1840                         return -EOPNOTSUPP;
1841
1842                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1843                 pfn = (dev->mdev->iseg_base +
1844                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1845                         PAGE_SHIFT;
1846                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1847                                        PAGE_SIZE, vma->vm_page_prot))
1848                         return -EAGAIN;
1849
1850                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1851                             vma->vm_start,
1852                             (unsigned long long)pfn << PAGE_SHIFT);
1853                 break;
1854
1855         default:
1856                 return -EINVAL;
1857         }
1858
1859         return 0;
1860 }
1861
1862 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1863                                       struct ib_ucontext *context,
1864                                       struct ib_udata *udata)
1865 {
1866         struct mlx5_ib_alloc_pd_resp resp;
1867         struct mlx5_ib_pd *pd;
1868         int err;
1869
1870         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1871         if (!pd)
1872                 return ERR_PTR(-ENOMEM);
1873
1874         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1875         if (err) {
1876                 kfree(pd);
1877                 return ERR_PTR(err);
1878         }
1879
1880         if (context) {
1881                 resp.pdn = pd->pdn;
1882                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1883                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1884                         kfree(pd);
1885                         return ERR_PTR(-EFAULT);
1886                 }
1887         }
1888
1889         return &pd->ibpd;
1890 }
1891
1892 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1893 {
1894         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1895         struct mlx5_ib_pd *mpd = to_mpd(pd);
1896
1897         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1898         kfree(mpd);
1899
1900         return 0;
1901 }
1902
1903 enum {
1904         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1905         MATCH_CRITERIA_ENABLE_MISC_BIT,
1906         MATCH_CRITERIA_ENABLE_INNER_BIT
1907 };
1908
1909 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1910         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1911                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1912
1913 static u8 get_match_criteria_enable(u32 *match_criteria)
1914 {
1915         u8 match_criteria_enable;
1916
1917         match_criteria_enable =
1918                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1919                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1920         match_criteria_enable |=
1921                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1922                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1923         match_criteria_enable |=
1924                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1925                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1926
1927         return match_criteria_enable;
1928 }
1929
1930 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1931 {
1932         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1933         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1934 }
1935
1936 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1937                            bool inner)
1938 {
1939         if (inner) {
1940                 MLX5_SET(fte_match_set_misc,
1941                          misc_c, inner_ipv6_flow_label, mask);
1942                 MLX5_SET(fte_match_set_misc,
1943                          misc_v, inner_ipv6_flow_label, val);
1944         } else {
1945                 MLX5_SET(fte_match_set_misc,
1946                          misc_c, outer_ipv6_flow_label, mask);
1947                 MLX5_SET(fte_match_set_misc,
1948                          misc_v, outer_ipv6_flow_label, val);
1949         }
1950 }
1951
1952 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1953 {
1954         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1955         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1956         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1957         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1958 }
1959
1960 #define LAST_ETH_FIELD vlan_tag
1961 #define LAST_IB_FIELD sl
1962 #define LAST_IPV4_FIELD tos
1963 #define LAST_IPV6_FIELD traffic_class
1964 #define LAST_TCP_UDP_FIELD src_port
1965 #define LAST_TUNNEL_FIELD tunnel_id
1966 #define LAST_FLOW_TAG_FIELD tag_id
1967 #define LAST_DROP_FIELD size
1968
1969 /* Field is the last supported field */
1970 #define FIELDS_NOT_SUPPORTED(filter, field)\
1971         memchr_inv((void *)&filter.field  +\
1972                    sizeof(filter.field), 0,\
1973                    sizeof(filter) -\
1974                    offsetof(typeof(filter), field) -\
1975                    sizeof(filter.field))
1976
1977 #define IPV4_VERSION 4
1978 #define IPV6_VERSION 6
1979 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1980                            u32 *match_v, const union ib_flow_spec *ib_spec,
1981                            u32 *tag_id, bool *is_drop)
1982 {
1983         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1984                                            misc_parameters);
1985         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1986                                            misc_parameters);
1987         void *headers_c;
1988         void *headers_v;
1989         int match_ipv;
1990
1991         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1992                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1993                                          inner_headers);
1994                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1995                                          inner_headers);
1996                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1997                                         ft_field_support.inner_ip_version);
1998         } else {
1999                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2000                                          outer_headers);
2001                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2002                                          outer_headers);
2003                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2004                                         ft_field_support.outer_ip_version);
2005         }
2006
2007         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2008         case IB_FLOW_SPEC_ETH:
2009                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2010                         return -EOPNOTSUPP;
2011
2012                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2013                                              dmac_47_16),
2014                                 ib_spec->eth.mask.dst_mac);
2015                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2016                                              dmac_47_16),
2017                                 ib_spec->eth.val.dst_mac);
2018
2019                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2020                                              smac_47_16),
2021                                 ib_spec->eth.mask.src_mac);
2022                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2023                                              smac_47_16),
2024                                 ib_spec->eth.val.src_mac);
2025
2026                 if (ib_spec->eth.mask.vlan_tag) {
2027                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2028                                  cvlan_tag, 1);
2029                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2030                                  cvlan_tag, 1);
2031
2032                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2033                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2034                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2035                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2036
2037                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2038                                  first_cfi,
2039                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2040                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2041                                  first_cfi,
2042                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2043
2044                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2045                                  first_prio,
2046                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2047                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2048                                  first_prio,
2049                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2050                 }
2051                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2052                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
2053                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2054                          ethertype, ntohs(ib_spec->eth.val.ether_type));
2055                 break;
2056         case IB_FLOW_SPEC_IPV4:
2057                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2058                         return -EOPNOTSUPP;
2059
2060                 if (match_ipv) {
2061                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2062                                  ip_version, 0xf);
2063                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2064                                  ip_version, IPV4_VERSION);
2065                 } else {
2066                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2067                                  ethertype, 0xffff);
2068                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2069                                  ethertype, ETH_P_IP);
2070                 }
2071
2072                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2073                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2074                        &ib_spec->ipv4.mask.src_ip,
2075                        sizeof(ib_spec->ipv4.mask.src_ip));
2076                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2077                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2078                        &ib_spec->ipv4.val.src_ip,
2079                        sizeof(ib_spec->ipv4.val.src_ip));
2080                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2081                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2082                        &ib_spec->ipv4.mask.dst_ip,
2083                        sizeof(ib_spec->ipv4.mask.dst_ip));
2084                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2085                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2086                        &ib_spec->ipv4.val.dst_ip,
2087                        sizeof(ib_spec->ipv4.val.dst_ip));
2088
2089                 set_tos(headers_c, headers_v,
2090                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2091
2092                 set_proto(headers_c, headers_v,
2093                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2094                 break;
2095         case IB_FLOW_SPEC_IPV6:
2096                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2097                         return -EOPNOTSUPP;
2098
2099                 if (match_ipv) {
2100                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2101                                  ip_version, 0xf);
2102                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2103                                  ip_version, IPV6_VERSION);
2104                 } else {
2105                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2106                                  ethertype, 0xffff);
2107                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2108                                  ethertype, ETH_P_IPV6);
2109                 }
2110
2111                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2112                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2113                        &ib_spec->ipv6.mask.src_ip,
2114                        sizeof(ib_spec->ipv6.mask.src_ip));
2115                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2116                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2117                        &ib_spec->ipv6.val.src_ip,
2118                        sizeof(ib_spec->ipv6.val.src_ip));
2119                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2120                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2121                        &ib_spec->ipv6.mask.dst_ip,
2122                        sizeof(ib_spec->ipv6.mask.dst_ip));
2123                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2124                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2125                        &ib_spec->ipv6.val.dst_ip,
2126                        sizeof(ib_spec->ipv6.val.dst_ip));
2127
2128                 set_tos(headers_c, headers_v,
2129                         ib_spec->ipv6.mask.traffic_class,
2130                         ib_spec->ipv6.val.traffic_class);
2131
2132                 set_proto(headers_c, headers_v,
2133                           ib_spec->ipv6.mask.next_hdr,
2134                           ib_spec->ipv6.val.next_hdr);
2135
2136                 set_flow_label(misc_params_c, misc_params_v,
2137                                ntohl(ib_spec->ipv6.mask.flow_label),
2138                                ntohl(ib_spec->ipv6.val.flow_label),
2139                                ib_spec->type & IB_FLOW_SPEC_INNER);
2140
2141                 break;
2142         case IB_FLOW_SPEC_TCP:
2143                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2144                                          LAST_TCP_UDP_FIELD))
2145                         return -EOPNOTSUPP;
2146
2147                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2148                          0xff);
2149                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2150                          IPPROTO_TCP);
2151
2152                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2153                          ntohs(ib_spec->tcp_udp.mask.src_port));
2154                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2155                          ntohs(ib_spec->tcp_udp.val.src_port));
2156
2157                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2158                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2159                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2160                          ntohs(ib_spec->tcp_udp.val.dst_port));
2161                 break;
2162         case IB_FLOW_SPEC_UDP:
2163                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2164                                          LAST_TCP_UDP_FIELD))
2165                         return -EOPNOTSUPP;
2166
2167                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2168                          0xff);
2169                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2170                          IPPROTO_UDP);
2171
2172                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2173                          ntohs(ib_spec->tcp_udp.mask.src_port));
2174                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2175                          ntohs(ib_spec->tcp_udp.val.src_port));
2176
2177                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2178                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2179                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2180                          ntohs(ib_spec->tcp_udp.val.dst_port));
2181                 break;
2182         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2183                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2184                                          LAST_TUNNEL_FIELD))
2185                         return -EOPNOTSUPP;
2186
2187                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2188                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2189                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2190                          ntohl(ib_spec->tunnel.val.tunnel_id));
2191                 break;
2192         case IB_FLOW_SPEC_ACTION_TAG:
2193                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2194                                          LAST_FLOW_TAG_FIELD))
2195                         return -EOPNOTSUPP;
2196                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2197                         return -EINVAL;
2198
2199                 *tag_id = ib_spec->flow_tag.tag_id;
2200                 break;
2201         case IB_FLOW_SPEC_ACTION_DROP:
2202                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2203                                          LAST_DROP_FIELD))
2204                         return -EOPNOTSUPP;
2205                 *is_drop = true;
2206                 break;
2207         default:
2208                 return -EINVAL;
2209         }
2210
2211         return 0;
2212 }
2213
2214 /* If a flow could catch both multicast and unicast packets,
2215  * it won't fall into the multicast flow steering table and this rule
2216  * could steal other multicast packets.
2217  */
2218 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2219 {
2220         union ib_flow_spec *flow_spec;
2221
2222         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2223             ib_attr->num_of_specs < 1)
2224                 return false;
2225
2226         flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2227         if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2228                 struct ib_flow_spec_ipv4 *ipv4_spec;
2229
2230                 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2231                 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2232                         return true;
2233
2234                 return false;
2235         }
2236
2237         if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2238                 struct ib_flow_spec_eth *eth_spec;
2239
2240                 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2241                 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2242                        is_multicast_ether_addr(eth_spec->val.dst_mac);
2243         }
2244
2245         return false;
2246 }
2247
2248 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2249                                const struct ib_flow_attr *flow_attr,
2250                                bool check_inner)
2251 {
2252         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2253         int match_ipv = check_inner ?
2254                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2255                                         ft_field_support.inner_ip_version) :
2256                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2257                                         ft_field_support.outer_ip_version);
2258         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2259         bool ipv4_spec_valid, ipv6_spec_valid;
2260         unsigned int ip_spec_type = 0;
2261         bool has_ethertype = false;
2262         unsigned int spec_index;
2263         bool mask_valid = true;
2264         u16 eth_type = 0;
2265         bool type_valid;
2266
2267         /* Validate that ethertype is correct */
2268         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2269                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2270                     ib_spec->eth.mask.ether_type) {
2271                         mask_valid = (ib_spec->eth.mask.ether_type ==
2272                                       htons(0xffff));
2273                         has_ethertype = true;
2274                         eth_type = ntohs(ib_spec->eth.val.ether_type);
2275                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2276                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2277                         ip_spec_type = ib_spec->type;
2278                 }
2279                 ib_spec = (void *)ib_spec + ib_spec->size;
2280         }
2281
2282         type_valid = (!has_ethertype) || (!ip_spec_type);
2283         if (!type_valid && mask_valid) {
2284                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2285                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2286                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2287                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2288
2289                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2290                              (((eth_type == ETH_P_MPLS_UC) ||
2291                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2292         }
2293
2294         return type_valid;
2295 }
2296
2297 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2298                           const struct ib_flow_attr *flow_attr)
2299 {
2300         return is_valid_ethertype(mdev, flow_attr, false) &&
2301                is_valid_ethertype(mdev, flow_attr, true);
2302 }
2303
2304 static void put_flow_table(struct mlx5_ib_dev *dev,
2305                            struct mlx5_ib_flow_prio *prio, bool ft_added)
2306 {
2307         prio->refcount -= !!ft_added;
2308         if (!prio->refcount) {
2309                 mlx5_destroy_flow_table(prio->flow_table);
2310                 prio->flow_table = NULL;
2311         }
2312 }
2313
2314 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2315 {
2316         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2317         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2318                                                           struct mlx5_ib_flow_handler,
2319                                                           ibflow);
2320         struct mlx5_ib_flow_handler *iter, *tmp;
2321
2322         mutex_lock(&dev->flow_db.lock);
2323
2324         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2325                 mlx5_del_flow_rules(iter->rule);
2326                 put_flow_table(dev, iter->prio, true);
2327                 list_del(&iter->list);
2328                 kfree(iter);
2329         }
2330
2331         mlx5_del_flow_rules(handler->rule);
2332         put_flow_table(dev, handler->prio, true);
2333         mutex_unlock(&dev->flow_db.lock);
2334
2335         kfree(handler);
2336
2337         return 0;
2338 }
2339
2340 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2341 {
2342         priority *= 2;
2343         if (!dont_trap)
2344                 priority++;
2345         return priority;
2346 }
2347
2348 enum flow_table_type {
2349         MLX5_IB_FT_RX,
2350         MLX5_IB_FT_TX
2351 };
2352
2353 #define MLX5_FS_MAX_TYPES        6
2354 #define MLX5_FS_MAX_ENTRIES      BIT(16)
2355 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2356                                                 struct ib_flow_attr *flow_attr,
2357                                                 enum flow_table_type ft_type)
2358 {
2359         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2360         struct mlx5_flow_namespace *ns = NULL;
2361         struct mlx5_ib_flow_prio *prio;
2362         struct mlx5_flow_table *ft;
2363         int max_table_size;
2364         int num_entries;
2365         int num_groups;
2366         int priority;
2367         int err = 0;
2368
2369         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2370                                                        log_max_ft_size));
2371         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2372                 if (flow_is_multicast_only(flow_attr) &&
2373                     !dont_trap)
2374                         priority = MLX5_IB_FLOW_MCAST_PRIO;
2375                 else
2376                         priority = ib_prio_to_core_prio(flow_attr->priority,
2377                                                         dont_trap);
2378                 ns = mlx5_get_flow_namespace(dev->mdev,
2379                                              MLX5_FLOW_NAMESPACE_BYPASS);
2380                 num_entries = MLX5_FS_MAX_ENTRIES;
2381                 num_groups = MLX5_FS_MAX_TYPES;
2382                 prio = &dev->flow_db.prios[priority];
2383         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2384                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2385                 ns = mlx5_get_flow_namespace(dev->mdev,
2386                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
2387                 build_leftovers_ft_param(&priority,
2388                                          &num_entries,
2389                                          &num_groups);
2390                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2391         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2392                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2393                                         allow_sniffer_and_nic_rx_shared_tir))
2394                         return ERR_PTR(-ENOTSUPP);
2395
2396                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2397                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2398                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2399
2400                 prio = &dev->flow_db.sniffer[ft_type];
2401                 priority = 0;
2402                 num_entries = 1;
2403                 num_groups = 1;
2404         }
2405
2406         if (!ns)
2407                 return ERR_PTR(-ENOTSUPP);
2408
2409         if (num_entries > max_table_size)
2410                 return ERR_PTR(-ENOMEM);
2411
2412         ft = prio->flow_table;
2413         if (!ft) {
2414                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2415                                                          num_entries,
2416                                                          num_groups,
2417                                                          0, 0);
2418
2419                 if (!IS_ERR(ft)) {
2420                         prio->refcount = 0;
2421                         prio->flow_table = ft;
2422                 } else {
2423                         err = PTR_ERR(ft);
2424                 }
2425         }
2426
2427         return err ? ERR_PTR(err) : prio;
2428 }
2429
2430 static void set_underlay_qp(struct mlx5_ib_dev *dev,
2431                             struct mlx5_flow_spec *spec,
2432                             u32 underlay_qpn)
2433 {
2434         void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2435                                            spec->match_criteria,
2436                                            misc_parameters);
2437         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2438                                            misc_parameters);
2439
2440         if (underlay_qpn &&
2441             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2442                                       ft_field_support.bth_dst_qp)) {
2443                 MLX5_SET(fte_match_set_misc,
2444                          misc_params_v, bth_dst_qp, underlay_qpn);
2445                 MLX5_SET(fte_match_set_misc,
2446                          misc_params_c, bth_dst_qp, 0xffffff);
2447         }
2448 }
2449
2450 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2451                                                       struct mlx5_ib_flow_prio *ft_prio,
2452                                                       const struct ib_flow_attr *flow_attr,
2453                                                       struct mlx5_flow_destination *dst,
2454                                                       u32 underlay_qpn)
2455 {
2456         struct mlx5_flow_table  *ft = ft_prio->flow_table;
2457         struct mlx5_ib_flow_handler *handler;
2458         struct mlx5_flow_act flow_act = {0};
2459         struct mlx5_flow_spec *spec;
2460         struct mlx5_flow_destination *rule_dst = dst;
2461         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2462         unsigned int spec_index;
2463         u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2464         bool is_drop = false;
2465         int err = 0;
2466         int dest_num = 1;
2467
2468         if (!is_valid_attr(dev->mdev, flow_attr))
2469                 return ERR_PTR(-EINVAL);
2470
2471         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2472         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2473         if (!handler || !spec) {
2474                 err = -ENOMEM;
2475                 goto free;
2476         }
2477
2478         INIT_LIST_HEAD(&handler->list);
2479
2480         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2481                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
2482                                       spec->match_value,
2483                                       ib_flow, &flow_tag, &is_drop);
2484                 if (err < 0)
2485                         goto free;
2486
2487                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2488         }
2489
2490         if (!flow_is_multicast_only(flow_attr))
2491                 set_underlay_qp(dev, spec, underlay_qpn);
2492
2493         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2494         if (is_drop) {
2495                 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2496                 rule_dst = NULL;
2497                 dest_num = 0;
2498         } else {
2499                 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2500                     MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2501         }
2502
2503         if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2504             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2505              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2506                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2507                              flow_tag, flow_attr->type);
2508                 err = -EINVAL;
2509                 goto free;
2510         }
2511         flow_act.flow_tag = flow_tag;
2512         handler->rule = mlx5_add_flow_rules(ft, spec,
2513                                             &flow_act,
2514                                             rule_dst, dest_num);
2515
2516         if (IS_ERR(handler->rule)) {
2517                 err = PTR_ERR(handler->rule);
2518                 goto free;
2519         }
2520
2521         ft_prio->refcount++;
2522         handler->prio = ft_prio;
2523
2524         ft_prio->flow_table = ft;
2525 free:
2526         if (err)
2527                 kfree(handler);
2528         kvfree(spec);
2529         return err ? ERR_PTR(err) : handler;
2530 }
2531
2532 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2533                                                      struct mlx5_ib_flow_prio *ft_prio,
2534                                                      const struct ib_flow_attr *flow_attr,
2535                                                      struct mlx5_flow_destination *dst)
2536 {
2537         return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2538 }
2539
2540 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2541                                                           struct mlx5_ib_flow_prio *ft_prio,
2542                                                           struct ib_flow_attr *flow_attr,
2543                                                           struct mlx5_flow_destination *dst)
2544 {
2545         struct mlx5_ib_flow_handler *handler_dst = NULL;
2546         struct mlx5_ib_flow_handler *handler = NULL;
2547
2548         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2549         if (!IS_ERR(handler)) {
2550                 handler_dst = create_flow_rule(dev, ft_prio,
2551                                                flow_attr, dst);
2552                 if (IS_ERR(handler_dst)) {
2553                         mlx5_del_flow_rules(handler->rule);
2554                         ft_prio->refcount--;
2555                         kfree(handler);
2556                         handler = handler_dst;
2557                 } else {
2558                         list_add(&handler_dst->list, &handler->list);
2559                 }
2560         }
2561
2562         return handler;
2563 }
2564 enum {
2565         LEFTOVERS_MC,
2566         LEFTOVERS_UC,
2567 };
2568
2569 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2570                                                           struct mlx5_ib_flow_prio *ft_prio,
2571                                                           struct ib_flow_attr *flow_attr,
2572                                                           struct mlx5_flow_destination *dst)
2573 {
2574         struct mlx5_ib_flow_handler *handler_ucast = NULL;
2575         struct mlx5_ib_flow_handler *handler = NULL;
2576
2577         static struct {
2578                 struct ib_flow_attr     flow_attr;
2579                 struct ib_flow_spec_eth eth_flow;
2580         } leftovers_specs[] = {
2581                 [LEFTOVERS_MC] = {
2582                         .flow_attr = {
2583                                 .num_of_specs = 1,
2584                                 .size = sizeof(leftovers_specs[0])
2585                         },
2586                         .eth_flow = {
2587                                 .type = IB_FLOW_SPEC_ETH,
2588                                 .size = sizeof(struct ib_flow_spec_eth),
2589                                 .mask = {.dst_mac = {0x1} },
2590                                 .val =  {.dst_mac = {0x1} }
2591                         }
2592                 },
2593                 [LEFTOVERS_UC] = {
2594                         .flow_attr = {
2595                                 .num_of_specs = 1,
2596                                 .size = sizeof(leftovers_specs[0])
2597                         },
2598                         .eth_flow = {
2599                                 .type = IB_FLOW_SPEC_ETH,
2600                                 .size = sizeof(struct ib_flow_spec_eth),
2601                                 .mask = {.dst_mac = {0x1} },
2602                                 .val = {.dst_mac = {} }
2603                         }
2604                 }
2605         };
2606
2607         handler = create_flow_rule(dev, ft_prio,
2608                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
2609                                    dst);
2610         if (!IS_ERR(handler) &&
2611             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2612                 handler_ucast = create_flow_rule(dev, ft_prio,
2613                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
2614                                                  dst);
2615                 if (IS_ERR(handler_ucast)) {
2616                         mlx5_del_flow_rules(handler->rule);
2617                         ft_prio->refcount--;
2618                         kfree(handler);
2619                         handler = handler_ucast;
2620                 } else {
2621                         list_add(&handler_ucast->list, &handler->list);
2622                 }
2623         }
2624
2625         return handler;
2626 }
2627
2628 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2629                                                         struct mlx5_ib_flow_prio *ft_rx,
2630                                                         struct mlx5_ib_flow_prio *ft_tx,
2631                                                         struct mlx5_flow_destination *dst)
2632 {
2633         struct mlx5_ib_flow_handler *handler_rx;
2634         struct mlx5_ib_flow_handler *handler_tx;
2635         int err;
2636         static const struct ib_flow_attr flow_attr  = {
2637                 .num_of_specs = 0,
2638                 .size = sizeof(flow_attr)
2639         };
2640
2641         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2642         if (IS_ERR(handler_rx)) {
2643                 err = PTR_ERR(handler_rx);
2644                 goto err;
2645         }
2646
2647         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2648         if (IS_ERR(handler_tx)) {
2649                 err = PTR_ERR(handler_tx);
2650                 goto err_tx;
2651         }
2652
2653         list_add(&handler_tx->list, &handler_rx->list);
2654
2655         return handler_rx;
2656
2657 err_tx:
2658         mlx5_del_flow_rules(handler_rx->rule);
2659         ft_rx->refcount--;
2660         kfree(handler_rx);
2661 err:
2662         return ERR_PTR(err);
2663 }
2664
2665 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2666                                            struct ib_flow_attr *flow_attr,
2667                                            int domain)
2668 {
2669         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2670         struct mlx5_ib_qp *mqp = to_mqp(qp);
2671         struct mlx5_ib_flow_handler *handler = NULL;
2672         struct mlx5_flow_destination *dst = NULL;
2673         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2674         struct mlx5_ib_flow_prio *ft_prio;
2675         int err;
2676         int underlay_qpn;
2677
2678         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2679                 return ERR_PTR(-ENOMEM);
2680
2681         if (domain != IB_FLOW_DOMAIN_USER ||
2682             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2683             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2684                 return ERR_PTR(-EINVAL);
2685
2686         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2687         if (!dst)
2688                 return ERR_PTR(-ENOMEM);
2689
2690         mutex_lock(&dev->flow_db.lock);
2691
2692         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2693         if (IS_ERR(ft_prio)) {
2694                 err = PTR_ERR(ft_prio);
2695                 goto unlock;
2696         }
2697         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2698                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2699                 if (IS_ERR(ft_prio_tx)) {
2700                         err = PTR_ERR(ft_prio_tx);
2701                         ft_prio_tx = NULL;
2702                         goto destroy_ft;
2703                 }
2704         }
2705
2706         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2707         if (mqp->flags & MLX5_IB_QP_RSS)
2708                 dst->tir_num = mqp->rss_qp.tirn;
2709         else
2710                 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2711
2712         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2713                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2714                         handler = create_dont_trap_rule(dev, ft_prio,
2715                                                         flow_attr, dst);
2716                 } else {
2717                         underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
2718                                         mqp->underlay_qpn : 0;
2719                         handler = _create_flow_rule(dev, ft_prio, flow_attr,
2720                                                     dst, underlay_qpn);
2721                 }
2722         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2723                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2724                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2725                                                 dst);
2726         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2727                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2728         } else {
2729                 err = -EINVAL;
2730                 goto destroy_ft;
2731         }
2732
2733         if (IS_ERR(handler)) {
2734                 err = PTR_ERR(handler);
2735                 handler = NULL;
2736                 goto destroy_ft;
2737         }
2738
2739         mutex_unlock(&dev->flow_db.lock);
2740         kfree(dst);
2741
2742         return &handler->ibflow;
2743
2744 destroy_ft:
2745         put_flow_table(dev, ft_prio, false);
2746         if (ft_prio_tx)
2747                 put_flow_table(dev, ft_prio_tx, false);
2748 unlock:
2749         mutex_unlock(&dev->flow_db.lock);
2750         kfree(dst);
2751         kfree(handler);
2752         return ERR_PTR(err);
2753 }
2754
2755 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2756 {
2757         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2758         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2759         int err;
2760
2761         if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
2762                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2763                 return -EOPNOTSUPP;
2764         }
2765
2766         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2767         if (err)
2768                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2769                              ibqp->qp_num, gid->raw);
2770
2771         return err;
2772 }
2773
2774 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2775 {
2776         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2777         int err;
2778
2779         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2780         if (err)
2781                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2782                              ibqp->qp_num, gid->raw);
2783
2784         return err;
2785 }
2786
2787 static int init_node_data(struct mlx5_ib_dev *dev)
2788 {
2789         int err;
2790
2791         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2792         if (err)
2793                 return err;
2794
2795         dev->mdev->rev_id = dev->mdev->pdev->revision;
2796
2797         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2798 }
2799
2800 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2801                              char *buf)
2802 {
2803         struct mlx5_ib_dev *dev =
2804                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2805
2806         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2807 }
2808
2809 static ssize_t show_reg_pages(struct device *device,
2810                               struct device_attribute *attr, char *buf)
2811 {
2812         struct mlx5_ib_dev *dev =
2813                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2814
2815         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2816 }
2817
2818 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2819                         char *buf)
2820 {
2821         struct mlx5_ib_dev *dev =
2822                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2823         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2824 }
2825
2826 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2827                         char *buf)
2828 {
2829         struct mlx5_ib_dev *dev =
2830                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2831         return sprintf(buf, "%x\n", dev->mdev->rev_id);
2832 }
2833
2834 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2835                           char *buf)
2836 {
2837         struct mlx5_ib_dev *dev =
2838                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2839         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2840                        dev->mdev->board_id);
2841 }
2842
2843 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2844 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2845 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2846 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2847 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2848
2849 static struct device_attribute *mlx5_class_attributes[] = {
2850         &dev_attr_hw_rev,
2851         &dev_attr_hca_type,
2852         &dev_attr_board_id,
2853         &dev_attr_fw_pages,
2854         &dev_attr_reg_pages,
2855 };
2856
2857 static void pkey_change_handler(struct work_struct *work)
2858 {
2859         struct mlx5_ib_port_resources *ports =
2860                 container_of(work, struct mlx5_ib_port_resources,
2861                              pkey_change_work);
2862
2863         mutex_lock(&ports->devr->mutex);
2864         mlx5_ib_gsi_pkey_change(ports->gsi);
2865         mutex_unlock(&ports->devr->mutex);
2866 }
2867
2868 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2869 {
2870         struct mlx5_ib_qp *mqp;
2871         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2872         struct mlx5_core_cq *mcq;
2873         struct list_head cq_armed_list;
2874         unsigned long flags_qp;
2875         unsigned long flags_cq;
2876         unsigned long flags;
2877
2878         INIT_LIST_HEAD(&cq_armed_list);
2879
2880         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2881         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2882         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2883                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2884                 if (mqp->sq.tail != mqp->sq.head) {
2885                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2886                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2887                         if (send_mcq->mcq.comp &&
2888                             mqp->ibqp.send_cq->comp_handler) {
2889                                 if (!send_mcq->mcq.reset_notify_added) {
2890                                         send_mcq->mcq.reset_notify_added = 1;
2891                                         list_add_tail(&send_mcq->mcq.reset_notify,
2892                                                       &cq_armed_list);
2893                                 }
2894                         }
2895                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2896                 }
2897                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2898                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2899                 /* no handling is needed for SRQ */
2900                 if (!mqp->ibqp.srq) {
2901                         if (mqp->rq.tail != mqp->rq.head) {
2902                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2903                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2904                                 if (recv_mcq->mcq.comp &&
2905                                     mqp->ibqp.recv_cq->comp_handler) {
2906                                         if (!recv_mcq->mcq.reset_notify_added) {
2907                                                 recv_mcq->mcq.reset_notify_added = 1;
2908                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2909                                                               &cq_armed_list);
2910                                         }
2911                                 }
2912                                 spin_unlock_irqrestore(&recv_mcq->lock,
2913                                                        flags_cq);
2914                         }
2915                 }
2916                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2917         }
2918         /*At that point all inflight post send were put to be executed as of we
2919          * lock/unlock above locks Now need to arm all involved CQs.
2920          */
2921         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2922                 mcq->comp(mcq);
2923         }
2924         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2925 }
2926
2927 static void delay_drop_handler(struct work_struct *work)
2928 {
2929         int err;
2930         struct mlx5_ib_delay_drop *delay_drop =
2931                 container_of(work, struct mlx5_ib_delay_drop,
2932                              delay_drop_work);
2933
2934         atomic_inc(&delay_drop->events_cnt);
2935
2936         mutex_lock(&delay_drop->lock);
2937         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
2938                                        delay_drop->timeout);
2939         if (err) {
2940                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2941                              delay_drop->timeout);
2942                 delay_drop->activate = false;
2943         }
2944         mutex_unlock(&delay_drop->lock);
2945 }
2946
2947 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2948                           enum mlx5_dev_event event, unsigned long param)
2949 {
2950         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2951         struct ib_event ibev;
2952         bool fatal = false;
2953         u8 port = 0;
2954
2955         switch (event) {
2956         case MLX5_DEV_EVENT_SYS_ERROR:
2957                 ibev.event = IB_EVENT_DEVICE_FATAL;
2958                 mlx5_ib_handle_internal_error(ibdev);
2959                 fatal = true;
2960                 break;
2961
2962         case MLX5_DEV_EVENT_PORT_UP:
2963         case MLX5_DEV_EVENT_PORT_DOWN:
2964         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2965                 port = (u8)param;
2966
2967                 /* In RoCE, port up/down events are handled in
2968                  * mlx5_netdev_event().
2969                  */
2970                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2971                         IB_LINK_LAYER_ETHERNET)
2972                         return;
2973
2974                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2975                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2976                 break;
2977
2978         case MLX5_DEV_EVENT_LID_CHANGE:
2979                 ibev.event = IB_EVENT_LID_CHANGE;
2980                 port = (u8)param;
2981                 break;
2982
2983         case MLX5_DEV_EVENT_PKEY_CHANGE:
2984                 ibev.event = IB_EVENT_PKEY_CHANGE;
2985                 port = (u8)param;
2986
2987                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2988                 break;
2989
2990         case MLX5_DEV_EVENT_GUID_CHANGE:
2991                 ibev.event = IB_EVENT_GID_CHANGE;
2992                 port = (u8)param;
2993                 break;
2994
2995         case MLX5_DEV_EVENT_CLIENT_REREG:
2996                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2997                 port = (u8)param;
2998                 break;
2999         case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3000                 schedule_work(&ibdev->delay_drop.delay_drop_work);
3001                 goto out;
3002         default:
3003                 goto out;
3004         }
3005
3006         ibev.device           = &ibdev->ib_dev;
3007         ibev.element.port_num = port;
3008
3009         if (port < 1 || port > ibdev->num_ports) {
3010                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
3011                 goto out;
3012         }
3013
3014         if (ibdev->ib_active)
3015                 ib_dispatch_event(&ibev);
3016
3017         if (fatal)
3018                 ibdev->ib_active = false;
3019
3020 out:
3021         return;
3022 }
3023
3024 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3025 {
3026         struct mlx5_hca_vport_context vport_ctx;
3027         int err;
3028         int port;
3029
3030         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
3031                 dev->mdev->port_caps[port - 1].has_smi = false;
3032                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3033                     MLX5_CAP_PORT_TYPE_IB) {
3034                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3035                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3036                                                                    port, 0,
3037                                                                    &vport_ctx);
3038                                 if (err) {
3039                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3040                                                     port, err);
3041                                         return err;
3042                                 }
3043                                 dev->mdev->port_caps[port - 1].has_smi =
3044                                         vport_ctx.has_smi;
3045                         } else {
3046                                 dev->mdev->port_caps[port - 1].has_smi = true;
3047                         }
3048                 }
3049         }
3050         return 0;
3051 }
3052
3053 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3054 {
3055         int port;
3056
3057         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
3058                 mlx5_query_ext_port_caps(dev, port);
3059 }
3060
3061 static int get_port_caps(struct mlx5_ib_dev *dev)
3062 {
3063         struct ib_device_attr *dprops = NULL;
3064         struct ib_port_attr *pprops = NULL;
3065         int err = -ENOMEM;
3066         int port;
3067         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
3068
3069         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3070         if (!pprops)
3071                 goto out;
3072
3073         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3074         if (!dprops)
3075                 goto out;
3076
3077         err = set_has_smi_cap(dev);
3078         if (err)
3079                 goto out;
3080
3081         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
3082         if (err) {
3083                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3084                 goto out;
3085         }
3086
3087         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
3088                 memset(pprops, 0, sizeof(*pprops));
3089                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3090                 if (err) {
3091                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
3092                                      port, err);
3093                         break;
3094                 }
3095                 dev->mdev->port_caps[port - 1].pkey_table_len =
3096                                                 dprops->max_pkeys;
3097                 dev->mdev->port_caps[port - 1].gid_table_len =
3098                                                 pprops->gid_tbl_len;
3099                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
3100                             dprops->max_pkeys, pprops->gid_tbl_len);
3101         }
3102
3103 out:
3104         kfree(pprops);
3105         kfree(dprops);
3106
3107         return err;
3108 }
3109
3110 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3111 {
3112         int err;
3113
3114         err = mlx5_mr_cache_cleanup(dev);
3115         if (err)
3116                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3117
3118         mlx5_ib_destroy_qp(dev->umrc.qp);
3119         ib_free_cq(dev->umrc.cq);
3120         ib_dealloc_pd(dev->umrc.pd);
3121 }
3122
3123 enum {
3124         MAX_UMR_WR = 128,
3125 };
3126
3127 static int create_umr_res(struct mlx5_ib_dev *dev)
3128 {
3129         struct ib_qp_init_attr *init_attr = NULL;
3130         struct ib_qp_attr *attr = NULL;
3131         struct ib_pd *pd;
3132         struct ib_cq *cq;
3133         struct ib_qp *qp;
3134         int ret;
3135
3136         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3137         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3138         if (!attr || !init_attr) {
3139                 ret = -ENOMEM;
3140                 goto error_0;
3141         }
3142
3143         pd = ib_alloc_pd(&dev->ib_dev, 0);
3144         if (IS_ERR(pd)) {
3145                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3146                 ret = PTR_ERR(pd);
3147                 goto error_0;
3148         }
3149
3150         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
3151         if (IS_ERR(cq)) {
3152                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3153                 ret = PTR_ERR(cq);
3154                 goto error_2;
3155         }
3156
3157         init_attr->send_cq = cq;
3158         init_attr->recv_cq = cq;
3159         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3160         init_attr->cap.max_send_wr = MAX_UMR_WR;
3161         init_attr->cap.max_send_sge = 1;
3162         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3163         init_attr->port_num = 1;
3164         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3165         if (IS_ERR(qp)) {
3166                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3167                 ret = PTR_ERR(qp);
3168                 goto error_3;
3169         }
3170         qp->device     = &dev->ib_dev;
3171         qp->real_qp    = qp;
3172         qp->uobject    = NULL;
3173         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
3174         qp->send_cq    = init_attr->send_cq;
3175         qp->recv_cq    = init_attr->recv_cq;
3176
3177         attr->qp_state = IB_QPS_INIT;
3178         attr->port_num = 1;
3179         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3180                                 IB_QP_PORT, NULL);
3181         if (ret) {
3182                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3183                 goto error_4;
3184         }
3185
3186         memset(attr, 0, sizeof(*attr));
3187         attr->qp_state = IB_QPS_RTR;
3188         attr->path_mtu = IB_MTU_256;
3189
3190         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3191         if (ret) {
3192                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3193                 goto error_4;
3194         }
3195
3196         memset(attr, 0, sizeof(*attr));
3197         attr->qp_state = IB_QPS_RTS;
3198         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3199         if (ret) {
3200                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3201                 goto error_4;
3202         }
3203
3204         dev->umrc.qp = qp;
3205         dev->umrc.cq = cq;
3206         dev->umrc.pd = pd;
3207
3208         sema_init(&dev->umrc.sem, MAX_UMR_WR);
3209         ret = mlx5_mr_cache_init(dev);
3210         if (ret) {
3211                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3212                 goto error_4;
3213         }
3214
3215         kfree(attr);
3216         kfree(init_attr);
3217
3218         return 0;
3219
3220 error_4:
3221         mlx5_ib_destroy_qp(qp);
3222
3223 error_3:
3224         ib_free_cq(cq);
3225
3226 error_2:
3227         ib_dealloc_pd(pd);
3228
3229 error_0:
3230         kfree(attr);
3231         kfree(init_attr);
3232         return ret;
3233 }
3234
3235 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3236 {
3237         switch (umr_fence_cap) {
3238         case MLX5_CAP_UMR_FENCE_NONE:
3239                 return MLX5_FENCE_MODE_NONE;
3240         case MLX5_CAP_UMR_FENCE_SMALL:
3241                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3242         default:
3243                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3244         }
3245 }
3246
3247 static int create_dev_resources(struct mlx5_ib_resources *devr)
3248 {
3249         struct ib_srq_init_attr attr;
3250         struct mlx5_ib_dev *dev;
3251         struct ib_cq_init_attr cq_attr = {.cqe = 1};
3252         int port;
3253         int ret = 0;
3254
3255         dev = container_of(devr, struct mlx5_ib_dev, devr);
3256
3257         mutex_init(&devr->mutex);
3258
3259         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3260         if (IS_ERR(devr->p0)) {
3261                 ret = PTR_ERR(devr->p0);
3262                 goto error0;
3263         }
3264         devr->p0->device  = &dev->ib_dev;
3265         devr->p0->uobject = NULL;
3266         atomic_set(&devr->p0->usecnt, 0);
3267
3268         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
3269         if (IS_ERR(devr->c0)) {
3270                 ret = PTR_ERR(devr->c0);
3271                 goto error1;
3272         }
3273         devr->c0->device        = &dev->ib_dev;
3274         devr->c0->uobject       = NULL;
3275         devr->c0->comp_handler  = NULL;
3276         devr->c0->event_handler = NULL;
3277         devr->c0->cq_context    = NULL;
3278         atomic_set(&devr->c0->usecnt, 0);
3279
3280         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3281         if (IS_ERR(devr->x0)) {
3282                 ret = PTR_ERR(devr->x0);
3283                 goto error2;
3284         }
3285         devr->x0->device = &dev->ib_dev;
3286         devr->x0->inode = NULL;
3287         atomic_set(&devr->x0->usecnt, 0);
3288         mutex_init(&devr->x0->tgt_qp_mutex);
3289         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3290
3291         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3292         if (IS_ERR(devr->x1)) {
3293                 ret = PTR_ERR(devr->x1);
3294                 goto error3;
3295         }
3296         devr->x1->device = &dev->ib_dev;
3297         devr->x1->inode = NULL;
3298         atomic_set(&devr->x1->usecnt, 0);
3299         mutex_init(&devr->x1->tgt_qp_mutex);
3300         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3301
3302         memset(&attr, 0, sizeof(attr));
3303         attr.attr.max_sge = 1;
3304         attr.attr.max_wr = 1;
3305         attr.srq_type = IB_SRQT_XRC;
3306         attr.ext.cq = devr->c0;
3307         attr.ext.xrc.xrcd = devr->x0;
3308
3309         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3310         if (IS_ERR(devr->s0)) {
3311                 ret = PTR_ERR(devr->s0);
3312                 goto error4;
3313         }
3314         devr->s0->device        = &dev->ib_dev;
3315         devr->s0->pd            = devr->p0;
3316         devr->s0->uobject       = NULL;
3317         devr->s0->event_handler = NULL;
3318         devr->s0->srq_context   = NULL;
3319         devr->s0->srq_type      = IB_SRQT_XRC;
3320         devr->s0->ext.xrc.xrcd  = devr->x0;
3321         devr->s0->ext.cq        = devr->c0;
3322         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3323         atomic_inc(&devr->s0->ext.cq->usecnt);
3324         atomic_inc(&devr->p0->usecnt);
3325         atomic_set(&devr->s0->usecnt, 0);
3326
3327         memset(&attr, 0, sizeof(attr));
3328         attr.attr.max_sge = 1;
3329         attr.attr.max_wr = 1;
3330         attr.srq_type = IB_SRQT_BASIC;
3331         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3332         if (IS_ERR(devr->s1)) {
3333                 ret = PTR_ERR(devr->s1);
3334                 goto error5;
3335         }
3336         devr->s1->device        = &dev->ib_dev;
3337         devr->s1->pd            = devr->p0;
3338         devr->s1->uobject       = NULL;
3339         devr->s1->event_handler = NULL;
3340         devr->s1->srq_context   = NULL;
3341         devr->s1->srq_type      = IB_SRQT_BASIC;
3342         devr->s1->ext.cq        = devr->c0;
3343         atomic_inc(&devr->p0->usecnt);
3344         atomic_set(&devr->s1->usecnt, 0);
3345
3346         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3347                 INIT_WORK(&devr->ports[port].pkey_change_work,
3348                           pkey_change_handler);
3349                 devr->ports[port].devr = devr;
3350         }
3351
3352         return 0;
3353
3354 error5:
3355         mlx5_ib_destroy_srq(devr->s0);
3356 error4:
3357         mlx5_ib_dealloc_xrcd(devr->x1);
3358 error3:
3359         mlx5_ib_dealloc_xrcd(devr->x0);
3360 error2:
3361         mlx5_ib_destroy_cq(devr->c0);
3362 error1:
3363         mlx5_ib_dealloc_pd(devr->p0);
3364 error0:
3365         return ret;
3366 }
3367
3368 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3369 {
3370         struct mlx5_ib_dev *dev =
3371                 container_of(devr, struct mlx5_ib_dev, devr);
3372         int port;
3373
3374         mlx5_ib_destroy_srq(devr->s1);
3375         mlx5_ib_destroy_srq(devr->s0);
3376         mlx5_ib_dealloc_xrcd(devr->x0);
3377         mlx5_ib_dealloc_xrcd(devr->x1);
3378         mlx5_ib_destroy_cq(devr->c0);
3379         mlx5_ib_dealloc_pd(devr->p0);
3380
3381         /* Make sure no change P_Key work items are still executing */
3382         for (port = 0; port < dev->num_ports; ++port)
3383                 cancel_work_sync(&devr->ports[port].pkey_change_work);
3384 }
3385
3386 static u32 get_core_cap_flags(struct ib_device *ibdev)
3387 {
3388         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3389         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3390         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3391         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3392         u32 ret = 0;
3393
3394         if (ll == IB_LINK_LAYER_INFINIBAND)
3395                 return RDMA_CORE_PORT_IBA_IB;
3396
3397         ret = RDMA_CORE_PORT_RAW_PACKET;
3398
3399         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3400                 return ret;
3401
3402         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3403                 return ret;
3404
3405         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3406                 ret |= RDMA_CORE_PORT_IBA_ROCE;
3407
3408         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3409                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3410
3411         return ret;
3412 }
3413
3414 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3415                                struct ib_port_immutable *immutable)
3416 {
3417         struct ib_port_attr attr;
3418         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3419         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3420         int err;
3421
3422         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3423
3424         err = ib_query_port(ibdev, port_num, &attr);
3425         if (err)
3426                 return err;
3427
3428         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3429         immutable->gid_tbl_len = attr.gid_tbl_len;
3430         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3431         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3432                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3433
3434         return 0;
3435 }
3436
3437 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3438 {
3439         struct mlx5_ib_dev *dev =
3440                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3441         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3442                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3443                  fw_rev_sub(dev->mdev));
3444 }
3445
3446 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3447 {
3448         struct mlx5_core_dev *mdev = dev->mdev;
3449         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3450                                                                  MLX5_FLOW_NAMESPACE_LAG);
3451         struct mlx5_flow_table *ft;
3452         int err;
3453
3454         if (!ns || !mlx5_lag_is_active(mdev))
3455                 return 0;
3456
3457         err = mlx5_cmd_create_vport_lag(mdev);
3458         if (err)
3459                 return err;
3460
3461         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3462         if (IS_ERR(ft)) {
3463                 err = PTR_ERR(ft);
3464                 goto err_destroy_vport_lag;
3465         }
3466
3467         dev->flow_db.lag_demux_ft = ft;
3468         return 0;
3469
3470 err_destroy_vport_lag:
3471         mlx5_cmd_destroy_vport_lag(mdev);
3472         return err;
3473 }
3474
3475 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3476 {
3477         struct mlx5_core_dev *mdev = dev->mdev;
3478
3479         if (dev->flow_db.lag_demux_ft) {
3480                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3481                 dev->flow_db.lag_demux_ft = NULL;
3482
3483                 mlx5_cmd_destroy_vport_lag(mdev);
3484         }
3485 }
3486
3487 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3488 {
3489         int err;
3490
3491         dev->roce.nb.notifier_call = mlx5_netdev_event;
3492         err = register_netdevice_notifier(&dev->roce.nb);
3493         if (err) {
3494                 dev->roce.nb.notifier_call = NULL;
3495                 return err;
3496         }
3497
3498         return 0;
3499 }
3500
3501 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
3502 {
3503         if (dev->roce.nb.notifier_call) {
3504                 unregister_netdevice_notifier(&dev->roce.nb);
3505                 dev->roce.nb.notifier_call = NULL;
3506         }
3507 }
3508
3509 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3510 {
3511         int err;
3512
3513         err = mlx5_add_netdev_notifier(dev);
3514         if (err)
3515                 return err;
3516
3517         if (MLX5_CAP_GEN(dev->mdev, roce)) {
3518                 err = mlx5_nic_vport_enable_roce(dev->mdev);
3519                 if (err)
3520                         goto err_unregister_netdevice_notifier;
3521         }
3522
3523         err = mlx5_eth_lag_init(dev);
3524         if (err)
3525                 goto err_disable_roce;
3526
3527         return 0;
3528
3529 err_disable_roce:
3530         if (MLX5_CAP_GEN(dev->mdev, roce))
3531                 mlx5_nic_vport_disable_roce(dev->mdev);
3532
3533 err_unregister_netdevice_notifier:
3534         mlx5_remove_netdev_notifier(dev);
3535         return err;
3536 }
3537
3538 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3539 {
3540         mlx5_eth_lag_cleanup(dev);
3541         if (MLX5_CAP_GEN(dev->mdev, roce))
3542                 mlx5_nic_vport_disable_roce(dev->mdev);
3543 }
3544
3545 struct mlx5_ib_counter {
3546         const char *name;
3547         size_t offset;
3548 };
3549
3550 #define INIT_Q_COUNTER(_name)           \
3551         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3552
3553 static const struct mlx5_ib_counter basic_q_cnts[] = {
3554         INIT_Q_COUNTER(rx_write_requests),
3555         INIT_Q_COUNTER(rx_read_requests),
3556         INIT_Q_COUNTER(rx_atomic_requests),
3557         INIT_Q_COUNTER(out_of_buffer),
3558 };
3559
3560 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
3561         INIT_Q_COUNTER(out_of_sequence),
3562 };
3563
3564 static const struct mlx5_ib_counter retrans_q_cnts[] = {
3565         INIT_Q_COUNTER(duplicate_request),
3566         INIT_Q_COUNTER(rnr_nak_retry_err),
3567         INIT_Q_COUNTER(packet_seq_err),
3568         INIT_Q_COUNTER(implied_nak_seq_err),
3569         INIT_Q_COUNTER(local_ack_timeout_err),
3570 };
3571
3572 #define INIT_CONG_COUNTER(_name)                \
3573         { .name = #_name, .offset =     \
3574                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3575
3576 static const struct mlx5_ib_counter cong_cnts[] = {
3577         INIT_CONG_COUNTER(rp_cnp_ignored),
3578         INIT_CONG_COUNTER(rp_cnp_handled),
3579         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3580         INIT_CONG_COUNTER(np_cnp_sent),
3581 };
3582
3583 static const struct mlx5_ib_counter extended_err_cnts[] = {
3584         INIT_Q_COUNTER(resp_local_length_error),
3585         INIT_Q_COUNTER(resp_cqe_error),
3586         INIT_Q_COUNTER(req_cqe_error),
3587         INIT_Q_COUNTER(req_remote_invalid_request),
3588         INIT_Q_COUNTER(req_remote_access_errors),
3589         INIT_Q_COUNTER(resp_remote_access_errors),
3590         INIT_Q_COUNTER(resp_cqe_flush_error),
3591         INIT_Q_COUNTER(req_cqe_flush_error),
3592 };
3593
3594 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
3595 {
3596         unsigned int i;
3597
3598         for (i = 0; i < dev->num_ports; i++) {
3599                 mlx5_core_dealloc_q_counter(dev->mdev,
3600                                             dev->port[i].cnts.set_id);
3601                 kfree(dev->port[i].cnts.names);
3602                 kfree(dev->port[i].cnts.offsets);
3603         }
3604 }
3605
3606 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3607                                     struct mlx5_ib_counters *cnts)
3608 {
3609         u32 num_counters;
3610
3611         num_counters = ARRAY_SIZE(basic_q_cnts);
3612
3613         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3614                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3615
3616         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3617                 num_counters += ARRAY_SIZE(retrans_q_cnts);
3618
3619         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3620                 num_counters += ARRAY_SIZE(extended_err_cnts);
3621
3622         cnts->num_q_counters = num_counters;
3623
3624         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3625                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3626                 num_counters += ARRAY_SIZE(cong_cnts);
3627         }
3628
3629         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3630         if (!cnts->names)
3631                 return -ENOMEM;
3632
3633         cnts->offsets = kcalloc(num_counters,
3634                                 sizeof(cnts->offsets), GFP_KERNEL);
3635         if (!cnts->offsets)
3636                 goto err_names;
3637
3638         return 0;
3639
3640 err_names:
3641         kfree(cnts->names);
3642         return -ENOMEM;
3643 }
3644
3645 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3646                                   const char **names,
3647                                   size_t *offsets)
3648 {
3649         int i;
3650         int j = 0;
3651
3652         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3653                 names[j] = basic_q_cnts[i].name;
3654                 offsets[j] = basic_q_cnts[i].offset;
3655         }
3656
3657         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3658                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3659                         names[j] = out_of_seq_q_cnts[i].name;
3660                         offsets[j] = out_of_seq_q_cnts[i].offset;
3661                 }
3662         }
3663
3664         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3665                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3666                         names[j] = retrans_q_cnts[i].name;
3667                         offsets[j] = retrans_q_cnts[i].offset;
3668                 }
3669         }
3670
3671         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
3672                 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
3673                         names[j] = extended_err_cnts[i].name;
3674                         offsets[j] = extended_err_cnts[i].offset;
3675                 }
3676         }
3677
3678         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3679                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3680                         names[j] = cong_cnts[i].name;
3681                         offsets[j] = cong_cnts[i].offset;
3682                 }
3683         }
3684 }
3685
3686 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
3687 {
3688         int i;
3689         int ret;
3690
3691         for (i = 0; i < dev->num_ports; i++) {
3692                 struct mlx5_ib_port *port = &dev->port[i];
3693
3694                 ret = mlx5_core_alloc_q_counter(dev->mdev,
3695                                                 &port->cnts.set_id);
3696                 if (ret) {
3697                         mlx5_ib_warn(dev,
3698                                      "couldn't allocate queue counter for port %d, err %d\n",
3699                                      i + 1, ret);
3700                         goto dealloc_counters;
3701                 }
3702
3703                 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
3704                 if (ret)
3705                         goto dealloc_counters;
3706
3707                 mlx5_ib_fill_counters(dev, port->cnts.names,
3708                                       port->cnts.offsets);
3709         }
3710
3711         return 0;
3712
3713 dealloc_counters:
3714         while (--i >= 0)
3715                 mlx5_core_dealloc_q_counter(dev->mdev,
3716                                             dev->port[i].cnts.set_id);
3717
3718         return ret;
3719 }
3720
3721 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3722                                                     u8 port_num)
3723 {
3724         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3725         struct mlx5_ib_port *port = &dev->port[port_num - 1];
3726
3727         /* We support only per port stats */
3728         if (port_num == 0)
3729                 return NULL;
3730
3731         return rdma_alloc_hw_stats_struct(port->cnts.names,
3732                                           port->cnts.num_q_counters +
3733                                           port->cnts.num_cong_counters,
3734                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
3735 }
3736
3737 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3738                                     struct mlx5_ib_port *port,
3739                                     struct rdma_hw_stats *stats)
3740 {
3741         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3742         void *out;
3743         __be32 val;
3744         int ret, i;
3745
3746         out = kvzalloc(outlen, GFP_KERNEL);
3747         if (!out)
3748                 return -ENOMEM;
3749
3750         ret = mlx5_core_query_q_counter(dev->mdev,
3751                                         port->cnts.set_id, 0,
3752                                         out, outlen);
3753         if (ret)
3754                 goto free;
3755
3756         for (i = 0; i < port->cnts.num_q_counters; i++) {
3757                 val = *(__be32 *)(out + port->cnts.offsets[i]);
3758                 stats->value[i] = (u64)be32_to_cpu(val);
3759         }
3760
3761 free:
3762         kvfree(out);
3763         return ret;
3764 }
3765
3766 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3767                                 struct rdma_hw_stats *stats,
3768                                 u8 port_num, int index)
3769 {
3770         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3771         struct mlx5_ib_port *port = &dev->port[port_num - 1];
3772         int ret, num_counters;
3773
3774         if (!stats)
3775                 return -EINVAL;
3776
3777         ret = mlx5_ib_query_q_counters(dev, port, stats);
3778         if (ret)
3779                 return ret;
3780         num_counters = port->cnts.num_q_counters;
3781
3782         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3783                 ret = mlx5_lag_query_cong_counters(dev->mdev,
3784                                                    stats->value +
3785                                                    port->cnts.num_q_counters,
3786                                                    port->cnts.num_cong_counters,
3787                                                    port->cnts.offsets +
3788                                                    port->cnts.num_q_counters);
3789                 if (ret)
3790                         return ret;
3791                 num_counters += port->cnts.num_cong_counters;
3792         }
3793
3794         return num_counters;
3795 }
3796
3797 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3798 {
3799         return mlx5_rdma_netdev_free(netdev);
3800 }
3801
3802 static struct net_device*
3803 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3804                           u8 port_num,
3805                           enum rdma_netdev_t type,
3806                           const char *name,
3807                           unsigned char name_assign_type,
3808                           void (*setup)(struct net_device *))
3809 {
3810         struct net_device *netdev;
3811         struct rdma_netdev *rn;
3812
3813         if (type != RDMA_NETDEV_IPOIB)
3814                 return ERR_PTR(-EOPNOTSUPP);
3815
3816         netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3817                                         name, setup);
3818         if (likely(!IS_ERR_OR_NULL(netdev))) {
3819                 rn = netdev_priv(netdev);
3820                 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3821         }
3822         return netdev;
3823 }
3824
3825 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
3826 {
3827         if (!dev->delay_drop.dbg)
3828                 return;
3829         debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
3830         kfree(dev->delay_drop.dbg);
3831         dev->delay_drop.dbg = NULL;
3832 }
3833
3834 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
3835 {
3836         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3837                 return;
3838
3839         cancel_work_sync(&dev->delay_drop.delay_drop_work);
3840         delay_drop_debugfs_cleanup(dev);
3841 }
3842
3843 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3844                                        size_t count, loff_t *pos)
3845 {
3846         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3847         char lbuf[20];
3848         int len;
3849
3850         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3851         return simple_read_from_buffer(buf, count, pos, lbuf, len);
3852 }
3853
3854 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3855                                         size_t count, loff_t *pos)
3856 {
3857         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3858         u32 timeout;
3859         u32 var;
3860
3861         if (kstrtouint_from_user(buf, count, 0, &var))
3862                 return -EFAULT;
3863
3864         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3865                         1000);
3866         if (timeout != var)
3867                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3868                             timeout);
3869
3870         delay_drop->timeout = timeout;
3871
3872         return count;
3873 }
3874
3875 static const struct file_operations fops_delay_drop_timeout = {
3876         .owner  = THIS_MODULE,
3877         .open   = simple_open,
3878         .write  = delay_drop_timeout_write,
3879         .read   = delay_drop_timeout_read,
3880 };
3881
3882 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
3883 {
3884         struct mlx5_ib_dbg_delay_drop *dbg;
3885
3886         if (!mlx5_debugfs_root)
3887                 return 0;
3888
3889         dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
3890         if (!dbg)
3891                 return -ENOMEM;
3892
3893         dev->delay_drop.dbg = dbg;
3894
3895         dbg->dir_debugfs =
3896                 debugfs_create_dir("delay_drop",
3897                                    dev->mdev->priv.dbg_root);
3898         if (!dbg->dir_debugfs)
3899                 goto out_debugfs;
3900
3901         dbg->events_cnt_debugfs =
3902                 debugfs_create_atomic_t("num_timeout_events", 0400,
3903                                         dbg->dir_debugfs,
3904                                         &dev->delay_drop.events_cnt);
3905         if (!dbg->events_cnt_debugfs)
3906                 goto out_debugfs;
3907
3908         dbg->rqs_cnt_debugfs =
3909                 debugfs_create_atomic_t("num_rqs", 0400,
3910                                         dbg->dir_debugfs,
3911                                         &dev->delay_drop.rqs_cnt);
3912         if (!dbg->rqs_cnt_debugfs)
3913                 goto out_debugfs;
3914
3915         dbg->timeout_debugfs =
3916                 debugfs_create_file("timeout", 0600,
3917                                     dbg->dir_debugfs,
3918                                     &dev->delay_drop,
3919                                     &fops_delay_drop_timeout);
3920         if (!dbg->timeout_debugfs)
3921                 goto out_debugfs;
3922
3923         return 0;
3924
3925 out_debugfs:
3926         delay_drop_debugfs_cleanup(dev);
3927         return -ENOMEM;
3928 }
3929
3930 static void init_delay_drop(struct mlx5_ib_dev *dev)
3931 {
3932         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3933                 return;
3934
3935         mutex_init(&dev->delay_drop.lock);
3936         dev->delay_drop.dev = dev;
3937         dev->delay_drop.activate = false;
3938         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
3939         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
3940         atomic_set(&dev->delay_drop.rqs_cnt, 0);
3941         atomic_set(&dev->delay_drop.events_cnt, 0);
3942
3943         if (delay_drop_debugfs_init(dev))
3944                 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
3945 }
3946
3947 static const struct cpumask *
3948 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
3949 {
3950         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3951
3952         return mlx5_get_vector_affinity(dev->mdev, comp_vector);
3953 }
3954
3955 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3956 {
3957         struct mlx5_ib_dev *dev;
3958         enum rdma_link_layer ll;
3959         int port_type_cap;
3960         const char *name;
3961         int err;
3962         int i;
3963
3964         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3965         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3966
3967         printk_once(KERN_INFO "%s", mlx5_version);
3968
3969         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3970         if (!dev)
3971                 return NULL;
3972
3973         dev->mdev = mdev;
3974
3975         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3976                             GFP_KERNEL);
3977         if (!dev->port)
3978                 goto err_dealloc;
3979
3980         rwlock_init(&dev->roce.netdev_lock);
3981         err = get_port_caps(dev);
3982         if (err)
3983                 goto err_free_port;
3984
3985         if (mlx5_use_mad_ifc(dev))
3986                 get_ext_port_caps(dev);
3987
3988         if (!mlx5_lag_is_active(mdev))
3989                 name = "mlx5_%d";
3990         else
3991                 name = "mlx5_bond_%d";
3992
3993         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3994         dev->ib_dev.owner               = THIS_MODULE;
3995         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
3996         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
3997         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
3998         dev->ib_dev.phys_port_cnt     = dev->num_ports;
3999         dev->ib_dev.num_comp_vectors    =
4000                 dev->mdev->priv.eq_table.num_comp_vectors;
4001         dev->ib_dev.dev.parent          = &mdev->pdev->dev;
4002
4003         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
4004         dev->ib_dev.uverbs_cmd_mask     =
4005                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
4006                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
4007                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
4008                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
4009                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
4010                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
4011                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
4012                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
4013                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
4014                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
4015                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
4016                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
4017                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
4018                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
4019                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
4020                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
4021                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
4022                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
4023                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
4024                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
4025                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
4026                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
4027                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
4028                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
4029                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
4030                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
4031         dev->ib_dev.uverbs_ex_cmd_mask =
4032                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
4033                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
4034                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
4035                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP)        |
4036                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
4037
4038         dev->ib_dev.query_device        = mlx5_ib_query_device;
4039         dev->ib_dev.query_port          = mlx5_ib_query_port;
4040         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
4041         if (ll == IB_LINK_LAYER_ETHERNET)
4042                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
4043         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
4044         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
4045         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
4046         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
4047         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
4048         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
4049         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
4050         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
4051         dev->ib_dev.mmap                = mlx5_ib_mmap;
4052         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
4053         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
4054         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
4055         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
4056         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
4057         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
4058         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
4059         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
4060         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
4061         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
4062         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
4063         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
4064         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
4065         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
4066         dev->ib_dev.post_send           = mlx5_ib_post_send;
4067         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
4068         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
4069         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
4070         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
4071         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
4072         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
4073         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
4074         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
4075         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
4076         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
4077         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
4078         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
4079         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
4080         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
4081         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
4082         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
4083         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
4084         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
4085         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
4086         dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
4087         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
4088                 dev->ib_dev.alloc_rdma_netdev   = mlx5_ib_alloc_rdma_netdev;
4089
4090         if (mlx5_core_is_pf(mdev)) {
4091                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
4092                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
4093                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
4094                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
4095         }
4096
4097         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4098
4099         mlx5_ib_internal_fill_odp_caps(dev);
4100
4101         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4102
4103         if (MLX5_CAP_GEN(mdev, imaicl)) {
4104                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
4105                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
4106                 dev->ib_dev.uverbs_cmd_mask |=
4107                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
4108                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4109         }
4110
4111         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4112                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
4113                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
4114         }
4115
4116         if (MLX5_CAP_GEN(mdev, xrc)) {
4117                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4118                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4119                 dev->ib_dev.uverbs_cmd_mask |=
4120                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4121                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4122         }
4123
4124         dev->ib_dev.create_flow = mlx5_ib_create_flow;
4125         dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4126         dev->ib_dev.uverbs_ex_cmd_mask |=
4127                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4128                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4129
4130         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
4131             IB_LINK_LAYER_ETHERNET) {
4132                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
4133                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
4134                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
4135                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4136                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
4137                 dev->ib_dev.uverbs_ex_cmd_mask |=
4138                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4139                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
4140                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4141                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4142                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
4143         }
4144         err = init_node_data(dev);
4145         if (err)
4146                 goto err_free_port;
4147
4148         mutex_init(&dev->flow_db.lock);
4149         mutex_init(&dev->cap_mask_mutex);
4150         INIT_LIST_HEAD(&dev->qp_list);
4151         spin_lock_init(&dev->reset_flow_resource_lock);
4152
4153         if (ll == IB_LINK_LAYER_ETHERNET) {
4154                 err = mlx5_enable_eth(dev);
4155                 if (err)
4156                         goto err_free_port;
4157                 dev->roce.last_port_state = IB_PORT_DOWN;
4158         }
4159
4160         err = create_dev_resources(&dev->devr);
4161         if (err)
4162                 goto err_disable_eth;
4163
4164         err = mlx5_ib_odp_init_one(dev);
4165         if (err)
4166                 goto err_rsrc;
4167
4168         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4169                 err = mlx5_ib_alloc_counters(dev);
4170                 if (err)
4171                         goto err_odp;
4172         }
4173
4174         err = mlx5_ib_init_cong_debugfs(dev);
4175         if (err)
4176                 goto err_cnt;
4177
4178         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4179         if (!dev->mdev->priv.uar)
4180                 goto err_cong;
4181
4182         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4183         if (err)
4184                 goto err_uar_page;
4185
4186         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4187         if (err)
4188                 goto err_bfreg;
4189
4190         err = ib_register_device(&dev->ib_dev, NULL);
4191         if (err)
4192                 goto err_fp_bfreg;
4193
4194         err = create_umr_res(dev);
4195         if (err)
4196                 goto err_dev;
4197
4198         init_delay_drop(dev);
4199
4200         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
4201                 err = device_create_file(&dev->ib_dev.dev,
4202                                          mlx5_class_attributes[i]);
4203                 if (err)
4204                         goto err_delay_drop;
4205         }
4206
4207         if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4208             MLX5_CAP_GEN(mdev, disable_local_lb))
4209                 mutex_init(&dev->lb_mutex);
4210
4211         dev->ib_active = true;
4212
4213         return dev;
4214
4215 err_delay_drop:
4216         cancel_delay_drop(dev);
4217         destroy_umrc_res(dev);
4218
4219 err_dev:
4220         ib_unregister_device(&dev->ib_dev);
4221
4222 err_fp_bfreg:
4223         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4224
4225 err_bfreg:
4226         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4227
4228 err_uar_page:
4229         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4230
4231 err_cong:
4232         mlx5_ib_cleanup_cong_debugfs(dev);
4233 err_cnt:
4234         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4235                 mlx5_ib_dealloc_counters(dev);
4236
4237 err_odp:
4238         mlx5_ib_odp_remove_one(dev);
4239
4240 err_rsrc:
4241         destroy_dev_resources(&dev->devr);
4242
4243 err_disable_eth:
4244         if (ll == IB_LINK_LAYER_ETHERNET) {
4245                 mlx5_disable_eth(dev);
4246                 mlx5_remove_netdev_notifier(dev);
4247         }
4248
4249 err_free_port:
4250         kfree(dev->port);
4251
4252 err_dealloc:
4253         ib_dealloc_device((struct ib_device *)dev);
4254
4255         return NULL;
4256 }
4257
4258 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
4259 {
4260         struct mlx5_ib_dev *dev = context;
4261         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
4262
4263         cancel_delay_drop(dev);
4264         mlx5_remove_netdev_notifier(dev);
4265         ib_unregister_device(&dev->ib_dev);
4266         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4267         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4268         mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
4269         mlx5_ib_cleanup_cong_debugfs(dev);
4270         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4271                 mlx5_ib_dealloc_counters(dev);
4272         destroy_umrc_res(dev);
4273         mlx5_ib_odp_remove_one(dev);
4274         destroy_dev_resources(&dev->devr);
4275         if (ll == IB_LINK_LAYER_ETHERNET)
4276                 mlx5_disable_eth(dev);
4277         kfree(dev->port);
4278         ib_dealloc_device(&dev->ib_dev);
4279 }
4280
4281 static struct mlx5_interface mlx5_ib_interface = {
4282         .add            = mlx5_ib_add,
4283         .remove         = mlx5_ib_remove,
4284         .event          = mlx5_ib_event,
4285 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4286         .pfault         = mlx5_ib_pfault,
4287 #endif
4288         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
4289 };
4290
4291 static int __init mlx5_ib_init(void)
4292 {
4293         int err;
4294
4295         mlx5_ib_odp_init();
4296
4297         err = mlx5_register_interface(&mlx5_ib_interface);
4298
4299         return err;
4300 }
4301
4302 static void __exit mlx5_ib_cleanup(void)
4303 {
4304         mlx5_unregister_interface(&mlx5_ib_interface);
4305 }
4306
4307 module_init(mlx5_ib_init);
4308 module_exit(mlx5_ib_cleanup);