2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/debugfs.h>
34 #include <linux/highmem.h>
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #if defined(CONFIG_X86)
44 #include <linux/sched.h>
45 #include <linux/sched/mm.h>
46 #include <linux/sched/task.h>
47 #include <linux/delay.h>
48 #include <rdma/ib_user_verbs.h>
49 #include <rdma/ib_addr.h>
50 #include <rdma/ib_cache.h>
51 #include <linux/mlx5/port.h>
52 #include <linux/mlx5/vport.h>
53 #include <linux/mlx5/fs.h>
54 #include <linux/list.h>
55 #include <rdma/ib_smi.h>
56 #include <rdma/ib_umem.h>
58 #include <linux/etherdevice.h>
62 #define DRIVER_NAME "mlx5_ib"
63 #define DRIVER_VERSION "5.0-0"
65 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
66 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
67 MODULE_LICENSE("Dual BSD/GPL");
69 static char mlx5_version[] =
70 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
73 struct mlx5_ib_event_work {
74 struct work_struct work;
75 struct mlx5_core_dev *dev;
77 enum mlx5_dev_event event;
82 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
85 static struct workqueue_struct *mlx5_ib_event_wq;
86 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
87 static LIST_HEAD(mlx5_ib_dev_list);
89 * This mutex should be held when accessing either of the above lists
91 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
93 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
95 struct mlx5_ib_dev *dev;
97 mutex_lock(&mlx5_ib_multiport_mutex);
99 mutex_unlock(&mlx5_ib_multiport_mutex);
103 static enum rdma_link_layer
104 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
106 switch (port_type_cap) {
107 case MLX5_CAP_PORT_TYPE_IB:
108 return IB_LINK_LAYER_INFINIBAND;
109 case MLX5_CAP_PORT_TYPE_ETH:
110 return IB_LINK_LAYER_ETHERNET;
112 return IB_LINK_LAYER_UNSPECIFIED;
116 static enum rdma_link_layer
117 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
119 struct mlx5_ib_dev *dev = to_mdev(device);
120 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
122 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
125 static int get_port_state(struct ib_device *ibdev,
127 enum ib_port_state *state)
129 struct ib_port_attr attr;
132 memset(&attr, 0, sizeof(attr));
133 ret = mlx5_ib_query_port(ibdev, port_num, &attr);
139 static int mlx5_netdev_event(struct notifier_block *this,
140 unsigned long event, void *ptr)
142 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
143 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
144 u8 port_num = roce->native_port_num;
145 struct mlx5_core_dev *mdev;
146 struct mlx5_ib_dev *ibdev;
149 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
154 case NETDEV_REGISTER:
155 case NETDEV_UNREGISTER:
156 write_lock(&roce->netdev_lock);
158 if (ndev->dev.parent == &mdev->pdev->dev)
159 roce->netdev = (event == NETDEV_UNREGISTER) ?
161 write_unlock(&roce->netdev_lock);
167 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
168 struct net_device *upper = NULL;
171 upper = netdev_master_upper_dev_get(lag_ndev);
175 if ((upper == ndev || (!upper && ndev == roce->netdev))
176 && ibdev->ib_active) {
177 struct ib_event ibev = { };
178 enum ib_port_state port_state;
180 if (get_port_state(&ibdev->ib_dev, port_num,
184 if (roce->last_port_state == port_state)
187 roce->last_port_state = port_state;
188 ibev.device = &ibdev->ib_dev;
189 if (port_state == IB_PORT_DOWN)
190 ibev.event = IB_EVENT_PORT_ERR;
191 else if (port_state == IB_PORT_ACTIVE)
192 ibev.event = IB_EVENT_PORT_ACTIVE;
196 ibev.element.port_num = port_num;
197 ib_dispatch_event(&ibev);
206 mlx5_ib_put_native_port_mdev(ibdev, port_num);
210 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
213 struct mlx5_ib_dev *ibdev = to_mdev(device);
214 struct net_device *ndev;
215 struct mlx5_core_dev *mdev;
217 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
221 ndev = mlx5_lag_get_roce_netdev(mdev);
225 /* Ensure ndev does not disappear before we invoke dev_hold()
227 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
228 ndev = ibdev->roce[port_num - 1].netdev;
231 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
234 mlx5_ib_put_native_port_mdev(ibdev, port_num);
238 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
242 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
244 struct mlx5_core_dev *mdev = NULL;
245 struct mlx5_ib_multiport_info *mpi;
246 struct mlx5_ib_port *port;
248 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
249 ll != IB_LINK_LAYER_ETHERNET) {
251 *native_port_num = ib_port_num;
256 *native_port_num = 1;
258 port = &ibdev->port[ib_port_num - 1];
262 spin_lock(&port->mp.mpi_lock);
263 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
264 if (mpi && !mpi->unaffiliate) {
266 /* If it's the master no need to refcount, it'll exist
267 * as long as the ib_dev exists.
272 spin_unlock(&port->mp.mpi_lock);
277 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
279 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
281 struct mlx5_ib_multiport_info *mpi;
282 struct mlx5_ib_port *port;
284 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
287 port = &ibdev->port[port_num - 1];
289 spin_lock(&port->mp.mpi_lock);
290 mpi = ibdev->port[port_num - 1].mp.mpi;
295 if (mpi->unaffiliate)
296 complete(&mpi->unref_comp);
298 spin_unlock(&port->mp.mpi_lock);
301 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
304 switch (eth_proto_oper) {
305 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
306 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
307 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
308 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
309 *active_width = IB_WIDTH_1X;
310 *active_speed = IB_SPEED_SDR;
312 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
313 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
314 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
315 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
316 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
317 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
318 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
319 *active_width = IB_WIDTH_1X;
320 *active_speed = IB_SPEED_QDR;
322 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
323 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
324 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
325 *active_width = IB_WIDTH_1X;
326 *active_speed = IB_SPEED_EDR;
328 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
329 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
330 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
331 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
332 *active_width = IB_WIDTH_4X;
333 *active_speed = IB_SPEED_QDR;
335 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
336 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
337 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
338 *active_width = IB_WIDTH_1X;
339 *active_speed = IB_SPEED_HDR;
341 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
342 *active_width = IB_WIDTH_4X;
343 *active_speed = IB_SPEED_FDR;
345 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
346 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
347 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
348 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
349 *active_width = IB_WIDTH_4X;
350 *active_speed = IB_SPEED_EDR;
359 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
360 struct ib_port_attr *props)
362 struct mlx5_ib_dev *dev = to_mdev(device);
363 struct mlx5_core_dev *mdev;
364 struct net_device *ndev, *upper;
365 enum ib_mtu ndev_ib_mtu;
366 bool put_mdev = true;
372 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
374 /* This means the port isn't affiliated yet. Get the
375 * info for the master port instead.
383 /* Possible bad flows are checked before filling out props so in case
384 * of an error it will still be zeroed out.
386 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper,
391 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
392 &props->active_width);
394 props->port_cap_flags |= IB_PORT_CM_SUP;
395 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
397 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
398 roce_address_table_size);
399 props->max_mtu = IB_MTU_4096;
400 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
401 props->pkey_tbl_len = 1;
402 props->state = IB_PORT_DOWN;
403 props->phys_state = 3;
405 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
406 props->qkey_viol_cntr = qkey_viol_cntr;
408 /* If this is a stub query for an unaffiliated port stop here */
412 ndev = mlx5_ib_get_netdev(device, port_num);
416 if (mlx5_lag_is_active(dev->mdev)) {
418 upper = netdev_master_upper_dev_get_rcu(ndev);
427 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
428 props->state = IB_PORT_ACTIVE;
429 props->phys_state = 5;
432 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
436 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
439 mlx5_ib_put_native_port_mdev(dev, port_num);
443 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
444 unsigned int index, const union ib_gid *gid,
445 const struct ib_gid_attr *attr)
447 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
455 gid_type = attr->gid_type;
456 ether_addr_copy(mac, attr->ndev->dev_addr);
458 if (is_vlan_dev(attr->ndev)) {
460 vlan_id = vlan_dev_vlan_id(attr->ndev);
466 roce_version = MLX5_ROCE_VERSION_1;
468 case IB_GID_TYPE_ROCE_UDP_ENCAP:
469 roce_version = MLX5_ROCE_VERSION_2;
470 if (ipv6_addr_v4mapped((void *)gid))
471 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
473 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
477 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
480 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
481 roce_l3_type, gid->raw, mac, vlan,
485 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
486 unsigned int index, const union ib_gid *gid,
487 const struct ib_gid_attr *attr,
488 __always_unused void **context)
490 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
493 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
494 unsigned int index, __always_unused void **context)
496 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
499 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
502 struct ib_gid_attr attr;
505 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
513 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
516 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
519 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
520 int index, enum ib_gid_type *gid_type)
522 struct ib_gid_attr attr;
526 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
535 *gid_type = attr.gid_type;
540 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
542 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
543 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
548 MLX5_VPORT_ACCESS_METHOD_MAD,
549 MLX5_VPORT_ACCESS_METHOD_HCA,
550 MLX5_VPORT_ACCESS_METHOD_NIC,
553 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
555 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
556 return MLX5_VPORT_ACCESS_METHOD_MAD;
558 if (mlx5_ib_port_link_layer(ibdev, 1) ==
559 IB_LINK_LAYER_ETHERNET)
560 return MLX5_VPORT_ACCESS_METHOD_NIC;
562 return MLX5_VPORT_ACCESS_METHOD_HCA;
565 static void get_atomic_caps(struct mlx5_ib_dev *dev,
567 struct ib_device_attr *props)
570 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
571 u8 atomic_req_8B_endianness_mode =
572 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
574 /* Check if HW supports 8 bytes standard atomic operations and capable
575 * of host endianness respond
577 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
578 if (((atomic_operations & tmp) == tmp) &&
579 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
580 (atomic_req_8B_endianness_mode)) {
581 props->atomic_cap = IB_ATOMIC_HCA;
583 props->atomic_cap = IB_ATOMIC_NONE;
587 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
588 struct ib_device_attr *props)
590 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
592 get_atomic_caps(dev, atomic_size_qp, props);
595 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
596 struct ib_device_attr *props)
598 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
600 get_atomic_caps(dev, atomic_size_qp, props);
603 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
605 struct ib_device_attr props = {};
607 get_atomic_caps_dc(dev, &props);
608 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
610 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
611 __be64 *sys_image_guid)
613 struct mlx5_ib_dev *dev = to_mdev(ibdev);
614 struct mlx5_core_dev *mdev = dev->mdev;
618 switch (mlx5_get_vport_access_method(ibdev)) {
619 case MLX5_VPORT_ACCESS_METHOD_MAD:
620 return mlx5_query_mad_ifc_system_image_guid(ibdev,
623 case MLX5_VPORT_ACCESS_METHOD_HCA:
624 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
627 case MLX5_VPORT_ACCESS_METHOD_NIC:
628 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
636 *sys_image_guid = cpu_to_be64(tmp);
642 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
645 struct mlx5_ib_dev *dev = to_mdev(ibdev);
646 struct mlx5_core_dev *mdev = dev->mdev;
648 switch (mlx5_get_vport_access_method(ibdev)) {
649 case MLX5_VPORT_ACCESS_METHOD_MAD:
650 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
652 case MLX5_VPORT_ACCESS_METHOD_HCA:
653 case MLX5_VPORT_ACCESS_METHOD_NIC:
654 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
663 static int mlx5_query_vendor_id(struct ib_device *ibdev,
666 struct mlx5_ib_dev *dev = to_mdev(ibdev);
668 switch (mlx5_get_vport_access_method(ibdev)) {
669 case MLX5_VPORT_ACCESS_METHOD_MAD:
670 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
672 case MLX5_VPORT_ACCESS_METHOD_HCA:
673 case MLX5_VPORT_ACCESS_METHOD_NIC:
674 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
681 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
687 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
688 case MLX5_VPORT_ACCESS_METHOD_MAD:
689 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
691 case MLX5_VPORT_ACCESS_METHOD_HCA:
692 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
695 case MLX5_VPORT_ACCESS_METHOD_NIC:
696 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
704 *node_guid = cpu_to_be64(tmp);
709 struct mlx5_reg_node_desc {
710 u8 desc[IB_DEVICE_NODE_DESC_MAX];
713 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
715 struct mlx5_reg_node_desc in;
717 if (mlx5_use_mad_ifc(dev))
718 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
720 memset(&in, 0, sizeof(in));
722 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
723 sizeof(struct mlx5_reg_node_desc),
724 MLX5_REG_NODE_DESC, 0, 0);
727 static int mlx5_ib_query_device(struct ib_device *ibdev,
728 struct ib_device_attr *props,
729 struct ib_udata *uhw)
731 struct mlx5_ib_dev *dev = to_mdev(ibdev);
732 struct mlx5_core_dev *mdev = dev->mdev;
737 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
738 bool raw_support = !mlx5_core_mp_enabled(mdev);
739 struct mlx5_ib_query_device_resp resp = {};
743 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
744 if (uhw->outlen && uhw->outlen < resp_len)
747 resp.response_length = resp_len;
749 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
752 memset(props, 0, sizeof(*props));
753 err = mlx5_query_system_image_guid(ibdev,
754 &props->sys_image_guid);
758 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
762 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
766 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
767 (fw_rev_min(dev->mdev) << 16) |
768 fw_rev_sub(dev->mdev);
769 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
770 IB_DEVICE_PORT_ACTIVE_EVENT |
771 IB_DEVICE_SYS_IMAGE_GUID |
772 IB_DEVICE_RC_RNR_NAK_GEN;
774 if (MLX5_CAP_GEN(mdev, pkv))
775 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
776 if (MLX5_CAP_GEN(mdev, qkv))
777 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
778 if (MLX5_CAP_GEN(mdev, apm))
779 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
780 if (MLX5_CAP_GEN(mdev, xrc))
781 props->device_cap_flags |= IB_DEVICE_XRC;
782 if (MLX5_CAP_GEN(mdev, imaicl)) {
783 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
784 IB_DEVICE_MEM_WINDOW_TYPE_2B;
785 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
786 /* We support 'Gappy' memory registration too */
787 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
789 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
790 if (MLX5_CAP_GEN(mdev, sho)) {
791 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
792 /* At this stage no support for signature handover */
793 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
794 IB_PROT_T10DIF_TYPE_2 |
795 IB_PROT_T10DIF_TYPE_3;
796 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
797 IB_GUARD_T10DIF_CSUM;
799 if (MLX5_CAP_GEN(mdev, block_lb_mc))
800 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
802 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
803 if (MLX5_CAP_ETH(mdev, csum_cap)) {
804 /* Legacy bit to support old userspace libraries */
805 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
806 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
809 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
810 props->raw_packet_caps |=
811 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
813 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
814 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
816 resp.tso_caps.max_tso = 1 << max_tso;
817 resp.tso_caps.supported_qpts |=
818 1 << IB_QPT_RAW_PACKET;
819 resp.response_length += sizeof(resp.tso_caps);
823 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
824 resp.rss_caps.rx_hash_function =
825 MLX5_RX_HASH_FUNC_TOEPLITZ;
826 resp.rss_caps.rx_hash_fields_mask =
827 MLX5_RX_HASH_SRC_IPV4 |
828 MLX5_RX_HASH_DST_IPV4 |
829 MLX5_RX_HASH_SRC_IPV6 |
830 MLX5_RX_HASH_DST_IPV6 |
831 MLX5_RX_HASH_SRC_PORT_TCP |
832 MLX5_RX_HASH_DST_PORT_TCP |
833 MLX5_RX_HASH_SRC_PORT_UDP |
834 MLX5_RX_HASH_DST_PORT_UDP |
836 resp.response_length += sizeof(resp.rss_caps);
839 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
840 resp.response_length += sizeof(resp.tso_caps);
841 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
842 resp.response_length += sizeof(resp.rss_caps);
845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
847 props->device_cap_flags |= IB_DEVICE_UD_TSO;
850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
851 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
862 /* Legacy bit to support old userspace libraries */
863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
867 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
868 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
870 if (MLX5_CAP_GEN(mdev, end_pad))
871 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
873 props->vendor_part_id = mdev->pdev->device;
874 props->hw_ver = mdev->pdev->revision;
876 props->max_mr_size = ~0ull;
877 props->page_size_cap = ~(min_page_size - 1);
878 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
879 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
880 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
881 sizeof(struct mlx5_wqe_data_seg);
882 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
883 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
884 sizeof(struct mlx5_wqe_raddr_seg)) /
885 sizeof(struct mlx5_wqe_data_seg);
886 props->max_sge = min(max_rq_sg, max_sq_sg);
887 props->max_sge_rd = MLX5_MAX_SGE_RD;
888 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
889 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
890 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
891 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
892 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
893 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
894 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
895 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
896 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
897 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
898 props->max_srq_sge = max_rq_sg - 1;
899 props->max_fast_reg_page_list_len =
900 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
901 get_atomic_caps_qp(dev, props);
902 props->masked_atomic_cap = IB_ATOMIC_NONE;
903 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
904 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
905 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
906 props->max_mcast_grp;
907 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
908 props->max_ah = INT_MAX;
909 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
910 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
912 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
913 if (MLX5_CAP_GEN(mdev, pg))
914 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
915 props->odp_caps = dev->odp_caps;
918 if (MLX5_CAP_GEN(mdev, cd))
919 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
921 if (!mlx5_core_is_pf(mdev))
922 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
924 if (mlx5_ib_port_link_layer(ibdev, 1) ==
925 IB_LINK_LAYER_ETHERNET && raw_support) {
926 props->rss_caps.max_rwq_indirection_tables =
927 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
928 props->rss_caps.max_rwq_indirection_table_size =
929 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
930 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
931 props->max_wq_type_rq =
932 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
935 if (MLX5_CAP_GEN(mdev, tag_matching)) {
936 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
937 props->tm_caps.max_num_tags =
938 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
939 props->tm_caps.flags = IB_TM_CAP_RC;
940 props->tm_caps.max_ops =
941 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
942 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
945 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
946 props->cq_caps.max_cq_moderation_count =
948 props->cq_caps.max_cq_moderation_period =
952 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
953 resp.cqe_comp_caps.max_num =
954 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
955 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
956 resp.cqe_comp_caps.supported_format =
957 MLX5_IB_CQE_RES_FORMAT_HASH |
958 MLX5_IB_CQE_RES_FORMAT_CSUM;
959 resp.response_length += sizeof(resp.cqe_comp_caps);
962 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
964 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
965 MLX5_CAP_GEN(mdev, qos)) {
966 resp.packet_pacing_caps.qp_rate_limit_max =
967 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
968 resp.packet_pacing_caps.qp_rate_limit_min =
969 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
970 resp.packet_pacing_caps.supported_qpts |=
971 1 << IB_QPT_RAW_PACKET;
973 resp.response_length += sizeof(resp.packet_pacing_caps);
976 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
978 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
979 resp.mlx5_ib_support_multi_pkt_send_wqes =
982 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
983 resp.mlx5_ib_support_multi_pkt_send_wqes |=
984 MLX5_IB_SUPPORT_EMPW;
986 resp.response_length +=
987 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
990 if (field_avail(typeof(resp), flags, uhw->outlen)) {
991 resp.response_length += sizeof(resp.flags);
993 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
995 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
997 if (MLX5_CAP_GEN(mdev, cqe_128_always))
998 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1001 if (field_avail(typeof(resp), sw_parsing_caps,
1003 resp.response_length += sizeof(resp.sw_parsing_caps);
1004 if (MLX5_CAP_ETH(mdev, swp)) {
1005 resp.sw_parsing_caps.sw_parsing_offloads |=
1008 if (MLX5_CAP_ETH(mdev, swp_csum))
1009 resp.sw_parsing_caps.sw_parsing_offloads |=
1010 MLX5_IB_SW_PARSING_CSUM;
1012 if (MLX5_CAP_ETH(mdev, swp_lso))
1013 resp.sw_parsing_caps.sw_parsing_offloads |=
1014 MLX5_IB_SW_PARSING_LSO;
1016 if (resp.sw_parsing_caps.sw_parsing_offloads)
1017 resp.sw_parsing_caps.supported_qpts =
1018 BIT(IB_QPT_RAW_PACKET);
1022 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1024 resp.response_length += sizeof(resp.striding_rq_caps);
1025 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1026 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1027 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1028 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1029 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1030 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1031 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1032 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1033 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1034 resp.striding_rq_caps.supported_qpts =
1035 BIT(IB_QPT_RAW_PACKET);
1039 if (field_avail(typeof(resp), tunnel_offloads_caps,
1041 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1042 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1043 resp.tunnel_offloads_caps |=
1044 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1045 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1046 resp.tunnel_offloads_caps |=
1047 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1048 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1049 resp.tunnel_offloads_caps |=
1050 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1054 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1063 enum mlx5_ib_width {
1064 MLX5_IB_WIDTH_1X = 1 << 0,
1065 MLX5_IB_WIDTH_2X = 1 << 1,
1066 MLX5_IB_WIDTH_4X = 1 << 2,
1067 MLX5_IB_WIDTH_8X = 1 << 3,
1068 MLX5_IB_WIDTH_12X = 1 << 4
1071 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1074 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1077 if (active_width & MLX5_IB_WIDTH_1X) {
1078 *ib_width = IB_WIDTH_1X;
1079 } else if (active_width & MLX5_IB_WIDTH_2X) {
1080 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1083 } else if (active_width & MLX5_IB_WIDTH_4X) {
1084 *ib_width = IB_WIDTH_4X;
1085 } else if (active_width & MLX5_IB_WIDTH_8X) {
1086 *ib_width = IB_WIDTH_8X;
1087 } else if (active_width & MLX5_IB_WIDTH_12X) {
1088 *ib_width = IB_WIDTH_12X;
1090 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1098 static int mlx5_mtu_to_ib_mtu(int mtu)
1103 case 1024: return 3;
1104 case 2048: return 4;
1105 case 4096: return 5;
1107 pr_warn("invalid mtu\n");
1112 enum ib_max_vl_num {
1114 __IB_MAX_VL_0_1 = 2,
1115 __IB_MAX_VL_0_3 = 3,
1116 __IB_MAX_VL_0_7 = 4,
1117 __IB_MAX_VL_0_14 = 5,
1120 enum mlx5_vl_hw_cap {
1129 MLX5_VL_HW_0_14 = 15
1132 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1135 switch (vl_hw_cap) {
1137 *max_vl_num = __IB_MAX_VL_0;
1139 case MLX5_VL_HW_0_1:
1140 *max_vl_num = __IB_MAX_VL_0_1;
1142 case MLX5_VL_HW_0_3:
1143 *max_vl_num = __IB_MAX_VL_0_3;
1145 case MLX5_VL_HW_0_7:
1146 *max_vl_num = __IB_MAX_VL_0_7;
1148 case MLX5_VL_HW_0_14:
1149 *max_vl_num = __IB_MAX_VL_0_14;
1159 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1160 struct ib_port_attr *props)
1162 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1163 struct mlx5_core_dev *mdev = dev->mdev;
1164 struct mlx5_hca_vport_context *rep;
1168 u8 ib_link_width_oper;
1171 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1177 /* props being zeroed by the caller, avoid zeroing it here */
1179 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1183 props->lid = rep->lid;
1184 props->lmc = rep->lmc;
1185 props->sm_lid = rep->sm_lid;
1186 props->sm_sl = rep->sm_sl;
1187 props->state = rep->vport_state;
1188 props->phys_state = rep->port_physical_state;
1189 props->port_cap_flags = rep->cap_mask1;
1190 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1191 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1192 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1193 props->bad_pkey_cntr = rep->pkey_violation_counter;
1194 props->qkey_viol_cntr = rep->qkey_violation_counter;
1195 props->subnet_timeout = rep->subnet_timeout;
1196 props->init_type_reply = rep->init_type_reply;
1197 props->grh_required = rep->grh_required;
1199 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1203 err = translate_active_width(ibdev, ib_link_width_oper,
1204 &props->active_width);
1207 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1211 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1213 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1215 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1217 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1219 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1223 err = translate_max_vl_num(ibdev, vl_hw_cap,
1224 &props->max_vl_num);
1230 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1231 struct ib_port_attr *props)
1236 switch (mlx5_get_vport_access_method(ibdev)) {
1237 case MLX5_VPORT_ACCESS_METHOD_MAD:
1238 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1241 case MLX5_VPORT_ACCESS_METHOD_HCA:
1242 ret = mlx5_query_hca_port(ibdev, port, props);
1245 case MLX5_VPORT_ACCESS_METHOD_NIC:
1246 ret = mlx5_query_port_roce(ibdev, port, props);
1253 if (!ret && props) {
1254 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1255 struct mlx5_core_dev *mdev;
1256 bool put_mdev = true;
1258 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1260 /* If the port isn't affiliated yet query the master.
1261 * The master and slave will have the same values.
1267 count = mlx5_core_reserved_gids_count(mdev);
1269 mlx5_ib_put_native_port_mdev(dev, port);
1270 props->gid_tbl_len -= count;
1275 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1278 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1279 struct mlx5_core_dev *mdev = dev->mdev;
1281 switch (mlx5_get_vport_access_method(ibdev)) {
1282 case MLX5_VPORT_ACCESS_METHOD_MAD:
1283 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1285 case MLX5_VPORT_ACCESS_METHOD_HCA:
1286 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1294 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1295 u16 index, u16 *pkey)
1297 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1298 struct mlx5_core_dev *mdev;
1299 bool put_mdev = true;
1303 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1305 /* The port isn't affiliated yet, get the PKey from the master
1306 * port. For RoCE the PKey tables will be the same.
1313 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1316 mlx5_ib_put_native_port_mdev(dev, port);
1321 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1324 switch (mlx5_get_vport_access_method(ibdev)) {
1325 case MLX5_VPORT_ACCESS_METHOD_MAD:
1326 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1328 case MLX5_VPORT_ACCESS_METHOD_HCA:
1329 case MLX5_VPORT_ACCESS_METHOD_NIC:
1330 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1336 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1337 struct ib_device_modify *props)
1339 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1340 struct mlx5_reg_node_desc in;
1341 struct mlx5_reg_node_desc out;
1344 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1347 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1351 * If possible, pass node desc to FW, so it can generate
1352 * a 144 trap. If cmd fails, just ignore.
1354 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1355 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1356 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1360 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1365 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1368 struct mlx5_hca_vport_context ctx = {};
1369 struct mlx5_core_dev *mdev;
1373 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1377 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1381 if (~ctx.cap_mask1_perm & mask) {
1382 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1383 mask, ctx.cap_mask1_perm);
1388 ctx.cap_mask1 = value;
1389 ctx.cap_mask1_perm = mask;
1390 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1394 mlx5_ib_put_native_port_mdev(dev, port_num);
1399 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1400 struct ib_port_modify *props)
1402 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1403 struct ib_port_attr attr;
1408 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1409 IB_LINK_LAYER_INFINIBAND);
1411 /* CM layer calls ib_modify_port() regardless of the link layer. For
1412 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1417 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1418 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1419 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1420 return set_port_caps_atomic(dev, port, change_mask, value);
1423 mutex_lock(&dev->cap_mask_mutex);
1425 err = ib_query_port(ibdev, port, &attr);
1429 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1430 ~props->clr_port_cap_mask;
1432 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1435 mutex_unlock(&dev->cap_mask_mutex);
1439 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1441 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1442 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1445 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1447 /* Large page with non 4k uar support might limit the dynamic size */
1448 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1449 return MLX5_MIN_DYN_BFREGS;
1451 return MLX5_MAX_DYN_BFREGS;
1454 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1455 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1456 struct mlx5_bfreg_info *bfregi)
1458 int uars_per_sys_page;
1459 int bfregs_per_sys_page;
1460 int ref_bfregs = req->total_num_bfregs;
1462 if (req->total_num_bfregs == 0)
1465 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1466 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1468 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1471 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1472 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1473 /* This holds the required static allocation asked by the user */
1474 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1475 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1478 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1479 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1480 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1481 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1483 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1484 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1485 lib_uar_4k ? "yes" : "no", ref_bfregs,
1486 req->total_num_bfregs, bfregi->total_num_bfregs,
1487 bfregi->num_sys_pages);
1492 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1494 struct mlx5_bfreg_info *bfregi;
1498 bfregi = &context->bfregi;
1499 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1500 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1504 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1507 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1508 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1513 for (--i; i >= 0; i--)
1514 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1515 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1520 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1522 struct mlx5_bfreg_info *bfregi;
1526 bfregi = &context->bfregi;
1527 for (i = 0; i < bfregi->num_sys_pages; i++) {
1528 if (i < bfregi->num_static_sys_pages ||
1529 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1530 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1532 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1541 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1545 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1549 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1550 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1551 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1554 mutex_lock(&dev->lb_mutex);
1557 if (dev->user_td == 2)
1558 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1560 mutex_unlock(&dev->lb_mutex);
1564 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1566 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1568 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1569 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1570 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1573 mutex_lock(&dev->lb_mutex);
1576 if (dev->user_td < 2)
1577 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1579 mutex_unlock(&dev->lb_mutex);
1582 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1583 struct ib_udata *udata)
1585 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1586 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1587 struct mlx5_ib_alloc_ucontext_resp resp = {};
1588 struct mlx5_core_dev *mdev = dev->mdev;
1589 struct mlx5_ib_ucontext *context;
1590 struct mlx5_bfreg_info *bfregi;
1593 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1597 if (!dev->ib_active)
1598 return ERR_PTR(-EAGAIN);
1600 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1602 else if (udata->inlen >= min_req_v2)
1605 return ERR_PTR(-EINVAL);
1607 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1609 return ERR_PTR(err);
1612 return ERR_PTR(-EINVAL);
1614 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1615 return ERR_PTR(-EOPNOTSUPP);
1617 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1618 MLX5_NON_FP_BFREGS_PER_UAR);
1619 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1620 return ERR_PTR(-EINVAL);
1622 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1623 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1624 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1625 resp.cache_line_size = cache_line_size();
1626 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1627 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1628 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1629 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1630 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1631 resp.cqe_version = min_t(__u8,
1632 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1633 req.max_cqe_version);
1634 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1635 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1636 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1637 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1638 resp.response_length = min(offsetof(typeof(resp), response_length) +
1639 sizeof(resp.response_length), udata->outlen);
1641 context = kzalloc(sizeof(*context), GFP_KERNEL);
1643 return ERR_PTR(-ENOMEM);
1645 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1646 bfregi = &context->bfregi;
1648 /* updates req->total_num_bfregs */
1649 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1653 mutex_init(&bfregi->lock);
1654 bfregi->lib_uar_4k = lib_uar_4k;
1655 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1657 if (!bfregi->count) {
1662 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1663 sizeof(*bfregi->sys_pages),
1665 if (!bfregi->sys_pages) {
1670 err = allocate_uars(dev, context);
1674 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1675 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1678 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1679 if (!context->upd_xlt_page) {
1683 mutex_init(&context->upd_xlt_page_mutex);
1685 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1686 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1691 INIT_LIST_HEAD(&context->vma_private_list);
1692 mutex_init(&context->vma_private_list_mutex);
1693 INIT_LIST_HEAD(&context->db_page_list);
1694 mutex_init(&context->db_page_mutex);
1696 resp.tot_bfregs = req.total_num_bfregs;
1697 resp.num_ports = dev->num_ports;
1699 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1700 resp.response_length += sizeof(resp.cqe_version);
1702 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1703 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1704 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1705 resp.response_length += sizeof(resp.cmds_supp_uhw);
1708 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1709 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1710 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1711 resp.eth_min_inline++;
1713 resp.response_length += sizeof(resp.eth_min_inline);
1716 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1717 if (mdev->clock_info)
1718 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1719 resp.response_length += sizeof(resp.clock_info_versions);
1723 * We don't want to expose information from the PCI bar that is located
1724 * after 4096 bytes, so if the arch only supports larger pages, let's
1725 * pretend we don't support reading the HCA's core clock. This is also
1726 * forced by mmap function.
1728 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1729 if (PAGE_SIZE <= 4096) {
1731 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1732 resp.hca_core_clock_offset =
1733 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1735 resp.response_length += sizeof(resp.hca_core_clock_offset);
1738 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1739 resp.response_length += sizeof(resp.log_uar_size);
1741 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1742 resp.response_length += sizeof(resp.num_uars_per_page);
1744 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1745 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1746 resp.response_length += sizeof(resp.num_dyn_bfregs);
1749 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1754 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1755 context->cqe_version = resp.cqe_version;
1756 context->lib_caps = req.lib_caps;
1757 print_lib_caps(dev, context->lib_caps);
1759 return &context->ibucontext;
1762 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1763 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1766 free_page(context->upd_xlt_page);
1769 deallocate_uars(dev, context);
1772 kfree(bfregi->sys_pages);
1775 kfree(bfregi->count);
1780 return ERR_PTR(err);
1783 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1785 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1786 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1787 struct mlx5_bfreg_info *bfregi;
1789 bfregi = &context->bfregi;
1790 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1791 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1793 free_page(context->upd_xlt_page);
1794 deallocate_uars(dev, context);
1795 kfree(bfregi->sys_pages);
1796 kfree(bfregi->count);
1802 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1805 int fw_uars_per_page;
1807 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1809 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1812 static int get_command(unsigned long offset)
1814 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1817 static int get_arg(unsigned long offset)
1819 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1822 static int get_index(unsigned long offset)
1824 return get_arg(offset);
1827 /* Index resides in an extra byte to enable larger values than 255 */
1828 static int get_extended_index(unsigned long offset)
1830 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1833 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1835 /* vma_open is called when a new VMA is created on top of our VMA. This
1836 * is done through either mremap flow or split_vma (usually due to
1837 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1838 * as this VMA is strongly hardware related. Therefore we set the
1839 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1840 * calling us again and trying to do incorrect actions. We assume that
1841 * the original VMA size is exactly a single page, and therefore all
1842 * "splitting" operation will not happen to it.
1844 area->vm_ops = NULL;
1847 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1849 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1851 /* It's guaranteed that all VMAs opened on a FD are closed before the
1852 * file itself is closed, therefore no sync is needed with the regular
1853 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1854 * However need a sync with accessing the vma as part of
1855 * mlx5_ib_disassociate_ucontext.
1856 * The close operation is usually called under mm->mmap_sem except when
1857 * process is exiting.
1858 * The exiting case is handled explicitly as part of
1859 * mlx5_ib_disassociate_ucontext.
1861 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1863 /* setting the vma context pointer to null in the mlx5_ib driver's
1864 * private data, to protect a race condition in
1865 * mlx5_ib_disassociate_ucontext().
1867 mlx5_ib_vma_priv_data->vma = NULL;
1868 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1869 list_del(&mlx5_ib_vma_priv_data->list);
1870 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1871 kfree(mlx5_ib_vma_priv_data);
1874 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1875 .open = mlx5_ib_vma_open,
1876 .close = mlx5_ib_vma_close
1879 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1880 struct mlx5_ib_ucontext *ctx)
1882 struct mlx5_ib_vma_private_data *vma_prv;
1883 struct list_head *vma_head = &ctx->vma_private_list;
1885 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1890 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1891 vma->vm_private_data = vma_prv;
1892 vma->vm_ops = &mlx5_ib_vm_ops;
1894 mutex_lock(&ctx->vma_private_list_mutex);
1895 list_add(&vma_prv->list, vma_head);
1896 mutex_unlock(&ctx->vma_private_list_mutex);
1901 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1904 struct vm_area_struct *vma;
1905 struct mlx5_ib_vma_private_data *vma_private, *n;
1906 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1907 struct task_struct *owning_process = NULL;
1908 struct mm_struct *owning_mm = NULL;
1910 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1911 if (!owning_process)
1914 owning_mm = get_task_mm(owning_process);
1916 pr_info("no mm, disassociate ucontext is pending task termination\n");
1918 put_task_struct(owning_process);
1919 usleep_range(1000, 2000);
1920 owning_process = get_pid_task(ibcontext->tgid,
1922 if (!owning_process ||
1923 owning_process->state == TASK_DEAD) {
1924 pr_info("disassociate ucontext done, task was terminated\n");
1925 /* in case task was dead need to release the
1929 put_task_struct(owning_process);
1935 /* need to protect from a race on closing the vma as part of
1936 * mlx5_ib_vma_close.
1938 down_write(&owning_mm->mmap_sem);
1939 mutex_lock(&context->vma_private_list_mutex);
1940 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1942 vma = vma_private->vma;
1943 ret = zap_vma_ptes(vma, vma->vm_start,
1945 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1946 /* context going to be destroyed, should
1947 * not access ops any more.
1949 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1951 list_del(&vma_private->list);
1954 mutex_unlock(&context->vma_private_list_mutex);
1955 up_write(&owning_mm->mmap_sem);
1957 put_task_struct(owning_process);
1960 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1963 case MLX5_IB_MMAP_WC_PAGE:
1965 case MLX5_IB_MMAP_REGULAR_PAGE:
1966 return "best effort WC";
1967 case MLX5_IB_MMAP_NC_PAGE:
1974 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
1975 struct vm_area_struct *vma,
1976 struct mlx5_ib_ucontext *context)
1981 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1984 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
1987 if (vma->vm_flags & VM_WRITE)
1990 if (!dev->mdev->clock_info_page)
1993 pfn = page_to_pfn(dev->mdev->clock_info_page);
1994 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
1999 mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n",
2001 (unsigned long long)pfn << PAGE_SHIFT);
2003 return mlx5_ib_set_vma_data(vma, context);
2006 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2007 struct vm_area_struct *vma,
2008 struct mlx5_ib_ucontext *context)
2010 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2013 phys_addr_t pfn, pa;
2015 u32 bfreg_dyn_idx = 0;
2017 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2018 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2019 bfregi->num_static_sys_pages;
2021 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2025 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2027 idx = get_index(vma->vm_pgoff);
2029 if (idx >= max_valid_idx) {
2030 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2031 idx, max_valid_idx);
2036 case MLX5_IB_MMAP_WC_PAGE:
2037 case MLX5_IB_MMAP_ALLOC_WC:
2038 /* Some architectures don't support WC memory */
2039 #if defined(CONFIG_X86)
2042 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2046 case MLX5_IB_MMAP_REGULAR_PAGE:
2047 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2048 prot = pgprot_writecombine(vma->vm_page_prot);
2050 case MLX5_IB_MMAP_NC_PAGE:
2051 prot = pgprot_noncached(vma->vm_page_prot);
2060 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2061 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2062 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2063 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2064 bfreg_dyn_idx, bfregi->total_num_bfregs);
2068 mutex_lock(&bfregi->lock);
2069 /* Fail if uar already allocated, first bfreg index of each
2070 * page holds its count.
2072 if (bfregi->count[bfreg_dyn_idx]) {
2073 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2074 mutex_unlock(&bfregi->lock);
2078 bfregi->count[bfreg_dyn_idx]++;
2079 mutex_unlock(&bfregi->lock);
2081 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2083 mlx5_ib_warn(dev, "UAR alloc failed\n");
2087 uar_index = bfregi->sys_pages[idx];
2090 pfn = uar_index2pfn(dev, uar_index);
2091 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2093 vma->vm_page_prot = prot;
2094 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2095 PAGE_SIZE, vma->vm_page_prot);
2097 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
2098 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
2103 pa = pfn << PAGE_SHIFT;
2104 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
2105 vma->vm_start, &pa);
2107 err = mlx5_ib_set_vma_data(vma, context);
2112 bfregi->sys_pages[idx] = uar_index;
2119 mlx5_cmd_free_uar(dev->mdev, idx);
2122 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2127 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2129 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2130 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2131 unsigned long command;
2134 command = get_command(vma->vm_pgoff);
2136 case MLX5_IB_MMAP_WC_PAGE:
2137 case MLX5_IB_MMAP_NC_PAGE:
2138 case MLX5_IB_MMAP_REGULAR_PAGE:
2139 case MLX5_IB_MMAP_ALLOC_WC:
2140 return uar_mmap(dev, command, vma, context);
2142 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2145 case MLX5_IB_MMAP_CORE_CLOCK:
2146 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2149 if (vma->vm_flags & VM_WRITE)
2152 /* Don't expose to user-space information it shouldn't have */
2153 if (PAGE_SIZE > 4096)
2156 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2157 pfn = (dev->mdev->iseg_base +
2158 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2160 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2161 PAGE_SIZE, vma->vm_page_prot))
2164 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2166 (unsigned long long)pfn << PAGE_SHIFT);
2168 case MLX5_IB_MMAP_CLOCK_INFO:
2169 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2178 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2179 struct ib_ucontext *context,
2180 struct ib_udata *udata)
2182 struct mlx5_ib_alloc_pd_resp resp;
2183 struct mlx5_ib_pd *pd;
2186 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2188 return ERR_PTR(-ENOMEM);
2190 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
2193 return ERR_PTR(err);
2198 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2199 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
2201 return ERR_PTR(-EFAULT);
2208 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2210 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2211 struct mlx5_ib_pd *mpd = to_mpd(pd);
2213 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
2220 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2221 MATCH_CRITERIA_ENABLE_MISC_BIT,
2222 MATCH_CRITERIA_ENABLE_INNER_BIT
2225 #define HEADER_IS_ZERO(match_criteria, headers) \
2226 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2227 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
2229 static u8 get_match_criteria_enable(u32 *match_criteria)
2231 u8 match_criteria_enable;
2233 match_criteria_enable =
2234 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2235 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2236 match_criteria_enable |=
2237 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2238 MATCH_CRITERIA_ENABLE_MISC_BIT;
2239 match_criteria_enable |=
2240 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2241 MATCH_CRITERIA_ENABLE_INNER_BIT;
2243 return match_criteria_enable;
2246 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2248 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2249 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2252 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2256 MLX5_SET(fte_match_set_misc,
2257 misc_c, inner_ipv6_flow_label, mask);
2258 MLX5_SET(fte_match_set_misc,
2259 misc_v, inner_ipv6_flow_label, val);
2261 MLX5_SET(fte_match_set_misc,
2262 misc_c, outer_ipv6_flow_label, mask);
2263 MLX5_SET(fte_match_set_misc,
2264 misc_v, outer_ipv6_flow_label, val);
2268 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2270 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2271 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2272 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2273 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2276 #define LAST_ETH_FIELD vlan_tag
2277 #define LAST_IB_FIELD sl
2278 #define LAST_IPV4_FIELD tos
2279 #define LAST_IPV6_FIELD traffic_class
2280 #define LAST_TCP_UDP_FIELD src_port
2281 #define LAST_TUNNEL_FIELD tunnel_id
2282 #define LAST_FLOW_TAG_FIELD tag_id
2283 #define LAST_DROP_FIELD size
2285 /* Field is the last supported field */
2286 #define FIELDS_NOT_SUPPORTED(filter, field)\
2287 memchr_inv((void *)&filter.field +\
2288 sizeof(filter.field), 0,\
2290 offsetof(typeof(filter), field) -\
2291 sizeof(filter.field))
2293 #define IPV4_VERSION 4
2294 #define IPV6_VERSION 6
2295 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2296 u32 *match_v, const union ib_flow_spec *ib_spec,
2297 u32 *tag_id, bool *is_drop)
2299 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2301 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2307 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2308 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2310 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2312 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2313 ft_field_support.inner_ip_version);
2315 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2317 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2319 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2320 ft_field_support.outer_ip_version);
2323 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2324 case IB_FLOW_SPEC_ETH:
2325 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2328 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2330 ib_spec->eth.mask.dst_mac);
2331 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2333 ib_spec->eth.val.dst_mac);
2335 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2337 ib_spec->eth.mask.src_mac);
2338 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2340 ib_spec->eth.val.src_mac);
2342 if (ib_spec->eth.mask.vlan_tag) {
2343 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2345 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2348 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2349 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2350 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2351 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2353 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2355 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2356 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2358 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2360 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2362 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2363 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2365 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2367 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2368 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2369 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2370 ethertype, ntohs(ib_spec->eth.val.ether_type));
2372 case IB_FLOW_SPEC_IPV4:
2373 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2377 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2379 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2380 ip_version, IPV4_VERSION);
2382 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2384 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2385 ethertype, ETH_P_IP);
2388 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2389 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2390 &ib_spec->ipv4.mask.src_ip,
2391 sizeof(ib_spec->ipv4.mask.src_ip));
2392 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2393 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2394 &ib_spec->ipv4.val.src_ip,
2395 sizeof(ib_spec->ipv4.val.src_ip));
2396 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2397 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2398 &ib_spec->ipv4.mask.dst_ip,
2399 sizeof(ib_spec->ipv4.mask.dst_ip));
2400 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2401 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2402 &ib_spec->ipv4.val.dst_ip,
2403 sizeof(ib_spec->ipv4.val.dst_ip));
2405 set_tos(headers_c, headers_v,
2406 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2408 set_proto(headers_c, headers_v,
2409 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2411 case IB_FLOW_SPEC_IPV6:
2412 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2416 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2418 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2419 ip_version, IPV6_VERSION);
2421 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2423 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2424 ethertype, ETH_P_IPV6);
2427 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2428 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2429 &ib_spec->ipv6.mask.src_ip,
2430 sizeof(ib_spec->ipv6.mask.src_ip));
2431 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2432 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2433 &ib_spec->ipv6.val.src_ip,
2434 sizeof(ib_spec->ipv6.val.src_ip));
2435 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2436 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2437 &ib_spec->ipv6.mask.dst_ip,
2438 sizeof(ib_spec->ipv6.mask.dst_ip));
2439 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2440 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2441 &ib_spec->ipv6.val.dst_ip,
2442 sizeof(ib_spec->ipv6.val.dst_ip));
2444 set_tos(headers_c, headers_v,
2445 ib_spec->ipv6.mask.traffic_class,
2446 ib_spec->ipv6.val.traffic_class);
2448 set_proto(headers_c, headers_v,
2449 ib_spec->ipv6.mask.next_hdr,
2450 ib_spec->ipv6.val.next_hdr);
2452 set_flow_label(misc_params_c, misc_params_v,
2453 ntohl(ib_spec->ipv6.mask.flow_label),
2454 ntohl(ib_spec->ipv6.val.flow_label),
2455 ib_spec->type & IB_FLOW_SPEC_INNER);
2458 case IB_FLOW_SPEC_TCP:
2459 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2460 LAST_TCP_UDP_FIELD))
2463 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2465 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2468 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2469 ntohs(ib_spec->tcp_udp.mask.src_port));
2470 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2471 ntohs(ib_spec->tcp_udp.val.src_port));
2473 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2474 ntohs(ib_spec->tcp_udp.mask.dst_port));
2475 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2476 ntohs(ib_spec->tcp_udp.val.dst_port));
2478 case IB_FLOW_SPEC_UDP:
2479 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2480 LAST_TCP_UDP_FIELD))
2483 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2485 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2488 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2489 ntohs(ib_spec->tcp_udp.mask.src_port));
2490 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2491 ntohs(ib_spec->tcp_udp.val.src_port));
2493 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2494 ntohs(ib_spec->tcp_udp.mask.dst_port));
2495 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2496 ntohs(ib_spec->tcp_udp.val.dst_port));
2498 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2499 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2503 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2504 ntohl(ib_spec->tunnel.mask.tunnel_id));
2505 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2506 ntohl(ib_spec->tunnel.val.tunnel_id));
2508 case IB_FLOW_SPEC_ACTION_TAG:
2509 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2510 LAST_FLOW_TAG_FIELD))
2512 if (ib_spec->flow_tag.tag_id >= BIT(24))
2515 *tag_id = ib_spec->flow_tag.tag_id;
2517 case IB_FLOW_SPEC_ACTION_DROP:
2518 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2530 /* If a flow could catch both multicast and unicast packets,
2531 * it won't fall into the multicast flow steering table and this rule
2532 * could steal other multicast packets.
2534 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2536 union ib_flow_spec *flow_spec;
2538 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2539 ib_attr->num_of_specs < 1)
2542 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2543 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2544 struct ib_flow_spec_ipv4 *ipv4_spec;
2546 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2547 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2553 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2554 struct ib_flow_spec_eth *eth_spec;
2556 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2557 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2558 is_multicast_ether_addr(eth_spec->val.dst_mac);
2564 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2565 const struct ib_flow_attr *flow_attr,
2568 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2569 int match_ipv = check_inner ?
2570 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2571 ft_field_support.inner_ip_version) :
2572 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2573 ft_field_support.outer_ip_version);
2574 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2575 bool ipv4_spec_valid, ipv6_spec_valid;
2576 unsigned int ip_spec_type = 0;
2577 bool has_ethertype = false;
2578 unsigned int spec_index;
2579 bool mask_valid = true;
2583 /* Validate that ethertype is correct */
2584 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2585 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2586 ib_spec->eth.mask.ether_type) {
2587 mask_valid = (ib_spec->eth.mask.ether_type ==
2589 has_ethertype = true;
2590 eth_type = ntohs(ib_spec->eth.val.ether_type);
2591 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2592 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2593 ip_spec_type = ib_spec->type;
2595 ib_spec = (void *)ib_spec + ib_spec->size;
2598 type_valid = (!has_ethertype) || (!ip_spec_type);
2599 if (!type_valid && mask_valid) {
2600 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2601 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2602 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2603 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2605 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2606 (((eth_type == ETH_P_MPLS_UC) ||
2607 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2613 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2614 const struct ib_flow_attr *flow_attr)
2616 return is_valid_ethertype(mdev, flow_attr, false) &&
2617 is_valid_ethertype(mdev, flow_attr, true);
2620 static void put_flow_table(struct mlx5_ib_dev *dev,
2621 struct mlx5_ib_flow_prio *prio, bool ft_added)
2623 prio->refcount -= !!ft_added;
2624 if (!prio->refcount) {
2625 mlx5_destroy_flow_table(prio->flow_table);
2626 prio->flow_table = NULL;
2630 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2632 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2633 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2634 struct mlx5_ib_flow_handler,
2636 struct mlx5_ib_flow_handler *iter, *tmp;
2638 mutex_lock(&dev->flow_db.lock);
2640 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2641 mlx5_del_flow_rules(iter->rule);
2642 put_flow_table(dev, iter->prio, true);
2643 list_del(&iter->list);
2647 mlx5_del_flow_rules(handler->rule);
2648 put_flow_table(dev, handler->prio, true);
2649 mutex_unlock(&dev->flow_db.lock);
2656 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2664 enum flow_table_type {
2669 #define MLX5_FS_MAX_TYPES 6
2670 #define MLX5_FS_MAX_ENTRIES BIT(16)
2671 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2672 struct ib_flow_attr *flow_attr,
2673 enum flow_table_type ft_type)
2675 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2676 struct mlx5_flow_namespace *ns = NULL;
2677 struct mlx5_ib_flow_prio *prio;
2678 struct mlx5_flow_table *ft;
2685 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2687 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2688 if (flow_is_multicast_only(flow_attr) &&
2690 priority = MLX5_IB_FLOW_MCAST_PRIO;
2692 priority = ib_prio_to_core_prio(flow_attr->priority,
2694 ns = mlx5_get_flow_namespace(dev->mdev,
2695 MLX5_FLOW_NAMESPACE_BYPASS);
2696 num_entries = MLX5_FS_MAX_ENTRIES;
2697 num_groups = MLX5_FS_MAX_TYPES;
2698 prio = &dev->flow_db.prios[priority];
2699 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2700 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2701 ns = mlx5_get_flow_namespace(dev->mdev,
2702 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2703 build_leftovers_ft_param(&priority,
2706 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2707 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2708 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2709 allow_sniffer_and_nic_rx_shared_tir))
2710 return ERR_PTR(-ENOTSUPP);
2712 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2713 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2714 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2716 prio = &dev->flow_db.sniffer[ft_type];
2723 return ERR_PTR(-ENOTSUPP);
2725 if (num_entries > max_table_size)
2726 return ERR_PTR(-ENOMEM);
2728 ft = prio->flow_table;
2730 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2737 prio->flow_table = ft;
2743 return err ? ERR_PTR(err) : prio;
2746 static void set_underlay_qp(struct mlx5_ib_dev *dev,
2747 struct mlx5_flow_spec *spec,
2750 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2751 spec->match_criteria,
2753 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2757 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2758 ft_field_support.bth_dst_qp)) {
2759 MLX5_SET(fte_match_set_misc,
2760 misc_params_v, bth_dst_qp, underlay_qpn);
2761 MLX5_SET(fte_match_set_misc,
2762 misc_params_c, bth_dst_qp, 0xffffff);
2766 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2767 struct mlx5_ib_flow_prio *ft_prio,
2768 const struct ib_flow_attr *flow_attr,
2769 struct mlx5_flow_destination *dst,
2772 struct mlx5_flow_table *ft = ft_prio->flow_table;
2773 struct mlx5_ib_flow_handler *handler;
2774 struct mlx5_flow_act flow_act = {0};
2775 struct mlx5_flow_spec *spec;
2776 struct mlx5_flow_destination *rule_dst = dst;
2777 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2778 unsigned int spec_index;
2779 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2780 bool is_drop = false;
2784 if (!is_valid_attr(dev->mdev, flow_attr))
2785 return ERR_PTR(-EINVAL);
2787 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2788 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2789 if (!handler || !spec) {
2794 INIT_LIST_HEAD(&handler->list);
2796 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2797 err = parse_flow_attr(dev->mdev, spec->match_criteria,
2799 ib_flow, &flow_tag, &is_drop);
2803 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2806 if (!flow_is_multicast_only(flow_attr))
2807 set_underlay_qp(dev, spec, underlay_qpn);
2809 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2811 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2815 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2816 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2819 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2820 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2821 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2822 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2823 flow_tag, flow_attr->type);
2827 flow_act.flow_tag = flow_tag;
2828 handler->rule = mlx5_add_flow_rules(ft, spec,
2830 rule_dst, dest_num);
2832 if (IS_ERR(handler->rule)) {
2833 err = PTR_ERR(handler->rule);
2837 ft_prio->refcount++;
2838 handler->prio = ft_prio;
2840 ft_prio->flow_table = ft;
2845 return err ? ERR_PTR(err) : handler;
2848 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2849 struct mlx5_ib_flow_prio *ft_prio,
2850 const struct ib_flow_attr *flow_attr,
2851 struct mlx5_flow_destination *dst)
2853 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2856 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2857 struct mlx5_ib_flow_prio *ft_prio,
2858 struct ib_flow_attr *flow_attr,
2859 struct mlx5_flow_destination *dst)
2861 struct mlx5_ib_flow_handler *handler_dst = NULL;
2862 struct mlx5_ib_flow_handler *handler = NULL;
2864 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2865 if (!IS_ERR(handler)) {
2866 handler_dst = create_flow_rule(dev, ft_prio,
2868 if (IS_ERR(handler_dst)) {
2869 mlx5_del_flow_rules(handler->rule);
2870 ft_prio->refcount--;
2872 handler = handler_dst;
2874 list_add(&handler_dst->list, &handler->list);
2885 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2886 struct mlx5_ib_flow_prio *ft_prio,
2887 struct ib_flow_attr *flow_attr,
2888 struct mlx5_flow_destination *dst)
2890 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2891 struct mlx5_ib_flow_handler *handler = NULL;
2894 struct ib_flow_attr flow_attr;
2895 struct ib_flow_spec_eth eth_flow;
2896 } leftovers_specs[] = {
2900 .size = sizeof(leftovers_specs[0])
2903 .type = IB_FLOW_SPEC_ETH,
2904 .size = sizeof(struct ib_flow_spec_eth),
2905 .mask = {.dst_mac = {0x1} },
2906 .val = {.dst_mac = {0x1} }
2912 .size = sizeof(leftovers_specs[0])
2915 .type = IB_FLOW_SPEC_ETH,
2916 .size = sizeof(struct ib_flow_spec_eth),
2917 .mask = {.dst_mac = {0x1} },
2918 .val = {.dst_mac = {} }
2923 handler = create_flow_rule(dev, ft_prio,
2924 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2926 if (!IS_ERR(handler) &&
2927 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2928 handler_ucast = create_flow_rule(dev, ft_prio,
2929 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2931 if (IS_ERR(handler_ucast)) {
2932 mlx5_del_flow_rules(handler->rule);
2933 ft_prio->refcount--;
2935 handler = handler_ucast;
2937 list_add(&handler_ucast->list, &handler->list);
2944 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2945 struct mlx5_ib_flow_prio *ft_rx,
2946 struct mlx5_ib_flow_prio *ft_tx,
2947 struct mlx5_flow_destination *dst)
2949 struct mlx5_ib_flow_handler *handler_rx;
2950 struct mlx5_ib_flow_handler *handler_tx;
2952 static const struct ib_flow_attr flow_attr = {
2954 .size = sizeof(flow_attr)
2957 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2958 if (IS_ERR(handler_rx)) {
2959 err = PTR_ERR(handler_rx);
2963 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2964 if (IS_ERR(handler_tx)) {
2965 err = PTR_ERR(handler_tx);
2969 list_add(&handler_tx->list, &handler_rx->list);
2974 mlx5_del_flow_rules(handler_rx->rule);
2978 return ERR_PTR(err);
2981 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2982 struct ib_flow_attr *flow_attr,
2985 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2986 struct mlx5_ib_qp *mqp = to_mqp(qp);
2987 struct mlx5_ib_flow_handler *handler = NULL;
2988 struct mlx5_flow_destination *dst = NULL;
2989 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2990 struct mlx5_ib_flow_prio *ft_prio;
2994 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2995 return ERR_PTR(-ENOMEM);
2997 if (domain != IB_FLOW_DOMAIN_USER ||
2998 flow_attr->port > dev->num_ports ||
2999 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
3000 return ERR_PTR(-EINVAL);
3002 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3004 return ERR_PTR(-ENOMEM);
3006 mutex_lock(&dev->flow_db.lock);
3008 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
3009 if (IS_ERR(ft_prio)) {
3010 err = PTR_ERR(ft_prio);
3013 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3014 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3015 if (IS_ERR(ft_prio_tx)) {
3016 err = PTR_ERR(ft_prio_tx);
3022 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3023 if (mqp->flags & MLX5_IB_QP_RSS)
3024 dst->tir_num = mqp->rss_qp.tirn;
3026 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3028 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3029 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3030 handler = create_dont_trap_rule(dev, ft_prio,
3033 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3034 mqp->underlay_qpn : 0;
3035 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3038 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3039 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3040 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3042 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3043 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3049 if (IS_ERR(handler)) {
3050 err = PTR_ERR(handler);
3055 mutex_unlock(&dev->flow_db.lock);
3058 return &handler->ibflow;
3061 put_flow_table(dev, ft_prio, false);
3063 put_flow_table(dev, ft_prio_tx, false);
3065 mutex_unlock(&dev->flow_db.lock);
3068 return ERR_PTR(err);
3071 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3073 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3074 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
3077 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3078 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3082 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
3084 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3085 ibqp->qp_num, gid->raw);
3090 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3092 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3095 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
3097 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3098 ibqp->qp_num, gid->raw);
3103 static int init_node_data(struct mlx5_ib_dev *dev)
3107 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
3111 dev->mdev->rev_id = dev->mdev->pdev->revision;
3113 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
3116 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3119 struct mlx5_ib_dev *dev =
3120 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3122 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
3125 static ssize_t show_reg_pages(struct device *device,
3126 struct device_attribute *attr, char *buf)
3128 struct mlx5_ib_dev *dev =
3129 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3131 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
3134 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3137 struct mlx5_ib_dev *dev =
3138 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3139 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
3142 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3145 struct mlx5_ib_dev *dev =
3146 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3147 return sprintf(buf, "%x\n", dev->mdev->rev_id);
3150 static ssize_t show_board(struct device *device, struct device_attribute *attr,
3153 struct mlx5_ib_dev *dev =
3154 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3155 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
3156 dev->mdev->board_id);
3159 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
3160 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
3161 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
3162 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3163 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3165 static struct device_attribute *mlx5_class_attributes[] = {
3170 &dev_attr_reg_pages,
3173 static void pkey_change_handler(struct work_struct *work)
3175 struct mlx5_ib_port_resources *ports =
3176 container_of(work, struct mlx5_ib_port_resources,
3179 mutex_lock(&ports->devr->mutex);
3180 mlx5_ib_gsi_pkey_change(ports->gsi);
3181 mutex_unlock(&ports->devr->mutex);
3184 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3186 struct mlx5_ib_qp *mqp;
3187 struct mlx5_ib_cq *send_mcq, *recv_mcq;
3188 struct mlx5_core_cq *mcq;
3189 struct list_head cq_armed_list;
3190 unsigned long flags_qp;
3191 unsigned long flags_cq;
3192 unsigned long flags;
3194 INIT_LIST_HEAD(&cq_armed_list);
3196 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3197 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3198 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3199 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3200 if (mqp->sq.tail != mqp->sq.head) {
3201 send_mcq = to_mcq(mqp->ibqp.send_cq);
3202 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3203 if (send_mcq->mcq.comp &&
3204 mqp->ibqp.send_cq->comp_handler) {
3205 if (!send_mcq->mcq.reset_notify_added) {
3206 send_mcq->mcq.reset_notify_added = 1;
3207 list_add_tail(&send_mcq->mcq.reset_notify,
3211 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3213 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3214 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3215 /* no handling is needed for SRQ */
3216 if (!mqp->ibqp.srq) {
3217 if (mqp->rq.tail != mqp->rq.head) {
3218 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3219 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3220 if (recv_mcq->mcq.comp &&
3221 mqp->ibqp.recv_cq->comp_handler) {
3222 if (!recv_mcq->mcq.reset_notify_added) {
3223 recv_mcq->mcq.reset_notify_added = 1;
3224 list_add_tail(&recv_mcq->mcq.reset_notify,
3228 spin_unlock_irqrestore(&recv_mcq->lock,
3232 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3234 /*At that point all inflight post send were put to be executed as of we
3235 * lock/unlock above locks Now need to arm all involved CQs.
3237 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3240 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3243 static void delay_drop_handler(struct work_struct *work)
3246 struct mlx5_ib_delay_drop *delay_drop =
3247 container_of(work, struct mlx5_ib_delay_drop,
3250 atomic_inc(&delay_drop->events_cnt);
3252 mutex_lock(&delay_drop->lock);
3253 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3254 delay_drop->timeout);
3256 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3257 delay_drop->timeout);
3258 delay_drop->activate = false;
3260 mutex_unlock(&delay_drop->lock);
3263 static void mlx5_ib_handle_event(struct work_struct *_work)
3265 struct mlx5_ib_event_work *work =
3266 container_of(_work, struct mlx5_ib_event_work, work);
3267 struct mlx5_ib_dev *ibdev;
3268 struct ib_event ibev;
3270 u8 port = (u8)work->param;
3272 if (mlx5_core_is_mp_slave(work->dev)) {
3273 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
3277 ibdev = work->context;
3280 switch (work->event) {
3281 case MLX5_DEV_EVENT_SYS_ERROR:
3282 ibev.event = IB_EVENT_DEVICE_FATAL;
3283 mlx5_ib_handle_internal_error(ibdev);
3287 case MLX5_DEV_EVENT_PORT_UP:
3288 case MLX5_DEV_EVENT_PORT_DOWN:
3289 case MLX5_DEV_EVENT_PORT_INITIALIZED:
3290 /* In RoCE, port up/down events are handled in
3291 * mlx5_netdev_event().
3293 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3294 IB_LINK_LAYER_ETHERNET)
3297 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
3298 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3301 case MLX5_DEV_EVENT_LID_CHANGE:
3302 ibev.event = IB_EVENT_LID_CHANGE;
3305 case MLX5_DEV_EVENT_PKEY_CHANGE:
3306 ibev.event = IB_EVENT_PKEY_CHANGE;
3307 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
3310 case MLX5_DEV_EVENT_GUID_CHANGE:
3311 ibev.event = IB_EVENT_GID_CHANGE;
3314 case MLX5_DEV_EVENT_CLIENT_REREG:
3315 ibev.event = IB_EVENT_CLIENT_REREGISTER;
3317 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3318 schedule_work(&ibdev->delay_drop.delay_drop_work);
3324 ibev.device = &ibdev->ib_dev;
3325 ibev.element.port_num = port;
3327 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
3328 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
3332 if (ibdev->ib_active)
3333 ib_dispatch_event(&ibev);
3336 ibdev->ib_active = false;
3341 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
3342 enum mlx5_dev_event event, unsigned long param)
3344 struct mlx5_ib_event_work *work;
3346 work = kmalloc(sizeof(*work), GFP_ATOMIC);
3350 INIT_WORK(&work->work, mlx5_ib_handle_event);
3352 work->param = param;
3353 work->context = context;
3354 work->event = event;
3356 queue_work(mlx5_ib_event_wq, &work->work);
3359 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3361 struct mlx5_hca_vport_context vport_ctx;
3365 for (port = 1; port <= dev->num_ports; port++) {
3366 dev->mdev->port_caps[port - 1].has_smi = false;
3367 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3368 MLX5_CAP_PORT_TYPE_IB) {
3369 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3370 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3374 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3378 dev->mdev->port_caps[port - 1].has_smi =
3381 dev->mdev->port_caps[port - 1].has_smi = true;
3388 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3392 for (port = 1; port <= dev->num_ports; port++)
3393 mlx5_query_ext_port_caps(dev, port);
3396 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
3398 struct ib_device_attr *dprops = NULL;
3399 struct ib_port_attr *pprops = NULL;
3401 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
3403 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3407 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3411 err = set_has_smi_cap(dev);
3415 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
3417 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3421 memset(pprops, 0, sizeof(*pprops));
3422 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3424 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3429 dev->mdev->port_caps[port - 1].pkey_table_len =
3431 dev->mdev->port_caps[port - 1].gid_table_len =
3432 pprops->gid_tbl_len;
3433 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
3434 port, dprops->max_pkeys, pprops->gid_tbl_len);
3443 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3447 err = mlx5_mr_cache_cleanup(dev);
3449 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3451 mlx5_ib_destroy_qp(dev->umrc.qp);
3452 ib_free_cq(dev->umrc.cq);
3453 ib_dealloc_pd(dev->umrc.pd);
3460 static int create_umr_res(struct mlx5_ib_dev *dev)
3462 struct ib_qp_init_attr *init_attr = NULL;
3463 struct ib_qp_attr *attr = NULL;
3469 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3470 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3471 if (!attr || !init_attr) {
3476 pd = ib_alloc_pd(&dev->ib_dev, 0);
3478 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3483 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
3485 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3490 init_attr->send_cq = cq;
3491 init_attr->recv_cq = cq;
3492 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3493 init_attr->cap.max_send_wr = MAX_UMR_WR;
3494 init_attr->cap.max_send_sge = 1;
3495 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3496 init_attr->port_num = 1;
3497 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3499 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3503 qp->device = &dev->ib_dev;
3506 qp->qp_type = MLX5_IB_QPT_REG_UMR;
3507 qp->send_cq = init_attr->send_cq;
3508 qp->recv_cq = init_attr->recv_cq;
3510 attr->qp_state = IB_QPS_INIT;
3512 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3515 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3519 memset(attr, 0, sizeof(*attr));
3520 attr->qp_state = IB_QPS_RTR;
3521 attr->path_mtu = IB_MTU_256;
3523 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3525 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3529 memset(attr, 0, sizeof(*attr));
3530 attr->qp_state = IB_QPS_RTS;
3531 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3533 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3541 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3542 ret = mlx5_mr_cache_init(dev);
3544 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3554 mlx5_ib_destroy_qp(qp);
3568 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3570 switch (umr_fence_cap) {
3571 case MLX5_CAP_UMR_FENCE_NONE:
3572 return MLX5_FENCE_MODE_NONE;
3573 case MLX5_CAP_UMR_FENCE_SMALL:
3574 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3576 return MLX5_FENCE_MODE_STRONG_ORDERING;
3580 static int create_dev_resources(struct mlx5_ib_resources *devr)
3582 struct ib_srq_init_attr attr;
3583 struct mlx5_ib_dev *dev;
3584 struct ib_cq_init_attr cq_attr = {.cqe = 1};
3588 dev = container_of(devr, struct mlx5_ib_dev, devr);
3590 mutex_init(&devr->mutex);
3592 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3593 if (IS_ERR(devr->p0)) {
3594 ret = PTR_ERR(devr->p0);
3597 devr->p0->device = &dev->ib_dev;
3598 devr->p0->uobject = NULL;
3599 atomic_set(&devr->p0->usecnt, 0);
3601 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
3602 if (IS_ERR(devr->c0)) {
3603 ret = PTR_ERR(devr->c0);
3606 devr->c0->device = &dev->ib_dev;
3607 devr->c0->uobject = NULL;
3608 devr->c0->comp_handler = NULL;
3609 devr->c0->event_handler = NULL;
3610 devr->c0->cq_context = NULL;
3611 atomic_set(&devr->c0->usecnt, 0);
3613 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3614 if (IS_ERR(devr->x0)) {
3615 ret = PTR_ERR(devr->x0);
3618 devr->x0->device = &dev->ib_dev;
3619 devr->x0->inode = NULL;
3620 atomic_set(&devr->x0->usecnt, 0);
3621 mutex_init(&devr->x0->tgt_qp_mutex);
3622 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3624 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3625 if (IS_ERR(devr->x1)) {
3626 ret = PTR_ERR(devr->x1);
3629 devr->x1->device = &dev->ib_dev;
3630 devr->x1->inode = NULL;
3631 atomic_set(&devr->x1->usecnt, 0);
3632 mutex_init(&devr->x1->tgt_qp_mutex);
3633 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3635 memset(&attr, 0, sizeof(attr));
3636 attr.attr.max_sge = 1;
3637 attr.attr.max_wr = 1;
3638 attr.srq_type = IB_SRQT_XRC;
3639 attr.ext.cq = devr->c0;
3640 attr.ext.xrc.xrcd = devr->x0;
3642 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3643 if (IS_ERR(devr->s0)) {
3644 ret = PTR_ERR(devr->s0);
3647 devr->s0->device = &dev->ib_dev;
3648 devr->s0->pd = devr->p0;
3649 devr->s0->uobject = NULL;
3650 devr->s0->event_handler = NULL;
3651 devr->s0->srq_context = NULL;
3652 devr->s0->srq_type = IB_SRQT_XRC;
3653 devr->s0->ext.xrc.xrcd = devr->x0;
3654 devr->s0->ext.cq = devr->c0;
3655 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3656 atomic_inc(&devr->s0->ext.cq->usecnt);
3657 atomic_inc(&devr->p0->usecnt);
3658 atomic_set(&devr->s0->usecnt, 0);
3660 memset(&attr, 0, sizeof(attr));
3661 attr.attr.max_sge = 1;
3662 attr.attr.max_wr = 1;
3663 attr.srq_type = IB_SRQT_BASIC;
3664 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3665 if (IS_ERR(devr->s1)) {
3666 ret = PTR_ERR(devr->s1);
3669 devr->s1->device = &dev->ib_dev;
3670 devr->s1->pd = devr->p0;
3671 devr->s1->uobject = NULL;
3672 devr->s1->event_handler = NULL;
3673 devr->s1->srq_context = NULL;
3674 devr->s1->srq_type = IB_SRQT_BASIC;
3675 devr->s1->ext.cq = devr->c0;
3676 atomic_inc(&devr->p0->usecnt);
3677 atomic_set(&devr->s1->usecnt, 0);
3679 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3680 INIT_WORK(&devr->ports[port].pkey_change_work,
3681 pkey_change_handler);
3682 devr->ports[port].devr = devr;
3688 mlx5_ib_destroy_srq(devr->s0);
3690 mlx5_ib_dealloc_xrcd(devr->x1);
3692 mlx5_ib_dealloc_xrcd(devr->x0);
3694 mlx5_ib_destroy_cq(devr->c0);
3696 mlx5_ib_dealloc_pd(devr->p0);
3701 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3703 struct mlx5_ib_dev *dev =
3704 container_of(devr, struct mlx5_ib_dev, devr);
3707 mlx5_ib_destroy_srq(devr->s1);
3708 mlx5_ib_destroy_srq(devr->s0);
3709 mlx5_ib_dealloc_xrcd(devr->x0);
3710 mlx5_ib_dealloc_xrcd(devr->x1);
3711 mlx5_ib_destroy_cq(devr->c0);
3712 mlx5_ib_dealloc_pd(devr->p0);
3714 /* Make sure no change P_Key work items are still executing */
3715 for (port = 0; port < dev->num_ports; ++port)
3716 cancel_work_sync(&devr->ports[port].pkey_change_work);
3719 static u32 get_core_cap_flags(struct ib_device *ibdev)
3721 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3722 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3723 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3724 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3725 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
3728 if (ll == IB_LINK_LAYER_INFINIBAND)
3729 return RDMA_CORE_PORT_IBA_IB;
3732 ret = RDMA_CORE_PORT_RAW_PACKET;
3734 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3737 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3740 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3741 ret |= RDMA_CORE_PORT_IBA_ROCE;
3743 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3744 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3749 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3750 struct ib_port_immutable *immutable)
3752 struct ib_port_attr attr;
3753 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3754 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3757 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3759 err = ib_query_port(ibdev, port_num, &attr);
3763 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3764 immutable->gid_tbl_len = attr.gid_tbl_len;
3765 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3766 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3767 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3772 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3774 struct mlx5_ib_dev *dev =
3775 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3776 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3777 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3778 fw_rev_sub(dev->mdev));
3781 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3783 struct mlx5_core_dev *mdev = dev->mdev;
3784 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3785 MLX5_FLOW_NAMESPACE_LAG);
3786 struct mlx5_flow_table *ft;
3789 if (!ns || !mlx5_lag_is_active(mdev))
3792 err = mlx5_cmd_create_vport_lag(mdev);
3796 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3799 goto err_destroy_vport_lag;
3802 dev->flow_db.lag_demux_ft = ft;
3805 err_destroy_vport_lag:
3806 mlx5_cmd_destroy_vport_lag(mdev);
3810 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3812 struct mlx5_core_dev *mdev = dev->mdev;
3814 if (dev->flow_db.lag_demux_ft) {
3815 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3816 dev->flow_db.lag_demux_ft = NULL;
3818 mlx5_cmd_destroy_vport_lag(mdev);
3822 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
3826 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
3827 err = register_netdevice_notifier(&dev->roce[port_num].nb);
3829 dev->roce[port_num].nb.notifier_call = NULL;
3836 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
3838 if (dev->roce[port_num].nb.notifier_call) {
3839 unregister_netdevice_notifier(&dev->roce[port_num].nb);
3840 dev->roce[port_num].nb.notifier_call = NULL;
3844 static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
3848 err = mlx5_add_netdev_notifier(dev, port_num);
3852 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3853 err = mlx5_nic_vport_enable_roce(dev->mdev);
3855 goto err_unregister_netdevice_notifier;
3858 err = mlx5_eth_lag_init(dev);
3860 goto err_disable_roce;
3865 if (MLX5_CAP_GEN(dev->mdev, roce))
3866 mlx5_nic_vport_disable_roce(dev->mdev);
3868 err_unregister_netdevice_notifier:
3869 mlx5_remove_netdev_notifier(dev, port_num);
3873 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3875 mlx5_eth_lag_cleanup(dev);
3876 if (MLX5_CAP_GEN(dev->mdev, roce))
3877 mlx5_nic_vport_disable_roce(dev->mdev);
3880 struct mlx5_ib_counter {
3885 #define INIT_Q_COUNTER(_name) \
3886 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3888 static const struct mlx5_ib_counter basic_q_cnts[] = {
3889 INIT_Q_COUNTER(rx_write_requests),
3890 INIT_Q_COUNTER(rx_read_requests),
3891 INIT_Q_COUNTER(rx_atomic_requests),
3892 INIT_Q_COUNTER(out_of_buffer),
3895 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
3896 INIT_Q_COUNTER(out_of_sequence),
3899 static const struct mlx5_ib_counter retrans_q_cnts[] = {
3900 INIT_Q_COUNTER(duplicate_request),
3901 INIT_Q_COUNTER(rnr_nak_retry_err),
3902 INIT_Q_COUNTER(packet_seq_err),
3903 INIT_Q_COUNTER(implied_nak_seq_err),
3904 INIT_Q_COUNTER(local_ack_timeout_err),
3907 #define INIT_CONG_COUNTER(_name) \
3908 { .name = #_name, .offset = \
3909 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3911 static const struct mlx5_ib_counter cong_cnts[] = {
3912 INIT_CONG_COUNTER(rp_cnp_ignored),
3913 INIT_CONG_COUNTER(rp_cnp_handled),
3914 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3915 INIT_CONG_COUNTER(np_cnp_sent),
3918 static const struct mlx5_ib_counter extended_err_cnts[] = {
3919 INIT_Q_COUNTER(resp_local_length_error),
3920 INIT_Q_COUNTER(resp_cqe_error),
3921 INIT_Q_COUNTER(req_cqe_error),
3922 INIT_Q_COUNTER(req_remote_invalid_request),
3923 INIT_Q_COUNTER(req_remote_access_errors),
3924 INIT_Q_COUNTER(resp_remote_access_errors),
3925 INIT_Q_COUNTER(resp_cqe_flush_error),
3926 INIT_Q_COUNTER(req_cqe_flush_error),
3929 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
3933 for (i = 0; i < dev->num_ports; i++) {
3934 if (dev->port[i].cnts.set_id)
3935 mlx5_core_dealloc_q_counter(dev->mdev,
3936 dev->port[i].cnts.set_id);
3937 kfree(dev->port[i].cnts.names);
3938 kfree(dev->port[i].cnts.offsets);
3942 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3943 struct mlx5_ib_counters *cnts)
3947 num_counters = ARRAY_SIZE(basic_q_cnts);
3949 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3950 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3952 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3953 num_counters += ARRAY_SIZE(retrans_q_cnts);
3955 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3956 num_counters += ARRAY_SIZE(extended_err_cnts);
3958 cnts->num_q_counters = num_counters;
3960 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3961 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3962 num_counters += ARRAY_SIZE(cong_cnts);
3965 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3969 cnts->offsets = kcalloc(num_counters,
3970 sizeof(cnts->offsets), GFP_KERNEL);
3982 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3989 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3990 names[j] = basic_q_cnts[i].name;
3991 offsets[j] = basic_q_cnts[i].offset;
3994 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3995 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3996 names[j] = out_of_seq_q_cnts[i].name;
3997 offsets[j] = out_of_seq_q_cnts[i].offset;
4001 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4002 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4003 names[j] = retrans_q_cnts[i].name;
4004 offsets[j] = retrans_q_cnts[i].offset;
4008 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4009 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4010 names[j] = extended_err_cnts[i].name;
4011 offsets[j] = extended_err_cnts[i].offset;
4015 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4016 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4017 names[j] = cong_cnts[i].name;
4018 offsets[j] = cong_cnts[i].offset;
4023 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
4028 for (i = 0; i < dev->num_ports; i++) {
4029 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4033 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4034 dev->port[i].cnts.offsets);
4036 err = mlx5_core_alloc_q_counter(dev->mdev,
4037 &dev->port[i].cnts.set_id);
4040 "couldn't allocate queue counter for port %d, err %d\n",
4044 dev->port[i].cnts.set_id_valid = true;
4050 mlx5_ib_dealloc_counters(dev);
4054 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4057 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4058 struct mlx5_ib_port *port = &dev->port[port_num - 1];
4060 /* We support only per port stats */
4064 return rdma_alloc_hw_stats_struct(port->cnts.names,
4065 port->cnts.num_q_counters +
4066 port->cnts.num_cong_counters,
4067 RDMA_HW_STATS_DEFAULT_LIFESPAN);
4070 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
4071 struct mlx5_ib_port *port,
4072 struct rdma_hw_stats *stats)
4074 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4079 out = kvzalloc(outlen, GFP_KERNEL);
4083 ret = mlx5_core_query_q_counter(mdev,
4084 port->cnts.set_id, 0,
4089 for (i = 0; i < port->cnts.num_q_counters; i++) {
4090 val = *(__be32 *)(out + port->cnts.offsets[i]);
4091 stats->value[i] = (u64)be32_to_cpu(val);
4099 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4100 struct rdma_hw_stats *stats,
4101 u8 port_num, int index)
4103 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4104 struct mlx5_ib_port *port = &dev->port[port_num - 1];
4105 struct mlx5_core_dev *mdev;
4106 int ret, num_counters;
4112 num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4114 /* q_counters are per IB device, query the master mdev */
4115 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
4119 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4120 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4123 /* If port is not affiliated yet, its in down state
4124 * which doesn't have any counters yet, so it would be
4125 * zero. So no need to read from the HCA.
4129 ret = mlx5_lag_query_cong_counters(dev->mdev,
4131 port->cnts.num_q_counters,
4132 port->cnts.num_cong_counters,
4133 port->cnts.offsets +
4134 port->cnts.num_q_counters);
4136 mlx5_ib_put_native_port_mdev(dev, port_num);
4142 return num_counters;
4145 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4147 return mlx5_rdma_netdev_free(netdev);
4150 static struct net_device*
4151 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4153 enum rdma_netdev_t type,
4155 unsigned char name_assign_type,
4156 void (*setup)(struct net_device *))
4158 struct net_device *netdev;
4159 struct rdma_netdev *rn;
4161 if (type != RDMA_NETDEV_IPOIB)
4162 return ERR_PTR(-EOPNOTSUPP);
4164 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4166 if (likely(!IS_ERR_OR_NULL(netdev))) {
4167 rn = netdev_priv(netdev);
4168 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4173 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4175 if (!dev->delay_drop.dbg)
4177 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4178 kfree(dev->delay_drop.dbg);
4179 dev->delay_drop.dbg = NULL;
4182 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4184 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4187 cancel_work_sync(&dev->delay_drop.delay_drop_work);
4188 delay_drop_debugfs_cleanup(dev);
4191 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4192 size_t count, loff_t *pos)
4194 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4198 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4199 return simple_read_from_buffer(buf, count, pos, lbuf, len);
4202 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4203 size_t count, loff_t *pos)
4205 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4209 if (kstrtouint_from_user(buf, count, 0, &var))
4212 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4215 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4218 delay_drop->timeout = timeout;
4223 static const struct file_operations fops_delay_drop_timeout = {
4224 .owner = THIS_MODULE,
4225 .open = simple_open,
4226 .write = delay_drop_timeout_write,
4227 .read = delay_drop_timeout_read,
4230 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
4232 struct mlx5_ib_dbg_delay_drop *dbg;
4234 if (!mlx5_debugfs_root)
4237 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
4241 dev->delay_drop.dbg = dbg;
4244 debugfs_create_dir("delay_drop",
4245 dev->mdev->priv.dbg_root);
4246 if (!dbg->dir_debugfs)
4249 dbg->events_cnt_debugfs =
4250 debugfs_create_atomic_t("num_timeout_events", 0400,
4252 &dev->delay_drop.events_cnt);
4253 if (!dbg->events_cnt_debugfs)
4256 dbg->rqs_cnt_debugfs =
4257 debugfs_create_atomic_t("num_rqs", 0400,
4259 &dev->delay_drop.rqs_cnt);
4260 if (!dbg->rqs_cnt_debugfs)
4263 dbg->timeout_debugfs =
4264 debugfs_create_file("timeout", 0600,
4267 &fops_delay_drop_timeout);
4268 if (!dbg->timeout_debugfs)
4274 delay_drop_debugfs_cleanup(dev);
4278 static void init_delay_drop(struct mlx5_ib_dev *dev)
4280 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4283 mutex_init(&dev->delay_drop.lock);
4284 dev->delay_drop.dev = dev;
4285 dev->delay_drop.activate = false;
4286 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4287 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4288 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4289 atomic_set(&dev->delay_drop.events_cnt, 0);
4291 if (delay_drop_debugfs_init(dev))
4292 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
4295 static const struct cpumask *
4296 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
4298 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4300 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
4303 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4304 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
4305 struct mlx5_ib_multiport_info *mpi)
4307 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4308 struct mlx5_ib_port *port = &ibdev->port[port_num];
4313 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
4315 spin_lock(&port->mp.mpi_lock);
4317 spin_unlock(&port->mp.mpi_lock);
4322 spin_unlock(&port->mp.mpi_lock);
4323 mlx5_remove_netdev_notifier(ibdev, port_num);
4324 spin_lock(&port->mp.mpi_lock);
4326 comps = mpi->mdev_refcnt;
4328 mpi->unaffiliate = true;
4329 init_completion(&mpi->unref_comp);
4330 spin_unlock(&port->mp.mpi_lock);
4332 for (i = 0; i < comps; i++)
4333 wait_for_completion(&mpi->unref_comp);
4335 spin_lock(&port->mp.mpi_lock);
4336 mpi->unaffiliate = false;
4339 port->mp.mpi = NULL;
4341 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4343 spin_unlock(&port->mp.mpi_lock);
4345 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
4347 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
4348 /* Log an error, still needed to cleanup the pointers and add
4349 * it back to the list.
4352 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
4355 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
4358 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4359 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
4360 struct mlx5_ib_multiport_info *mpi)
4362 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4365 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
4366 if (ibdev->port[port_num].mp.mpi) {
4367 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
4369 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4373 ibdev->port[port_num].mp.mpi = mpi;
4375 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4377 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
4381 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
4385 err = mlx5_add_netdev_notifier(ibdev, port_num);
4387 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
4392 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
4399 mlx5_ib_unbind_slave_port(ibdev, mpi);
4403 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
4405 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4406 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4408 struct mlx5_ib_multiport_info *mpi;
4412 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4415 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
4416 &dev->sys_image_guid);
4420 err = mlx5_nic_vport_enable_roce(dev->mdev);
4424 mutex_lock(&mlx5_ib_multiport_mutex);
4425 for (i = 0; i < dev->num_ports; i++) {
4428 /* build a stub multiport info struct for the native port. */
4429 if (i == port_num) {
4430 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4432 mutex_unlock(&mlx5_ib_multiport_mutex);
4433 mlx5_nic_vport_disable_roce(dev->mdev);
4437 mpi->is_master = true;
4438 mpi->mdev = dev->mdev;
4439 mpi->sys_image_guid = dev->sys_image_guid;
4440 dev->port[i].mp.mpi = mpi;
4446 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
4448 if (dev->sys_image_guid == mpi->sys_image_guid &&
4449 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
4450 bound = mlx5_ib_bind_slave_port(dev, mpi);
4454 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
4455 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
4456 list_del(&mpi->list);
4461 get_port_caps(dev, i + 1);
4462 mlx5_ib_dbg(dev, "no free port found for port %d\n",
4467 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
4468 mutex_unlock(&mlx5_ib_multiport_mutex);
4472 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
4474 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4475 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4479 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4482 mutex_lock(&mlx5_ib_multiport_mutex);
4483 for (i = 0; i < dev->num_ports; i++) {
4484 if (dev->port[i].mp.mpi) {
4485 /* Destroy the native port stub */
4486 if (i == port_num) {
4487 kfree(dev->port[i].mp.mpi);
4488 dev->port[i].mp.mpi = NULL;
4490 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
4491 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
4496 mlx5_ib_dbg(dev, "removing from devlist\n");
4497 list_del(&dev->ib_dev_list);
4498 mutex_unlock(&mlx5_ib_multiport_mutex);
4500 mlx5_nic_vport_disable_roce(dev->mdev);
4503 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
4505 mlx5_ib_cleanup_multiport_master(dev);
4506 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4507 cleanup_srcu_struct(&dev->mr_srcu);
4512 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
4514 struct mlx5_core_dev *mdev = dev->mdev;
4519 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
4524 for (i = 0; i < dev->num_ports; i++) {
4525 spin_lock_init(&dev->port[i].mp.mpi_lock);
4526 rwlock_init(&dev->roce[i].netdev_lock);
4529 err = mlx5_ib_init_multiport_master(dev);
4533 if (!mlx5_core_mp_enabled(mdev)) {
4536 for (i = 1; i <= dev->num_ports; i++) {
4537 err = get_port_caps(dev, i);
4542 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
4547 if (mlx5_use_mad_ifc(dev))
4548 get_ext_port_caps(dev);
4550 if (!mlx5_lag_is_active(mdev))
4553 name = "mlx5_bond_%d";
4555 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
4556 dev->ib_dev.owner = THIS_MODULE;
4557 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
4558 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
4559 dev->ib_dev.phys_port_cnt = dev->num_ports;
4560 dev->ib_dev.num_comp_vectors =
4561 dev->mdev->priv.eq_table.num_comp_vectors;
4562 dev->ib_dev.dev.parent = &mdev->pdev->dev;
4564 mutex_init(&dev->flow_db.lock);
4565 mutex_init(&dev->cap_mask_mutex);
4566 INIT_LIST_HEAD(&dev->qp_list);
4567 spin_lock_init(&dev->reset_flow_resource_lock);
4569 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4570 err = init_srcu_struct(&dev->mr_srcu);
4577 mlx5_ib_cleanup_multiport_master(dev);
4585 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
4587 struct mlx5_core_dev *mdev = dev->mdev;
4590 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
4591 dev->ib_dev.uverbs_cmd_mask =
4592 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
4593 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
4594 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
4595 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
4596 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
4597 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
4598 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
4599 (1ull << IB_USER_VERBS_CMD_REG_MR) |
4600 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
4601 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
4602 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
4603 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
4604 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
4605 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
4606 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
4607 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
4608 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
4609 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
4610 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
4611 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
4612 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
4613 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
4614 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
4615 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
4616 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
4617 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
4618 dev->ib_dev.uverbs_ex_cmd_mask =
4619 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
4620 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
4621 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
4622 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
4623 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
4625 dev->ib_dev.query_device = mlx5_ib_query_device;
4626 dev->ib_dev.query_port = mlx5_ib_query_port;
4627 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
4628 dev->ib_dev.query_gid = mlx5_ib_query_gid;
4629 dev->ib_dev.add_gid = mlx5_ib_add_gid;
4630 dev->ib_dev.del_gid = mlx5_ib_del_gid;
4631 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
4632 dev->ib_dev.modify_device = mlx5_ib_modify_device;
4633 dev->ib_dev.modify_port = mlx5_ib_modify_port;
4634 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
4635 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
4636 dev->ib_dev.mmap = mlx5_ib_mmap;
4637 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
4638 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
4639 dev->ib_dev.create_ah = mlx5_ib_create_ah;
4640 dev->ib_dev.query_ah = mlx5_ib_query_ah;
4641 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
4642 dev->ib_dev.create_srq = mlx5_ib_create_srq;
4643 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
4644 dev->ib_dev.query_srq = mlx5_ib_query_srq;
4645 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
4646 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
4647 dev->ib_dev.create_qp = mlx5_ib_create_qp;
4648 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
4649 dev->ib_dev.query_qp = mlx5_ib_query_qp;
4650 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
4651 dev->ib_dev.post_send = mlx5_ib_post_send;
4652 dev->ib_dev.post_recv = mlx5_ib_post_recv;
4653 dev->ib_dev.create_cq = mlx5_ib_create_cq;
4654 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
4655 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
4656 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
4657 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
4658 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
4659 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
4660 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
4661 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
4662 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
4663 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
4664 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
4665 dev->ib_dev.process_mad = mlx5_ib_process_mad;
4666 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
4667 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
4668 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
4669 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
4670 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
4671 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
4672 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
4673 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
4675 if (mlx5_core_is_pf(mdev)) {
4676 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
4677 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
4678 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
4679 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
4682 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4684 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4686 if (MLX5_CAP_GEN(mdev, imaicl)) {
4687 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
4688 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
4689 dev->ib_dev.uverbs_cmd_mask |=
4690 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
4691 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4694 if (MLX5_CAP_GEN(mdev, xrc)) {
4695 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4696 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4697 dev->ib_dev.uverbs_cmd_mask |=
4698 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4699 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4702 dev->ib_dev.create_flow = mlx5_ib_create_flow;
4703 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4704 dev->ib_dev.uverbs_ex_cmd_mask |=
4705 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4706 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4708 err = init_node_data(dev);
4712 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4713 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
4714 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
4715 mutex_init(&dev->lb_mutex);
4720 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
4722 struct mlx5_core_dev *mdev = dev->mdev;
4723 enum rdma_link_layer ll;
4729 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4730 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4731 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4733 if (ll == IB_LINK_LAYER_ETHERNET) {
4734 for (i = 0; i < dev->num_ports; i++) {
4735 dev->roce[i].dev = dev;
4736 dev->roce[i].native_port_num = i + 1;
4737 dev->roce[i].last_port_state = IB_PORT_DOWN;
4740 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
4741 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4742 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4743 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
4744 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4745 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
4746 dev->ib_dev.uverbs_ex_cmd_mask |=
4747 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4748 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
4749 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4750 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4751 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
4752 err = mlx5_enable_eth(dev, port_num);
4760 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
4762 struct mlx5_core_dev *mdev = dev->mdev;
4763 enum rdma_link_layer ll;
4767 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4768 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4769 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4771 if (ll == IB_LINK_LAYER_ETHERNET) {
4772 mlx5_disable_eth(dev);
4773 mlx5_remove_netdev_notifier(dev, port_num);
4777 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
4779 return create_dev_resources(&dev->devr);
4782 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
4784 destroy_dev_resources(&dev->devr);
4787 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
4789 mlx5_ib_internal_fill_odp_caps(dev);
4791 return mlx5_ib_odp_init_one(dev);
4794 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
4796 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4797 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
4798 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
4800 return mlx5_ib_alloc_counters(dev);
4806 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
4808 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4809 mlx5_ib_dealloc_counters(dev);
4812 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4814 return mlx5_ib_init_cong_debugfs(dev,
4815 mlx5_core_native_port_num(dev->mdev) - 1);
4818 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4820 mlx5_ib_cleanup_cong_debugfs(dev,
4821 mlx5_core_native_port_num(dev->mdev) - 1);
4824 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4826 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4827 if (!dev->mdev->priv.uar)
4832 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4834 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4837 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4841 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4845 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4847 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4852 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4854 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4855 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4858 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4860 return ib_register_device(&dev->ib_dev, NULL);
4863 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4865 ib_unregister_device(&dev->ib_dev);
4868 static int mlx5_ib_stage_umr_res_init(struct mlx5_ib_dev *dev)
4870 return create_umr_res(dev);
4873 static void mlx5_ib_stage_umr_res_cleanup(struct mlx5_ib_dev *dev)
4875 destroy_umrc_res(dev);
4878 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4880 init_delay_drop(dev);
4885 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4887 cancel_delay_drop(dev);
4890 static int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
4895 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
4896 err = device_create_file(&dev->ib_dev.dev,
4897 mlx5_class_attributes[i]);
4905 static void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4906 const struct mlx5_ib_profile *profile,
4909 /* Number of stages to cleanup */
4912 if (profile->stage[stage].cleanup)
4913 profile->stage[stage].cleanup(dev);
4916 ib_dealloc_device((struct ib_device *)dev);
4919 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
4921 static void *__mlx5_ib_add(struct mlx5_core_dev *mdev,
4922 const struct mlx5_ib_profile *profile)
4924 struct mlx5_ib_dev *dev;
4928 printk_once(KERN_INFO "%s", mlx5_version);
4930 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
4935 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4936 MLX5_CAP_GEN(mdev, num_vhca_ports));
4938 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4939 if (profile->stage[i].init) {
4940 err = profile->stage[i].init(dev);
4946 dev->profile = profile;
4947 dev->ib_active = true;
4952 __mlx5_ib_remove(dev, profile, i);
4957 static const struct mlx5_ib_profile pf_profile = {
4958 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4959 mlx5_ib_stage_init_init,
4960 mlx5_ib_stage_init_cleanup),
4961 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4962 mlx5_ib_stage_caps_init,
4964 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4965 mlx5_ib_stage_roce_init,
4966 mlx5_ib_stage_roce_cleanup),
4967 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4968 mlx5_ib_stage_dev_res_init,
4969 mlx5_ib_stage_dev_res_cleanup),
4970 STAGE_CREATE(MLX5_IB_STAGE_ODP,
4971 mlx5_ib_stage_odp_init,
4973 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4974 mlx5_ib_stage_counters_init,
4975 mlx5_ib_stage_counters_cleanup),
4976 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4977 mlx5_ib_stage_cong_debugfs_init,
4978 mlx5_ib_stage_cong_debugfs_cleanup),
4979 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4980 mlx5_ib_stage_uar_init,
4981 mlx5_ib_stage_uar_cleanup),
4982 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4983 mlx5_ib_stage_bfrag_init,
4984 mlx5_ib_stage_bfrag_cleanup),
4985 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4986 mlx5_ib_stage_ib_reg_init,
4987 mlx5_ib_stage_ib_reg_cleanup),
4988 STAGE_CREATE(MLX5_IB_STAGE_UMR_RESOURCES,
4989 mlx5_ib_stage_umr_res_init,
4990 mlx5_ib_stage_umr_res_cleanup),
4991 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4992 mlx5_ib_stage_delay_drop_init,
4993 mlx5_ib_stage_delay_drop_cleanup),
4994 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
4995 mlx5_ib_stage_class_attr_init,
4999 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
5001 struct mlx5_ib_multiport_info *mpi;
5002 struct mlx5_ib_dev *dev;
5006 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5012 err = mlx5_query_nic_vport_system_image_guid(mdev,
5013 &mpi->sys_image_guid);
5019 mutex_lock(&mlx5_ib_multiport_mutex);
5020 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
5021 if (dev->sys_image_guid == mpi->sys_image_guid)
5022 bound = mlx5_ib_bind_slave_port(dev, mpi);
5025 rdma_roce_rescan_device(&dev->ib_dev);
5031 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5032 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
5034 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
5036 mutex_unlock(&mlx5_ib_multiport_mutex);
5041 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
5043 enum rdma_link_layer ll;
5046 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5047 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5049 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
5050 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
5052 return mlx5_ib_add_slave_port(mdev, port_num);
5055 return __mlx5_ib_add(mdev, &pf_profile);
5058 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
5060 struct mlx5_ib_multiport_info *mpi;
5061 struct mlx5_ib_dev *dev;
5063 if (mlx5_core_is_mp_slave(mdev)) {
5065 mutex_lock(&mlx5_ib_multiport_mutex);
5067 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
5068 list_del(&mpi->list);
5069 mutex_unlock(&mlx5_ib_multiport_mutex);
5074 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
5077 static struct mlx5_interface mlx5_ib_interface = {
5079 .remove = mlx5_ib_remove,
5080 .event = mlx5_ib_event,
5081 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5082 .pfault = mlx5_ib_pfault,
5084 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
5087 static int __init mlx5_ib_init(void)
5091 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
5092 if (!mlx5_ib_event_wq)
5097 err = mlx5_register_interface(&mlx5_ib_interface);
5102 static void __exit mlx5_ib_cleanup(void)
5104 mlx5_unregister_interface(&mlx5_ib_interface);
5105 destroy_workqueue(mlx5_ib_event_wq);
5108 module_init(mlx5_ib_init);
5109 module_exit(mlx5_ib_cleanup);