2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/kref.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_user_verbs.h>
36 #include <rdma/ib_cache.h>
39 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq)
41 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
43 ibcq->comp_handler(ibcq, ibcq->cq_context);
46 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
48 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
49 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
50 struct ib_cq *ibcq = &cq->ibcq;
51 struct ib_event event;
53 if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
54 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
59 if (ibcq->event_handler) {
60 event.device = &dev->ib_dev;
61 event.event = IB_EVENT_CQ_ERR;
62 event.element.cq = ibcq;
63 ibcq->event_handler(&event, ibcq->cq_context);
67 static void *get_cqe(struct mlx5_ib_cq *cq, int n)
69 return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n);
72 static u8 sw_ownership_bit(int n, int nent)
74 return (n & nent) ? 1 : 0;
77 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
79 void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
80 struct mlx5_cqe64 *cqe64;
82 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
84 if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) &&
85 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
92 static void *next_cqe_sw(struct mlx5_ib_cq *cq)
94 return get_sw_cqe(cq, cq->mcq.cons_index);
97 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
99 switch (wq->wr_data[idx]) {
103 case IB_WR_LOCAL_INV:
104 return IB_WC_LOCAL_INV;
110 pr_warn("unknown completion status\n");
115 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
116 struct mlx5_ib_wq *wq, int idx)
119 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
120 case MLX5_OPCODE_RDMA_WRITE_IMM:
121 wc->wc_flags |= IB_WC_WITH_IMM;
123 case MLX5_OPCODE_RDMA_WRITE:
124 wc->opcode = IB_WC_RDMA_WRITE;
126 case MLX5_OPCODE_SEND_IMM:
127 wc->wc_flags |= IB_WC_WITH_IMM;
129 case MLX5_OPCODE_SEND:
130 case MLX5_OPCODE_SEND_INVAL:
131 wc->opcode = IB_WC_SEND;
133 case MLX5_OPCODE_RDMA_READ:
134 wc->opcode = IB_WC_RDMA_READ;
135 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
137 case MLX5_OPCODE_ATOMIC_CS:
138 wc->opcode = IB_WC_COMP_SWAP;
141 case MLX5_OPCODE_ATOMIC_FA:
142 wc->opcode = IB_WC_FETCH_ADD;
145 case MLX5_OPCODE_ATOMIC_MASKED_CS:
146 wc->opcode = IB_WC_MASKED_COMP_SWAP;
149 case MLX5_OPCODE_ATOMIC_MASKED_FA:
150 wc->opcode = IB_WC_MASKED_FETCH_ADD;
153 case MLX5_OPCODE_UMR:
154 wc->opcode = get_umr_comp(wq, idx);
160 MLX5_GRH_IN_BUFFER = 1,
164 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
165 struct mlx5_ib_qp *qp)
167 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
168 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
169 struct mlx5_ib_srq *srq;
170 struct mlx5_ib_wq *wq;
176 if (qp->ibqp.srq || qp->ibqp.xrcd) {
177 struct mlx5_core_srq *msrq = NULL;
180 msrq = mlx5_core_get_srq(dev->mdev,
181 be32_to_cpu(cqe->srqn));
182 srq = to_mibsrq(msrq);
184 srq = to_msrq(qp->ibqp.srq);
187 wqe_ctr = be16_to_cpu(cqe->wqe_counter);
188 wc->wr_id = srq->wrid[wqe_ctr];
189 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
190 if (msrq && atomic_dec_and_test(&msrq->refcount))
191 complete(&msrq->free);
195 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
198 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
200 switch (cqe->op_own >> 4) {
201 case MLX5_CQE_RESP_WR_IMM:
202 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
203 wc->wc_flags = IB_WC_WITH_IMM;
204 wc->ex.imm_data = cqe->imm_inval_pkey;
206 case MLX5_CQE_RESP_SEND:
207 wc->opcode = IB_WC_RECV;
208 wc->wc_flags = IB_WC_IP_CSUM_OK;
209 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
210 (cqe->hds_ip_ext & CQE_L4_OK))))
213 case MLX5_CQE_RESP_SEND_IMM:
214 wc->opcode = IB_WC_RECV;
215 wc->wc_flags = IB_WC_WITH_IMM;
216 wc->ex.imm_data = cqe->imm_inval_pkey;
218 case MLX5_CQE_RESP_SEND_INV:
219 wc->opcode = IB_WC_RECV;
220 wc->wc_flags = IB_WC_WITH_INVALIDATE;
221 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
224 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
225 wc->dlid_path_bits = cqe->ml_path;
226 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
227 wc->wc_flags |= g ? IB_WC_GRH : 0;
228 if (unlikely(is_qp1(qp->ibqp.qp_type))) {
229 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
231 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
237 if (ll != IB_LINK_LAYER_ETHERNET) {
238 wc->slid = be16_to_cpu(cqe->slid);
239 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
244 vlan_present = cqe->l4_l3_hdr_type & 0x1;
245 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3;
247 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff;
248 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7;
249 wc->wc_flags |= IB_WC_WITH_VLAN;
254 switch (roce_packet_type) {
255 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
256 wc->network_hdr_type = RDMA_NETWORK_IB;
258 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
259 wc->network_hdr_type = RDMA_NETWORK_IPV6;
261 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
262 wc->network_hdr_type = RDMA_NETWORK_IPV4;
265 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
268 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
270 mlx5_ib_warn(dev, "dump error cqe\n");
271 mlx5_dump_err_cqe(dev->mdev, cqe);
274 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
275 struct mlx5_err_cqe *cqe,
280 switch (cqe->syndrome) {
281 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
282 wc->status = IB_WC_LOC_LEN_ERR;
284 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
285 wc->status = IB_WC_LOC_QP_OP_ERR;
287 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
288 wc->status = IB_WC_LOC_PROT_ERR;
290 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
292 wc->status = IB_WC_WR_FLUSH_ERR;
294 case MLX5_CQE_SYNDROME_MW_BIND_ERR:
295 wc->status = IB_WC_MW_BIND_ERR;
297 case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
298 wc->status = IB_WC_BAD_RESP_ERR;
300 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
301 wc->status = IB_WC_LOC_ACCESS_ERR;
303 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
304 wc->status = IB_WC_REM_INV_REQ_ERR;
306 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
307 wc->status = IB_WC_REM_ACCESS_ERR;
309 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
310 wc->status = IB_WC_REM_OP_ERR;
312 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
313 wc->status = IB_WC_RETRY_EXC_ERR;
316 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
317 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
320 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
321 wc->status = IB_WC_REM_ABORT_ERR;
324 wc->status = IB_WC_GENERAL_ERR;
328 wc->vendor_err = cqe->vendor_err_synd;
333 static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx)
335 /* TBD: waiting decision
340 static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx)
342 struct mlx5_wqe_data_seg *dpseg;
345 dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) +
346 sizeof(struct mlx5_wqe_raddr_seg) +
347 sizeof(struct mlx5_wqe_atomic_seg);
348 addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr);
352 static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
359 if (!is_atomic_response(qp, idx))
362 byte_count = be32_to_cpu(cqe64->byte_cnt);
363 addr = mlx5_get_atomic_laddr(qp, idx);
365 if (byte_count == 4) {
366 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr));
368 for (i = 0; i < byte_count; i += 8) {
369 *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr));
377 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
383 idx = tail & (qp->sq.wqe_cnt - 1);
384 handle_atomic(qp, cqe64, idx);
388 tail = qp->sq.w_list[idx].next;
390 tail = qp->sq.w_list[idx].next;
391 qp->sq.last_poll = tail;
394 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
396 mlx5_frag_buf_free(dev->mdev, &buf->frag_buf);
399 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
400 struct ib_sig_err *item)
402 u16 syndrome = be16_to_cpu(cqe->syndrome);
404 #define GUARD_ERR (1 << 13)
405 #define APPTAG_ERR (1 << 12)
406 #define REFTAG_ERR (1 << 11)
408 if (syndrome & GUARD_ERR) {
409 item->err_type = IB_SIG_BAD_GUARD;
410 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
411 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
413 if (syndrome & REFTAG_ERR) {
414 item->err_type = IB_SIG_BAD_REFTAG;
415 item->expected = be32_to_cpu(cqe->expected_reftag);
416 item->actual = be32_to_cpu(cqe->actual_reftag);
418 if (syndrome & APPTAG_ERR) {
419 item->err_type = IB_SIG_BAD_APPTAG;
420 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
421 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
423 pr_err("Got signature completion error with bad syndrome %04x\n",
427 item->sig_err_offset = be64_to_cpu(cqe->err_offset);
428 item->key = be32_to_cpu(cqe->mkey);
431 static void sw_send_comp(struct mlx5_ib_qp *qp, int num_entries,
432 struct ib_wc *wc, int *npolled)
434 struct mlx5_ib_wq *wq;
441 cur = wq->head - wq->tail;
447 for (i = 0; i < cur && np < num_entries; i++) {
448 idx = wq->last_poll & (wq->wqe_cnt - 1);
449 wc->wr_id = wq->wrid[idx];
450 wc->status = IB_WC_WR_FLUSH_ERR;
451 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
456 wq->last_poll = wq->w_list[idx].next;
461 static void sw_recv_comp(struct mlx5_ib_qp *qp, int num_entries,
462 struct ib_wc *wc, int *npolled)
464 struct mlx5_ib_wq *wq;
470 cur = wq->head - wq->tail;
476 for (i = 0; i < cur && np < num_entries; i++) {
477 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
478 wc->status = IB_WC_WR_FLUSH_ERR;
479 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
488 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
489 struct ib_wc *wc, int *npolled)
491 struct mlx5_ib_qp *qp;
494 /* Find uncompleted WQEs belonging to that cq and return mmics ones */
495 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
496 sw_send_comp(qp, num_entries, wc + *npolled, npolled);
497 if (*npolled >= num_entries)
501 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
502 sw_recv_comp(qp, num_entries, wc + *npolled, npolled);
503 if (*npolled >= num_entries)
508 static int mlx5_poll_one(struct mlx5_ib_cq *cq,
509 struct mlx5_ib_qp **cur_qp,
512 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
513 struct mlx5_err_cqe *err_cqe;
514 struct mlx5_cqe64 *cqe64;
515 struct mlx5_core_qp *mqp;
516 struct mlx5_ib_wq *wq;
517 struct mlx5_sig_err_cqe *sig_err_cqe;
518 struct mlx5_core_mkey *mmkey;
519 struct mlx5_ib_mr *mr;
527 cqe = next_cqe_sw(cq);
531 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
533 ++cq->mcq.cons_index;
535 /* Make sure we read CQ entry contents after we've checked the
540 opcode = cqe64->op_own >> 4;
541 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
542 if (likely(cq->resize_buf)) {
543 free_cq_buf(dev, &cq->buf);
544 cq->buf = *cq->resize_buf;
545 kfree(cq->resize_buf);
546 cq->resize_buf = NULL;
549 mlx5_ib_warn(dev, "unexpected resize cqe\n");
553 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
554 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
555 /* We do not have to take the QP table lock here,
556 * because CQs will be locked while QPs are removed
559 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
560 *cur_qp = to_mibqp(mqp);
563 wc->qp = &(*cur_qp)->ibqp;
567 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
568 idx = wqe_ctr & (wq->wqe_cnt - 1);
569 handle_good_req(wc, cqe64, wq, idx);
570 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
571 wc->wr_id = wq->wrid[idx];
572 wq->tail = wq->wqe_head[idx] + 1;
573 wc->status = IB_WC_SUCCESS;
575 case MLX5_CQE_RESP_WR_IMM:
576 case MLX5_CQE_RESP_SEND:
577 case MLX5_CQE_RESP_SEND_IMM:
578 case MLX5_CQE_RESP_SEND_INV:
579 handle_responder(wc, cqe64, *cur_qp);
580 wc->status = IB_WC_SUCCESS;
582 case MLX5_CQE_RESIZE_CQ:
584 case MLX5_CQE_REQ_ERR:
585 case MLX5_CQE_RESP_ERR:
586 err_cqe = (struct mlx5_err_cqe *)cqe64;
587 mlx5_handle_error_cqe(dev, err_cqe, wc);
588 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
589 opcode == MLX5_CQE_REQ_ERR ?
590 "Requestor" : "Responder", cq->mcq.cqn);
591 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
592 err_cqe->syndrome, err_cqe->vendor_err_synd);
593 if (opcode == MLX5_CQE_REQ_ERR) {
595 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
596 idx = wqe_ctr & (wq->wqe_cnt - 1);
597 wc->wr_id = wq->wrid[idx];
598 wq->tail = wq->wqe_head[idx] + 1;
600 struct mlx5_ib_srq *srq;
602 if ((*cur_qp)->ibqp.srq) {
603 srq = to_msrq((*cur_qp)->ibqp.srq);
604 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
605 wc->wr_id = srq->wrid[wqe_ctr];
606 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
609 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
614 case MLX5_CQE_SIG_ERR:
615 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
617 read_lock(&dev->mdev->priv.mkey_table.lock);
618 mmkey = __mlx5_mr_lookup(dev->mdev,
619 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
620 mr = to_mibmr(mmkey);
621 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
622 mr->sig->sig_err_exists = true;
623 mr->sig->sigerr_count++;
625 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
626 cq->mcq.cqn, mr->sig->err_item.key,
627 mr->sig->err_item.err_type,
628 mr->sig->err_item.sig_err_offset,
629 mr->sig->err_item.expected,
630 mr->sig->err_item.actual);
632 read_unlock(&dev->mdev->priv.mkey_table.lock);
639 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
640 struct ib_wc *wc, bool is_fatal_err)
642 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
643 struct mlx5_ib_wc *soft_wc, *next;
646 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
647 if (npolled >= num_entries)
650 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
653 if (unlikely(is_fatal_err)) {
654 soft_wc->wc.status = IB_WC_WR_FLUSH_ERR;
655 soft_wc->wc.vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
657 wc[npolled++] = soft_wc->wc;
658 list_del(&soft_wc->list);
665 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
667 struct mlx5_ib_cq *cq = to_mcq(ibcq);
668 struct mlx5_ib_qp *cur_qp = NULL;
669 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
670 struct mlx5_core_dev *mdev = dev->mdev;
675 spin_lock_irqsave(&cq->lock, flags);
676 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
677 /* make sure no soft wqe's are waiting */
678 if (unlikely(!list_empty(&cq->wc_list)))
679 soft_polled = poll_soft_wc(cq, num_entries, wc, true);
681 mlx5_ib_poll_sw_comp(cq, num_entries - soft_polled,
682 wc + soft_polled, &npolled);
686 if (unlikely(!list_empty(&cq->wc_list)))
687 soft_polled = poll_soft_wc(cq, num_entries, wc, false);
689 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
690 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
695 mlx5_cq_set_ci(&cq->mcq);
697 spin_unlock_irqrestore(&cq->lock, flags);
699 return soft_polled + npolled;
702 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
704 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
705 struct mlx5_ib_cq *cq = to_mcq(ibcq);
706 void __iomem *uar_page = mdev->priv.uar->map;
707 unsigned long irq_flags;
710 spin_lock_irqsave(&cq->lock, irq_flags);
711 if (cq->notify_flags != IB_CQ_NEXT_COMP)
712 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
714 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
716 spin_unlock_irqrestore(&cq->lock, irq_flags);
718 mlx5_cq_arm(&cq->mcq,
719 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
720 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
721 uar_page, to_mcq(ibcq)->mcq.cons_index);
726 static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev,
727 struct mlx5_ib_cq_buf *buf,
731 struct mlx5_frag_buf *frag_buf = &buf->frag_buf;
732 u8 log_wq_stride = 6 + (cqe_size == 128 ? 1 : 0);
733 u8 log_wq_sz = ilog2(cqe_size);
736 err = mlx5_frag_buf_alloc_node(dev->mdev,
739 dev->mdev->priv.numa_node);
743 mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc);
745 buf->cqe_size = cqe_size;
752 MLX5_CQE_RES_FORMAT_HASH = 0,
753 MLX5_CQE_RES_FORMAT_CSUM = 1,
754 MLX5_CQE_RES_FORMAT_CSUM_STRIDX = 3,
757 static int mini_cqe_res_format_to_hw(struct mlx5_ib_dev *dev, u8 format)
760 case MLX5_IB_CQE_RES_FORMAT_HASH:
761 return MLX5_CQE_RES_FORMAT_HASH;
762 case MLX5_IB_CQE_RES_FORMAT_CSUM:
763 return MLX5_CQE_RES_FORMAT_CSUM;
764 case MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX:
765 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
766 return MLX5_CQE_RES_FORMAT_CSUM_STRIDX;
773 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
774 struct ib_ucontext *context, struct mlx5_ib_cq *cq,
775 int entries, u32 **cqb,
776 int *cqe_size, int *index, int *inlen)
778 struct mlx5_ib_create_cq ucmd = {};
787 ucmdlen = udata->inlen < sizeof(ucmd) ?
788 (sizeof(ucmd) - sizeof(ucmd.flags)) : sizeof(ucmd);
790 if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
793 if (ucmdlen == sizeof(ucmd) &&
794 (ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD)))
797 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
800 *cqe_size = ucmd.cqe_size;
802 cq->buf.umem = ib_umem_get(context, ucmd.buf_addr,
803 entries * ucmd.cqe_size,
804 IB_ACCESS_LOCAL_WRITE, 1);
805 if (IS_ERR(cq->buf.umem)) {
806 err = PTR_ERR(cq->buf.umem);
810 err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
815 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift,
817 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
818 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
820 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
821 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont;
822 *cqb = kvzalloc(*inlen, GFP_KERNEL);
828 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
829 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0);
831 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
832 MLX5_SET(cqc, cqc, log_page_size,
833 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
835 *index = to_mucontext(context)->bfregi.sys_pages[0];
837 if (ucmd.cqe_comp_en == 1) {
840 if (!((*cqe_size == 128 &&
841 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) ||
843 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) {
845 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n",
851 mini_cqe_res_format_to_hw(dev,
852 ucmd.cqe_comp_res_format);
853 if (mini_cqe_format < 0) {
854 err = mini_cqe_format;
855 mlx5_ib_dbg(dev, "CQE compression res format %d error: %d\n",
856 ucmd.cqe_comp_res_format, err);
860 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
861 MLX5_SET(cqc, cqc, mini_cqe_res_format, mini_cqe_format);
864 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) {
865 if (*cqe_size != 128 ||
866 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) {
869 "CQE padding is not supported for CQE size of %dB!\n",
874 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD;
877 MLX5_SET(create_cq_in, *cqb, uid, to_mucontext(context)->devx_uid);
884 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
887 ib_umem_release(cq->buf.umem);
891 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context)
893 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
894 ib_umem_release(cq->buf.umem);
897 static void init_cq_frag_buf(struct mlx5_ib_cq *cq,
898 struct mlx5_ib_cq_buf *buf)
902 struct mlx5_cqe64 *cqe64;
904 for (i = 0; i < buf->nent; i++) {
905 cqe = get_cqe(cq, i);
906 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
907 cqe64->op_own = MLX5_CQE_INVALID << 4;
911 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
912 int entries, int cqe_size,
913 u32 **cqb, int *index, int *inlen)
919 err = mlx5_db_alloc(dev->mdev, &cq->db);
923 cq->mcq.set_ci_db = cq->db.db;
924 cq->mcq.arm_db = cq->db.db + 1;
925 cq->mcq.cqe_sz = cqe_size;
927 err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size);
931 init_cq_frag_buf(cq, &cq->buf);
933 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
934 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) *
935 cq->buf.frag_buf.npages;
936 *cqb = kvzalloc(*inlen, GFP_KERNEL);
942 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
943 mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas);
945 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
946 MLX5_SET(cqc, cqc, log_page_size,
947 cq->buf.frag_buf.page_shift -
948 MLX5_ADAPTER_PAGE_SHIFT);
950 *index = dev->mdev->priv.uar->index;
955 free_cq_buf(dev, &cq->buf);
958 mlx5_db_free(dev->mdev, &cq->db);
962 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
964 free_cq_buf(dev, &cq->buf);
965 mlx5_db_free(dev->mdev, &cq->db);
968 static void notify_soft_wc_handler(struct work_struct *work)
970 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
973 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
976 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
977 const struct ib_cq_init_attr *attr,
978 struct ib_ucontext *context,
979 struct ib_udata *udata)
981 int entries = attr->cqe;
982 int vector = attr->comp_vector;
983 struct mlx5_ib_dev *dev = to_mdev(ibdev);
984 struct mlx5_ib_cq *cq;
985 int uninitialized_var(index);
986 int uninitialized_var(inlen);
995 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
996 return ERR_PTR(-EINVAL);
998 if (check_cq_create_flags(attr->flags))
999 return ERR_PTR(-EOPNOTSUPP);
1001 entries = roundup_pow_of_two(entries + 1);
1002 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
1003 return ERR_PTR(-EINVAL);
1005 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
1007 return ERR_PTR(-ENOMEM);
1009 cq->ibcq.cqe = entries - 1;
1010 mutex_init(&cq->resize_mutex);
1011 spin_lock_init(&cq->lock);
1012 cq->resize_buf = NULL;
1013 cq->resize_umem = NULL;
1014 cq->create_flags = attr->flags;
1015 INIT_LIST_HEAD(&cq->list_send_qp);
1016 INIT_LIST_HEAD(&cq->list_recv_qp);
1019 err = create_cq_user(dev, udata, context, cq, entries,
1020 &cqb, &cqe_size, &index, &inlen);
1024 cqe_size = cache_line_size() == 128 ? 128 : 64;
1025 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
1030 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
1033 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
1037 cq->cqe_size = cqe_size;
1039 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
1040 MLX5_SET(cqc, cqc, cqe_sz,
1041 cqe_sz_to_mlx_sz(cqe_size,
1043 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1044 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1045 MLX5_SET(cqc, cqc, uar_page, index);
1046 MLX5_SET(cqc, cqc, c_eqn, eqn);
1047 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma);
1048 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN)
1049 MLX5_SET(cqc, cqc, oi, 1);
1051 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen);
1055 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
1056 cq->mcq.irqn = irqn;
1058 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
1060 cq->mcq.comp = mlx5_ib_cq_comp;
1061 cq->mcq.event = mlx5_ib_cq_event;
1063 INIT_LIST_HEAD(&cq->wc_list);
1066 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
1076 mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
1081 destroy_cq_user(cq, context);
1083 destroy_cq_kernel(dev, cq);
1088 return ERR_PTR(err);
1092 int mlx5_ib_destroy_cq(struct ib_cq *cq)
1094 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1095 struct mlx5_ib_cq *mcq = to_mcq(cq);
1096 struct ib_ucontext *context = NULL;
1099 context = cq->uobject->context;
1101 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
1103 destroy_cq_user(mcq, context);
1105 destroy_cq_kernel(dev, mcq);
1112 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
1114 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
1117 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1119 struct mlx5_cqe64 *cqe64, *dest64;
1128 /* First we need to find the current producer index, so we
1129 * know where to start cleaning from. It doesn't matter if HW
1130 * adds new entries after this loop -- the QP we're worried
1131 * about is already in RESET, so the new entries won't come
1132 * from our QP and therefore don't need to be checked.
1134 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1135 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1138 /* Now sweep backwards through the CQ, removing CQ entries
1139 * that match our QP by copying older entries on top of them.
1141 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1142 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1143 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
1144 if (is_equal_rsn(cqe64, rsn)) {
1145 if (srq && (ntohl(cqe64->srqn) & 0xffffff))
1146 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1148 } else if (nfreed) {
1149 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1150 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1151 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1152 memcpy(dest, cqe, cq->mcq.cqe_sz);
1153 dest64->op_own = owner_bit |
1154 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1159 cq->mcq.cons_index += nfreed;
1160 /* Make sure update of buffer contents is done before
1161 * updating consumer index.
1164 mlx5_cq_set_ci(&cq->mcq);
1168 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1173 spin_lock_irq(&cq->lock);
1174 __mlx5_ib_cq_clean(cq, qpn, srq);
1175 spin_unlock_irq(&cq->lock);
1178 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1180 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1181 struct mlx5_ib_cq *mcq = to_mcq(cq);
1184 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1187 if (cq_period > MLX5_MAX_CQ_PERIOD)
1190 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1191 cq_period, cq_count);
1193 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1198 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1199 int entries, struct ib_udata *udata, int *npas,
1200 int *page_shift, int *cqe_size)
1202 struct mlx5_ib_resize_cq ucmd;
1203 struct ib_umem *umem;
1206 struct ib_ucontext *context = cq->buf.umem->context;
1208 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1212 if (ucmd.reserved0 || ucmd.reserved1)
1215 /* check multiplication overflow */
1216 if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1)
1219 umem = ib_umem_get(context, ucmd.buf_addr,
1220 (size_t)ucmd.cqe_size * entries,
1221 IB_ACCESS_LOCAL_WRITE, 1);
1223 err = PTR_ERR(umem);
1227 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift,
1230 cq->resize_umem = umem;
1231 *cqe_size = ucmd.cqe_size;
1236 static void un_resize_user(struct mlx5_ib_cq *cq)
1238 ib_umem_release(cq->resize_umem);
1241 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1242 int entries, int cqe_size)
1246 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1247 if (!cq->resize_buf)
1250 err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size);
1254 init_cq_frag_buf(cq, cq->resize_buf);
1259 kfree(cq->resize_buf);
1263 static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
1265 free_cq_buf(dev, cq->resize_buf);
1266 cq->resize_buf = NULL;
1269 static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1271 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1272 struct mlx5_cqe64 *scqe64;
1273 struct mlx5_cqe64 *dcqe64;
1282 ssize = cq->buf.cqe_size;
1283 dsize = cq->resize_buf->cqe_size;
1284 if (ssize != dsize) {
1285 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1289 i = cq->mcq.cons_index;
1290 scqe = get_sw_cqe(cq, i);
1291 scqe64 = ssize == 64 ? scqe : scqe + 64;
1294 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1298 while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) {
1299 dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc,
1300 (i + 1) & cq->resize_buf->nent);
1301 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1302 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1303 memcpy(dcqe, scqe, dsize);
1304 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1307 scqe = get_sw_cqe(cq, i);
1308 scqe64 = ssize == 64 ? scqe : scqe + 64;
1310 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1314 if (scqe == start_cqe) {
1315 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1320 ++cq->mcq.cons_index;
1324 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1326 struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1327 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1335 int uninitialized_var(cqe_size);
1336 unsigned long flags;
1338 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1339 pr_info("Firmware does not support resize CQ\n");
1344 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1345 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1347 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
1351 entries = roundup_pow_of_two(entries + 1);
1352 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1355 if (entries == ibcq->cqe + 1)
1358 mutex_lock(&cq->resize_mutex);
1360 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1364 err = resize_kernel(dev, cq, entries, cqe_size);
1366 struct mlx5_frag_buf *frag_buf = &cq->resize_buf->frag_buf;
1368 npas = frag_buf->npages;
1369 page_shift = frag_buf->page_shift;
1376 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) +
1377 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas;
1379 in = kvzalloc(inlen, GFP_KERNEL);
1385 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas);
1387 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1390 mlx5_fill_page_frag_array(&cq->resize_buf->frag_buf, pas);
1392 MLX5_SET(modify_cq_in, in,
1393 modify_field_select_resize_field_select.resize_field_select.resize_field_select,
1394 MLX5_MODIFY_CQ_MASK_LOG_SIZE |
1395 MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1396 MLX5_MODIFY_CQ_MASK_PG_SIZE);
1398 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
1400 MLX5_SET(cqc, cqc, log_page_size,
1401 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1402 MLX5_SET(cqc, cqc, cqe_sz,
1403 cqe_sz_to_mlx_sz(cqe_size,
1405 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1406 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1408 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
1409 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn);
1411 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1416 cq->ibcq.cqe = entries - 1;
1417 ib_umem_release(cq->buf.umem);
1418 cq->buf.umem = cq->resize_umem;
1419 cq->resize_umem = NULL;
1421 struct mlx5_ib_cq_buf tbuf;
1424 spin_lock_irqsave(&cq->lock, flags);
1425 if (cq->resize_buf) {
1426 err = copy_resize_cqes(cq);
1429 cq->buf = *cq->resize_buf;
1430 kfree(cq->resize_buf);
1431 cq->resize_buf = NULL;
1435 cq->ibcq.cqe = entries - 1;
1436 spin_unlock_irqrestore(&cq->lock, flags);
1438 free_cq_buf(dev, &tbuf);
1440 mutex_unlock(&cq->resize_mutex);
1452 un_resize_kernel(dev, cq);
1454 mutex_unlock(&cq->resize_mutex);
1458 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq)
1460 struct mlx5_ib_cq *cq;
1466 return cq->cqe_size;
1469 /* Called from atomic context */
1470 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1472 struct mlx5_ib_wc *soft_wc;
1473 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1474 unsigned long flags;
1476 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1481 spin_lock_irqsave(&cq->lock, flags);
1482 list_add_tail(&soft_wc->list, &cq->wc_list);
1483 if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1484 wc->status != IB_WC_SUCCESS) {
1485 cq->notify_flags = 0;
1486 schedule_work(&cq->notify_work);
1488 spin_unlock_irqrestore(&cq->lock, flags);