2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <rdma/ib_cache.h>
34 #include <rdma/ib_pack.h>
36 #include <linux/mlx4/qp.h>
42 MLX4_IB_ACK_REQ_FREQ = 8,
46 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
47 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
52 * Largest possible UD header: send with GRH and immediate data.
54 MLX4_IB_UD_HEADER_SIZE = 72
62 struct ib_ud_header ud_header;
63 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
67 MLX4_IB_MIN_SQ_STRIDE = 6
70 static const __be32 mlx4_ib_opcode[] = {
71 [IB_WR_SEND] = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
72 [IB_WR_SEND_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
73 [IB_WR_RDMA_WRITE] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
74 [IB_WR_RDMA_WRITE_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
75 [IB_WR_RDMA_READ] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
76 [IB_WR_ATOMIC_CMP_AND_SWP] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
77 [IB_WR_ATOMIC_FETCH_AND_ADD] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
80 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
82 return container_of(mqp, struct mlx4_ib_sqp, qp);
85 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
87 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
88 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
91 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
93 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
94 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
97 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
99 return mlx4_buf_offset(&qp->buf, offset);
102 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
104 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
107 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
109 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
113 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
114 * first four bytes of every 64 byte chunk with 0xffffffff, except for
115 * the very first chunk of the WQE.
117 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
119 u32 *wqe = get_send_wqe(qp, n);
122 for (i = 16; i < 1 << (qp->sq.wqe_shift - 2); i += 16)
126 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
128 struct ib_event event;
129 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
131 if (type == MLX4_EVENT_TYPE_PATH_MIG)
132 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
134 if (ibqp->event_handler) {
135 event.device = ibqp->device;
136 event.element.qp = ibqp;
138 case MLX4_EVENT_TYPE_PATH_MIG:
139 event.event = IB_EVENT_PATH_MIG;
141 case MLX4_EVENT_TYPE_COMM_EST:
142 event.event = IB_EVENT_COMM_EST;
144 case MLX4_EVENT_TYPE_SQ_DRAINED:
145 event.event = IB_EVENT_SQ_DRAINED;
147 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
148 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
150 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
151 event.event = IB_EVENT_QP_FATAL;
153 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
154 event.event = IB_EVENT_PATH_MIG_ERR;
156 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
157 event.event = IB_EVENT_QP_REQ_ERR;
159 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
160 event.event = IB_EVENT_QP_ACCESS_ERR;
163 printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
164 "on QP %06x\n", type, qp->qpn);
168 ibqp->event_handler(&event, ibqp->qp_context);
172 static int send_wqe_overhead(enum ib_qp_type type)
175 * UD WQEs must have a datagram segment.
176 * RC and UC WQEs might have a remote address segment.
177 * MLX WQEs need two extra inline data segments (for the UD
178 * header and space for the ICRC).
182 return sizeof (struct mlx4_wqe_ctrl_seg) +
183 sizeof (struct mlx4_wqe_datagram_seg);
185 return sizeof (struct mlx4_wqe_ctrl_seg) +
186 sizeof (struct mlx4_wqe_raddr_seg);
188 return sizeof (struct mlx4_wqe_ctrl_seg) +
189 sizeof (struct mlx4_wqe_atomic_seg) +
190 sizeof (struct mlx4_wqe_raddr_seg);
193 return sizeof (struct mlx4_wqe_ctrl_seg) +
194 ALIGN(MLX4_IB_UD_HEADER_SIZE +
195 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
197 sizeof (struct mlx4_wqe_inline_seg),
198 sizeof (struct mlx4_wqe_data_seg)) +
200 sizeof (struct mlx4_wqe_inline_seg),
201 sizeof (struct mlx4_wqe_data_seg));
203 return sizeof (struct mlx4_wqe_ctrl_seg);
207 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
208 int is_user, int has_srq, struct mlx4_ib_qp *qp)
210 /* Sanity check RQ size before proceeding */
211 if (cap->max_recv_wr > dev->dev->caps.max_wqes ||
212 cap->max_recv_sge > dev->dev->caps.max_rq_sg)
216 /* QPs attached to an SRQ should have no RQ */
217 if (cap->max_recv_wr)
220 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
222 /* HW requires >= 1 RQ entry with >= 1 gather entry */
223 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
226 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
227 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
228 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
231 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
232 cap->max_recv_sge = qp->rq.max_gs;
237 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
238 enum ib_qp_type type, struct mlx4_ib_qp *qp)
240 /* Sanity check SQ size before proceeding */
241 if (cap->max_send_wr > dev->dev->caps.max_wqes ||
242 cap->max_send_sge > dev->dev->caps.max_sq_sg ||
243 cap->max_inline_data + send_wqe_overhead(type) +
244 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
248 * For MLX transport we need 2 extra S/G entries:
249 * one for the header and one for the checksum at the end
251 if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
252 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
255 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(max(cap->max_send_sge *
256 sizeof (struct mlx4_wqe_data_seg),
257 cap->max_inline_data +
258 sizeof (struct mlx4_wqe_inline_seg)) +
259 send_wqe_overhead(type)));
260 qp->sq.max_gs = ((1 << qp->sq.wqe_shift) - send_wqe_overhead(type)) /
261 sizeof (struct mlx4_wqe_data_seg);
264 * We need to leave 2 KB + 1 WQE of headroom in the SQ to
265 * allow HW to prefetch.
267 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + 1;
268 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr + qp->sq_spare_wqes);
270 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
271 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
272 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
274 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
276 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
280 cap->max_send_wr = qp->sq.max_post = qp->sq.wqe_cnt - qp->sq_spare_wqes;
281 cap->max_send_sge = qp->sq.max_gs;
282 /* We don't support inline sends for kernel QPs (yet) */
283 cap->max_inline_data = 0;
288 static int set_user_sq_size(struct mlx4_ib_dev *dev,
289 struct mlx4_ib_qp *qp,
290 struct mlx4_ib_create_qp *ucmd)
292 /* Sanity check SQ size before proceeding */
293 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
294 ucmd->log_sq_stride >
295 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
296 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
299 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
300 qp->sq.wqe_shift = ucmd->log_sq_stride;
302 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
303 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
308 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
309 struct ib_qp_init_attr *init_attr,
310 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
314 mutex_init(&qp->mutex);
315 spin_lock_init(&qp->sq.lock);
316 spin_lock_init(&qp->rq.lock);
318 qp->state = IB_QPS_RESET;
319 qp->atomic_rd_en = 0;
327 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
332 struct mlx4_ib_create_qp ucmd;
334 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
339 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
341 err = set_user_sq_size(dev, qp, &ucmd);
345 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
347 if (IS_ERR(qp->umem)) {
348 err = PTR_ERR(qp->umem);
352 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
353 ilog2(qp->umem->page_size), &qp->mtt);
357 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
361 if (!init_attr->srq) {
362 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
363 ucmd.db_addr, &qp->db);
368 qp->sq_no_prefetch = 0;
370 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
374 if (!init_attr->srq) {
375 err = mlx4_ib_db_alloc(dev, &qp->db, 0);
382 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
387 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
392 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
396 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
397 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
399 if (!qp->sq.wrid || !qp->rq.wrid) {
405 err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
410 * Hardware wants QPN written in big-endian order (after
411 * shifting) for send doorbell. Precompute this value to save
412 * a little bit when posting sends.
414 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
416 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
417 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
419 qp->sq_signal_bits = 0;
421 qp->mqp.event = mlx4_ib_qp_event;
428 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context),
436 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
440 ib_umem_release(qp->umem);
442 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
445 if (!pd->uobject && !init_attr->srq)
446 mlx4_ib_db_free(dev, &qp->db);
452 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
455 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
456 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
457 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
458 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
459 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
460 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
461 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
466 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
468 if (send_cq == recv_cq)
469 spin_lock_irq(&send_cq->lock);
470 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
471 spin_lock_irq(&send_cq->lock);
472 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
474 spin_lock_irq(&recv_cq->lock);
475 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
479 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
481 if (send_cq == recv_cq)
482 spin_unlock_irq(&send_cq->lock);
483 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
484 spin_unlock(&recv_cq->lock);
485 spin_unlock_irq(&send_cq->lock);
487 spin_unlock(&send_cq->lock);
488 spin_unlock_irq(&recv_cq->lock);
492 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
495 struct mlx4_ib_cq *send_cq, *recv_cq;
497 if (qp->state != IB_QPS_RESET)
498 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
499 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
500 printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
503 send_cq = to_mcq(qp->ibqp.send_cq);
504 recv_cq = to_mcq(qp->ibqp.recv_cq);
506 mlx4_ib_lock_cqs(send_cq, recv_cq);
509 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
510 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
511 if (send_cq != recv_cq)
512 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
515 mlx4_qp_remove(dev->dev, &qp->mqp);
517 mlx4_ib_unlock_cqs(send_cq, recv_cq);
519 mlx4_qp_free(dev->dev, &qp->mqp);
520 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
524 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
526 ib_umem_release(qp->umem);
530 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
532 mlx4_ib_db_free(dev, &qp->db);
536 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
537 struct ib_qp_init_attr *init_attr,
538 struct ib_udata *udata)
540 struct mlx4_ib_dev *dev = to_mdev(pd->device);
541 struct mlx4_ib_sqp *sqp;
542 struct mlx4_ib_qp *qp;
545 switch (init_attr->qp_type) {
550 qp = kmalloc(sizeof *qp, GFP_KERNEL);
552 return ERR_PTR(-ENOMEM);
554 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
560 qp->ibqp.qp_num = qp->mqp.qpn;
567 /* Userspace is not allowed to create special QPs: */
569 return ERR_PTR(-EINVAL);
571 sqp = kmalloc(sizeof *sqp, GFP_KERNEL);
573 return ERR_PTR(-ENOMEM);
577 err = create_qp_common(dev, pd, init_attr, udata,
578 dev->dev->caps.sqp_start +
579 (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
580 init_attr->port_num - 1,
587 qp->port = init_attr->port_num;
588 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
593 /* Don't support raw QPs */
594 return ERR_PTR(-EINVAL);
600 int mlx4_ib_destroy_qp(struct ib_qp *qp)
602 struct mlx4_ib_dev *dev = to_mdev(qp->device);
603 struct mlx4_ib_qp *mqp = to_mqp(qp);
605 if (is_qp0(dev, mqp))
606 mlx4_CLOSE_PORT(dev->dev, mqp->port);
608 destroy_qp_common(dev, mqp, !!qp->pd->uobject);
610 if (is_sqp(dev, mqp))
618 static int to_mlx4_st(enum ib_qp_type type)
621 case IB_QPT_RC: return MLX4_QP_ST_RC;
622 case IB_QPT_UC: return MLX4_QP_ST_UC;
623 case IB_QPT_UD: return MLX4_QP_ST_UD;
625 case IB_QPT_GSI: return MLX4_QP_ST_MLX;
630 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
635 u32 hw_access_flags = 0;
637 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
638 dest_rd_atomic = attr->max_dest_rd_atomic;
640 dest_rd_atomic = qp->resp_depth;
642 if (attr_mask & IB_QP_ACCESS_FLAGS)
643 access_flags = attr->qp_access_flags;
645 access_flags = qp->atomic_rd_en;
648 access_flags &= IB_ACCESS_REMOTE_WRITE;
650 if (access_flags & IB_ACCESS_REMOTE_READ)
651 hw_access_flags |= MLX4_QP_BIT_RRE;
652 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
653 hw_access_flags |= MLX4_QP_BIT_RAE;
654 if (access_flags & IB_ACCESS_REMOTE_WRITE)
655 hw_access_flags |= MLX4_QP_BIT_RWE;
657 return cpu_to_be32(hw_access_flags);
660 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
663 if (attr_mask & IB_QP_PKEY_INDEX)
664 sqp->pkey_index = attr->pkey_index;
665 if (attr_mask & IB_QP_QKEY)
666 sqp->qkey = attr->qkey;
667 if (attr_mask & IB_QP_SQ_PSN)
668 sqp->send_psn = attr->sq_psn;
671 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
673 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
676 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
677 struct mlx4_qp_path *path, u8 port)
679 path->grh_mylmc = ah->src_path_bits & 0x7f;
680 path->rlid = cpu_to_be16(ah->dlid);
681 if (ah->static_rate) {
682 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
683 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
684 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
687 path->static_rate = 0;
688 path->counter_index = 0xff;
690 if (ah->ah_flags & IB_AH_GRH) {
691 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
692 printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
693 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
697 path->grh_mylmc |= 1 << 7;
698 path->mgid_index = ah->grh.sgid_index;
699 path->hop_limit = ah->grh.hop_limit;
700 path->tclass_flowlabel =
701 cpu_to_be32((ah->grh.traffic_class << 20) |
702 (ah->grh.flow_label));
703 memcpy(path->rgid, ah->grh.dgid.raw, 16);
706 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
707 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
712 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
713 const struct ib_qp_attr *attr, int attr_mask,
714 enum ib_qp_state cur_state, enum ib_qp_state new_state)
716 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
717 struct mlx4_ib_qp *qp = to_mqp(ibqp);
718 struct mlx4_qp_context *context;
719 enum mlx4_qp_optpar optpar = 0;
723 context = kzalloc(sizeof *context, GFP_KERNEL);
727 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
728 (to_mlx4_st(ibqp->qp_type) << 16));
729 context->flags |= cpu_to_be32(1 << 8); /* DE? */
731 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
732 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
734 optpar |= MLX4_QP_OPTPAR_PM_STATE;
735 switch (attr->path_mig_state) {
736 case IB_MIG_MIGRATED:
737 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
740 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
743 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
748 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
749 ibqp->qp_type == IB_QPT_UD)
750 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
751 else if (attr_mask & IB_QP_PATH_MTU) {
752 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
753 printk(KERN_ERR "path MTU (%u) is invalid\n",
757 context->mtu_msgmax = (attr->path_mtu << 5) | 31;
761 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
762 context->rq_size_stride |= qp->rq.wqe_shift - 4;
765 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
766 context->sq_size_stride |= qp->sq.wqe_shift - 4;
768 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
769 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
771 if (qp->ibqp.uobject)
772 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
774 context->usr_page = cpu_to_be32(dev->priv_uar.index);
776 if (attr_mask & IB_QP_DEST_QPN)
777 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
779 if (attr_mask & IB_QP_PORT) {
780 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
781 !(attr_mask & IB_QP_AV)) {
782 mlx4_set_sched(&context->pri_path, attr->port_num);
783 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
787 if (attr_mask & IB_QP_PKEY_INDEX) {
788 context->pri_path.pkey_index = attr->pkey_index;
789 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
792 if (attr_mask & IB_QP_AV) {
793 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
794 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
797 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
798 MLX4_QP_OPTPAR_SCHED_QUEUE);
801 if (attr_mask & IB_QP_TIMEOUT) {
802 context->pri_path.ackto = attr->timeout << 3;
803 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
806 if (attr_mask & IB_QP_ALT_PATH) {
807 if (attr->alt_port_num == 0 ||
808 attr->alt_port_num > dev->dev->caps.num_ports)
811 if (attr->alt_pkey_index >=
812 dev->dev->caps.pkey_table_len[attr->alt_port_num])
815 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
819 context->alt_path.pkey_index = attr->alt_pkey_index;
820 context->alt_path.ackto = attr->alt_timeout << 3;
821 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
824 context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
825 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
827 if (attr_mask & IB_QP_RNR_RETRY) {
828 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
829 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
832 if (attr_mask & IB_QP_RETRY_CNT) {
833 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
834 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
837 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
838 if (attr->max_rd_atomic)
840 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
841 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
844 if (attr_mask & IB_QP_SQ_PSN)
845 context->next_send_psn = cpu_to_be32(attr->sq_psn);
847 context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
849 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
850 if (attr->max_dest_rd_atomic)
852 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
853 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
856 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
857 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
858 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
862 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
864 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
865 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
866 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
868 if (attr_mask & IB_QP_RQ_PSN)
869 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
871 context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
873 if (attr_mask & IB_QP_QKEY) {
874 context->qkey = cpu_to_be32(attr->qkey);
875 optpar |= MLX4_QP_OPTPAR_Q_KEY;
879 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
881 if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
882 context->db_rec_addr = cpu_to_be64(qp->db.dma);
884 if (cur_state == IB_QPS_INIT &&
885 new_state == IB_QPS_RTR &&
886 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
887 ibqp->qp_type == IB_QPT_UD)) {
888 context->pri_path.sched_queue = (qp->port - 1) << 6;
890 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
892 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
895 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
896 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
902 * Before passing a kernel QP to the HW, make sure that the
903 * ownership bits of the send queue are set and the SQ
904 * headroom is stamped so that the hardware doesn't start
905 * processing stale work requests.
907 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
908 struct mlx4_wqe_ctrl_seg *ctrl;
911 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
912 ctrl = get_send_wqe(qp, i);
913 ctrl->owner_opcode = cpu_to_be32(1 << 31);
915 stamp_send_wqe(qp, i);
919 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
920 to_mlx4_state(new_state), context, optpar,
921 sqd_event, &qp->mqp);
925 qp->state = new_state;
927 if (attr_mask & IB_QP_ACCESS_FLAGS)
928 qp->atomic_rd_en = attr->qp_access_flags;
929 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
930 qp->resp_depth = attr->max_dest_rd_atomic;
931 if (attr_mask & IB_QP_PORT)
932 qp->port = attr->port_num;
933 if (attr_mask & IB_QP_ALT_PATH)
934 qp->alt_port = attr->alt_port_num;
937 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
940 * If we moved QP0 to RTR, bring the IB link up; if we moved
941 * QP0 to RESET or ERROR, bring the link back down.
943 if (is_qp0(dev, qp)) {
944 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
945 if (mlx4_INIT_PORT(dev->dev, qp->port))
946 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
949 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
950 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
951 mlx4_CLOSE_PORT(dev->dev, qp->port);
955 * If we moved a kernel QP to RESET, clean up all old CQ
956 * entries and reinitialize the QP.
958 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
959 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
960 ibqp->srq ? to_msrq(ibqp->srq): NULL);
961 if (ibqp->send_cq != ibqp->recv_cq)
962 mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
977 static const struct ib_qp_attr mlx4_ib_qp_attr = { .port_num = 1 };
978 static const int mlx4_ib_qp_attr_mask_table[IB_QPT_UD + 1] = {
979 [IB_QPT_UD] = (IB_QP_PKEY_INDEX |
982 [IB_QPT_UC] = (IB_QP_PKEY_INDEX |
985 [IB_QPT_RC] = (IB_QP_PKEY_INDEX |
988 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX |
990 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX |
994 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
995 int attr_mask, struct ib_udata *udata)
997 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
998 struct mlx4_ib_qp *qp = to_mqp(ibqp);
999 enum ib_qp_state cur_state, new_state;
1002 mutex_lock(&qp->mutex);
1004 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1005 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1007 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1010 if ((attr_mask & IB_QP_PORT) &&
1011 (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1015 if (attr_mask & IB_QP_PKEY_INDEX) {
1016 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1017 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1021 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1022 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1026 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1027 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1031 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1036 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
1037 err = __mlx4_ib_modify_qp(ibqp, &mlx4_ib_qp_attr,
1038 mlx4_ib_qp_attr_mask_table[ibqp->qp_type],
1039 IB_QPS_RESET, IB_QPS_INIT);
1042 cur_state = IB_QPS_INIT;
1045 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1048 mutex_unlock(&qp->mutex);
1052 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1055 struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1056 struct mlx4_wqe_mlx_seg *mlx = wqe;
1057 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1058 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1066 for (i = 0; i < wr->num_sge; ++i)
1067 send_size += wr->sg_list[i].length;
1069 ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1071 sqp->ud_header.lrh.service_level =
1072 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1073 sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1074 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.g_slid & 0x7f);
1075 if (mlx4_ib_ah_grh_present(ah)) {
1076 sqp->ud_header.grh.traffic_class =
1077 (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1078 sqp->ud_header.grh.flow_label =
1079 ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1080 sqp->ud_header.grh.hop_limit = ah->av.hop_limit;
1081 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1082 ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1083 memcpy(sqp->ud_header.grh.destination_gid.raw,
1087 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1088 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1089 (sqp->ud_header.lrh.destination_lid ==
1090 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1091 (sqp->ud_header.lrh.service_level << 8));
1092 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1094 switch (wr->opcode) {
1096 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1097 sqp->ud_header.immediate_present = 0;
1099 case IB_WR_SEND_WITH_IMM:
1100 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1101 sqp->ud_header.immediate_present = 1;
1102 sqp->ud_header.immediate_data = wr->imm_data;
1108 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1109 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1110 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1111 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1112 if (!sqp->qp.ibqp.qp_num)
1113 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1115 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1116 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1117 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1118 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1119 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1120 sqp->qkey : wr->wr.ud.remote_qkey);
1121 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1123 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1126 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1127 for (i = 0; i < header_size / 4; ++i) {
1129 printk(" [%02x] ", i * 4);
1131 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1132 if ((i + 1) % 8 == 0)
1139 * Inline data segments may not cross a 64 byte boundary. If
1140 * our UD header is bigger than the space available up to the
1141 * next 64 byte boundary in the WQE, use two inline data
1142 * segments to hold the UD header.
1144 spc = MLX4_INLINE_ALIGN -
1145 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1146 if (header_size <= spc) {
1147 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1148 memcpy(inl + 1, sqp->header_buf, header_size);
1151 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1152 memcpy(inl + 1, sqp->header_buf, spc);
1154 inl = (void *) (inl + 1) + spc;
1155 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1157 * Need a barrier here to make sure all the data is
1158 * visible before the byte_count field is set.
1159 * Otherwise the HCA prefetcher could grab the 64-byte
1160 * chunk with this inline segment and get a valid (!=
1161 * 0xffffffff) byte count but stale data, and end up
1162 * generating a packet with bad headers.
1164 * The first inline segment's byte_count field doesn't
1165 * need a barrier, because it comes after a
1166 * control/MLX segment and therefore is at an offset
1170 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1174 return ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1177 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1180 struct mlx4_ib_cq *cq;
1182 cur = wq->head - wq->tail;
1183 if (likely(cur + nreq < wq->max_post))
1187 spin_lock(&cq->lock);
1188 cur = wq->head - wq->tail;
1189 spin_unlock(&cq->lock);
1191 return cur + nreq >= wq->max_post;
1194 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1195 u64 remote_addr, u32 rkey)
1197 rseg->raddr = cpu_to_be64(remote_addr);
1198 rseg->rkey = cpu_to_be32(rkey);
1202 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1204 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1205 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1206 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
1208 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1214 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1215 struct ib_send_wr *wr)
1217 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1218 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1219 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1222 static void set_mlx_icrc_seg(void *dseg)
1225 struct mlx4_wqe_inline_seg *iseg = dseg;
1230 * Need a barrier here before writing the byte_count field to
1231 * make sure that all the data is visible before the
1232 * byte_count field is set. Otherwise, if the segment begins
1233 * a new cacheline, the HCA prefetcher could grab the 64-byte
1234 * chunk and get a valid (!= * 0xffffffff) byte count but
1235 * stale data, and end up sending the wrong data.
1239 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1242 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1244 dseg->lkey = cpu_to_be32(sg->lkey);
1245 dseg->addr = cpu_to_be64(sg->addr);
1248 * Need a barrier here before writing the byte_count field to
1249 * make sure that all the data is visible before the
1250 * byte_count field is set. Otherwise, if the segment begins
1251 * a new cacheline, the HCA prefetcher could grab the 64-byte
1252 * chunk and get a valid (!= * 0xffffffff) byte count but
1253 * stale data, and end up sending the wrong data.
1257 dseg->byte_count = cpu_to_be32(sg->length);
1260 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1262 dseg->byte_count = cpu_to_be32(sg->length);
1263 dseg->lkey = cpu_to_be32(sg->lkey);
1264 dseg->addr = cpu_to_be64(sg->addr);
1267 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1268 struct ib_send_wr **bad_wr)
1270 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1272 struct mlx4_wqe_ctrl_seg *ctrl;
1273 struct mlx4_wqe_data_seg *dseg;
1274 unsigned long flags;
1281 spin_lock_irqsave(&qp->sq.lock, flags);
1285 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1286 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1292 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1298 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1299 qp->sq.wrid[ind & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
1302 (wr->send_flags & IB_SEND_SIGNALED ?
1303 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1304 (wr->send_flags & IB_SEND_SOLICITED ?
1305 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1308 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1309 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1310 ctrl->imm = wr->imm_data;
1314 wqe += sizeof *ctrl;
1315 size = sizeof *ctrl / 16;
1317 switch (ibqp->qp_type) {
1320 switch (wr->opcode) {
1321 case IB_WR_ATOMIC_CMP_AND_SWP:
1322 case IB_WR_ATOMIC_FETCH_AND_ADD:
1323 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1324 wr->wr.atomic.rkey);
1325 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1327 set_atomic_seg(wqe, wr);
1328 wqe += sizeof (struct mlx4_wqe_atomic_seg);
1330 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1331 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1335 case IB_WR_RDMA_READ:
1336 case IB_WR_RDMA_WRITE:
1337 case IB_WR_RDMA_WRITE_WITH_IMM:
1338 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1340 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1341 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1345 /* No extra segments required for sends */
1351 set_datagram_seg(wqe, wr);
1352 wqe += sizeof (struct mlx4_wqe_datagram_seg);
1353 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1358 err = build_mlx_header(to_msqp(qp), wr, ctrl);
1374 * Write data segments in reverse order, so as to
1375 * overwrite cacheline stamp last within each
1376 * cacheline. This avoids issues with WQE
1381 dseg += wr->num_sge - 1;
1382 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
1384 /* Add one more inline data segment for ICRC for MLX sends */
1385 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1386 qp->ibqp.qp_type == IB_QPT_GSI)) {
1387 set_mlx_icrc_seg(dseg + 1);
1388 size += sizeof (struct mlx4_wqe_data_seg) / 16;
1391 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1392 set_data_seg(dseg, wr->sg_list + i);
1394 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1395 MLX4_WQE_CTRL_FENCE : 0) | size;
1398 * Make sure descriptor is fully written before
1399 * setting ownership bit (because HW can start
1400 * executing as soon as we do).
1404 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1409 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1410 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
1413 * We can improve latency by not stamping the last
1414 * send queue WQE until after ringing the doorbell, so
1415 * only stamp here if there are still more WQEs to post.
1418 stamp_send_wqe(qp, (ind + qp->sq_spare_wqes) &
1419 (qp->sq.wqe_cnt - 1));
1426 qp->sq.head += nreq;
1429 * Make sure that descriptors are written before
1434 writel(qp->doorbell_qpn,
1435 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1438 * Make sure doorbells don't leak out of SQ spinlock
1439 * and reach the HCA out of order.
1443 stamp_send_wqe(qp, (ind + qp->sq_spare_wqes - 1) &
1444 (qp->sq.wqe_cnt - 1));
1447 spin_unlock_irqrestore(&qp->sq.lock, flags);
1452 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1453 struct ib_recv_wr **bad_wr)
1455 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1456 struct mlx4_wqe_data_seg *scat;
1457 unsigned long flags;
1463 spin_lock_irqsave(&qp->rq.lock, flags);
1465 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
1467 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1468 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1474 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1480 scat = get_recv_wqe(qp, ind);
1482 for (i = 0; i < wr->num_sge; ++i)
1483 __set_data_seg(scat + i, wr->sg_list + i);
1485 if (i < qp->rq.max_gs) {
1486 scat[i].byte_count = 0;
1487 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
1491 qp->rq.wrid[ind] = wr->wr_id;
1493 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
1498 qp->rq.head += nreq;
1501 * Make sure that descriptors are written before
1506 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1509 spin_unlock_irqrestore(&qp->rq.lock, flags);
1514 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
1516 switch (mlx4_state) {
1517 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
1518 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
1519 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
1520 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
1521 case MLX4_QP_STATE_SQ_DRAINING:
1522 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
1523 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
1524 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
1529 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
1531 switch (mlx4_mig_state) {
1532 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
1533 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
1534 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
1539 static int to_ib_qp_access_flags(int mlx4_flags)
1543 if (mlx4_flags & MLX4_QP_BIT_RRE)
1544 ib_flags |= IB_ACCESS_REMOTE_READ;
1545 if (mlx4_flags & MLX4_QP_BIT_RWE)
1546 ib_flags |= IB_ACCESS_REMOTE_WRITE;
1547 if (mlx4_flags & MLX4_QP_BIT_RAE)
1548 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
1553 static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr,
1554 struct mlx4_qp_path *path)
1556 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
1557 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
1559 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
1562 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
1563 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
1564 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
1565 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
1566 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
1567 if (ib_ah_attr->ah_flags) {
1568 ib_ah_attr->grh.sgid_index = path->mgid_index;
1569 ib_ah_attr->grh.hop_limit = path->hop_limit;
1570 ib_ah_attr->grh.traffic_class =
1571 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
1572 ib_ah_attr->grh.flow_label =
1573 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
1574 memcpy(ib_ah_attr->grh.dgid.raw,
1575 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
1579 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1580 struct ib_qp_init_attr *qp_init_attr)
1582 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1583 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1584 struct mlx4_qp_context context;
1588 if (qp->state == IB_QPS_RESET) {
1589 qp_attr->qp_state = IB_QPS_RESET;
1593 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
1597 mlx4_state = be32_to_cpu(context.flags) >> 28;
1599 qp_attr->qp_state = to_ib_qp_state(mlx4_state);
1600 qp_attr->path_mtu = context.mtu_msgmax >> 5;
1601 qp_attr->path_mig_state =
1602 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
1603 qp_attr->qkey = be32_to_cpu(context.qkey);
1604 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
1605 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
1606 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
1607 qp_attr->qp_access_flags =
1608 to_ib_qp_access_flags(be32_to_cpu(context.params2));
1610 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
1611 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path);
1612 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path);
1613 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
1614 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
1617 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1618 if (qp_attr->qp_state == IB_QPS_INIT)
1619 qp_attr->port_num = qp->port;
1621 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
1623 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1624 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
1626 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
1628 qp_attr->max_dest_rd_atomic =
1629 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
1630 qp_attr->min_rnr_timer =
1631 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
1632 qp_attr->timeout = context.pri_path.ackto >> 3;
1633 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
1634 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
1635 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
1638 qp_attr->cur_qp_state = qp_attr->qp_state;
1639 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
1640 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
1642 if (!ibqp->uobject) {
1643 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
1644 qp_attr->cap.max_send_sge = qp->sq.max_gs;
1646 qp_attr->cap.max_send_wr = 0;
1647 qp_attr->cap.max_send_sge = 0;
1651 * We don't support inline sends for kernel QPs (yet), and we
1652 * don't know what userspace's value should be.
1654 qp_attr->cap.max_inline_data = 0;
1656 qp_init_attr->cap = qp_attr->cap;