2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/log2.h>
35 #include <linux/etherdevice.h>
37 #include <linux/slab.h>
38 #include <linux/netdevice.h>
39 #include <linux/vmalloc.h>
41 #include <rdma/ib_cache.h>
42 #include <rdma/ib_pack.h>
43 #include <rdma/ib_addr.h>
44 #include <rdma/ib_mad.h>
46 #include <linux/mlx4/driver.h>
47 #include <linux/mlx4/qp.h>
52 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
55 struct mlx4_ib_cq *recv_cq);
58 MLX4_IB_ACK_REQ_FREQ = 8,
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
70 * Largest possible UD header: send with GRH and immediate
71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
75 MLX4_IB_UD_HEADER_SIZE = 82,
76 MLX4_IB_LSO_HEADER_SPARE = 128,
80 MLX4_IB_IBOE_ETHERTYPE = 0x8915
88 struct ib_ud_header ud_header;
89 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
90 struct ib_qp *roce_v2_gsi;
94 MLX4_IB_MIN_SQ_STRIDE = 6,
95 MLX4_IB_CACHE_LINE_SIZE = 64,
100 MLX4_RAW_QP_MSGMAX = 31,
107 static const __be32 mlx4_ib_opcode[] = {
108 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
109 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
110 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
111 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
112 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
113 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
114 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
115 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
116 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
117 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
118 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
119 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
120 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
123 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
125 return container_of(mqp, struct mlx4_ib_sqp, qp);
128 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
130 if (!mlx4_is_master(dev->dev))
133 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
134 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
138 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
143 /* PPF or Native -- real SQP */
144 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
145 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
146 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
149 /* VF or PF -- proxy SQP */
150 if (mlx4_is_mfunc(dev->dev)) {
151 for (i = 0; i < dev->dev->caps.num_ports; i++) {
152 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
153 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
162 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
165 /* used for INIT/CLOSE port logic */
166 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
171 /* PPF or Native -- real QP0 */
172 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
173 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
174 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
177 /* VF or PF -- proxy QP0 */
178 if (mlx4_is_mfunc(dev->dev)) {
179 for (i = 0; i < dev->dev->caps.num_ports; i++) {
180 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
189 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
191 return mlx4_buf_offset(&qp->buf, offset);
194 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
196 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
199 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
201 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
205 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
206 * first four bytes of every 64 byte chunk with
207 * 0x7FFFFFF | (invalid_ownership_value << 31).
209 * When the max work request size is less than or equal to the WQE
210 * basic block size, as an optimization, we can stamp all WQEs with
211 * 0xffffffff, and skip the very first chunk of each WQE.
213 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
221 struct mlx4_wqe_ctrl_seg *ctrl;
223 if (qp->sq_max_wqes_per_wr > 1) {
224 s = roundup(size, 1U << qp->sq.wqe_shift);
225 for (i = 0; i < s; i += 64) {
226 ind = (i >> qp->sq.wqe_shift) + n;
227 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
228 cpu_to_be32(0xffffffff);
229 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
230 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
234 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
235 s = (ctrl->fence_size & 0x3f) << 4;
236 for (i = 64; i < s; i += 64) {
238 *wqe = cpu_to_be32(0xffffffff);
243 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
245 struct mlx4_wqe_ctrl_seg *ctrl;
246 struct mlx4_wqe_inline_seg *inl;
250 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
251 s = sizeof(struct mlx4_wqe_ctrl_seg);
253 if (qp->ibqp.qp_type == IB_QPT_UD) {
254 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
255 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
256 memset(dgram, 0, sizeof *dgram);
257 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
258 s += sizeof(struct mlx4_wqe_datagram_seg);
261 /* Pad the remainder of the WQE with an inline data segment. */
264 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
266 ctrl->srcrb_flags = 0;
267 ctrl->fence_size = size / 16;
269 * Make sure descriptor is fully written before setting ownership bit
270 * (because HW can start executing as soon as we do).
274 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
275 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
277 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
280 /* Post NOP WQE to prevent wrap-around in the middle of WR */
281 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
283 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
284 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
285 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
291 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
293 struct ib_event event;
294 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
296 if (type == MLX4_EVENT_TYPE_PATH_MIG)
297 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
299 if (ibqp->event_handler) {
300 event.device = ibqp->device;
301 event.element.qp = ibqp;
303 case MLX4_EVENT_TYPE_PATH_MIG:
304 event.event = IB_EVENT_PATH_MIG;
306 case MLX4_EVENT_TYPE_COMM_EST:
307 event.event = IB_EVENT_COMM_EST;
309 case MLX4_EVENT_TYPE_SQ_DRAINED:
310 event.event = IB_EVENT_SQ_DRAINED;
312 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
313 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
315 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
316 event.event = IB_EVENT_QP_FATAL;
318 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
319 event.event = IB_EVENT_PATH_MIG_ERR;
321 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
322 event.event = IB_EVENT_QP_REQ_ERR;
324 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
325 event.event = IB_EVENT_QP_ACCESS_ERR;
328 pr_warn("Unexpected event type %d "
329 "on QP %06x\n", type, qp->qpn);
333 ibqp->event_handler(&event, ibqp->qp_context);
337 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
340 * UD WQEs must have a datagram segment.
341 * RC and UC WQEs might have a remote address segment.
342 * MLX WQEs need two extra inline data segments (for the UD
343 * header and space for the ICRC).
347 return sizeof (struct mlx4_wqe_ctrl_seg) +
348 sizeof (struct mlx4_wqe_datagram_seg) +
349 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
350 case MLX4_IB_QPT_PROXY_SMI_OWNER:
351 case MLX4_IB_QPT_PROXY_SMI:
352 case MLX4_IB_QPT_PROXY_GSI:
353 return sizeof (struct mlx4_wqe_ctrl_seg) +
354 sizeof (struct mlx4_wqe_datagram_seg) + 64;
355 case MLX4_IB_QPT_TUN_SMI_OWNER:
356 case MLX4_IB_QPT_TUN_GSI:
357 return sizeof (struct mlx4_wqe_ctrl_seg) +
358 sizeof (struct mlx4_wqe_datagram_seg);
361 return sizeof (struct mlx4_wqe_ctrl_seg) +
362 sizeof (struct mlx4_wqe_raddr_seg);
364 return sizeof (struct mlx4_wqe_ctrl_seg) +
365 sizeof (struct mlx4_wqe_atomic_seg) +
366 sizeof (struct mlx4_wqe_raddr_seg);
367 case MLX4_IB_QPT_SMI:
368 case MLX4_IB_QPT_GSI:
369 return sizeof (struct mlx4_wqe_ctrl_seg) +
370 ALIGN(MLX4_IB_UD_HEADER_SIZE +
371 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
373 sizeof (struct mlx4_wqe_inline_seg),
374 sizeof (struct mlx4_wqe_data_seg)) +
376 sizeof (struct mlx4_wqe_inline_seg),
377 sizeof (struct mlx4_wqe_data_seg));
379 return sizeof (struct mlx4_wqe_ctrl_seg);
383 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
384 int is_user, int has_rq, struct mlx4_ib_qp *qp)
386 /* Sanity check RQ size before proceeding */
387 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
388 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
392 if (cap->max_recv_wr)
395 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
397 /* HW requires >= 1 RQ entry with >= 1 gather entry */
398 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
401 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
402 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
403 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
406 /* leave userspace return values as they were, so as not to break ABI */
408 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
409 cap->max_recv_sge = qp->rq.max_gs;
411 cap->max_recv_wr = qp->rq.max_post =
412 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
413 cap->max_recv_sge = min(qp->rq.max_gs,
414 min(dev->dev->caps.max_sq_sg,
415 dev->dev->caps.max_rq_sg));
421 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
422 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
426 /* Sanity check SQ size before proceeding */
427 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
428 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
429 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
430 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
434 * For MLX transport we need 2 extra S/G entries:
435 * one for the header and one for the checksum at the end
437 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
438 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
439 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
442 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
443 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
444 send_wqe_overhead(type, qp->flags);
446 if (s > dev->dev->caps.max_sq_desc_sz)
450 * Hermon supports shrinking WQEs, such that a single work
451 * request can include multiple units of 1 << wqe_shift. This
452 * way, work requests can differ in size, and do not have to
453 * be a power of 2 in size, saving memory and speeding up send
454 * WR posting. Unfortunately, if we do this then the
455 * wqe_index field in CQEs can't be used to look up the WR ID
456 * anymore, so we do this only if selective signaling is off.
458 * Further, on 32-bit platforms, we can't use vmap() to make
459 * the QP buffer virtually contiguous. Thus we have to use
460 * constant-sized WRs to make sure a WR is always fully within
461 * a single page-sized chunk.
463 * Finally, we use NOP work requests to pad the end of the
464 * work queue, to avoid wrap-around in the middle of WR. We
465 * set NEC bit to avoid getting completions with error for
466 * these NOP WRs, but since NEC is only supported starting
467 * with firmware 2.2.232, we use constant-sized WRs for older
470 * And, since MLX QPs only support SEND, we use constant-sized
473 * We look for the smallest value of wqe_shift such that the
474 * resulting number of wqes does not exceed device
477 * We set WQE size to at least 64 bytes, this way stamping
478 * invalidates each WQE.
480 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
481 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
482 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
483 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
484 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
485 qp->sq.wqe_shift = ilog2(64);
487 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
490 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
493 * We need to leave 2 KB + 1 WR of headroom in the SQ to
494 * allow HW to prefetch.
496 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
497 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
498 qp->sq_max_wqes_per_wr +
501 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
504 if (qp->sq_max_wqes_per_wr <= 1)
510 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
511 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
512 send_wqe_overhead(type, qp->flags)) /
513 sizeof (struct mlx4_wqe_data_seg);
515 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
516 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
517 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
519 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
521 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
525 cap->max_send_wr = qp->sq.max_post =
526 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
527 cap->max_send_sge = min(qp->sq.max_gs,
528 min(dev->dev->caps.max_sq_sg,
529 dev->dev->caps.max_rq_sg));
530 /* We don't support inline sends for kernel QPs (yet) */
531 cap->max_inline_data = 0;
536 static int set_user_sq_size(struct mlx4_ib_dev *dev,
537 struct mlx4_ib_qp *qp,
538 struct mlx4_ib_create_qp *ucmd)
540 /* Sanity check SQ size before proceeding */
541 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
542 ucmd->log_sq_stride >
543 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
544 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
547 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
548 qp->sq.wqe_shift = ucmd->log_sq_stride;
550 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
551 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
556 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
561 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
563 if (!qp->sqp_proxy_rcv)
565 for (i = 0; i < qp->rq.wqe_cnt; i++) {
566 qp->sqp_proxy_rcv[i].addr =
567 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
569 if (!qp->sqp_proxy_rcv[i].addr)
571 qp->sqp_proxy_rcv[i].map =
572 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
573 sizeof (struct mlx4_ib_proxy_sqp_hdr),
575 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
576 kfree(qp->sqp_proxy_rcv[i].addr);
585 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
586 sizeof (struct mlx4_ib_proxy_sqp_hdr),
588 kfree(qp->sqp_proxy_rcv[i].addr);
590 kfree(qp->sqp_proxy_rcv);
591 qp->sqp_proxy_rcv = NULL;
595 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
599 for (i = 0; i < qp->rq.wqe_cnt; i++) {
600 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
601 sizeof (struct mlx4_ib_proxy_sqp_hdr),
603 kfree(qp->sqp_proxy_rcv[i].addr);
605 kfree(qp->sqp_proxy_rcv);
608 static int qp_has_rq(struct ib_qp_init_attr *attr)
610 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
616 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
619 for (i = 0; i < dev->caps.num_ports; i++) {
620 if (qpn == dev->caps.qp0_proxy[i])
621 return !!dev->caps.qp0_qkey[i];
626 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
627 struct mlx4_ib_qp *qp)
629 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
630 mlx4_counter_free(dev->dev, qp->counter_index->index);
631 list_del(&qp->counter_index->list);
632 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
634 kfree(qp->counter_index);
635 qp->counter_index = NULL;
638 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
639 struct ib_qp_init_attr *init_attr,
640 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
645 struct mlx4_ib_sqp *sqp;
646 struct mlx4_ib_qp *qp;
647 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
648 struct mlx4_ib_cq *mcq;
651 /* When tunneling special qps, we use a plain UD qp */
653 if (mlx4_is_mfunc(dev->dev) &&
654 (!mlx4_is_master(dev->dev) ||
655 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
656 if (init_attr->qp_type == IB_QPT_GSI)
657 qp_type = MLX4_IB_QPT_PROXY_GSI;
659 if (mlx4_is_master(dev->dev) ||
660 qp0_enabled_vf(dev->dev, sqpn))
661 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
663 qp_type = MLX4_IB_QPT_PROXY_SMI;
667 /* add extra sg entry for tunneling */
668 init_attr->cap.max_recv_sge++;
669 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
670 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
671 container_of(init_attr,
672 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
673 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
674 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
675 !mlx4_is_master(dev->dev))
677 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
678 qp_type = MLX4_IB_QPT_TUN_GSI;
679 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
680 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
682 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
684 qp_type = MLX4_IB_QPT_TUN_SMI;
685 /* we are definitely in the PPF here, since we are creating
686 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
687 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
688 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
693 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
694 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
695 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
696 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
700 qp->pri.vid = 0xFFFF;
701 qp->alt.vid = 0xFFFF;
703 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
706 qp->pri.vid = 0xFFFF;
707 qp->alt.vid = 0xFFFF;
712 qp->mlx4_ib_qp_type = qp_type;
714 mutex_init(&qp->mutex);
715 spin_lock_init(&qp->sq.lock);
716 spin_lock_init(&qp->rq.lock);
717 INIT_LIST_HEAD(&qp->gid_list);
718 INIT_LIST_HEAD(&qp->steering_rules);
720 qp->state = IB_QPS_RESET;
721 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
722 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
724 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
729 struct mlx4_ib_create_qp ucmd;
731 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
736 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
738 err = set_user_sq_size(dev, qp, &ucmd);
742 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
744 if (IS_ERR(qp->umem)) {
745 err = PTR_ERR(qp->umem);
749 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
750 ilog2(qp->umem->page_size), &qp->mtt);
754 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
758 if (qp_has_rq(init_attr)) {
759 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
760 ucmd.db_addr, &qp->db);
765 qp->sq_no_prefetch = 0;
767 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
768 qp->flags |= MLX4_IB_QP_LSO;
770 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
771 if (dev->steering_support ==
772 MLX4_STEERING_MODE_DEVICE_MANAGED)
773 qp->flags |= MLX4_IB_QP_NETIF;
778 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
782 if (qp_has_rq(init_attr)) {
783 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
790 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
795 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
800 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
804 qp->sq.wrid = kmalloc_array(qp->sq.wqe_cnt, sizeof(u64),
807 qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64),
809 qp->rq.wrid = kmalloc_array(qp->rq.wqe_cnt, sizeof(u64),
812 qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64),
814 if (!qp->sq.wrid || !qp->rq.wrid) {
821 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
822 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
823 if (alloc_proxy_bufs(pd->device, qp)) {
829 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
830 * otherwise, the WQE BlueFlame setup flow wrongly causes
832 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
833 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
834 (init_attr->cap.max_send_wr ?
835 MLX4_RESERVE_ETH_BF_QP : 0) |
836 (init_attr->cap.max_recv_wr ?
837 MLX4_RESERVE_A0_QP : 0));
839 if (qp->flags & MLX4_IB_QP_NETIF)
840 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
842 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
848 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
849 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
851 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
855 if (init_attr->qp_type == IB_QPT_XRC_TGT)
856 qp->mqp.qpn |= (1 << 23);
859 * Hardware wants QPN written in big-endian order (after
860 * shifting) for send doorbell. Precompute this value to save
861 * a little bit when posting sends.
863 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
865 qp->mqp.event = mlx4_ib_qp_event;
869 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
870 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
871 to_mcq(init_attr->recv_cq));
872 /* Maintain device to QPs access, needed for further handling
875 list_add_tail(&qp->qps_list, &dev->qp_list);
876 /* Maintain CQ to QPs access, needed for further handling
879 mcq = to_mcq(init_attr->send_cq);
880 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
881 mcq = to_mcq(init_attr->recv_cq);
882 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
883 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
884 to_mcq(init_attr->recv_cq));
885 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
890 if (qp->flags & MLX4_IB_QP_NETIF)
891 mlx4_ib_steer_qp_free(dev, qpn, 1);
893 mlx4_qp_release_range(dev->dev, qpn, 1);
896 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
897 free_proxy_bufs(pd->device, qp);
900 if (qp_has_rq(init_attr))
901 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
908 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
912 ib_umem_release(qp->umem);
914 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
917 if (!pd->uobject && qp_has_rq(init_attr))
918 mlx4_db_free(dev->dev, &qp->db);
926 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
929 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
930 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
931 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
932 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
933 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
934 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
935 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
940 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
941 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
943 if (send_cq == recv_cq) {
944 spin_lock(&send_cq->lock);
945 __acquire(&recv_cq->lock);
946 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
947 spin_lock(&send_cq->lock);
948 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
950 spin_lock(&recv_cq->lock);
951 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
955 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
956 __releases(&send_cq->lock) __releases(&recv_cq->lock)
958 if (send_cq == recv_cq) {
959 __release(&recv_cq->lock);
960 spin_unlock(&send_cq->lock);
961 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
962 spin_unlock(&recv_cq->lock);
963 spin_unlock(&send_cq->lock);
965 spin_unlock(&send_cq->lock);
966 spin_unlock(&recv_cq->lock);
970 static void del_gid_entries(struct mlx4_ib_qp *qp)
972 struct mlx4_ib_gid_entry *ge, *tmp;
974 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
980 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
982 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
983 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
985 return to_mpd(qp->ibqp.pd);
988 static void get_cqs(struct mlx4_ib_qp *qp,
989 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
991 switch (qp->ibqp.qp_type) {
993 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
997 *send_cq = to_mcq(qp->ibqp.send_cq);
1001 *send_cq = to_mcq(qp->ibqp.send_cq);
1002 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1007 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1010 struct mlx4_ib_cq *send_cq, *recv_cq;
1011 unsigned long flags;
1013 if (qp->state != IB_QPS_RESET) {
1014 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1015 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1016 pr_warn("modify QP %06x to RESET failed.\n",
1018 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1019 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1021 qp->pri.smac_port = 0;
1024 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1027 if (qp->pri.vid < 0x1000) {
1028 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1029 qp->pri.vid = 0xFFFF;
1030 qp->pri.candidate_vid = 0xFFFF;
1031 qp->pri.update_vid = 0;
1033 if (qp->alt.vid < 0x1000) {
1034 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1035 qp->alt.vid = 0xFFFF;
1036 qp->alt.candidate_vid = 0xFFFF;
1037 qp->alt.update_vid = 0;
1041 get_cqs(qp, &send_cq, &recv_cq);
1043 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1044 mlx4_ib_lock_cqs(send_cq, recv_cq);
1046 /* del from lists under both locks above to protect reset flow paths */
1047 list_del(&qp->qps_list);
1048 list_del(&qp->cq_send_list);
1049 list_del(&qp->cq_recv_list);
1051 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1052 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1053 if (send_cq != recv_cq)
1054 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1057 mlx4_qp_remove(dev->dev, &qp->mqp);
1059 mlx4_ib_unlock_cqs(send_cq, recv_cq);
1060 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1062 mlx4_qp_free(dev->dev, &qp->mqp);
1064 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1065 if (qp->flags & MLX4_IB_QP_NETIF)
1066 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1068 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1071 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1075 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1077 ib_umem_release(qp->umem);
1079 kvfree(qp->sq.wrid);
1080 kvfree(qp->rq.wrid);
1081 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1082 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1083 free_proxy_bufs(&dev->ib_dev, qp);
1084 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1086 mlx4_db_free(dev->dev, &qp->db);
1089 del_gid_entries(qp);
1092 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1095 if (!mlx4_is_mfunc(dev->dev) ||
1096 (mlx4_is_master(dev->dev) &&
1097 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1098 return dev->dev->phys_caps.base_sqpn +
1099 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1102 /* PF or VF -- creating proxies */
1103 if (attr->qp_type == IB_QPT_SMI)
1104 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1106 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1109 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1110 struct ib_qp_init_attr *init_attr,
1111 struct ib_udata *udata)
1113 struct mlx4_ib_qp *qp = NULL;
1115 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1119 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1120 GFP_NOIO : GFP_KERNEL;
1122 * We only support LSO, vendor flag1, and multicast loopback blocking,
1123 * and only for kernel UD QPs.
1125 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1126 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1127 MLX4_IB_SRIOV_TUNNEL_QP |
1130 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1131 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
1132 return ERR_PTR(-EINVAL);
1134 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1135 if (init_attr->qp_type != IB_QPT_UD)
1136 return ERR_PTR(-EINVAL);
1139 if (init_attr->create_flags) {
1140 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1141 return ERR_PTR(-EINVAL);
1143 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1144 MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1145 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1146 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1147 init_attr->qp_type != IB_QPT_UD) ||
1148 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1149 init_attr->qp_type > IB_QPT_GSI) ||
1150 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1151 init_attr->qp_type != IB_QPT_GSI))
1152 return ERR_PTR(-EINVAL);
1155 switch (init_attr->qp_type) {
1156 case IB_QPT_XRC_TGT:
1157 pd = to_mxrcd(init_attr->xrcd)->pd;
1158 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1159 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1161 case IB_QPT_XRC_INI:
1162 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1163 return ERR_PTR(-ENOSYS);
1164 init_attr->recv_cq = init_attr->send_cq;
1168 case IB_QPT_RAW_PACKET:
1169 qp = kzalloc(sizeof *qp, gfp);
1171 return ERR_PTR(-ENOMEM);
1172 qp->pri.vid = 0xFFFF;
1173 qp->alt.vid = 0xFFFF;
1177 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1178 udata, 0, &qp, gfp);
1180 return ERR_PTR(err);
1182 qp->ibqp.qp_num = qp->mqp.qpn;
1192 /* Userspace is not allowed to create special QPs: */
1194 return ERR_PTR(-EINVAL);
1195 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1196 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1, 1, &sqpn, 0);
1199 return ERR_PTR(res);
1201 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1204 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1208 return ERR_PTR(err);
1210 qp->port = init_attr->port_num;
1211 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1212 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
1216 /* Don't support raw QPs */
1217 return ERR_PTR(-EINVAL);
1223 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1224 struct ib_qp_init_attr *init_attr,
1225 struct ib_udata *udata) {
1226 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1228 struct mlx4_ib_dev *dev = to_mdev(device);
1230 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1232 if (!IS_ERR(ibqp) &&
1233 (init_attr->qp_type == IB_QPT_GSI) &&
1234 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1235 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1236 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1239 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1240 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1241 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1243 if (IS_ERR(sqp->roce_v2_gsi)) {
1244 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1245 sqp->roce_v2_gsi = NULL;
1247 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1248 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1251 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1257 static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
1259 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1260 struct mlx4_ib_qp *mqp = to_mqp(qp);
1261 struct mlx4_ib_pd *pd;
1263 if (is_qp0(dev, mqp))
1264 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1266 if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1267 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1268 dev->qp1_proxy[mqp->port - 1] = NULL;
1269 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1272 if (mqp->counter_index)
1273 mlx4_ib_free_qp_counter(dev, mqp);
1276 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1278 if (is_sqp(dev, mqp))
1279 kfree(to_msqp(mqp));
1286 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1288 struct mlx4_ib_qp *mqp = to_mqp(qp);
1290 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1291 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1293 if (sqp->roce_v2_gsi)
1294 ib_destroy_qp(sqp->roce_v2_gsi);
1297 return _mlx4_ib_destroy_qp(qp);
1300 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1303 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1304 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1305 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1306 case MLX4_IB_QPT_XRC_INI:
1307 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1308 case MLX4_IB_QPT_SMI:
1309 case MLX4_IB_QPT_GSI:
1310 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1312 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1313 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1314 MLX4_QP_ST_MLX : -1);
1315 case MLX4_IB_QPT_PROXY_SMI:
1316 case MLX4_IB_QPT_TUN_SMI:
1317 case MLX4_IB_QPT_PROXY_GSI:
1318 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1319 MLX4_QP_ST_UD : -1);
1324 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1329 u32 hw_access_flags = 0;
1331 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1332 dest_rd_atomic = attr->max_dest_rd_atomic;
1334 dest_rd_atomic = qp->resp_depth;
1336 if (attr_mask & IB_QP_ACCESS_FLAGS)
1337 access_flags = attr->qp_access_flags;
1339 access_flags = qp->atomic_rd_en;
1341 if (!dest_rd_atomic)
1342 access_flags &= IB_ACCESS_REMOTE_WRITE;
1344 if (access_flags & IB_ACCESS_REMOTE_READ)
1345 hw_access_flags |= MLX4_QP_BIT_RRE;
1346 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1347 hw_access_flags |= MLX4_QP_BIT_RAE;
1348 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1349 hw_access_flags |= MLX4_QP_BIT_RWE;
1351 return cpu_to_be32(hw_access_flags);
1354 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1357 if (attr_mask & IB_QP_PKEY_INDEX)
1358 sqp->pkey_index = attr->pkey_index;
1359 if (attr_mask & IB_QP_QKEY)
1360 sqp->qkey = attr->qkey;
1361 if (attr_mask & IB_QP_SQ_PSN)
1362 sqp->send_psn = attr->sq_psn;
1365 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1367 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1370 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1371 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1372 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1374 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1375 IB_LINK_LAYER_ETHERNET;
1381 path->grh_mylmc = ah->src_path_bits & 0x7f;
1382 path->rlid = cpu_to_be16(ah->dlid);
1383 if (ah->static_rate) {
1384 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1385 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1386 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1387 --path->static_rate;
1389 path->static_rate = 0;
1391 if (ah->ah_flags & IB_AH_GRH) {
1392 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1394 ah->grh.sgid_index);
1396 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1397 pr_err("sgid_index (%u) too large. max is %d\n",
1398 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1402 path->grh_mylmc |= 1 << 7;
1403 path->mgid_index = real_sgid_index;
1404 path->hop_limit = ah->grh.hop_limit;
1405 path->tclass_flowlabel =
1406 cpu_to_be32((ah->grh.traffic_class << 20) |
1407 (ah->grh.flow_label));
1408 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1412 if (!(ah->ah_flags & IB_AH_GRH))
1415 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1416 ((port - 1) << 6) | ((ah->sl & 7) << 3);
1418 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1419 if (vlan_tag < 0x1000) {
1420 if (smac_info->vid < 0x1000) {
1421 /* both valid vlan ids */
1422 if (smac_info->vid != vlan_tag) {
1423 /* different VIDs. unreg old and reg new */
1424 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1427 smac_info->candidate_vid = vlan_tag;
1428 smac_info->candidate_vlan_index = vidx;
1429 smac_info->candidate_vlan_port = port;
1430 smac_info->update_vid = 1;
1431 path->vlan_index = vidx;
1433 path->vlan_index = smac_info->vlan_index;
1436 /* no current vlan tag in qp */
1437 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1440 smac_info->candidate_vid = vlan_tag;
1441 smac_info->candidate_vlan_index = vidx;
1442 smac_info->candidate_vlan_port = port;
1443 smac_info->update_vid = 1;
1444 path->vlan_index = vidx;
1446 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1449 /* have current vlan tag. unregister it at modify-qp success */
1450 if (smac_info->vid < 0x1000) {
1451 smac_info->candidate_vid = 0xFFFF;
1452 smac_info->update_vid = 1;
1456 /* get smac_index for RoCE use.
1457 * If no smac was yet assigned, register one.
1458 * If one was already assigned, but the new mac differs,
1459 * unregister the old one and register the new one.
1461 if ((!smac_info->smac && !smac_info->smac_port) ||
1462 smac_info->smac != smac) {
1463 /* register candidate now, unreg if needed, after success */
1464 smac_index = mlx4_register_mac(dev->dev, port, smac);
1465 if (smac_index >= 0) {
1466 smac_info->candidate_smac_index = smac_index;
1467 smac_info->candidate_smac = smac;
1468 smac_info->candidate_smac_port = port;
1473 smac_index = smac_info->smac_index;
1476 memcpy(path->dmac, ah->dmac, 6);
1477 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1478 /* put MAC table smac index for IBoE */
1479 path->grh_mylmc = (u8) (smac_index) | 0x80;
1481 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1482 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1488 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1489 enum ib_qp_attr_mask qp_attr_mask,
1490 struct mlx4_ib_qp *mqp,
1491 struct mlx4_qp_path *path, u8 port,
1492 u16 vlan_id, u8 *smac)
1494 return _mlx4_set_path(dev, &qp->ah_attr,
1495 mlx4_mac_to_u64(smac),
1497 path, &mqp->pri, port);
1500 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1501 const struct ib_qp_attr *qp,
1502 enum ib_qp_attr_mask qp_attr_mask,
1503 struct mlx4_ib_qp *mqp,
1504 struct mlx4_qp_path *path, u8 port)
1506 return _mlx4_set_path(dev, &qp->alt_ah_attr,
1509 path, &mqp->alt, port);
1512 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1514 struct mlx4_ib_gid_entry *ge, *tmp;
1516 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1517 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1519 ge->port = qp->port;
1524 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1525 struct mlx4_ib_qp *qp,
1526 struct mlx4_qp_context *context)
1531 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1533 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1534 if (!qp->pri.smac && !qp->pri.smac_port) {
1535 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1536 if (smac_index >= 0) {
1537 qp->pri.candidate_smac_index = smac_index;
1538 qp->pri.candidate_smac = u64_mac;
1539 qp->pri.candidate_smac_port = qp->port;
1540 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1548 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1550 struct counter_index *new_counter_index;
1554 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1555 IB_LINK_LAYER_ETHERNET ||
1556 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1557 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1560 err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1564 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1565 if (!new_counter_index) {
1566 mlx4_counter_free(dev->dev, tmp_idx);
1570 new_counter_index->index = tmp_idx;
1571 new_counter_index->allocated = 1;
1572 qp->counter_index = new_counter_index;
1574 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1575 list_add_tail(&new_counter_index->list,
1576 &dev->counters_table[qp->port - 1].counters_list);
1577 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1583 MLX4_QPC_ROCE_MODE_1 = 0,
1584 MLX4_QPC_ROCE_MODE_2 = 2,
1585 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1588 static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1591 case IB_GID_TYPE_ROCE:
1592 return MLX4_QPC_ROCE_MODE_1;
1593 case IB_GID_TYPE_ROCE_UDP_ENCAP:
1594 return MLX4_QPC_ROCE_MODE_2;
1596 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1600 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1601 const struct ib_qp_attr *attr, int attr_mask,
1602 enum ib_qp_state cur_state, enum ib_qp_state new_state)
1604 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1605 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1606 struct mlx4_ib_pd *pd;
1607 struct mlx4_ib_cq *send_cq, *recv_cq;
1608 struct mlx4_qp_context *context;
1609 enum mlx4_qp_optpar optpar = 0;
1615 /* APM is not supported under RoCE */
1616 if (attr_mask & IB_QP_ALT_PATH &&
1617 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1618 IB_LINK_LAYER_ETHERNET)
1621 context = kzalloc(sizeof *context, GFP_KERNEL);
1625 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1626 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1628 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1629 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1631 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1632 switch (attr->path_mig_state) {
1633 case IB_MIG_MIGRATED:
1634 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1637 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1640 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1645 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1646 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1647 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1648 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1649 else if (ibqp->qp_type == IB_QPT_UD) {
1650 if (qp->flags & MLX4_IB_QP_LSO)
1651 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1652 ilog2(dev->dev->caps.max_gso_sz);
1654 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1655 } else if (attr_mask & IB_QP_PATH_MTU) {
1656 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1657 pr_err("path MTU (%u) is invalid\n",
1661 context->mtu_msgmax = (attr->path_mtu << 5) |
1662 ilog2(dev->dev->caps.max_msg_sz);
1666 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1667 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1670 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1671 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1673 if (new_state == IB_QPS_RESET && qp->counter_index)
1674 mlx4_ib_free_qp_counter(dev, qp);
1676 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1677 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1678 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1679 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1680 context->param3 |= cpu_to_be32(1 << 30);
1683 if (qp->ibqp.uobject)
1684 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1686 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1688 if (attr_mask & IB_QP_DEST_QPN)
1689 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1691 if (attr_mask & IB_QP_PORT) {
1692 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1693 !(attr_mask & IB_QP_AV)) {
1694 mlx4_set_sched(&context->pri_path, attr->port_num);
1695 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1699 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1700 err = create_qp_lb_counter(dev, qp);
1705 dev->counters_table[qp->port - 1].default_counter;
1706 if (qp->counter_index)
1707 counter_index = qp->counter_index->index;
1709 if (counter_index != -1) {
1710 context->pri_path.counter_index = counter_index;
1711 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1712 if (qp->counter_index) {
1713 context->pri_path.fl |=
1714 MLX4_FL_ETH_SRC_CHECK_MC_LB;
1715 context->pri_path.vlan_control |=
1716 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1719 context->pri_path.counter_index =
1720 MLX4_SINK_COUNTER_INDEX(dev->dev);
1722 if (qp->flags & MLX4_IB_QP_NETIF) {
1723 mlx4_ib_steer_qp_reg(dev, qp, 1);
1727 if (ibqp->qp_type == IB_QPT_GSI) {
1728 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
1729 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
1730 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
1732 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1736 if (attr_mask & IB_QP_PKEY_INDEX) {
1737 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1738 context->pri_path.disable_pkey_check = 0x40;
1739 context->pri_path.pkey_index = attr->pkey_index;
1740 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1743 if (attr_mask & IB_QP_AV) {
1744 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1745 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1747 struct ib_gid_attr gid_attr;
1751 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1752 attr->ah_attr.ah_flags & IB_AH_GRH;
1755 int index = attr->ah_attr.grh.sgid_index;
1757 status = ib_get_cached_gid(ibqp->device, port_num,
1758 index, &gid, &gid_attr);
1759 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1761 if (!status && gid_attr.ndev) {
1762 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1763 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1764 dev_put(gid_attr.ndev);
1770 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1771 port_num, vlan, smac))
1774 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1775 MLX4_QP_OPTPAR_SCHED_QUEUE);
1778 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
1779 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
1781 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
1785 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1790 if (attr_mask & IB_QP_TIMEOUT) {
1791 context->pri_path.ackto |= attr->timeout << 3;
1792 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1795 if (attr_mask & IB_QP_ALT_PATH) {
1796 if (attr->alt_port_num == 0 ||
1797 attr->alt_port_num > dev->dev->caps.num_ports)
1800 if (attr->alt_pkey_index >=
1801 dev->dev->caps.pkey_table_len[attr->alt_port_num])
1804 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1806 attr->alt_port_num))
1809 context->alt_path.pkey_index = attr->alt_pkey_index;
1810 context->alt_path.ackto = attr->alt_timeout << 3;
1811 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1815 get_cqs(qp, &send_cq, &recv_cq);
1816 context->pd = cpu_to_be32(pd->pdn);
1817 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1818 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1819 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1821 /* Set "fast registration enabled" for all kernel QPs */
1822 if (!qp->ibqp.uobject)
1823 context->params1 |= cpu_to_be32(1 << 11);
1825 if (attr_mask & IB_QP_RNR_RETRY) {
1826 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1827 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1830 if (attr_mask & IB_QP_RETRY_CNT) {
1831 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1832 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1835 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1836 if (attr->max_rd_atomic)
1838 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1839 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1842 if (attr_mask & IB_QP_SQ_PSN)
1843 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1845 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1846 if (attr->max_dest_rd_atomic)
1848 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1849 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1852 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1853 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1854 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1858 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1860 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1861 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1862 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1864 if (attr_mask & IB_QP_RQ_PSN)
1865 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1867 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1868 if (attr_mask & IB_QP_QKEY) {
1869 if (qp->mlx4_ib_qp_type &
1870 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1871 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1873 if (mlx4_is_mfunc(dev->dev) &&
1874 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1875 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1876 MLX4_RESERVED_QKEY_BASE) {
1877 pr_err("Cannot use reserved QKEY"
1878 " 0x%x (range 0xffff0000..0xffffffff"
1879 " is reserved)\n", attr->qkey);
1883 context->qkey = cpu_to_be32(attr->qkey);
1885 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1889 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1891 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1892 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1894 if (cur_state == IB_QPS_INIT &&
1895 new_state == IB_QPS_RTR &&
1896 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1897 ibqp->qp_type == IB_QPT_UD ||
1898 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1899 context->pri_path.sched_queue = (qp->port - 1) << 6;
1900 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1901 qp->mlx4_ib_qp_type &
1902 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1903 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1904 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1905 context->pri_path.fl = 0x80;
1907 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1908 context->pri_path.fl = 0x80;
1909 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1911 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1912 IB_LINK_LAYER_ETHERNET) {
1913 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1914 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1915 context->pri_path.feup = 1 << 7; /* don't fsm */
1916 /* handle smac_index */
1917 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1918 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1919 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1920 err = handle_eth_ud_smac_index(dev, qp, context);
1925 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1926 dev->qp1_proxy[qp->port - 1] = qp;
1931 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1932 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1933 MLX4_IB_LINK_TYPE_ETH;
1934 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1935 /* set QP to receive both tunneled & non-tunneled packets */
1936 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
1937 context->srqn = cpu_to_be32(7 << 28);
1941 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1942 int is_eth = rdma_port_get_link_layer(
1943 &dev->ib_dev, qp->port) ==
1944 IB_LINK_LAYER_ETHERNET;
1946 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1947 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1952 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1953 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1958 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1959 context->rlkey_roce_mode |= (1 << 4);
1962 * Before passing a kernel QP to the HW, make sure that the
1963 * ownership bits of the send queue are set and the SQ
1964 * headroom is stamped so that the hardware doesn't start
1965 * processing stale work requests.
1967 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1968 struct mlx4_wqe_ctrl_seg *ctrl;
1971 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1972 ctrl = get_send_wqe(qp, i);
1973 ctrl->owner_opcode = cpu_to_be32(1 << 31);
1974 if (qp->sq_max_wqes_per_wr == 1)
1975 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1977 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1981 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1982 to_mlx4_state(new_state), context, optpar,
1983 sqd_event, &qp->mqp);
1987 qp->state = new_state;
1989 if (attr_mask & IB_QP_ACCESS_FLAGS)
1990 qp->atomic_rd_en = attr->qp_access_flags;
1991 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1992 qp->resp_depth = attr->max_dest_rd_atomic;
1993 if (attr_mask & IB_QP_PORT) {
1994 qp->port = attr->port_num;
1995 update_mcg_macs(dev, qp);
1997 if (attr_mask & IB_QP_ALT_PATH)
1998 qp->alt_port = attr->alt_port_num;
2000 if (is_sqp(dev, qp))
2001 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2004 * If we moved QP0 to RTR, bring the IB link up; if we moved
2005 * QP0 to RESET or ERROR, bring the link back down.
2007 if (is_qp0(dev, qp)) {
2008 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
2009 if (mlx4_INIT_PORT(dev->dev, qp->port))
2010 pr_warn("INIT_PORT failed for port %d\n",
2013 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2014 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2015 mlx4_CLOSE_PORT(dev->dev, qp->port);
2019 * If we moved a kernel QP to RESET, clean up all old CQ
2020 * entries and reinitialize the QP.
2022 if (new_state == IB_QPS_RESET) {
2023 if (!ibqp->uobject) {
2024 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2025 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2026 if (send_cq != recv_cq)
2027 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2033 qp->sq_next_wqe = 0;
2037 if (qp->flags & MLX4_IB_QP_NETIF)
2038 mlx4_ib_steer_qp_reg(dev, qp, 0);
2040 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2041 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2043 qp->pri.smac_port = 0;
2046 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2049 if (qp->pri.vid < 0x1000) {
2050 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2051 qp->pri.vid = 0xFFFF;
2052 qp->pri.candidate_vid = 0xFFFF;
2053 qp->pri.update_vid = 0;
2056 if (qp->alt.vid < 0x1000) {
2057 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2058 qp->alt.vid = 0xFFFF;
2059 qp->alt.candidate_vid = 0xFFFF;
2060 qp->alt.update_vid = 0;
2064 if (err && qp->counter_index)
2065 mlx4_ib_free_qp_counter(dev, qp);
2066 if (err && steer_qp)
2067 mlx4_ib_steer_qp_reg(dev, qp, 0);
2069 if (qp->pri.candidate_smac ||
2070 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2072 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2074 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2075 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2076 qp->pri.smac = qp->pri.candidate_smac;
2077 qp->pri.smac_index = qp->pri.candidate_smac_index;
2078 qp->pri.smac_port = qp->pri.candidate_smac_port;
2080 qp->pri.candidate_smac = 0;
2081 qp->pri.candidate_smac_index = 0;
2082 qp->pri.candidate_smac_port = 0;
2084 if (qp->alt.candidate_smac) {
2086 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2089 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2090 qp->alt.smac = qp->alt.candidate_smac;
2091 qp->alt.smac_index = qp->alt.candidate_smac_index;
2092 qp->alt.smac_port = qp->alt.candidate_smac_port;
2094 qp->alt.candidate_smac = 0;
2095 qp->alt.candidate_smac_index = 0;
2096 qp->alt.candidate_smac_port = 0;
2099 if (qp->pri.update_vid) {
2101 if (qp->pri.candidate_vid < 0x1000)
2102 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2103 qp->pri.candidate_vid);
2105 if (qp->pri.vid < 0x1000)
2106 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2108 qp->pri.vid = qp->pri.candidate_vid;
2109 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2110 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2112 qp->pri.candidate_vid = 0xFFFF;
2113 qp->pri.update_vid = 0;
2116 if (qp->alt.update_vid) {
2118 if (qp->alt.candidate_vid < 0x1000)
2119 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2120 qp->alt.candidate_vid);
2122 if (qp->alt.vid < 0x1000)
2123 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2125 qp->alt.vid = qp->alt.candidate_vid;
2126 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2127 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2129 qp->alt.candidate_vid = 0xFFFF;
2130 qp->alt.update_vid = 0;
2136 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2137 int attr_mask, struct ib_udata *udata)
2139 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2140 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2141 enum ib_qp_state cur_state, new_state;
2144 mutex_lock(&qp->mutex);
2146 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2147 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2149 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2150 ll = IB_LINK_LAYER_UNSPECIFIED;
2152 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2153 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2156 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2158 pr_debug("qpn 0x%x: invalid attribute mask specified "
2159 "for transition %d to %d. qp_type %d,"
2160 " attr_mask 0x%x\n",
2161 ibqp->qp_num, cur_state, new_state,
2162 ibqp->qp_type, attr_mask);
2166 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2167 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2168 if ((ibqp->qp_type == IB_QPT_RC) ||
2169 (ibqp->qp_type == IB_QPT_UD) ||
2170 (ibqp->qp_type == IB_QPT_UC) ||
2171 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2172 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2173 attr->port_num = mlx4_ib_bond_next_port(dev);
2176 /* no sense in changing port_num
2177 * when ports are bonded */
2178 attr_mask &= ~IB_QP_PORT;
2182 if ((attr_mask & IB_QP_PORT) &&
2183 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2184 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2185 "for transition %d to %d. qp_type %d\n",
2186 ibqp->qp_num, attr->port_num, cur_state,
2187 new_state, ibqp->qp_type);
2191 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2192 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2193 IB_LINK_LAYER_ETHERNET))
2196 if (attr_mask & IB_QP_PKEY_INDEX) {
2197 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2198 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2199 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2200 "for transition %d to %d. qp_type %d\n",
2201 ibqp->qp_num, attr->pkey_index, cur_state,
2202 new_state, ibqp->qp_type);
2207 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2208 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2209 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2210 "Transition %d to %d. qp_type %d\n",
2211 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2212 new_state, ibqp->qp_type);
2216 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2217 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2218 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2219 "Transition %d to %d. qp_type %d\n",
2220 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2221 new_state, ibqp->qp_type);
2225 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2230 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2232 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2236 mutex_unlock(&qp->mutex);
2240 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2241 int attr_mask, struct ib_udata *udata)
2243 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2246 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2248 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2249 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2252 if (sqp->roce_v2_gsi)
2253 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2255 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2261 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2264 for (i = 0; i < dev->caps.num_ports; i++) {
2265 if (qpn == dev->caps.qp0_proxy[i] ||
2266 qpn == dev->caps.qp0_tunnel[i]) {
2267 *qkey = dev->caps.qp0_qkey[i];
2274 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2275 struct ib_ud_wr *wr,
2276 void *wqe, unsigned *mlx_seg_len)
2278 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2279 struct ib_device *ib_dev = &mdev->ib_dev;
2280 struct mlx4_wqe_mlx_seg *mlx = wqe;
2281 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2282 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2290 if (wr->wr.opcode != IB_WR_SEND)
2295 for (i = 0; i < wr->wr.num_sge; ++i)
2296 send_size += wr->wr.sg_list[i].length;
2298 /* for proxy-qp0 sends, need to add in size of tunnel header */
2299 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2300 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2301 send_size += sizeof (struct mlx4_ib_tunnel_header);
2303 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
2305 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2306 sqp->ud_header.lrh.service_level =
2307 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2308 sqp->ud_header.lrh.destination_lid =
2309 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2310 sqp->ud_header.lrh.source_lid =
2311 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2314 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2316 /* force loopback */
2317 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2318 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2320 sqp->ud_header.lrh.virtual_lane = 0;
2321 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2322 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2323 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2324 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2325 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2327 sqp->ud_header.bth.destination_qpn =
2328 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
2330 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2331 if (mlx4_is_master(mdev->dev)) {
2332 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2335 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2338 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2339 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2341 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2342 sqp->ud_header.immediate_present = 0;
2344 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2347 * Inline data segments may not cross a 64 byte boundary. If
2348 * our UD header is bigger than the space available up to the
2349 * next 64 byte boundary in the WQE, use two inline data
2350 * segments to hold the UD header.
2352 spc = MLX4_INLINE_ALIGN -
2353 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2354 if (header_size <= spc) {
2355 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2356 memcpy(inl + 1, sqp->header_buf, header_size);
2359 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2360 memcpy(inl + 1, sqp->header_buf, spc);
2362 inl = (void *) (inl + 1) + spc;
2363 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2365 * Need a barrier here to make sure all the data is
2366 * visible before the byte_count field is set.
2367 * Otherwise the HCA prefetcher could grab the 64-byte
2368 * chunk with this inline segment and get a valid (!=
2369 * 0xffffffff) byte count but stale data, and end up
2370 * generating a packet with bad headers.
2372 * The first inline segment's byte_count field doesn't
2373 * need a barrier, because it comes after a
2374 * control/MLX segment and therefore is at an offset
2378 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2383 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2387 #define MLX4_ROCEV2_QP1_SPORT 0xC000
2388 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
2389 void *wqe, unsigned *mlx_seg_len)
2391 struct ib_device *ib_dev = sqp->qp.ibqp.device;
2392 struct mlx4_wqe_mlx_seg *mlx = wqe;
2393 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2394 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2395 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2405 bool is_vlan = false;
2407 bool is_udp = false;
2411 for (i = 0; i < wr->wr.num_sge; ++i)
2412 send_size += wr->wr.sg_list[i].length;
2414 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2415 is_grh = mlx4_ib_ah_grh_present(ah);
2417 struct ib_gid_attr gid_attr;
2419 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2420 /* When multi-function is enabled, the ib_core gid
2421 * indexes don't necessarily match the hw ones, so
2422 * we must use our own cache */
2423 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2424 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2425 ah->av.ib.gid_index, &sgid.raw[0]);
2429 err = ib_get_cached_gid(ib_dev,
2430 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2431 ah->av.ib.gid_index, &sgid,
2435 dev_put(gid_attr.ndev);
2436 if (!memcmp(&sgid, &zgid, sizeof(sgid)))
2440 is_udp = gid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2442 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
2452 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2453 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2457 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
2458 ip_version, is_udp, 0, &sqp->ud_header);
2463 sqp->ud_header.lrh.service_level =
2464 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2465 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2466 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2469 if (is_grh || (ip_version == 6)) {
2470 sqp->ud_header.grh.traffic_class =
2471 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2472 sqp->ud_header.grh.flow_label =
2473 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2474 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
2476 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2478 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2479 /* When multi-function is enabled, the ib_core gid
2480 * indexes don't necessarily match the hw ones, so
2481 * we must use our own cache */
2482 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2483 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2485 sqp->ud_header.grh.source_gid.global.interface_id =
2486 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2487 guid_cache[ah->av.ib.gid_index];
2489 ib_get_cached_gid(ib_dev,
2490 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2491 ah->av.ib.gid_index,
2492 &sqp->ud_header.grh.source_gid, NULL);
2494 memcpy(sqp->ud_header.grh.destination_gid.raw,
2495 ah->av.ib.dgid, 16);
2498 if (ip_version == 4) {
2499 sqp->ud_header.ip4.tos =
2500 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2501 sqp->ud_header.ip4.id = 0;
2502 sqp->ud_header.ip4.frag_off = htons(IP_DF);
2503 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
2505 memcpy(&sqp->ud_header.ip4.saddr,
2507 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
2508 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
2512 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
2513 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
2514 sqp->ud_header.udp.csum = 0;
2517 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2520 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2521 (sqp->ud_header.lrh.destination_lid ==
2522 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2523 (sqp->ud_header.lrh.service_level << 8));
2524 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2525 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2526 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2529 switch (wr->wr.opcode) {
2531 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2532 sqp->ud_header.immediate_present = 0;
2534 case IB_WR_SEND_WITH_IMM:
2535 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2536 sqp->ud_header.immediate_present = 1;
2537 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
2544 struct in6_addr in6;
2546 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2548 ether_type = (!is_udp) ? MLX4_IB_IBOE_ETHERTYPE :
2549 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
2551 mlx->sched_prio = cpu_to_be16(pcp);
2553 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
2554 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2555 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2556 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2557 memcpy(&in6, sgid.raw, sizeof(in6));
2560 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2561 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2563 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
2565 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
2566 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2569 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
2570 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2571 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2573 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2574 if (!sqp->qp.ibqp.qp_num)
2575 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2577 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
2578 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2579 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2580 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2581 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2582 sqp->qkey : wr->remote_qkey);
2583 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2585 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2588 pr_err("built UD header of size %d:\n", header_size);
2589 for (i = 0; i < header_size / 4; ++i) {
2591 pr_err(" [%02x] ", i * 4);
2593 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2594 if ((i + 1) % 8 == 0)
2601 * Inline data segments may not cross a 64 byte boundary. If
2602 * our UD header is bigger than the space available up to the
2603 * next 64 byte boundary in the WQE, use two inline data
2604 * segments to hold the UD header.
2606 spc = MLX4_INLINE_ALIGN -
2607 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2608 if (header_size <= spc) {
2609 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2610 memcpy(inl + 1, sqp->header_buf, header_size);
2613 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2614 memcpy(inl + 1, sqp->header_buf, spc);
2616 inl = (void *) (inl + 1) + spc;
2617 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2619 * Need a barrier here to make sure all the data is
2620 * visible before the byte_count field is set.
2621 * Otherwise the HCA prefetcher could grab the 64-byte
2622 * chunk with this inline segment and get a valid (!=
2623 * 0xffffffff) byte count but stale data, and end up
2624 * generating a packet with bad headers.
2626 * The first inline segment's byte_count field doesn't
2627 * need a barrier, because it comes after a
2628 * control/MLX segment and therefore is at an offset
2632 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2637 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2641 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2644 struct mlx4_ib_cq *cq;
2646 cur = wq->head - wq->tail;
2647 if (likely(cur + nreq < wq->max_post))
2651 spin_lock(&cq->lock);
2652 cur = wq->head - wq->tail;
2653 spin_unlock(&cq->lock);
2655 return cur + nreq >= wq->max_post;
2658 static __be32 convert_access(int acc)
2660 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2661 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2662 (acc & IB_ACCESS_REMOTE_WRITE ?
2663 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2664 (acc & IB_ACCESS_REMOTE_READ ?
2665 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
2666 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2667 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2670 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2671 struct ib_reg_wr *wr)
2673 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2675 fseg->flags = convert_access(wr->access);
2676 fseg->mem_key = cpu_to_be32(wr->key);
2677 fseg->buf_list = cpu_to_be64(mr->page_map);
2678 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
2679 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
2680 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2681 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
2682 fseg->reserved[0] = 0;
2683 fseg->reserved[1] = 0;
2686 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2688 memset(iseg, 0, sizeof(*iseg));
2689 iseg->mem_key = cpu_to_be32(rkey);
2692 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2693 u64 remote_addr, u32 rkey)
2695 rseg->raddr = cpu_to_be64(remote_addr);
2696 rseg->rkey = cpu_to_be32(rkey);
2700 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2701 struct ib_atomic_wr *wr)
2703 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2704 aseg->swap_add = cpu_to_be64(wr->swap);
2705 aseg->compare = cpu_to_be64(wr->compare_add);
2706 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2707 aseg->swap_add = cpu_to_be64(wr->compare_add);
2708 aseg->compare = cpu_to_be64(wr->compare_add_mask);
2710 aseg->swap_add = cpu_to_be64(wr->compare_add);
2716 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2717 struct ib_atomic_wr *wr)
2719 aseg->swap_add = cpu_to_be64(wr->swap);
2720 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
2721 aseg->compare = cpu_to_be64(wr->compare_add);
2722 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
2725 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2726 struct ib_ud_wr *wr)
2728 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2729 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2730 dseg->qkey = cpu_to_be32(wr->remote_qkey);
2731 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2732 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
2735 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2736 struct mlx4_wqe_datagram_seg *dseg,
2737 struct ib_ud_wr *wr,
2738 enum mlx4_ib_qp_type qpt)
2740 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
2741 struct mlx4_av sqp_av = {0};
2742 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2744 /* force loopback */
2745 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2746 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2747 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2748 cpu_to_be32(0xf0000000);
2750 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2751 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2752 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2754 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
2755 /* Use QKEY from the QP context, which is set by master */
2756 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2759 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
2761 struct mlx4_wqe_inline_seg *inl = wqe;
2762 struct mlx4_ib_tunnel_header hdr;
2763 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2767 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2768 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2769 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2770 hdr.qkey = cpu_to_be32(wr->remote_qkey);
2771 memcpy(hdr.mac, ah->av.eth.mac, 6);
2772 hdr.vlan = ah->av.eth.vlan;
2774 spc = MLX4_INLINE_ALIGN -
2775 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2776 if (sizeof (hdr) <= spc) {
2777 memcpy(inl + 1, &hdr, sizeof (hdr));
2779 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2782 memcpy(inl + 1, &hdr, spc);
2784 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2786 inl = (void *) (inl + 1) + spc;
2787 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2789 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2794 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2797 static void set_mlx_icrc_seg(void *dseg)
2800 struct mlx4_wqe_inline_seg *iseg = dseg;
2805 * Need a barrier here before writing the byte_count field to
2806 * make sure that all the data is visible before the
2807 * byte_count field is set. Otherwise, if the segment begins
2808 * a new cacheline, the HCA prefetcher could grab the 64-byte
2809 * chunk and get a valid (!= * 0xffffffff) byte count but
2810 * stale data, and end up sending the wrong data.
2814 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2817 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2819 dseg->lkey = cpu_to_be32(sg->lkey);
2820 dseg->addr = cpu_to_be64(sg->addr);
2823 * Need a barrier here before writing the byte_count field to
2824 * make sure that all the data is visible before the
2825 * byte_count field is set. Otherwise, if the segment begins
2826 * a new cacheline, the HCA prefetcher could grab the 64-byte
2827 * chunk and get a valid (!= * 0xffffffff) byte count but
2828 * stale data, and end up sending the wrong data.
2832 dseg->byte_count = cpu_to_be32(sg->length);
2835 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2837 dseg->byte_count = cpu_to_be32(sg->length);
2838 dseg->lkey = cpu_to_be32(sg->lkey);
2839 dseg->addr = cpu_to_be64(sg->addr);
2842 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
2843 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2844 __be32 *lso_hdr_sz, __be32 *blh)
2846 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
2848 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2849 *blh = cpu_to_be32(1 << 6);
2851 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2852 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
2855 memcpy(wqe->header, wr->header, wr->hlen);
2857 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
2858 *lso_seg_len = halign;
2862 static __be32 send_ieth(struct ib_send_wr *wr)
2864 switch (wr->opcode) {
2865 case IB_WR_SEND_WITH_IMM:
2866 case IB_WR_RDMA_WRITE_WITH_IMM:
2867 return wr->ex.imm_data;
2869 case IB_WR_SEND_WITH_INV:
2870 return cpu_to_be32(wr->ex.invalidate_rkey);
2877 static void add_zero_len_inline(void *wqe)
2879 struct mlx4_wqe_inline_seg *inl = wqe;
2881 inl->byte_count = cpu_to_be32(1 << 31);
2884 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2885 struct ib_send_wr **bad_wr)
2887 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2889 struct mlx4_wqe_ctrl_seg *ctrl;
2890 struct mlx4_wqe_data_seg *dseg;
2891 unsigned long flags;
2895 int uninitialized_var(stamp);
2896 int uninitialized_var(size);
2897 unsigned uninitialized_var(seglen);
2900 __be32 uninitialized_var(lso_hdr_sz);
2903 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2905 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2906 struct mlx4_ib_sqp *sqp = to_msqp(qp);
2908 if (sqp->roce_v2_gsi) {
2909 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
2910 struct ib_gid_attr gid_attr;
2913 if (!ib_get_cached_gid(ibqp->device,
2914 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2915 ah->av.ib.gid_index, &gid,
2918 dev_put(gid_attr.ndev);
2919 qp = (gid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
2920 to_mqp(sqp->roce_v2_gsi) : qp;
2922 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
2923 ah->av.ib.gid_index);
2928 spin_lock_irqsave(&qp->sq.lock, flags);
2929 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2936 ind = qp->sq_next_wqe;
2938 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2942 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2948 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2954 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2955 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2958 (wr->send_flags & IB_SEND_SIGNALED ?
2959 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2960 (wr->send_flags & IB_SEND_SOLICITED ?
2961 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2962 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2963 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2964 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2967 ctrl->imm = send_ieth(wr);
2969 wqe += sizeof *ctrl;
2970 size = sizeof *ctrl / 16;
2972 switch (qp->mlx4_ib_qp_type) {
2973 case MLX4_IB_QPT_RC:
2974 case MLX4_IB_QPT_UC:
2975 switch (wr->opcode) {
2976 case IB_WR_ATOMIC_CMP_AND_SWP:
2977 case IB_WR_ATOMIC_FETCH_AND_ADD:
2978 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2979 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2980 atomic_wr(wr)->rkey);
2981 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2983 set_atomic_seg(wqe, atomic_wr(wr));
2984 wqe += sizeof (struct mlx4_wqe_atomic_seg);
2986 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2987 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2991 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2992 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2993 atomic_wr(wr)->rkey);
2994 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2996 set_masked_atomic_seg(wqe, atomic_wr(wr));
2997 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
2999 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3000 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
3004 case IB_WR_RDMA_READ:
3005 case IB_WR_RDMA_WRITE:
3006 case IB_WR_RDMA_WRITE_WITH_IMM:
3007 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3009 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3010 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
3013 case IB_WR_LOCAL_INV:
3014 ctrl->srcrb_flags |=
3015 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3016 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3017 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3018 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3022 ctrl->srcrb_flags |=
3023 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3024 set_reg_seg(wqe, reg_wr(wr));
3025 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3026 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3030 /* No extra segments required for sends */
3035 case MLX4_IB_QPT_TUN_SMI_OWNER:
3036 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3038 if (unlikely(err)) {
3043 size += seglen / 16;
3045 case MLX4_IB_QPT_TUN_SMI:
3046 case MLX4_IB_QPT_TUN_GSI:
3047 /* this is a UD qp used in MAD responses to slaves. */
3048 set_datagram_seg(wqe, ud_wr(wr));
3049 /* set the forced-loopback bit in the data seg av */
3050 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3051 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3052 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3054 case MLX4_IB_QPT_UD:
3055 set_datagram_seg(wqe, ud_wr(wr));
3056 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3057 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3059 if (wr->opcode == IB_WR_LSO) {
3060 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3062 if (unlikely(err)) {
3066 lso_wqe = (__be32 *) wqe;
3068 size += seglen / 16;
3072 case MLX4_IB_QPT_PROXY_SMI_OWNER:
3073 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3075 if (unlikely(err)) {
3080 size += seglen / 16;
3081 /* to start tunnel header on a cache-line boundary */
3082 add_zero_len_inline(wqe);
3085 build_tunnel_header(ud_wr(wr), wqe, &seglen);
3087 size += seglen / 16;
3089 case MLX4_IB_QPT_PROXY_SMI:
3090 case MLX4_IB_QPT_PROXY_GSI:
3091 /* If we are tunneling special qps, this is a UD qp.
3092 * In this case we first add a UD segment targeting
3093 * the tunnel qp, and then add a header with address
3095 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3097 qp->mlx4_ib_qp_type);
3098 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3099 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3100 build_tunnel_header(ud_wr(wr), wqe, &seglen);
3102 size += seglen / 16;
3105 case MLX4_IB_QPT_SMI:
3106 case MLX4_IB_QPT_GSI:
3107 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3109 if (unlikely(err)) {
3114 size += seglen / 16;
3122 * Write data segments in reverse order, so as to
3123 * overwrite cacheline stamp last within each
3124 * cacheline. This avoids issues with WQE
3129 dseg += wr->num_sge - 1;
3130 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
3132 /* Add one more inline data segment for ICRC for MLX sends */
3133 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3134 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3135 qp->mlx4_ib_qp_type &
3136 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3137 set_mlx_icrc_seg(dseg + 1);
3138 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3141 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3142 set_data_seg(dseg, wr->sg_list + i);
3145 * Possibly overwrite stamping in cacheline with LSO
3146 * segment only after making sure all data segments
3150 *lso_wqe = lso_hdr_sz;
3152 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
3153 MLX4_WQE_CTRL_FENCE : 0) | size;
3156 * Make sure descriptor is fully written before
3157 * setting ownership bit (because HW can start
3158 * executing as soon as we do).
3162 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3168 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3169 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3171 stamp = ind + qp->sq_spare_wqes;
3172 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3175 * We can improve latency by not stamping the last
3176 * send queue WQE until after ringing the doorbell, so
3177 * only stamp here if there are still more WQEs to post.
3179 * Same optimization applies to padding with NOP wqe
3180 * in case of WQE shrinking (used to prevent wrap-around
3181 * in the middle of WR).
3184 stamp_send_wqe(qp, stamp, size * 16);
3185 ind = pad_wraparound(qp, ind);
3191 qp->sq.head += nreq;
3194 * Make sure that descriptors are written before
3199 writel(qp->doorbell_qpn,
3200 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3203 * Make sure doorbells don't leak out of SQ spinlock
3204 * and reach the HCA out of order.
3208 stamp_send_wqe(qp, stamp, size * 16);
3210 ind = pad_wraparound(qp, ind);
3211 qp->sq_next_wqe = ind;
3214 spin_unlock_irqrestore(&qp->sq.lock, flags);
3219 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3220 struct ib_recv_wr **bad_wr)
3222 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3223 struct mlx4_wqe_data_seg *scat;
3224 unsigned long flags;
3230 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3232 max_gs = qp->rq.max_gs;
3233 spin_lock_irqsave(&qp->rq.lock, flags);
3235 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3242 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3244 for (nreq = 0; wr; ++nreq, wr = wr->next) {
3245 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3251 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3257 scat = get_recv_wqe(qp, ind);
3259 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3260 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3261 ib_dma_sync_single_for_device(ibqp->device,
3262 qp->sqp_proxy_rcv[ind].map,
3263 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3266 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3267 /* use dma lkey from upper layer entry */
3268 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3269 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3274 for (i = 0; i < wr->num_sge; ++i)
3275 __set_data_seg(scat + i, wr->sg_list + i);
3278 scat[i].byte_count = 0;
3279 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3283 qp->rq.wrid[ind] = wr->wr_id;
3285 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3290 qp->rq.head += nreq;
3293 * Make sure that descriptors are written before
3298 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3301 spin_unlock_irqrestore(&qp->rq.lock, flags);
3306 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3308 switch (mlx4_state) {
3309 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3310 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3311 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3312 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3313 case MLX4_QP_STATE_SQ_DRAINING:
3314 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3315 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3316 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3321 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3323 switch (mlx4_mig_state) {
3324 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3325 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3326 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3331 static int to_ib_qp_access_flags(int mlx4_flags)
3335 if (mlx4_flags & MLX4_QP_BIT_RRE)
3336 ib_flags |= IB_ACCESS_REMOTE_READ;
3337 if (mlx4_flags & MLX4_QP_BIT_RWE)
3338 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3339 if (mlx4_flags & MLX4_QP_BIT_RAE)
3340 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3345 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3346 struct mlx4_qp_path *path)
3348 struct mlx4_dev *dev = ibdev->dev;
3351 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
3352 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3354 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3357 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3358 IB_LINK_LAYER_ETHERNET;
3360 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3361 ((path->sched_queue & 4) << 1);
3363 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3365 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
3366 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3367 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3368 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3369 if (ib_ah_attr->ah_flags) {
3370 ib_ah_attr->grh.sgid_index = path->mgid_index;
3371 ib_ah_attr->grh.hop_limit = path->hop_limit;
3372 ib_ah_attr->grh.traffic_class =
3373 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3374 ib_ah_attr->grh.flow_label =
3375 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3376 memcpy(ib_ah_attr->grh.dgid.raw,
3377 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3381 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3382 struct ib_qp_init_attr *qp_init_attr)
3384 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3385 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3386 struct mlx4_qp_context context;
3390 mutex_lock(&qp->mutex);
3392 if (qp->state == IB_QPS_RESET) {
3393 qp_attr->qp_state = IB_QPS_RESET;
3397 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3403 mlx4_state = be32_to_cpu(context.flags) >> 28;
3405 qp->state = to_ib_qp_state(mlx4_state);
3406 qp_attr->qp_state = qp->state;
3407 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3408 qp_attr->path_mig_state =
3409 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3410 qp_attr->qkey = be32_to_cpu(context.qkey);
3411 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3412 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3413 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3414 qp_attr->qp_access_flags =
3415 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3417 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3418 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3419 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3420 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3421 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3424 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3425 if (qp_attr->qp_state == IB_QPS_INIT)
3426 qp_attr->port_num = qp->port;
3428 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3430 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3431 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3433 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3435 qp_attr->max_dest_rd_atomic =
3436 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3437 qp_attr->min_rnr_timer =
3438 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3439 qp_attr->timeout = context.pri_path.ackto >> 3;
3440 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3441 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3442 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3445 qp_attr->cur_qp_state = qp_attr->qp_state;
3446 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3447 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3449 if (!ibqp->uobject) {
3450 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3451 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3453 qp_attr->cap.max_send_wr = 0;
3454 qp_attr->cap.max_send_sge = 0;
3458 * We don't support inline sends for kernel QPs (yet), and we
3459 * don't know what userspace's value should be.
3461 qp_attr->cap.max_inline_data = 0;
3463 qp_init_attr->cap = qp_attr->cap;
3465 qp_init_attr->create_flags = 0;
3466 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3467 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3469 if (qp->flags & MLX4_IB_QP_LSO)
3470 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3472 if (qp->flags & MLX4_IB_QP_NETIF)
3473 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3475 qp_init_attr->sq_sig_type =
3476 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3477 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3480 mutex_unlock(&qp->mutex);