2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38 #include <linux/netdevice.h>
39 #include <linux/inetdevice.h>
40 #include <linux/rtnetlink.h>
41 #include <linux/if_vlan.h>
42 #include <linux/sched/mm.h>
43 #include <linux/sched/task.h>
46 #include <net/addrconf.h>
47 #include <net/devlink.h>
49 #include <rdma/ib_smi.h>
50 #include <rdma/ib_user_verbs.h>
51 #include <rdma/ib_addr.h>
52 #include <rdma/ib_cache.h>
54 #include <net/bonding.h>
56 #include <linux/mlx4/driver.h>
57 #include <linux/mlx4/cmd.h>
58 #include <linux/mlx4/qp.h>
61 #include <rdma/mlx4-abi.h>
63 #define DRV_NAME MLX4_IB_DRV_NAME
64 #define DRV_VERSION "4.0-0"
66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
68 #define MLX4_IB_CARD_REV_A0 0xA0
70 MODULE_AUTHOR("Roland Dreier");
71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
72 MODULE_LICENSE("Dual BSD/GPL");
74 int mlx4_ib_sm_guid_assign = 0;
75 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
76 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
78 static const char mlx4_ib_version[] =
79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
82 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
83 static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device,
86 static struct workqueue_struct *wq;
88 static void init_query_mad(struct ib_smp *mad)
90 mad->base_version = 1;
91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
92 mad->class_version = 1;
93 mad->method = IB_MGMT_METHOD_GET;
96 static int check_flow_steering_support(struct mlx4_dev *dev)
98 int eth_num_ports = 0;
101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
109 dmfs &= (!ib_num_ports ||
110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
113 if (ib_num_ports && mlx4_is_mfunc(dev)) {
114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
121 static int num_ib_ports(struct mlx4_dev *dev)
126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
134 struct mlx4_ib_dev *ibdev = to_mdev(device);
135 struct net_device *dev;
138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
141 if (mlx4_is_bonded(ibdev->dev)) {
142 struct net_device *upper = NULL;
144 upper = netdev_master_upper_dev_get_rcu(dev);
146 struct net_device *active;
148 active = bond_option_active_slave_get_rcu(netdev_priv(upper));
161 static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
162 struct mlx4_ib_dev *ibdev,
165 struct mlx4_cmd_mailbox *mailbox;
167 struct mlx4_dev *dev = ibdev->dev;
169 union ib_gid *gid_tbl;
171 mailbox = mlx4_alloc_cmd_mailbox(dev);
175 gid_tbl = mailbox->buf;
177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
180 err = mlx4_cmd(dev, mailbox->dma,
181 MLX4_SET_PORT_GID_TABLE << 8 | port_num,
182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
184 if (mlx4_is_bonded(dev))
185 err += mlx4_cmd(dev, mailbox->dma,
186 MLX4_SET_PORT_GID_TABLE << 8 | 2,
187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
190 mlx4_free_cmd_mailbox(dev, mailbox);
194 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
195 struct mlx4_ib_dev *ibdev,
198 struct mlx4_cmd_mailbox *mailbox;
200 struct mlx4_dev *dev = ibdev->dev;
211 mailbox = mlx4_alloc_cmd_mailbox(dev);
215 gid_tbl = mailbox->buf;
216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
219 gid_tbl[i].version = 2;
220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
225 err = mlx4_cmd(dev, mailbox->dma,
226 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
227 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
229 if (mlx4_is_bonded(dev))
230 err += mlx4_cmd(dev, mailbox->dma,
231 MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
232 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
235 mlx4_free_cmd_mailbox(dev, mailbox);
239 static int mlx4_ib_update_gids(struct gid_entry *gids,
240 struct mlx4_ib_dev *ibdev,
243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
244 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
246 return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
249 static int mlx4_ib_add_gid(const struct ib_gid_attr *attr, void **context)
251 struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
252 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
253 struct mlx4_port_gid_table *port_gid_table;
254 int free = -1, found = -1;
258 struct gid_entry *gids = NULL;
260 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
263 if (attr->port_num > MLX4_MAX_PORTS)
269 port_gid_table = &iboe->gids[attr->port_num - 1];
270 spin_lock_bh(&iboe->lock);
271 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
272 if (!memcmp(&port_gid_table->gids[i].gid,
273 &attr->gid, sizeof(attr->gid)) &&
274 port_gid_table->gids[i].gid_type == attr->gid_type) {
278 if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid))
279 free = i; /* HW has space */
286 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
287 if (!port_gid_table->gids[free].ctx) {
290 *context = port_gid_table->gids[free].ctx;
291 memcpy(&port_gid_table->gids[free].gid,
292 &attr->gid, sizeof(attr->gid));
293 port_gid_table->gids[free].gid_type = attr->gid_type;
294 port_gid_table->gids[free].ctx->real_index = free;
295 port_gid_table->gids[free].ctx->refcount = 1;
300 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
304 if (!ret && hw_update) {
305 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
310 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
311 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
312 gids[i].gid_type = port_gid_table->gids[i].gid_type;
316 spin_unlock_bh(&iboe->lock);
318 if (!ret && hw_update) {
319 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
326 static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context)
328 struct gid_cache_context *ctx = *context;
329 struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
330 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
331 struct mlx4_port_gid_table *port_gid_table;
334 struct gid_entry *gids = NULL;
336 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
339 if (attr->port_num > MLX4_MAX_PORTS)
342 port_gid_table = &iboe->gids[attr->port_num - 1];
343 spin_lock_bh(&iboe->lock);
346 if (!ctx->refcount) {
347 unsigned int real_index = ctx->real_index;
349 memset(&port_gid_table->gids[real_index].gid, 0,
350 sizeof(port_gid_table->gids[real_index].gid));
351 kfree(port_gid_table->gids[real_index].ctx);
352 port_gid_table->gids[real_index].ctx = NULL;
356 if (!ret && hw_update) {
359 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
364 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
366 &port_gid_table->gids[i].gid,
367 sizeof(union ib_gid));
369 port_gid_table->gids[i].gid_type;
373 spin_unlock_bh(&iboe->lock);
375 if (!ret && hw_update) {
376 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
382 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
383 const struct ib_gid_attr *attr)
385 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
386 struct gid_cache_context *ctx = NULL;
387 struct mlx4_port_gid_table *port_gid_table;
388 int real_index = -EINVAL;
391 u8 port_num = attr->port_num;
393 if (port_num > MLX4_MAX_PORTS)
396 if (mlx4_is_bonded(ibdev->dev))
399 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
402 spin_lock_irqsave(&iboe->lock, flags);
403 port_gid_table = &iboe->gids[port_num - 1];
405 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
406 if (!memcmp(&port_gid_table->gids[i].gid,
407 &attr->gid, sizeof(attr->gid)) &&
408 attr->gid_type == port_gid_table->gids[i].gid_type) {
409 ctx = port_gid_table->gids[i].ctx;
413 real_index = ctx->real_index;
414 spin_unlock_irqrestore(&iboe->lock, flags);
418 #define field_avail(type, fld, sz) (offsetof(type, fld) + \
419 sizeof(((type *)0)->fld) <= (sz))
421 static int mlx4_ib_query_device(struct ib_device *ibdev,
422 struct ib_device_attr *props,
423 struct ib_udata *uhw)
425 struct mlx4_ib_dev *dev = to_mdev(ibdev);
426 struct ib_smp *in_mad = NULL;
427 struct ib_smp *out_mad = NULL;
430 struct mlx4_uverbs_ex_query_device cmd;
431 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
432 struct mlx4_clock_params clock_params;
435 if (uhw->inlen < sizeof(cmd))
438 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
449 resp.response_length = offsetof(typeof(resp), response_length) +
450 sizeof(resp.response_length);
451 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
452 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
454 if (!in_mad || !out_mad)
457 init_query_mad(in_mad);
458 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
460 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
461 1, NULL, NULL, in_mad, out_mad);
465 memset(props, 0, sizeof *props);
467 have_ib_ports = num_ib_ports(dev->dev);
469 props->fw_ver = dev->dev->caps.fw_ver;
470 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
471 IB_DEVICE_PORT_ACTIVE_EVENT |
472 IB_DEVICE_SYS_IMAGE_GUID |
473 IB_DEVICE_RC_RNR_NAK_GEN |
474 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
475 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
476 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
477 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
478 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
479 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
480 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
481 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
482 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
483 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
484 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
485 if (dev->dev->caps.max_gso_sz &&
486 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
487 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
488 props->device_cap_flags |= IB_DEVICE_UD_TSO;
489 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
490 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
491 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
492 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
493 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
494 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
495 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
496 props->device_cap_flags |= IB_DEVICE_XRC;
497 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
498 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
499 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
500 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
501 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
503 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
505 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
506 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
508 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
510 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
512 props->vendor_part_id = dev->dev->persist->pdev->device;
513 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
514 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
516 props->max_mr_size = ~0ull;
517 props->page_size_cap = dev->dev->caps.page_size_cap;
518 props->max_qp = dev->dev->quotas.qp;
519 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
520 props->max_send_sge = dev->dev->caps.max_sq_sg;
521 props->max_recv_sge = dev->dev->caps.max_rq_sg;
522 props->max_sge_rd = MLX4_MAX_SGE_RD;
523 props->max_cq = dev->dev->quotas.cq;
524 props->max_cqe = dev->dev->caps.max_cqes;
525 props->max_mr = dev->dev->quotas.mpt;
526 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
527 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
528 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
529 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
530 props->max_srq = dev->dev->quotas.srq;
531 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
532 props->max_srq_sge = dev->dev->caps.max_srq_sge;
533 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
534 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
535 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
536 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
537 props->masked_atomic_cap = props->atomic_cap;
538 props->max_pkeys = dev->dev->caps.pkey_table_len[1];
539 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
540 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
541 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
542 props->max_mcast_grp;
543 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
544 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
545 props->timestamp_mask = 0xFFFFFFFFFFFFULL;
546 props->max_ah = INT_MAX;
548 if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET ||
549 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) {
550 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) {
551 props->rss_caps.max_rwq_indirection_tables =
553 props->rss_caps.max_rwq_indirection_table_size =
554 dev->dev->caps.max_rss_tbl_sz;
555 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
556 props->max_wq_type_rq = props->max_qp;
559 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
560 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
563 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT;
564 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD;
566 if (!mlx4_is_slave(dev->dev))
567 err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
569 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
570 resp.response_length += sizeof(resp.hca_core_clock_offset);
571 if (!err && !mlx4_is_slave(dev->dev)) {
572 resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET;
573 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
577 if (uhw->outlen >= resp.response_length +
578 sizeof(resp.max_inl_recv_sz)) {
579 resp.response_length += sizeof(resp.max_inl_recv_sz);
580 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg *
581 sizeof(struct mlx4_wqe_data_seg);
584 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
585 if (props->rss_caps.supported_qpts) {
586 resp.rss_caps.rx_hash_function =
587 MLX4_IB_RX_HASH_FUNC_TOEPLITZ;
589 resp.rss_caps.rx_hash_fields_mask =
590 MLX4_IB_RX_HASH_SRC_IPV4 |
591 MLX4_IB_RX_HASH_DST_IPV4 |
592 MLX4_IB_RX_HASH_SRC_IPV6 |
593 MLX4_IB_RX_HASH_DST_IPV6 |
594 MLX4_IB_RX_HASH_SRC_PORT_TCP |
595 MLX4_IB_RX_HASH_DST_PORT_TCP |
596 MLX4_IB_RX_HASH_SRC_PORT_UDP |
597 MLX4_IB_RX_HASH_DST_PORT_UDP;
599 if (dev->dev->caps.tunnel_offload_mode ==
600 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
601 resp.rss_caps.rx_hash_fields_mask |=
602 MLX4_IB_RX_HASH_INNER;
604 resp.response_length = offsetof(typeof(resp), rss_caps) +
605 sizeof(resp.rss_caps);
608 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
609 if (dev->dev->caps.max_gso_sz &&
610 ((mlx4_ib_port_link_layer(ibdev, 1) ==
611 IB_LINK_LAYER_ETHERNET) ||
612 (mlx4_ib_port_link_layer(ibdev, 2) ==
613 IB_LINK_LAYER_ETHERNET))) {
614 resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz;
615 resp.tso_caps.supported_qpts |=
616 1 << IB_QPT_RAW_PACKET;
618 resp.response_length = offsetof(typeof(resp), tso_caps) +
619 sizeof(resp.tso_caps);
623 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
634 static enum rdma_link_layer
635 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
637 struct mlx4_dev *dev = to_mdev(device)->dev;
639 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
640 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
643 static int ib_link_query_port(struct ib_device *ibdev, u8 port,
644 struct ib_port_attr *props, int netw_view)
646 struct ib_smp *in_mad = NULL;
647 struct ib_smp *out_mad = NULL;
648 int ext_active_speed;
649 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
652 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
653 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
654 if (!in_mad || !out_mad)
657 init_query_mad(in_mad);
658 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
659 in_mad->attr_mod = cpu_to_be32(port);
661 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
662 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
664 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
670 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
671 props->lmc = out_mad->data[34] & 0x7;
672 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
673 props->sm_sl = out_mad->data[36] & 0xf;
674 props->state = out_mad->data[32] & 0xf;
675 props->phys_state = out_mad->data[33] >> 4;
676 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
678 props->gid_tbl_len = out_mad->data[50];
680 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
681 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
682 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
683 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
684 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
685 props->active_width = out_mad->data[31] & 0xf;
686 props->active_speed = out_mad->data[35] >> 4;
687 props->max_mtu = out_mad->data[41] & 0xf;
688 props->active_mtu = out_mad->data[36] >> 4;
689 props->subnet_timeout = out_mad->data[51] & 0x1f;
690 props->max_vl_num = out_mad->data[37] >> 4;
691 props->init_type_reply = out_mad->data[41] >> 4;
693 /* Check if extended speeds (EDR/FDR/...) are supported */
694 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
695 ext_active_speed = out_mad->data[62] >> 4;
697 switch (ext_active_speed) {
699 props->active_speed = IB_SPEED_FDR;
702 props->active_speed = IB_SPEED_EDR;
707 /* If reported active speed is QDR, check if is FDR-10 */
708 if (props->active_speed == IB_SPEED_QDR) {
709 init_query_mad(in_mad);
710 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
711 in_mad->attr_mod = cpu_to_be32(port);
713 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
714 NULL, NULL, in_mad, out_mad);
718 /* Checking LinkSpeedActive for FDR-10 */
719 if (out_mad->data[15] & 0x1)
720 props->active_speed = IB_SPEED_FDR10;
723 /* Avoid wrong speed value returned by FW if the IB link is down. */
724 if (props->state == IB_PORT_DOWN)
725 props->active_speed = IB_SPEED_SDR;
733 static u8 state_to_phys_state(enum ib_port_state state)
735 return state == IB_PORT_ACTIVE ? 5 : 3;
738 static int eth_link_query_port(struct ib_device *ibdev, u8 port,
739 struct ib_port_attr *props)
742 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
743 struct mlx4_ib_iboe *iboe = &mdev->iboe;
744 struct net_device *ndev;
746 struct mlx4_cmd_mailbox *mailbox;
748 int is_bonded = mlx4_is_bonded(mdev->dev);
750 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
752 return PTR_ERR(mailbox);
754 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
755 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
760 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
761 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
762 IB_WIDTH_4X : IB_WIDTH_1X;
763 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
764 IB_SPEED_FDR : IB_SPEED_QDR;
765 props->port_cap_flags = IB_PORT_CM_SUP;
766 props->ip_gids = true;
767 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
768 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
769 props->pkey_tbl_len = 1;
770 props->max_mtu = IB_MTU_4096;
771 props->max_vl_num = 2;
772 props->state = IB_PORT_DOWN;
773 props->phys_state = state_to_phys_state(props->state);
774 props->active_mtu = IB_MTU_256;
775 spin_lock_bh(&iboe->lock);
776 ndev = iboe->netdevs[port - 1];
777 if (ndev && is_bonded) {
778 rcu_read_lock(); /* required to get upper dev */
779 ndev = netdev_master_upper_dev_get_rcu(ndev);
785 tmp = iboe_get_mtu(ndev->mtu);
786 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
788 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
789 IB_PORT_ACTIVE : IB_PORT_DOWN;
790 props->phys_state = state_to_phys_state(props->state);
792 spin_unlock_bh(&iboe->lock);
794 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
798 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
799 struct ib_port_attr *props, int netw_view)
803 /* props being zeroed by the caller, avoid zeroing it here */
805 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
806 ib_link_query_port(ibdev, port, props, netw_view) :
807 eth_link_query_port(ibdev, port, props);
812 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
813 struct ib_port_attr *props)
815 /* returns host view */
816 return __mlx4_ib_query_port(ibdev, port, props, 0);
819 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
820 union ib_gid *gid, int netw_view)
822 struct ib_smp *in_mad = NULL;
823 struct ib_smp *out_mad = NULL;
825 struct mlx4_ib_dev *dev = to_mdev(ibdev);
827 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
829 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
830 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
831 if (!in_mad || !out_mad)
834 init_query_mad(in_mad);
835 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
836 in_mad->attr_mod = cpu_to_be32(port);
838 if (mlx4_is_mfunc(dev->dev) && netw_view)
839 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
841 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
845 memcpy(gid->raw, out_mad->data + 8, 8);
847 if (mlx4_is_mfunc(dev->dev) && !netw_view) {
849 /* For any index > 0, return the null guid */
856 init_query_mad(in_mad);
857 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
858 in_mad->attr_mod = cpu_to_be32(index / 8);
860 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
861 NULL, NULL, in_mad, out_mad);
865 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
869 memset(gid->raw + 8, 0, 8);
875 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
878 if (rdma_protocol_ib(ibdev, port))
879 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
883 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
885 union sl2vl_tbl_to_u64 sl2vl64;
886 struct ib_smp *in_mad = NULL;
887 struct ib_smp *out_mad = NULL;
888 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
892 if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
897 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
898 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
899 if (!in_mad || !out_mad)
902 init_query_mad(in_mad);
903 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
904 in_mad->attr_mod = 0;
906 if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
907 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
909 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
914 for (jj = 0; jj < 8; jj++)
915 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
916 *sl2vl_tbl = sl2vl64.sl64;
924 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
930 for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
931 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
933 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
935 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
939 atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
943 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
944 u16 *pkey, int netw_view)
946 struct ib_smp *in_mad = NULL;
947 struct ib_smp *out_mad = NULL;
948 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
951 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
952 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
953 if (!in_mad || !out_mad)
956 init_query_mad(in_mad);
957 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
958 in_mad->attr_mod = cpu_to_be32(index / 32);
960 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
961 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
963 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
968 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
976 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
978 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
981 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
982 struct ib_device_modify *props)
984 struct mlx4_cmd_mailbox *mailbox;
987 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
990 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
993 if (mlx4_is_slave(to_mdev(ibdev)->dev))
996 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
997 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
998 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
1001 * If possible, pass node desc to FW, so it can generate
1002 * a 144 trap. If cmd fails, just ignore.
1004 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
1005 if (IS_ERR(mailbox))
1008 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1009 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
1010 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1012 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
1017 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
1020 struct mlx4_cmd_mailbox *mailbox;
1023 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
1024 if (IS_ERR(mailbox))
1025 return PTR_ERR(mailbox);
1027 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1028 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
1029 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
1031 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
1032 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
1035 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
1036 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1039 mlx4_free_cmd_mailbox(dev->dev, mailbox);
1043 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1044 struct ib_port_modify *props)
1046 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
1047 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
1048 struct ib_port_attr attr;
1052 /* return OK if this is RoCE. CM calls ib_modify_port() regardless
1053 * of whether port link layer is ETH or IB. For ETH ports, qkey
1054 * violations and port capabilities are not meaningful.
1059 mutex_lock(&mdev->cap_mask_mutex);
1061 err = ib_query_port(ibdev, port, &attr);
1065 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
1066 ~props->clr_port_cap_mask;
1068 err = mlx4_ib_SET_PORT(mdev, port,
1069 !!(mask & IB_PORT_RESET_QKEY_CNTR),
1073 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
1077 static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
1078 struct ib_udata *udata)
1080 struct mlx4_ib_dev *dev = to_mdev(ibdev);
1081 struct mlx4_ib_ucontext *context;
1082 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
1083 struct mlx4_ib_alloc_ucontext_resp resp;
1086 if (!dev->ib_active)
1087 return ERR_PTR(-EAGAIN);
1089 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
1090 resp_v3.qp_tab_size = dev->dev->caps.num_qps;
1091 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
1092 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1094 resp.dev_caps = dev->dev->caps.userspace_caps;
1095 resp.qp_tab_size = dev->dev->caps.num_qps;
1096 resp.bf_reg_size = dev->dev->caps.bf_reg_size;
1097 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1098 resp.cqe_size = dev->dev->caps.cqe_size;
1101 context = kzalloc(sizeof(*context), GFP_KERNEL);
1103 return ERR_PTR(-ENOMEM);
1105 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
1108 return ERR_PTR(err);
1111 INIT_LIST_HEAD(&context->db_page_list);
1112 mutex_init(&context->db_page_mutex);
1114 INIT_LIST_HEAD(&context->wqn_ranges_list);
1115 mutex_init(&context->wqn_ranges_mutex);
1117 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
1118 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
1120 err = ib_copy_to_udata(udata, &resp, sizeof(resp));
1123 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
1125 return ERR_PTR(-EFAULT);
1128 return &context->ibucontext;
1131 static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1133 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1135 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
1141 static void mlx4_ib_vma_open(struct vm_area_struct *area)
1143 /* vma_open is called when a new VMA is created on top of our VMA.
1144 * This is done through either mremap flow or split_vma (usually due
1145 * to mlock, madvise, munmap, etc.). We do not support a clone of the
1146 * vma, as this VMA is strongly hardware related. Therefore we set the
1147 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1148 * calling us again and trying to do incorrect actions. We assume that
1149 * the original vma size is exactly a single page that there will be no
1150 * "splitting" operations on.
1152 area->vm_ops = NULL;
1155 static void mlx4_ib_vma_close(struct vm_area_struct *area)
1157 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
1159 /* It's guaranteed that all VMAs opened on a FD are closed before the
1160 * file itself is closed, therefore no sync is needed with the regular
1161 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
1162 * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
1163 * The close operation is usually called under mm->mmap_sem except when
1164 * process is exiting. The exiting case is handled explicitly as part
1165 * of mlx4_ib_disassociate_ucontext.
1167 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
1168 area->vm_private_data;
1170 /* set the vma context pointer to null in the mlx4_ib driver's private
1171 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
1173 mlx4_ib_vma_priv_data->vma = NULL;
1176 static const struct vm_operations_struct mlx4_ib_vm_ops = {
1177 .open = mlx4_ib_vma_open,
1178 .close = mlx4_ib_vma_close
1181 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1184 struct vm_area_struct *vma;
1185 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1187 /* need to protect from a race on closing the vma as part of
1188 * mlx4_ib_vma_close().
1190 for (i = 0; i < HW_BAR_COUNT; i++) {
1191 vma = context->hw_bar_info[i].vma;
1195 zap_vma_ptes(context->hw_bar_info[i].vma,
1196 context->hw_bar_info[i].vma->vm_start, PAGE_SIZE);
1198 context->hw_bar_info[i].vma->vm_flags &=
1199 ~(VM_SHARED | VM_MAYSHARE);
1200 /* context going to be destroyed, should not access ops any more */
1201 context->hw_bar_info[i].vma->vm_ops = NULL;
1205 static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
1206 struct mlx4_ib_vma_private_data *vma_private_data)
1208 vma_private_data->vma = vma;
1209 vma->vm_private_data = vma_private_data;
1210 vma->vm_ops = &mlx4_ib_vm_ops;
1213 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
1215 struct mlx4_ib_dev *dev = to_mdev(context->device);
1216 struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
1218 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1221 if (vma->vm_pgoff == 0) {
1222 /* We prevent double mmaping on same context */
1223 if (mucontext->hw_bar_info[HW_BAR_DB].vma)
1226 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1228 if (io_remap_pfn_range(vma, vma->vm_start,
1229 to_mucontext(context)->uar.pfn,
1230 PAGE_SIZE, vma->vm_page_prot))
1233 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
1235 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
1236 /* We prevent double mmaping on same context */
1237 if (mucontext->hw_bar_info[HW_BAR_BF].vma)
1240 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1242 if (io_remap_pfn_range(vma, vma->vm_start,
1243 to_mucontext(context)->uar.pfn +
1244 dev->dev->caps.num_uars,
1245 PAGE_SIZE, vma->vm_page_prot))
1248 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
1250 } else if (vma->vm_pgoff == 3) {
1251 struct mlx4_clock_params params;
1254 /* We prevent double mmaping on same context */
1255 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
1258 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms);
1263 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1264 if (io_remap_pfn_range(vma, vma->vm_start,
1265 (pci_resource_start(dev->dev->persist->pdev,
1269 PAGE_SIZE, vma->vm_page_prot))
1272 mlx4_ib_set_vma_data(vma,
1273 &mucontext->hw_bar_info[HW_BAR_CLOCK]);
1281 static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
1282 struct ib_ucontext *context,
1283 struct ib_udata *udata)
1285 struct mlx4_ib_pd *pd;
1288 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
1290 return ERR_PTR(-ENOMEM);
1292 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
1295 return ERR_PTR(err);
1299 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
1300 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
1302 return ERR_PTR(-EFAULT);
1307 static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
1309 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
1315 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
1316 struct ib_ucontext *context,
1317 struct ib_udata *udata)
1319 struct mlx4_ib_xrcd *xrcd;
1320 struct ib_cq_init_attr cq_attr = {};
1323 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1324 return ERR_PTR(-ENOSYS);
1326 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
1328 return ERR_PTR(-ENOMEM);
1330 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
1334 xrcd->pd = ib_alloc_pd(ibdev, 0);
1335 if (IS_ERR(xrcd->pd)) {
1336 err = PTR_ERR(xrcd->pd);
1341 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
1342 if (IS_ERR(xrcd->cq)) {
1343 err = PTR_ERR(xrcd->cq);
1347 return &xrcd->ibxrcd;
1350 ib_dealloc_pd(xrcd->pd);
1352 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
1355 return ERR_PTR(err);
1358 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
1360 ib_destroy_cq(to_mxrcd(xrcd)->cq);
1361 ib_dealloc_pd(to_mxrcd(xrcd)->pd);
1362 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
1368 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
1370 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1371 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1372 struct mlx4_ib_gid_entry *ge;
1374 ge = kzalloc(sizeof *ge, GFP_KERNEL);
1379 if (mlx4_ib_add_mc(mdev, mqp, gid)) {
1380 ge->port = mqp->port;
1384 mutex_lock(&mqp->mutex);
1385 list_add_tail(&ge->list, &mqp->gid_list);
1386 mutex_unlock(&mqp->mutex);
1391 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
1392 struct mlx4_ib_counters *ctr_table)
1394 struct counter_index *counter, *tmp_count;
1396 mutex_lock(&ctr_table->mutex);
1397 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
1399 if (counter->allocated)
1400 mlx4_counter_free(ibdev->dev, counter->index);
1401 list_del(&counter->list);
1404 mutex_unlock(&ctr_table->mutex);
1407 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
1410 struct net_device *ndev;
1416 spin_lock_bh(&mdev->iboe.lock);
1417 ndev = mdev->iboe.netdevs[mqp->port - 1];
1420 spin_unlock_bh(&mdev->iboe.lock);
1430 struct mlx4_ib_steering {
1431 struct list_head list;
1432 struct mlx4_flow_reg_id reg_id;
1436 #define LAST_ETH_FIELD vlan_tag
1437 #define LAST_IB_FIELD sl
1438 #define LAST_IPV4_FIELD dst_ip
1439 #define LAST_TCP_UDP_FIELD src_port
1441 /* Field is the last supported field */
1442 #define FIELDS_NOT_SUPPORTED(filter, field)\
1443 memchr_inv((void *)&filter.field +\
1444 sizeof(filter.field), 0,\
1446 offsetof(typeof(filter), field) -\
1447 sizeof(filter.field))
1449 static int parse_flow_attr(struct mlx4_dev *dev,
1451 union ib_flow_spec *ib_spec,
1452 struct _rule_hw *mlx4_spec)
1454 enum mlx4_net_trans_rule_id type;
1456 switch (ib_spec->type) {
1457 case IB_FLOW_SPEC_ETH:
1458 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1461 type = MLX4_NET_TRANS_RULE_ID_ETH;
1462 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
1464 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
1466 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
1467 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
1469 case IB_FLOW_SPEC_IB:
1470 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
1473 type = MLX4_NET_TRANS_RULE_ID_IB;
1474 mlx4_spec->ib.l3_qpn =
1475 cpu_to_be32(qp_num);
1476 mlx4_spec->ib.qpn_mask =
1477 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
1481 case IB_FLOW_SPEC_IPV4:
1482 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1485 type = MLX4_NET_TRANS_RULE_ID_IPV4;
1486 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
1487 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
1488 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
1489 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
1492 case IB_FLOW_SPEC_TCP:
1493 case IB_FLOW_SPEC_UDP:
1494 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
1497 type = ib_spec->type == IB_FLOW_SPEC_TCP ?
1498 MLX4_NET_TRANS_RULE_ID_TCP :
1499 MLX4_NET_TRANS_RULE_ID_UDP;
1500 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
1501 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
1502 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
1503 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
1509 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
1510 mlx4_hw_rule_sz(dev, type) < 0)
1512 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
1513 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
1514 return mlx4_hw_rule_sz(dev, type);
1517 struct default_rules {
1518 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1519 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1520 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
1523 static const struct default_rules default_table[] = {
1525 .mandatory_fields = {IB_FLOW_SPEC_IPV4},
1526 .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
1527 .rules_create_list = {IB_FLOW_SPEC_IB},
1528 .link_layer = IB_LINK_LAYER_INFINIBAND
1532 static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
1533 struct ib_flow_attr *flow_attr)
1537 const struct default_rules *pdefault_rules = default_table;
1538 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
1540 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
1541 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
1542 memset(&field_types, 0, sizeof(field_types));
1544 if (link_layer != pdefault_rules->link_layer)
1547 ib_flow = flow_attr + 1;
1548 /* we assume the specs are sorted */
1549 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
1550 j < flow_attr->num_of_specs; k++) {
1551 union ib_flow_spec *current_flow =
1552 (union ib_flow_spec *)ib_flow;
1554 /* same layer but different type */
1555 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
1556 (pdefault_rules->mandatory_fields[k] &
1557 IB_FLOW_SPEC_LAYER_MASK)) &&
1558 (current_flow->type !=
1559 pdefault_rules->mandatory_fields[k]))
1562 /* same layer, try match next one */
1563 if (current_flow->type ==
1564 pdefault_rules->mandatory_fields[k]) {
1567 ((union ib_flow_spec *)ib_flow)->size;
1571 ib_flow = flow_attr + 1;
1572 for (j = 0; j < flow_attr->num_of_specs;
1573 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
1574 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
1575 /* same layer and same type */
1576 if (((union ib_flow_spec *)ib_flow)->type ==
1577 pdefault_rules->mandatory_not_fields[k])
1586 static int __mlx4_ib_create_default_rules(
1587 struct mlx4_ib_dev *mdev,
1589 const struct default_rules *pdefault_rules,
1590 struct _rule_hw *mlx4_spec) {
1594 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
1596 union ib_flow_spec ib_spec;
1597 switch (pdefault_rules->rules_create_list[i]) {
1601 case IB_FLOW_SPEC_IB:
1602 ib_spec.type = IB_FLOW_SPEC_IB;
1603 ib_spec.size = sizeof(struct ib_flow_spec_ib);
1610 /* We must put empty rule, qpn is being ignored */
1611 ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
1614 pr_info("invalid parsing\n");
1618 mlx4_spec = (void *)mlx4_spec + ret;
1624 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1626 enum mlx4_net_trans_promisc_mode flow_type,
1632 struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1633 struct mlx4_cmd_mailbox *mailbox;
1634 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
1637 static const u16 __mlx4_domain[] = {
1638 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
1639 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
1640 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
1641 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
1644 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1645 pr_err("Invalid priority value %d\n", flow_attr->priority);
1649 if (domain >= IB_FLOW_DOMAIN_NUM) {
1650 pr_err("Invalid domain value %d\n", domain);
1654 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1657 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1658 if (IS_ERR(mailbox))
1659 return PTR_ERR(mailbox);
1660 ctrl = mailbox->buf;
1662 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
1663 flow_attr->priority);
1664 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1665 ctrl->port = flow_attr->port;
1666 ctrl->qpn = cpu_to_be32(qp->qp_num);
1668 ib_flow = flow_attr + 1;
1669 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
1670 /* Add default flows */
1671 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1672 if (default_flow >= 0) {
1673 ret = __mlx4_ib_create_default_rules(
1674 mdev, qp, default_table + default_flow,
1675 mailbox->buf + size);
1677 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1682 for (i = 0; i < flow_attr->num_of_specs; i++) {
1683 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1684 mailbox->buf + size);
1686 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1689 ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1693 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR &&
1694 flow_attr->num_of_specs == 1) {
1695 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1);
1696 enum ib_flow_spec_type header_spec =
1697 ((union ib_flow_spec *)(flow_attr + 1))->type;
1699 if (header_spec == IB_FLOW_SPEC_ETH)
1700 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
1703 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1704 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
1707 pr_err("mcg table is full. Fail to register network rule.\n");
1708 else if (ret == -ENXIO)
1709 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1711 pr_err("Invalid argument. Fail to register network rule.\n");
1713 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1717 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1720 err = mlx4_cmd(dev, reg_id, 0, 0,
1721 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1724 pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1729 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1733 union ib_flow_spec *ib_spec;
1734 struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1737 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
1738 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
1739 return 0; /* do nothing */
1741 ib_flow = flow_attr + 1;
1742 ib_spec = (union ib_flow_spec *)ib_flow;
1744 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1745 return 0; /* do nothing */
1747 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1748 flow_attr->port, qp->qp_num,
1749 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1754 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
1755 struct ib_flow_attr *flow_attr,
1756 enum mlx4_net_trans_promisc_mode *type)
1760 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
1761 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
1762 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
1766 if (flow_attr->num_of_specs == 0) {
1767 type[0] = MLX4_FS_MC_SNIFFER;
1768 type[1] = MLX4_FS_UC_SNIFFER;
1770 union ib_flow_spec *ib_spec;
1772 ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1773 if (ib_spec->type != IB_FLOW_SPEC_ETH)
1776 /* if all is zero than MC and UC */
1777 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
1778 type[0] = MLX4_FS_MC_SNIFFER;
1779 type[1] = MLX4_FS_UC_SNIFFER;
1781 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
1782 ib_spec->eth.mask.dst_mac[1],
1783 ib_spec->eth.mask.dst_mac[2],
1784 ib_spec->eth.mask.dst_mac[3],
1785 ib_spec->eth.mask.dst_mac[4],
1786 ib_spec->eth.mask.dst_mac[5]};
1788 /* Above xor was only on MC bit, non empty mask is valid
1789 * only if this bit is set and rest are zero.
1791 if (!is_zero_ether_addr(&mac[0]))
1794 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
1795 type[0] = MLX4_FS_MC_SNIFFER;
1797 type[0] = MLX4_FS_UC_SNIFFER;
1804 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1805 struct ib_flow_attr *flow_attr,
1806 int domain, struct ib_udata *udata)
1808 int err = 0, i = 0, j = 0;
1809 struct mlx4_ib_flow *mflow;
1810 enum mlx4_net_trans_promisc_mode type[2];
1811 struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1812 int is_bonded = mlx4_is_bonded(dev);
1814 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
1815 return ERR_PTR(-EINVAL);
1817 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)
1818 return ERR_PTR(-EOPNOTSUPP);
1820 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
1821 (flow_attr->type != IB_FLOW_ATTR_NORMAL))
1822 return ERR_PTR(-EOPNOTSUPP);
1825 udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen))
1826 return ERR_PTR(-EOPNOTSUPP);
1828 memset(type, 0, sizeof(type));
1830 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1836 switch (flow_attr->type) {
1837 case IB_FLOW_ATTR_NORMAL:
1838 /* If dont trap flag (continue match) is set, under specific
1839 * condition traffic be replicated to given qp,
1840 * without stealing it
1842 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
1843 err = mlx4_ib_add_dont_trap_rule(dev,
1849 type[0] = MLX4_FS_REGULAR;
1853 case IB_FLOW_ATTR_ALL_DEFAULT:
1854 type[0] = MLX4_FS_ALL_DEFAULT;
1857 case IB_FLOW_ATTR_MC_DEFAULT:
1858 type[0] = MLX4_FS_MC_DEFAULT;
1861 case IB_FLOW_ATTR_SNIFFER:
1862 type[0] = MLX4_FS_MIRROR_RX_PORT;
1863 type[1] = MLX4_FS_MIRROR_SX_PORT;
1871 while (i < ARRAY_SIZE(type) && type[i]) {
1872 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
1873 &mflow->reg_id[i].id);
1875 goto err_create_flow;
1877 /* Application always sees one port so the mirror rule
1878 * must be on port #2
1880 flow_attr->port = 2;
1881 err = __mlx4_ib_create_flow(qp, flow_attr,
1883 &mflow->reg_id[j].mirror);
1884 flow_attr->port = 1;
1886 goto err_create_flow;
1893 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1894 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1895 &mflow->reg_id[i].id);
1897 goto err_create_flow;
1900 flow_attr->port = 2;
1901 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1902 &mflow->reg_id[j].mirror);
1903 flow_attr->port = 1;
1905 goto err_create_flow;
1908 /* function to create mirror rule */
1912 return &mflow->ibflow;
1916 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1917 mflow->reg_id[i].id);
1922 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1923 mflow->reg_id[j].mirror);
1928 return ERR_PTR(err);
1931 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1935 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1936 struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1938 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
1939 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
1942 if (mflow->reg_id[i].mirror) {
1943 err = __mlx4_ib_destroy_flow(mdev->dev,
1944 mflow->reg_id[i].mirror);
1955 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1958 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1959 struct mlx4_dev *dev = mdev->dev;
1960 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1961 struct mlx4_ib_steering *ib_steering = NULL;
1962 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
1963 struct mlx4_flow_reg_id reg_id;
1965 if (mdev->dev->caps.steering_mode ==
1966 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1967 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
1972 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
1974 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1977 pr_err("multicast attach op failed, err %d\n", err);
1982 if (mlx4_is_bonded(dev)) {
1983 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
1984 (mqp->port == 1) ? 2 : 1,
1986 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1987 prot, ®_id.mirror);
1992 err = add_gid_entry(ibqp, gid);
1997 memcpy(ib_steering->gid.raw, gid->raw, 16);
1998 ib_steering->reg_id = reg_id;
1999 mutex_lock(&mqp->mutex);
2000 list_add(&ib_steering->list, &mqp->steering_rules);
2001 mutex_unlock(&mqp->mutex);
2006 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2009 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2010 prot, reg_id.mirror);
2017 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
2019 struct mlx4_ib_gid_entry *ge;
2020 struct mlx4_ib_gid_entry *tmp;
2021 struct mlx4_ib_gid_entry *ret = NULL;
2023 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
2024 if (!memcmp(raw, ge->gid.raw, 16)) {
2033 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2036 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2037 struct mlx4_dev *dev = mdev->dev;
2038 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2039 struct net_device *ndev;
2040 struct mlx4_ib_gid_entry *ge;
2041 struct mlx4_flow_reg_id reg_id = {0, 0};
2042 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
2044 if (mdev->dev->caps.steering_mode ==
2045 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2046 struct mlx4_ib_steering *ib_steering;
2048 mutex_lock(&mqp->mutex);
2049 list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
2050 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
2051 list_del(&ib_steering->list);
2055 mutex_unlock(&mqp->mutex);
2056 if (&ib_steering->list == &mqp->steering_rules) {
2057 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
2060 reg_id = ib_steering->reg_id;
2064 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2069 if (mlx4_is_bonded(dev)) {
2070 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2071 prot, reg_id.mirror);
2076 mutex_lock(&mqp->mutex);
2077 ge = find_gid_entry(mqp, gid->raw);
2079 spin_lock_bh(&mdev->iboe.lock);
2080 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
2083 spin_unlock_bh(&mdev->iboe.lock);
2086 list_del(&ge->list);
2089 pr_warn("could not find mgid entry\n");
2091 mutex_unlock(&mqp->mutex);
2096 static int init_node_data(struct mlx4_ib_dev *dev)
2098 struct ib_smp *in_mad = NULL;
2099 struct ib_smp *out_mad = NULL;
2100 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
2103 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
2104 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
2105 if (!in_mad || !out_mad)
2108 init_query_mad(in_mad);
2109 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
2110 if (mlx4_is_master(dev->dev))
2111 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
2113 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2117 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
2119 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
2121 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2125 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
2126 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
2134 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2137 struct mlx4_ib_dev *dev =
2138 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2139 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
2142 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2145 struct mlx4_ib_dev *dev =
2146 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2147 return sprintf(buf, "%x\n", dev->dev->rev_id);
2150 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2153 struct mlx4_ib_dev *dev =
2154 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2155 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
2156 dev->dev->board_id);
2159 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2160 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2161 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2163 static struct device_attribute *mlx4_class_attributes[] = {
2169 struct diag_counter {
2174 #define DIAG_COUNTER(_name, _offset) \
2175 { .name = #_name, .offset = _offset }
2177 static const struct diag_counter diag_basic[] = {
2178 DIAG_COUNTER(rq_num_lle, 0x00),
2179 DIAG_COUNTER(sq_num_lle, 0x04),
2180 DIAG_COUNTER(rq_num_lqpoe, 0x08),
2181 DIAG_COUNTER(sq_num_lqpoe, 0x0C),
2182 DIAG_COUNTER(rq_num_lpe, 0x18),
2183 DIAG_COUNTER(sq_num_lpe, 0x1C),
2184 DIAG_COUNTER(rq_num_wrfe, 0x20),
2185 DIAG_COUNTER(sq_num_wrfe, 0x24),
2186 DIAG_COUNTER(sq_num_mwbe, 0x2C),
2187 DIAG_COUNTER(sq_num_bre, 0x34),
2188 DIAG_COUNTER(sq_num_rire, 0x44),
2189 DIAG_COUNTER(rq_num_rire, 0x48),
2190 DIAG_COUNTER(sq_num_rae, 0x4C),
2191 DIAG_COUNTER(rq_num_rae, 0x50),
2192 DIAG_COUNTER(sq_num_roe, 0x54),
2193 DIAG_COUNTER(sq_num_tree, 0x5C),
2194 DIAG_COUNTER(sq_num_rree, 0x64),
2195 DIAG_COUNTER(rq_num_rnr, 0x68),
2196 DIAG_COUNTER(sq_num_rnr, 0x6C),
2197 DIAG_COUNTER(rq_num_oos, 0x100),
2198 DIAG_COUNTER(sq_num_oos, 0x104),
2201 static const struct diag_counter diag_ext[] = {
2202 DIAG_COUNTER(rq_num_dup, 0x130),
2203 DIAG_COUNTER(sq_num_to, 0x134),
2206 static const struct diag_counter diag_device_only[] = {
2207 DIAG_COUNTER(num_cqovf, 0x1A0),
2208 DIAG_COUNTER(rq_num_udsdprd, 0x118),
2211 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
2214 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2215 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2217 if (!diag[!!port_num].name)
2220 return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
2221 diag[!!port_num].num_counters,
2222 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2225 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
2226 struct rdma_hw_stats *stats,
2229 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2230 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2231 u32 hw_value[ARRAY_SIZE(diag_device_only) +
2232 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
2236 ret = mlx4_query_diag_counters(dev->dev,
2237 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
2238 diag[!!port].offset, hw_value,
2239 diag[!!port].num_counters, port);
2244 for (i = 0; i < diag[!!port].num_counters; i++)
2245 stats->value[i] = hw_value[i];
2247 return diag[!!port].num_counters;
2250 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
2258 num_counters = ARRAY_SIZE(diag_basic);
2260 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
2261 num_counters += ARRAY_SIZE(diag_ext);
2264 num_counters += ARRAY_SIZE(diag_device_only);
2266 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
2270 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
2274 *num = num_counters;
2283 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
2291 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
2292 name[i] = diag_basic[i].name;
2293 offset[i] = diag_basic[i].offset;
2296 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
2297 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
2298 name[j] = diag_ext[i].name;
2299 offset[j] = diag_ext[i].offset;
2304 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
2305 name[j] = diag_device_only[i].name;
2306 offset[j] = diag_device_only[i].offset;
2311 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
2313 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
2316 bool per_port = !!(ibdev->dev->caps.flags2 &
2317 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
2319 if (mlx4_is_slave(ibdev->dev))
2322 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2323 /* i == 1 means we are building port counters */
2327 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
2329 &diag[i].num_counters, i);
2333 mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
2337 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats;
2338 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats;
2344 kfree(diag[i - 1].name);
2345 kfree(diag[i - 1].offset);
2351 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
2355 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2356 kfree(ibdev->diag_counters[i].offset);
2357 kfree(ibdev->diag_counters[i].name);
2361 #define MLX4_IB_INVALID_MAC ((u64)-1)
2362 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
2363 struct net_device *dev,
2367 u64 release_mac = MLX4_IB_INVALID_MAC;
2368 struct mlx4_ib_qp *qp;
2370 read_lock(&dev_base_lock);
2371 new_smac = mlx4_mac_to_u64(dev->dev_addr);
2372 read_unlock(&dev_base_lock);
2374 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
2376 /* no need for update QP1 and mac registration in non-SRIOV */
2377 if (!mlx4_is_mfunc(ibdev->dev))
2380 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
2381 qp = ibdev->qp1_proxy[port - 1];
2385 struct mlx4_update_qp_params update_params;
2387 mutex_lock(&qp->mutex);
2388 old_smac = qp->pri.smac;
2389 if (new_smac == old_smac)
2392 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
2394 if (new_smac_index < 0)
2397 update_params.smac_index = new_smac_index;
2398 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
2400 release_mac = new_smac;
2403 /* if old port was zero, no mac was yet registered for this QP */
2404 if (qp->pri.smac_port)
2405 release_mac = old_smac;
2406 qp->pri.smac = new_smac;
2407 qp->pri.smac_port = port;
2408 qp->pri.smac_index = new_smac_index;
2412 if (release_mac != MLX4_IB_INVALID_MAC)
2413 mlx4_unregister_mac(ibdev->dev, port, release_mac);
2415 mutex_unlock(&qp->mutex);
2416 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
2419 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
2420 struct net_device *dev,
2421 unsigned long event)
2424 struct mlx4_ib_iboe *iboe;
2425 int update_qps_port = -1;
2430 iboe = &ibdev->iboe;
2432 spin_lock_bh(&iboe->lock);
2433 mlx4_foreach_ib_transport_port(port, ibdev->dev) {
2435 iboe->netdevs[port - 1] =
2436 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
2438 if (dev == iboe->netdevs[port - 1] &&
2439 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
2440 event == NETDEV_UP || event == NETDEV_CHANGE))
2441 update_qps_port = port;
2444 spin_unlock_bh(&iboe->lock);
2446 if (update_qps_port > 0)
2447 mlx4_ib_update_qps(ibdev, dev, update_qps_port);
2450 static int mlx4_ib_netdev_event(struct notifier_block *this,
2451 unsigned long event, void *ptr)
2453 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2454 struct mlx4_ib_dev *ibdev;
2456 if (!net_eq(dev_net(dev), &init_net))
2459 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
2460 mlx4_ib_scan_netdevs(ibdev, dev, event);
2465 static void init_pkeys(struct mlx4_ib_dev *ibdev)
2471 if (mlx4_is_master(ibdev->dev)) {
2472 for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
2474 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2476 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2478 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
2479 /* master has the identity virt2phys pkey mapping */
2480 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
2481 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
2482 mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
2483 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
2487 /* initialize pkey cache */
2488 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2490 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2492 ibdev->pkeys.phys_pkey_cache[port-1][i] =
2498 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2500 int i, j, eq = 0, total_eqs = 0;
2502 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
2503 sizeof(ibdev->eq_table[0]), GFP_KERNEL);
2504 if (!ibdev->eq_table)
2507 for (i = 1; i <= dev->caps.num_ports; i++) {
2508 for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
2510 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
2512 ibdev->eq_table[eq] = total_eqs;
2513 if (!mlx4_assign_eq(dev, i,
2514 &ibdev->eq_table[eq]))
2517 ibdev->eq_table[eq] = -1;
2521 for (i = eq; i < dev->caps.num_comp_vectors;
2522 ibdev->eq_table[i++] = -1)
2525 /* Advertise the new number of EQs to clients */
2526 ibdev->ib_dev.num_comp_vectors = eq;
2529 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2532 int total_eqs = ibdev->ib_dev.num_comp_vectors;
2534 /* no eqs were allocated */
2535 if (!ibdev->eq_table)
2538 /* Reset the advertised EQ number */
2539 ibdev->ib_dev.num_comp_vectors = 0;
2541 for (i = 0; i < total_eqs; i++)
2542 mlx4_release_eq(dev, ibdev->eq_table[i]);
2544 kfree(ibdev->eq_table);
2545 ibdev->eq_table = NULL;
2548 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
2549 struct ib_port_immutable *immutable)
2551 struct ib_port_attr attr;
2552 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
2555 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
2556 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
2557 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2559 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
2560 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
2561 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
2562 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
2563 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2564 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET;
2565 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE |
2566 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP))
2567 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2570 err = ib_query_port(ibdev, port_num, &attr);
2574 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2575 immutable->gid_tbl_len = attr.gid_tbl_len;
2580 static void get_fw_ver_str(struct ib_device *device, char *str)
2582 struct mlx4_ib_dev *dev =
2583 container_of(device, struct mlx4_ib_dev, ib_dev);
2584 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d",
2585 (int) (dev->dev->caps.fw_ver >> 32),
2586 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
2587 (int) dev->dev->caps.fw_ver & 0xffff);
2590 static void *mlx4_ib_add(struct mlx4_dev *dev)
2592 struct mlx4_ib_dev *ibdev;
2596 struct mlx4_ib_iboe *iboe;
2597 int ib_num_ports = 0;
2598 int num_req_counters;
2601 struct counter_index *new_counter_index = NULL;
2603 pr_info_once("%s", mlx4_ib_version);
2606 mlx4_foreach_ib_transport_port(i, dev)
2609 /* No point in registering a device with no ports... */
2613 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
2615 dev_err(&dev->persist->pdev->dev,
2616 "Device struct alloc failed\n");
2620 iboe = &ibdev->iboe;
2622 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2625 if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2628 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2630 if (!ibdev->uar_map)
2632 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
2635 ibdev->bond_next_port = 0;
2637 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
2638 ibdev->ib_dev.owner = THIS_MODULE;
2639 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
2640 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
2641 ibdev->num_ports = num_ports;
2642 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
2643 1 : ibdev->num_ports;
2644 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
2645 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev;
2646 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
2647 ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
2648 ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
2650 if (dev->caps.userspace_caps)
2651 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
2653 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2655 ibdev->ib_dev.uverbs_cmd_mask =
2656 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2657 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2658 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2659 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2660 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2661 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2662 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2663 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2664 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2665 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2666 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2667 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2668 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2669 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2670 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2671 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2672 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2673 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2674 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2675 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2676 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2677 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2678 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2679 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2681 ibdev->ib_dev.query_device = mlx4_ib_query_device;
2682 ibdev->ib_dev.query_port = mlx4_ib_query_port;
2683 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
2684 ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
2685 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
2686 ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
2687 ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
2688 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
2689 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
2690 ibdev->ib_dev.mmap = mlx4_ib_mmap;
2691 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
2692 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
2693 ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
2694 ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
2695 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
2696 ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
2697 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
2698 ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
2699 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
2700 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
2701 ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
2702 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
2703 ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
2704 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
2705 ibdev->ib_dev.drain_sq = mlx4_ib_drain_sq;
2706 ibdev->ib_dev.drain_rq = mlx4_ib_drain_rq;
2707 ibdev->ib_dev.post_send = mlx4_ib_post_send;
2708 ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
2709 ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
2710 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
2711 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
2712 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
2713 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
2714 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
2715 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
2716 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
2717 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
2718 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
2719 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
2720 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
2721 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
2722 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
2723 ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
2724 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
2725 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str;
2726 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
2728 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2729 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
2731 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
2732 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) ==
2733 IB_LINK_LAYER_ETHERNET) ||
2734 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) ==
2735 IB_LINK_LAYER_ETHERNET))) {
2736 ibdev->ib_dev.create_wq = mlx4_ib_create_wq;
2737 ibdev->ib_dev.modify_wq = mlx4_ib_modify_wq;
2738 ibdev->ib_dev.destroy_wq = mlx4_ib_destroy_wq;
2739 ibdev->ib_dev.create_rwq_ind_table =
2740 mlx4_ib_create_rwq_ind_table;
2741 ibdev->ib_dev.destroy_rwq_ind_table =
2742 mlx4_ib_destroy_rwq_ind_table;
2743 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2744 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
2745 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
2746 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
2747 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
2748 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
2751 if (!mlx4_is_slave(ibdev->dev)) {
2752 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
2753 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
2754 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
2755 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
2758 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2759 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2760 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
2761 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
2763 ibdev->ib_dev.uverbs_cmd_mask |=
2764 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2765 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2768 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2769 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
2770 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
2771 ibdev->ib_dev.uverbs_cmd_mask |=
2772 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2773 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2776 if (check_flow_steering_support(dev)) {
2777 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
2778 ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
2779 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
2781 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2782 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2783 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2786 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2787 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2788 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2789 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2791 mlx4_ib_alloc_eqs(dev, ibdev);
2793 spin_lock_init(&iboe->lock);
2795 if (init_node_data(ibdev))
2797 mlx4_init_sl2vl_tbl(ibdev);
2799 for (i = 0; i < ibdev->num_ports; ++i) {
2800 mutex_init(&ibdev->counters_table[i].mutex);
2801 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
2804 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
2805 for (i = 0; i < num_req_counters; ++i) {
2806 mutex_init(&ibdev->qp1_proxy_lock[i]);
2808 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2809 IB_LINK_LAYER_ETHERNET) {
2810 err = mlx4_counter_alloc(ibdev->dev, &counter_index,
2811 MLX4_RES_USAGE_DRIVER);
2812 /* if failed to allocate a new counter, use default */
2815 mlx4_get_default_counter_index(dev,
2819 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
2820 counter_index = mlx4_get_default_counter_index(dev,
2823 new_counter_index = kmalloc(sizeof(*new_counter_index),
2825 if (!new_counter_index) {
2827 mlx4_counter_free(ibdev->dev, counter_index);
2830 new_counter_index->index = counter_index;
2831 new_counter_index->allocated = allocated;
2832 list_add_tail(&new_counter_index->list,
2833 &ibdev->counters_table[i].counters_list);
2834 ibdev->counters_table[i].default_counter = counter_index;
2835 pr_info("counter index %d for port %d allocated %d\n",
2836 counter_index, i + 1, allocated);
2838 if (mlx4_is_bonded(dev))
2839 for (i = 1; i < ibdev->num_ports ; ++i) {
2841 kmalloc(sizeof(struct counter_index),
2843 if (!new_counter_index)
2845 new_counter_index->index = counter_index;
2846 new_counter_index->allocated = 0;
2847 list_add_tail(&new_counter_index->list,
2848 &ibdev->counters_table[i].counters_list);
2849 ibdev->counters_table[i].default_counter =
2853 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2856 spin_lock_init(&ibdev->sm_lock);
2857 mutex_init(&ibdev->cap_mask_mutex);
2858 INIT_LIST_HEAD(&ibdev->qp_list);
2859 spin_lock_init(&ibdev->reset_flow_resource_lock);
2861 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2863 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2864 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2865 MLX4_IB_UC_STEER_QPN_ALIGN,
2866 &ibdev->steer_qpn_base, 0,
2867 MLX4_RES_USAGE_DRIVER);
2871 ibdev->ib_uc_qpns_bitmap =
2872 kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count),
2875 if (!ibdev->ib_uc_qpns_bitmap)
2876 goto err_steer_qp_release;
2878 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
2879 bitmap_zero(ibdev->ib_uc_qpns_bitmap,
2880 ibdev->steer_qpn_count);
2881 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2882 dev, ibdev->steer_qpn_base,
2883 ibdev->steer_qpn_base +
2884 ibdev->steer_qpn_count - 1);
2886 goto err_steer_free_bitmap;
2888 bitmap_fill(ibdev->ib_uc_qpns_bitmap,
2889 ibdev->steer_qpn_count);
2893 for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
2894 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
2896 if (mlx4_ib_alloc_diag_counters(ibdev))
2897 goto err_steer_free_bitmap;
2899 ibdev->ib_dev.driver_id = RDMA_DRIVER_MLX4;
2900 if (ib_register_device(&ibdev->ib_dev, NULL))
2901 goto err_diag_counters;
2903 if (mlx4_ib_mad_init(ibdev))
2906 if (mlx4_ib_init_sriov(ibdev))
2909 if (!iboe->nb.notifier_call) {
2910 iboe->nb.notifier_call = mlx4_ib_netdev_event;
2911 err = register_netdevice_notifier(&iboe->nb);
2913 iboe->nb.notifier_call = NULL;
2917 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2918 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
2923 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
2924 if (device_create_file(&ibdev->ib_dev.dev,
2925 mlx4_class_attributes[j]))
2929 ibdev->ib_active = true;
2930 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2931 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
2934 if (mlx4_is_mfunc(ibdev->dev))
2937 /* create paravirt contexts for any VFs which are active */
2938 if (mlx4_is_master(ibdev->dev)) {
2939 for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2940 if (j == mlx4_master_func_num(ibdev->dev))
2942 if (mlx4_is_slave_active(ibdev->dev, j))
2943 do_slave_init(ibdev, j, 1);
2949 if (ibdev->iboe.nb.notifier_call) {
2950 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2951 pr_warn("failure unregistering notifier\n");
2952 ibdev->iboe.nb.notifier_call = NULL;
2954 flush_workqueue(wq);
2956 mlx4_ib_close_sriov(ibdev);
2959 mlx4_ib_mad_cleanup(ibdev);
2962 ib_unregister_device(&ibdev->ib_dev);
2965 mlx4_ib_diag_cleanup(ibdev);
2967 err_steer_free_bitmap:
2968 kfree(ibdev->ib_uc_qpns_bitmap);
2970 err_steer_qp_release:
2971 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2972 ibdev->steer_qpn_count);
2974 for (i = 0; i < ibdev->num_ports; ++i)
2975 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
2978 mlx4_ib_free_eqs(dev, ibdev);
2979 iounmap(ibdev->uar_map);
2982 mlx4_uar_free(dev, &ibdev->priv_uar);
2985 mlx4_pd_free(dev, ibdev->priv_pdn);
2988 ib_dealloc_device(&ibdev->ib_dev);
2993 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
2997 WARN_ON(!dev->ib_uc_qpns_bitmap);
2999 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
3000 dev->steer_qpn_count,
3001 get_count_order(count));
3005 *qpn = dev->steer_qpn_base + offset;
3009 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
3012 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
3015 if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n",
3016 qpn, dev->steer_qpn_base))
3017 /* not supposed to be here */
3020 bitmap_release_region(dev->ib_uc_qpns_bitmap,
3021 qpn - dev->steer_qpn_base,
3022 get_count_order(count));
3025 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
3030 struct ib_flow_attr *flow = NULL;
3031 struct ib_flow_spec_ib *ib_spec;
3034 flow_size = sizeof(struct ib_flow_attr) +
3035 sizeof(struct ib_flow_spec_ib);
3036 flow = kzalloc(flow_size, GFP_KERNEL);
3039 flow->port = mqp->port;
3040 flow->num_of_specs = 1;
3041 flow->size = flow_size;
3042 ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
3043 ib_spec->type = IB_FLOW_SPEC_IB;
3044 ib_spec->size = sizeof(struct ib_flow_spec_ib);
3045 /* Add an empty rule for IB L2 */
3046 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
3048 err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
3053 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
3059 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
3061 struct mlx4_ib_dev *ibdev = ibdev_ptr;
3065 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
3066 devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
3067 ibdev->ib_active = false;
3068 flush_workqueue(wq);
3070 mlx4_ib_close_sriov(ibdev);
3071 mlx4_ib_mad_cleanup(ibdev);
3072 ib_unregister_device(&ibdev->ib_dev);
3073 mlx4_ib_diag_cleanup(ibdev);
3074 if (ibdev->iboe.nb.notifier_call) {
3075 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
3076 pr_warn("failure unregistering notifier\n");
3077 ibdev->iboe.nb.notifier_call = NULL;
3080 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
3081 ibdev->steer_qpn_count);
3082 kfree(ibdev->ib_uc_qpns_bitmap);
3084 iounmap(ibdev->uar_map);
3085 for (p = 0; p < ibdev->num_ports; ++p)
3086 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
3088 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
3089 mlx4_CLOSE_PORT(dev, p);
3091 mlx4_ib_free_eqs(dev, ibdev);
3093 mlx4_uar_free(dev, &ibdev->priv_uar);
3094 mlx4_pd_free(dev, ibdev->priv_pdn);
3095 ib_dealloc_device(&ibdev->ib_dev);
3098 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
3100 struct mlx4_ib_demux_work **dm = NULL;
3101 struct mlx4_dev *dev = ibdev->dev;
3103 unsigned long flags;
3104 struct mlx4_active_ports actv_ports;
3106 unsigned int first_port;
3108 if (!mlx4_is_master(dev))
3111 actv_ports = mlx4_get_active_ports(dev, slave);
3112 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
3113 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
3115 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
3119 for (i = 0; i < ports; i++) {
3120 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
3126 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
3127 dm[i]->port = first_port + i + 1;
3128 dm[i]->slave = slave;
3129 dm[i]->do_init = do_init;
3132 /* initialize or tear down tunnel QPs for the slave */
3133 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
3134 if (!ibdev->sriov.is_going_down) {
3135 for (i = 0; i < ports; i++)
3136 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
3137 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3139 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3140 for (i = 0; i < ports; i++)
3148 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
3150 struct mlx4_ib_qp *mqp;
3151 unsigned long flags_qp;
3152 unsigned long flags_cq;
3153 struct mlx4_ib_cq *send_mcq, *recv_mcq;
3154 struct list_head cq_notify_list;
3155 struct mlx4_cq *mcq;
3156 unsigned long flags;
3158 pr_warn("mlx4_ib_handle_catas_error was started\n");
3159 INIT_LIST_HEAD(&cq_notify_list);
3161 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3162 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3164 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3165 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3166 if (mqp->sq.tail != mqp->sq.head) {
3167 send_mcq = to_mcq(mqp->ibqp.send_cq);
3168 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3169 if (send_mcq->mcq.comp &&
3170 mqp->ibqp.send_cq->comp_handler) {
3171 if (!send_mcq->mcq.reset_notify_added) {
3172 send_mcq->mcq.reset_notify_added = 1;
3173 list_add_tail(&send_mcq->mcq.reset_notify,
3177 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3179 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3180 /* Now, handle the QP's receive queue */
3181 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3182 /* no handling is needed for SRQ */
3183 if (!mqp->ibqp.srq) {
3184 if (mqp->rq.tail != mqp->rq.head) {
3185 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3186 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3187 if (recv_mcq->mcq.comp &&
3188 mqp->ibqp.recv_cq->comp_handler) {
3189 if (!recv_mcq->mcq.reset_notify_added) {
3190 recv_mcq->mcq.reset_notify_added = 1;
3191 list_add_tail(&recv_mcq->mcq.reset_notify,
3195 spin_unlock_irqrestore(&recv_mcq->lock,
3199 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3202 list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
3205 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3206 pr_warn("mlx4_ib_handle_catas_error ended\n");
3209 static void handle_bonded_port_state_event(struct work_struct *work)
3211 struct ib_event_work *ew =
3212 container_of(work, struct ib_event_work, work);
3213 struct mlx4_ib_dev *ibdev = ew->ib_dev;
3214 enum ib_port_state bonded_port_state = IB_PORT_NOP;
3216 struct ib_event ibev;
3219 spin_lock_bh(&ibdev->iboe.lock);
3220 for (i = 0; i < MLX4_MAX_PORTS; ++i) {
3221 struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
3222 enum ib_port_state curr_port_state;
3228 (netif_running(curr_netdev) &&
3229 netif_carrier_ok(curr_netdev)) ?
3230 IB_PORT_ACTIVE : IB_PORT_DOWN;
3232 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
3233 curr_port_state : IB_PORT_ACTIVE;
3235 spin_unlock_bh(&ibdev->iboe.lock);
3237 ibev.device = &ibdev->ib_dev;
3238 ibev.element.port_num = 1;
3239 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
3240 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3242 ib_dispatch_event(&ibev);
3245 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
3250 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
3252 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
3256 atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
3259 static void ib_sl2vl_update_work(struct work_struct *work)
3261 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
3262 struct mlx4_ib_dev *mdev = ew->ib_dev;
3263 int port = ew->port;
3265 mlx4_ib_sl2vl_update(mdev, port);
3270 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
3273 struct ib_event_work *ew;
3275 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3277 INIT_WORK(&ew->work, ib_sl2vl_update_work);
3280 queue_work(wq, &ew->work);
3284 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
3285 enum mlx4_dev_event event, unsigned long param)
3287 struct ib_event ibev;
3288 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
3289 struct mlx4_eqe *eqe = NULL;
3290 struct ib_event_work *ew;
3293 if (mlx4_is_bonded(dev) &&
3294 ((event == MLX4_DEV_EVENT_PORT_UP) ||
3295 (event == MLX4_DEV_EVENT_PORT_DOWN))) {
3296 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3299 INIT_WORK(&ew->work, handle_bonded_port_state_event);
3301 queue_work(wq, &ew->work);
3305 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
3306 eqe = (struct mlx4_eqe *)param;
3311 case MLX4_DEV_EVENT_PORT_UP:
3312 if (p > ibdev->num_ports)
3314 if (!mlx4_is_slave(dev) &&
3315 rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
3316 IB_LINK_LAYER_INFINIBAND) {
3317 if (mlx4_is_master(dev))
3318 mlx4_ib_invalidate_all_guid_record(ibdev, p);
3319 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
3320 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
3321 mlx4_sched_ib_sl2vl_update_work(ibdev, p);
3323 ibev.event = IB_EVENT_PORT_ACTIVE;
3326 case MLX4_DEV_EVENT_PORT_DOWN:
3327 if (p > ibdev->num_ports)
3329 ibev.event = IB_EVENT_PORT_ERR;
3332 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3333 ibdev->ib_active = false;
3334 ibev.event = IB_EVENT_DEVICE_FATAL;
3335 mlx4_ib_handle_catas_error(ibdev);
3338 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
3339 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
3343 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
3344 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
3346 /* need to queue only for port owner, which uses GEN_EQE */
3347 if (mlx4_is_master(dev))
3348 queue_work(wq, &ew->work);
3350 handle_port_mgmt_change_event(&ew->work);
3353 case MLX4_DEV_EVENT_SLAVE_INIT:
3354 /* here, p is the slave id */
3355 do_slave_init(ibdev, p, 1);
3356 if (mlx4_is_master(dev)) {
3359 for (i = 1; i <= ibdev->num_ports; i++) {
3360 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3361 == IB_LINK_LAYER_INFINIBAND)
3362 mlx4_ib_slave_alias_guid_event(ibdev,
3369 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
3370 if (mlx4_is_master(dev)) {
3373 for (i = 1; i <= ibdev->num_ports; i++) {
3374 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3375 == IB_LINK_LAYER_INFINIBAND)
3376 mlx4_ib_slave_alias_guid_event(ibdev,
3381 /* here, p is the slave id */
3382 do_slave_init(ibdev, p, 0);
3389 ibev.device = ibdev_ptr;
3390 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
3392 ib_dispatch_event(&ibev);
3395 static struct mlx4_interface mlx4_ib_interface = {
3397 .remove = mlx4_ib_remove,
3398 .event = mlx4_ib_event,
3399 .protocol = MLX4_PROT_IB_IPV6,
3400 .flags = MLX4_INTFF_BONDING
3403 static int __init mlx4_ib_init(void)
3407 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
3411 err = mlx4_ib_mcg_init();
3415 err = mlx4_register_interface(&mlx4_ib_interface);
3422 mlx4_ib_mcg_destroy();
3425 destroy_workqueue(wq);
3429 static void __exit mlx4_ib_cleanup(void)
3431 mlx4_unregister_interface(&mlx4_ib_interface);
3432 mlx4_ib_mcg_destroy();
3433 destroy_workqueue(wq);
3436 module_init(mlx4_ib_init);
3437 module_exit(mlx4_ib_cleanup);