2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38 #include <linux/netdevice.h>
39 #include <linux/inetdevice.h>
40 #include <linux/rtnetlink.h>
41 #include <linux/if_vlan.h>
42 #include <linux/sched/mm.h>
43 #include <linux/sched/task.h>
46 #include <net/addrconf.h>
47 #include <net/devlink.h>
49 #include <rdma/ib_smi.h>
50 #include <rdma/ib_user_verbs.h>
51 #include <rdma/ib_addr.h>
52 #include <rdma/ib_cache.h>
54 #include <net/bonding.h>
56 #include <linux/mlx4/driver.h>
57 #include <linux/mlx4/cmd.h>
58 #include <linux/mlx4/qp.h>
61 #include <rdma/mlx4-abi.h>
63 #define DRV_NAME MLX4_IB_DRV_NAME
64 #define DRV_VERSION "4.0-0"
66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
68 #define MLX4_IB_CARD_REV_A0 0xA0
70 MODULE_AUTHOR("Roland Dreier");
71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
72 MODULE_LICENSE("Dual BSD/GPL");
74 int mlx4_ib_sm_guid_assign = 0;
75 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
76 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
78 static const char mlx4_ib_version[] =
79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
82 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
83 static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device,
86 static struct workqueue_struct *wq;
88 static void init_query_mad(struct ib_smp *mad)
90 mad->base_version = 1;
91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
92 mad->class_version = 1;
93 mad->method = IB_MGMT_METHOD_GET;
96 static int check_flow_steering_support(struct mlx4_dev *dev)
98 int eth_num_ports = 0;
101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
109 dmfs &= (!ib_num_ports ||
110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
113 if (ib_num_ports && mlx4_is_mfunc(dev)) {
114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
121 static int num_ib_ports(struct mlx4_dev *dev)
126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
134 struct mlx4_ib_dev *ibdev = to_mdev(device);
135 struct net_device *dev;
138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
141 if (mlx4_is_bonded(ibdev->dev)) {
142 struct net_device *upper = NULL;
144 upper = netdev_master_upper_dev_get_rcu(dev);
146 struct net_device *active;
148 active = bond_option_active_slave_get_rcu(netdev_priv(upper));
161 static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
162 struct mlx4_ib_dev *ibdev,
165 struct mlx4_cmd_mailbox *mailbox;
167 struct mlx4_dev *dev = ibdev->dev;
169 union ib_gid *gid_tbl;
171 mailbox = mlx4_alloc_cmd_mailbox(dev);
175 gid_tbl = mailbox->buf;
177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
180 err = mlx4_cmd(dev, mailbox->dma,
181 MLX4_SET_PORT_GID_TABLE << 8 | port_num,
182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
184 if (mlx4_is_bonded(dev))
185 err += mlx4_cmd(dev, mailbox->dma,
186 MLX4_SET_PORT_GID_TABLE << 8 | 2,
187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
190 mlx4_free_cmd_mailbox(dev, mailbox);
194 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
195 struct mlx4_ib_dev *ibdev,
198 struct mlx4_cmd_mailbox *mailbox;
200 struct mlx4_dev *dev = ibdev->dev;
211 mailbox = mlx4_alloc_cmd_mailbox(dev);
215 gid_tbl = mailbox->buf;
216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
219 gid_tbl[i].version = 2;
220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
225 err = mlx4_cmd(dev, mailbox->dma,
226 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
227 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
229 if (mlx4_is_bonded(dev))
230 err += mlx4_cmd(dev, mailbox->dma,
231 MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
232 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
235 mlx4_free_cmd_mailbox(dev, mailbox);
239 static int mlx4_ib_update_gids(struct gid_entry *gids,
240 struct mlx4_ib_dev *ibdev,
243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
244 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
246 return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
249 static int mlx4_ib_add_gid(struct ib_device *device,
252 const union ib_gid *gid,
253 const struct ib_gid_attr *attr,
256 struct mlx4_ib_dev *ibdev = to_mdev(device);
257 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
258 struct mlx4_port_gid_table *port_gid_table;
259 int free = -1, found = -1;
263 struct gid_entry *gids = NULL;
265 if (!rdma_cap_roce_gid_table(device, port_num))
268 if (port_num > MLX4_MAX_PORTS)
274 port_gid_table = &iboe->gids[port_num - 1];
275 spin_lock_bh(&iboe->lock);
276 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
277 if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) &&
278 (port_gid_table->gids[i].gid_type == attr->gid_type)) {
282 if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid)))
283 free = i; /* HW has space */
290 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
291 if (!port_gid_table->gids[free].ctx) {
294 *context = port_gid_table->gids[free].ctx;
295 memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid));
296 port_gid_table->gids[free].gid_type = attr->gid_type;
297 port_gid_table->gids[free].ctx->real_index = free;
298 port_gid_table->gids[free].ctx->refcount = 1;
303 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
307 if (!ret && hw_update) {
308 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
312 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
313 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
314 gids[i].gid_type = port_gid_table->gids[i].gid_type;
318 spin_unlock_bh(&iboe->lock);
320 if (!ret && hw_update) {
321 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
328 static int mlx4_ib_del_gid(struct ib_device *device,
333 struct gid_cache_context *ctx = *context;
334 struct mlx4_ib_dev *ibdev = to_mdev(device);
335 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
336 struct mlx4_port_gid_table *port_gid_table;
339 struct gid_entry *gids = NULL;
341 if (!rdma_cap_roce_gid_table(device, port_num))
344 if (port_num > MLX4_MAX_PORTS)
347 port_gid_table = &iboe->gids[port_num - 1];
348 spin_lock_bh(&iboe->lock);
351 if (!ctx->refcount) {
352 unsigned int real_index = ctx->real_index;
354 memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid));
355 kfree(port_gid_table->gids[real_index].ctx);
356 port_gid_table->gids[real_index].ctx = NULL;
360 if (!ret && hw_update) {
363 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
367 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
369 &port_gid_table->gids[i].gid,
370 sizeof(union ib_gid));
372 port_gid_table->gids[i].gid_type;
376 spin_unlock_bh(&iboe->lock);
378 if (!ret && hw_update) {
379 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
385 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
386 u8 port_num, int index)
388 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
389 struct gid_cache_context *ctx = NULL;
391 struct mlx4_port_gid_table *port_gid_table;
392 int real_index = -EINVAL;
396 struct ib_gid_attr attr;
398 if (port_num > MLX4_MAX_PORTS)
401 if (mlx4_is_bonded(ibdev->dev))
404 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
407 ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr);
414 if (!memcmp(&gid, &zgid, sizeof(gid)))
417 spin_lock_irqsave(&iboe->lock, flags);
418 port_gid_table = &iboe->gids[port_num - 1];
420 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
421 if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) &&
422 attr.gid_type == port_gid_table->gids[i].gid_type) {
423 ctx = port_gid_table->gids[i].ctx;
427 real_index = ctx->real_index;
428 spin_unlock_irqrestore(&iboe->lock, flags);
432 static int mlx4_ib_query_device(struct ib_device *ibdev,
433 struct ib_device_attr *props,
434 struct ib_udata *uhw)
436 struct mlx4_ib_dev *dev = to_mdev(ibdev);
437 struct ib_smp *in_mad = NULL;
438 struct ib_smp *out_mad = NULL;
441 struct mlx4_uverbs_ex_query_device cmd;
442 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
443 struct mlx4_clock_params clock_params;
446 if (uhw->inlen < sizeof(cmd))
449 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
460 resp.response_length = offsetof(typeof(resp), response_length) +
461 sizeof(resp.response_length);
462 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
463 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
465 if (!in_mad || !out_mad)
468 init_query_mad(in_mad);
469 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
471 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
472 1, NULL, NULL, in_mad, out_mad);
476 memset(props, 0, sizeof *props);
478 have_ib_ports = num_ib_ports(dev->dev);
480 props->fw_ver = dev->dev->caps.fw_ver;
481 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
482 IB_DEVICE_PORT_ACTIVE_EVENT |
483 IB_DEVICE_SYS_IMAGE_GUID |
484 IB_DEVICE_RC_RNR_NAK_GEN |
485 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
486 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
487 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
488 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
489 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
490 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
491 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
492 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
493 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
494 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
495 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
496 if (dev->dev->caps.max_gso_sz &&
497 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
498 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
499 props->device_cap_flags |= IB_DEVICE_UD_TSO;
500 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
501 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
502 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
503 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
504 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
505 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
506 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
507 props->device_cap_flags |= IB_DEVICE_XRC;
508 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
509 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
510 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
511 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
512 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
514 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
516 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
517 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
519 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
521 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
523 props->vendor_part_id = dev->dev->persist->pdev->device;
524 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
525 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
527 props->max_mr_size = ~0ull;
528 props->page_size_cap = dev->dev->caps.page_size_cap;
529 props->max_qp = dev->dev->quotas.qp;
530 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
531 props->max_sge = min(dev->dev->caps.max_sq_sg,
532 dev->dev->caps.max_rq_sg);
533 props->max_sge_rd = MLX4_MAX_SGE_RD;
534 props->max_cq = dev->dev->quotas.cq;
535 props->max_cqe = dev->dev->caps.max_cqes;
536 props->max_mr = dev->dev->quotas.mpt;
537 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
538 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
539 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
540 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
541 props->max_srq = dev->dev->quotas.srq;
542 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
543 props->max_srq_sge = dev->dev->caps.max_srq_sge;
544 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
545 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
546 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
547 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
548 props->masked_atomic_cap = props->atomic_cap;
549 props->max_pkeys = dev->dev->caps.pkey_table_len[1];
550 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
551 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
552 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
553 props->max_mcast_grp;
554 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
555 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
556 props->timestamp_mask = 0xFFFFFFFFFFFFULL;
557 props->max_ah = INT_MAX;
559 if ((dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
560 (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET ||
561 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET)) {
562 props->rss_caps.max_rwq_indirection_tables = props->max_qp;
563 props->rss_caps.max_rwq_indirection_table_size =
564 dev->dev->caps.max_rss_tbl_sz;
565 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
566 props->max_wq_type_rq = props->max_qp;
569 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT;
570 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD;
572 if (!mlx4_is_slave(dev->dev))
573 err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
575 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
576 resp.response_length += sizeof(resp.hca_core_clock_offset);
577 if (!err && !mlx4_is_slave(dev->dev)) {
578 resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP;
579 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
583 if (uhw->outlen >= resp.response_length +
584 sizeof(resp.max_inl_recv_sz)) {
585 resp.response_length += sizeof(resp.max_inl_recv_sz);
586 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg *
587 sizeof(struct mlx4_wqe_data_seg);
590 if (uhw->outlen >= resp.response_length + sizeof(resp.rss_caps)) {
591 resp.response_length += sizeof(resp.rss_caps);
592 if (props->rss_caps.supported_qpts) {
593 resp.rss_caps.rx_hash_function =
594 MLX4_IB_RX_HASH_FUNC_TOEPLITZ;
596 resp.rss_caps.rx_hash_fields_mask =
597 MLX4_IB_RX_HASH_SRC_IPV4 |
598 MLX4_IB_RX_HASH_DST_IPV4 |
599 MLX4_IB_RX_HASH_SRC_IPV6 |
600 MLX4_IB_RX_HASH_DST_IPV6 |
601 MLX4_IB_RX_HASH_SRC_PORT_TCP |
602 MLX4_IB_RX_HASH_DST_PORT_TCP |
603 MLX4_IB_RX_HASH_SRC_PORT_UDP |
604 MLX4_IB_RX_HASH_DST_PORT_UDP;
606 if (dev->dev->caps.tunnel_offload_mode ==
607 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
608 resp.rss_caps.rx_hash_fields_mask |=
609 MLX4_IB_RX_HASH_INNER;
614 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
625 static enum rdma_link_layer
626 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
628 struct mlx4_dev *dev = to_mdev(device)->dev;
630 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
631 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
634 static int ib_link_query_port(struct ib_device *ibdev, u8 port,
635 struct ib_port_attr *props, int netw_view)
637 struct ib_smp *in_mad = NULL;
638 struct ib_smp *out_mad = NULL;
639 int ext_active_speed;
640 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
643 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
644 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
645 if (!in_mad || !out_mad)
648 init_query_mad(in_mad);
649 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
650 in_mad->attr_mod = cpu_to_be32(port);
652 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
653 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
655 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
661 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
662 props->lmc = out_mad->data[34] & 0x7;
663 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
664 props->sm_sl = out_mad->data[36] & 0xf;
665 props->state = out_mad->data[32] & 0xf;
666 props->phys_state = out_mad->data[33] >> 4;
667 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
669 props->gid_tbl_len = out_mad->data[50];
671 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
672 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
673 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
674 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
675 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
676 props->active_width = out_mad->data[31] & 0xf;
677 props->active_speed = out_mad->data[35] >> 4;
678 props->max_mtu = out_mad->data[41] & 0xf;
679 props->active_mtu = out_mad->data[36] >> 4;
680 props->subnet_timeout = out_mad->data[51] & 0x1f;
681 props->max_vl_num = out_mad->data[37] >> 4;
682 props->init_type_reply = out_mad->data[41] >> 4;
684 /* Check if extended speeds (EDR/FDR/...) are supported */
685 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
686 ext_active_speed = out_mad->data[62] >> 4;
688 switch (ext_active_speed) {
690 props->active_speed = IB_SPEED_FDR;
693 props->active_speed = IB_SPEED_EDR;
698 /* If reported active speed is QDR, check if is FDR-10 */
699 if (props->active_speed == IB_SPEED_QDR) {
700 init_query_mad(in_mad);
701 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
702 in_mad->attr_mod = cpu_to_be32(port);
704 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
705 NULL, NULL, in_mad, out_mad);
709 /* Checking LinkSpeedActive for FDR-10 */
710 if (out_mad->data[15] & 0x1)
711 props->active_speed = IB_SPEED_FDR10;
714 /* Avoid wrong speed value returned by FW if the IB link is down. */
715 if (props->state == IB_PORT_DOWN)
716 props->active_speed = IB_SPEED_SDR;
724 static u8 state_to_phys_state(enum ib_port_state state)
726 return state == IB_PORT_ACTIVE ? 5 : 3;
729 static int eth_link_query_port(struct ib_device *ibdev, u8 port,
730 struct ib_port_attr *props)
733 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
734 struct mlx4_ib_iboe *iboe = &mdev->iboe;
735 struct net_device *ndev;
737 struct mlx4_cmd_mailbox *mailbox;
739 int is_bonded = mlx4_is_bonded(mdev->dev);
741 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
743 return PTR_ERR(mailbox);
745 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
746 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
751 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
752 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
753 IB_WIDTH_4X : IB_WIDTH_1X;
754 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
755 IB_SPEED_FDR : IB_SPEED_QDR;
756 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
757 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
758 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
759 props->pkey_tbl_len = 1;
760 props->max_mtu = IB_MTU_4096;
761 props->max_vl_num = 2;
762 props->state = IB_PORT_DOWN;
763 props->phys_state = state_to_phys_state(props->state);
764 props->active_mtu = IB_MTU_256;
765 spin_lock_bh(&iboe->lock);
766 ndev = iboe->netdevs[port - 1];
767 if (ndev && is_bonded) {
768 rcu_read_lock(); /* required to get upper dev */
769 ndev = netdev_master_upper_dev_get_rcu(ndev);
775 tmp = iboe_get_mtu(ndev->mtu);
776 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
778 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
779 IB_PORT_ACTIVE : IB_PORT_DOWN;
780 props->phys_state = state_to_phys_state(props->state);
782 spin_unlock_bh(&iboe->lock);
784 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
788 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
789 struct ib_port_attr *props, int netw_view)
793 /* props being zeroed by the caller, avoid zeroing it here */
795 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
796 ib_link_query_port(ibdev, port, props, netw_view) :
797 eth_link_query_port(ibdev, port, props);
802 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
803 struct ib_port_attr *props)
805 /* returns host view */
806 return __mlx4_ib_query_port(ibdev, port, props, 0);
809 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
810 union ib_gid *gid, int netw_view)
812 struct ib_smp *in_mad = NULL;
813 struct ib_smp *out_mad = NULL;
815 struct mlx4_ib_dev *dev = to_mdev(ibdev);
817 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
819 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
820 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
821 if (!in_mad || !out_mad)
824 init_query_mad(in_mad);
825 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
826 in_mad->attr_mod = cpu_to_be32(port);
828 if (mlx4_is_mfunc(dev->dev) && netw_view)
829 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
831 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
835 memcpy(gid->raw, out_mad->data + 8, 8);
837 if (mlx4_is_mfunc(dev->dev) && !netw_view) {
839 /* For any index > 0, return the null guid */
846 init_query_mad(in_mad);
847 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
848 in_mad->attr_mod = cpu_to_be32(index / 8);
850 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
851 NULL, NULL, in_mad, out_mad);
855 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
859 memset(gid->raw + 8, 0, 8);
865 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
870 if (rdma_protocol_ib(ibdev, port))
871 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
873 if (!rdma_protocol_roce(ibdev, port))
876 if (!rdma_cap_roce_gid_table(ibdev, port))
879 ret = ib_get_cached_gid(ibdev, port, index, gid, NULL);
880 if (ret == -EAGAIN) {
881 memcpy(gid, &zgid, sizeof(*gid));
888 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
890 union sl2vl_tbl_to_u64 sl2vl64;
891 struct ib_smp *in_mad = NULL;
892 struct ib_smp *out_mad = NULL;
893 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
897 if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
902 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
903 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
904 if (!in_mad || !out_mad)
907 init_query_mad(in_mad);
908 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
909 in_mad->attr_mod = 0;
911 if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
912 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
914 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
919 for (jj = 0; jj < 8; jj++)
920 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
921 *sl2vl_tbl = sl2vl64.sl64;
929 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
935 for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
936 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
938 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
940 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
944 atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
948 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
949 u16 *pkey, int netw_view)
951 struct ib_smp *in_mad = NULL;
952 struct ib_smp *out_mad = NULL;
953 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
956 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
957 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
958 if (!in_mad || !out_mad)
961 init_query_mad(in_mad);
962 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
963 in_mad->attr_mod = cpu_to_be32(index / 32);
965 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
966 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
968 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
973 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
981 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
983 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
986 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
987 struct ib_device_modify *props)
989 struct mlx4_cmd_mailbox *mailbox;
992 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
995 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
998 if (mlx4_is_slave(to_mdev(ibdev)->dev))
1001 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
1002 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1003 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
1006 * If possible, pass node desc to FW, so it can generate
1007 * a 144 trap. If cmd fails, just ignore.
1009 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
1010 if (IS_ERR(mailbox))
1013 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1014 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
1015 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1017 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
1022 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
1025 struct mlx4_cmd_mailbox *mailbox;
1028 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
1029 if (IS_ERR(mailbox))
1030 return PTR_ERR(mailbox);
1032 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1033 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
1034 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
1036 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
1037 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
1040 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
1041 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1044 mlx4_free_cmd_mailbox(dev->dev, mailbox);
1048 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1049 struct ib_port_modify *props)
1051 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
1052 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
1053 struct ib_port_attr attr;
1057 /* return OK if this is RoCE. CM calls ib_modify_port() regardless
1058 * of whether port link layer is ETH or IB. For ETH ports, qkey
1059 * violations and port capabilities are not meaningful.
1064 mutex_lock(&mdev->cap_mask_mutex);
1066 err = ib_query_port(ibdev, port, &attr);
1070 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
1071 ~props->clr_port_cap_mask;
1073 err = mlx4_ib_SET_PORT(mdev, port,
1074 !!(mask & IB_PORT_RESET_QKEY_CNTR),
1078 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
1082 static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
1083 struct ib_udata *udata)
1085 struct mlx4_ib_dev *dev = to_mdev(ibdev);
1086 struct mlx4_ib_ucontext *context;
1087 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
1088 struct mlx4_ib_alloc_ucontext_resp resp;
1091 if (!dev->ib_active)
1092 return ERR_PTR(-EAGAIN);
1094 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
1095 resp_v3.qp_tab_size = dev->dev->caps.num_qps;
1096 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
1097 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1099 resp.dev_caps = dev->dev->caps.userspace_caps;
1100 resp.qp_tab_size = dev->dev->caps.num_qps;
1101 resp.bf_reg_size = dev->dev->caps.bf_reg_size;
1102 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1103 resp.cqe_size = dev->dev->caps.cqe_size;
1106 context = kzalloc(sizeof(*context), GFP_KERNEL);
1108 return ERR_PTR(-ENOMEM);
1110 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
1113 return ERR_PTR(err);
1116 INIT_LIST_HEAD(&context->db_page_list);
1117 mutex_init(&context->db_page_mutex);
1119 INIT_LIST_HEAD(&context->wqn_ranges_list);
1120 mutex_init(&context->wqn_ranges_mutex);
1122 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
1123 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
1125 err = ib_copy_to_udata(udata, &resp, sizeof(resp));
1128 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
1130 return ERR_PTR(-EFAULT);
1133 return &context->ibucontext;
1136 static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1138 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1140 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
1146 static void mlx4_ib_vma_open(struct vm_area_struct *area)
1148 /* vma_open is called when a new VMA is created on top of our VMA.
1149 * This is done through either mremap flow or split_vma (usually due
1150 * to mlock, madvise, munmap, etc.). We do not support a clone of the
1151 * vma, as this VMA is strongly hardware related. Therefore we set the
1152 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1153 * calling us again and trying to do incorrect actions. We assume that
1154 * the original vma size is exactly a single page that there will be no
1155 * "splitting" operations on.
1157 area->vm_ops = NULL;
1160 static void mlx4_ib_vma_close(struct vm_area_struct *area)
1162 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
1164 /* It's guaranteed that all VMAs opened on a FD are closed before the
1165 * file itself is closed, therefore no sync is needed with the regular
1166 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
1167 * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
1168 * The close operation is usually called under mm->mmap_sem except when
1169 * process is exiting. The exiting case is handled explicitly as part
1170 * of mlx4_ib_disassociate_ucontext.
1172 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
1173 area->vm_private_data;
1175 /* set the vma context pointer to null in the mlx4_ib driver's private
1176 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
1178 mlx4_ib_vma_priv_data->vma = NULL;
1181 static const struct vm_operations_struct mlx4_ib_vm_ops = {
1182 .open = mlx4_ib_vma_open,
1183 .close = mlx4_ib_vma_close
1186 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1190 struct vm_area_struct *vma;
1191 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1192 struct task_struct *owning_process = NULL;
1193 struct mm_struct *owning_mm = NULL;
1195 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1196 if (!owning_process)
1199 owning_mm = get_task_mm(owning_process);
1201 pr_info("no mm, disassociate ucontext is pending task termination\n");
1203 /* make sure that task is dead before returning, it may
1204 * prevent a rare case of module down in parallel to a
1205 * call to mlx4_ib_vma_close.
1207 put_task_struct(owning_process);
1208 usleep_range(1000, 2000);
1209 owning_process = get_pid_task(ibcontext->tgid,
1211 if (!owning_process ||
1212 owning_process->state == TASK_DEAD) {
1213 pr_info("disassociate ucontext done, task was terminated\n");
1214 /* in case task was dead need to release the task struct */
1216 put_task_struct(owning_process);
1222 /* need to protect from a race on closing the vma as part of
1223 * mlx4_ib_vma_close().
1225 down_write(&owning_mm->mmap_sem);
1226 for (i = 0; i < HW_BAR_COUNT; i++) {
1227 vma = context->hw_bar_info[i].vma;
1231 ret = zap_vma_ptes(context->hw_bar_info[i].vma,
1232 context->hw_bar_info[i].vma->vm_start,
1235 pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret);
1239 context->hw_bar_info[i].vma->vm_flags &=
1240 ~(VM_SHARED | VM_MAYSHARE);
1241 /* context going to be destroyed, should not access ops any more */
1242 context->hw_bar_info[i].vma->vm_ops = NULL;
1245 up_write(&owning_mm->mmap_sem);
1247 put_task_struct(owning_process);
1250 static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
1251 struct mlx4_ib_vma_private_data *vma_private_data)
1253 vma_private_data->vma = vma;
1254 vma->vm_private_data = vma_private_data;
1255 vma->vm_ops = &mlx4_ib_vm_ops;
1258 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
1260 struct mlx4_ib_dev *dev = to_mdev(context->device);
1261 struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
1263 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1266 if (vma->vm_pgoff == 0) {
1267 /* We prevent double mmaping on same context */
1268 if (mucontext->hw_bar_info[HW_BAR_DB].vma)
1271 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1273 if (io_remap_pfn_range(vma, vma->vm_start,
1274 to_mucontext(context)->uar.pfn,
1275 PAGE_SIZE, vma->vm_page_prot))
1278 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
1280 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
1281 /* We prevent double mmaping on same context */
1282 if (mucontext->hw_bar_info[HW_BAR_BF].vma)
1285 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1287 if (io_remap_pfn_range(vma, vma->vm_start,
1288 to_mucontext(context)->uar.pfn +
1289 dev->dev->caps.num_uars,
1290 PAGE_SIZE, vma->vm_page_prot))
1293 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
1295 } else if (vma->vm_pgoff == 3) {
1296 struct mlx4_clock_params params;
1299 /* We prevent double mmaping on same context */
1300 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
1303 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms);
1308 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1309 if (io_remap_pfn_range(vma, vma->vm_start,
1310 (pci_resource_start(dev->dev->persist->pdev,
1314 PAGE_SIZE, vma->vm_page_prot))
1317 mlx4_ib_set_vma_data(vma,
1318 &mucontext->hw_bar_info[HW_BAR_CLOCK]);
1326 static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
1327 struct ib_ucontext *context,
1328 struct ib_udata *udata)
1330 struct mlx4_ib_pd *pd;
1333 pd = kmalloc(sizeof *pd, GFP_KERNEL);
1335 return ERR_PTR(-ENOMEM);
1337 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
1340 return ERR_PTR(err);
1344 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
1345 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
1347 return ERR_PTR(-EFAULT);
1353 static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
1355 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
1361 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
1362 struct ib_ucontext *context,
1363 struct ib_udata *udata)
1365 struct mlx4_ib_xrcd *xrcd;
1366 struct ib_cq_init_attr cq_attr = {};
1369 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1370 return ERR_PTR(-ENOSYS);
1372 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
1374 return ERR_PTR(-ENOMEM);
1376 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
1380 xrcd->pd = ib_alloc_pd(ibdev, 0);
1381 if (IS_ERR(xrcd->pd)) {
1382 err = PTR_ERR(xrcd->pd);
1387 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
1388 if (IS_ERR(xrcd->cq)) {
1389 err = PTR_ERR(xrcd->cq);
1393 return &xrcd->ibxrcd;
1396 ib_dealloc_pd(xrcd->pd);
1398 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
1401 return ERR_PTR(err);
1404 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
1406 ib_destroy_cq(to_mxrcd(xrcd)->cq);
1407 ib_dealloc_pd(to_mxrcd(xrcd)->pd);
1408 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
1414 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
1416 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1417 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1418 struct mlx4_ib_gid_entry *ge;
1420 ge = kzalloc(sizeof *ge, GFP_KERNEL);
1425 if (mlx4_ib_add_mc(mdev, mqp, gid)) {
1426 ge->port = mqp->port;
1430 mutex_lock(&mqp->mutex);
1431 list_add_tail(&ge->list, &mqp->gid_list);
1432 mutex_unlock(&mqp->mutex);
1437 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
1438 struct mlx4_ib_counters *ctr_table)
1440 struct counter_index *counter, *tmp_count;
1442 mutex_lock(&ctr_table->mutex);
1443 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
1445 if (counter->allocated)
1446 mlx4_counter_free(ibdev->dev, counter->index);
1447 list_del(&counter->list);
1450 mutex_unlock(&ctr_table->mutex);
1453 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
1456 struct net_device *ndev;
1462 spin_lock_bh(&mdev->iboe.lock);
1463 ndev = mdev->iboe.netdevs[mqp->port - 1];
1466 spin_unlock_bh(&mdev->iboe.lock);
1476 struct mlx4_ib_steering {
1477 struct list_head list;
1478 struct mlx4_flow_reg_id reg_id;
1482 #define LAST_ETH_FIELD vlan_tag
1483 #define LAST_IB_FIELD sl
1484 #define LAST_IPV4_FIELD dst_ip
1485 #define LAST_TCP_UDP_FIELD src_port
1487 /* Field is the last supported field */
1488 #define FIELDS_NOT_SUPPORTED(filter, field)\
1489 memchr_inv((void *)&filter.field +\
1490 sizeof(filter.field), 0,\
1492 offsetof(typeof(filter), field) -\
1493 sizeof(filter.field))
1495 static int parse_flow_attr(struct mlx4_dev *dev,
1497 union ib_flow_spec *ib_spec,
1498 struct _rule_hw *mlx4_spec)
1500 enum mlx4_net_trans_rule_id type;
1502 switch (ib_spec->type) {
1503 case IB_FLOW_SPEC_ETH:
1504 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1507 type = MLX4_NET_TRANS_RULE_ID_ETH;
1508 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
1510 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
1512 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
1513 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
1515 case IB_FLOW_SPEC_IB:
1516 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
1519 type = MLX4_NET_TRANS_RULE_ID_IB;
1520 mlx4_spec->ib.l3_qpn =
1521 cpu_to_be32(qp_num);
1522 mlx4_spec->ib.qpn_mask =
1523 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
1527 case IB_FLOW_SPEC_IPV4:
1528 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1531 type = MLX4_NET_TRANS_RULE_ID_IPV4;
1532 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
1533 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
1534 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
1535 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
1538 case IB_FLOW_SPEC_TCP:
1539 case IB_FLOW_SPEC_UDP:
1540 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
1543 type = ib_spec->type == IB_FLOW_SPEC_TCP ?
1544 MLX4_NET_TRANS_RULE_ID_TCP :
1545 MLX4_NET_TRANS_RULE_ID_UDP;
1546 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
1547 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
1548 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
1549 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
1555 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
1556 mlx4_hw_rule_sz(dev, type) < 0)
1558 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
1559 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
1560 return mlx4_hw_rule_sz(dev, type);
1563 struct default_rules {
1564 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1565 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1566 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
1569 static const struct default_rules default_table[] = {
1571 .mandatory_fields = {IB_FLOW_SPEC_IPV4},
1572 .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
1573 .rules_create_list = {IB_FLOW_SPEC_IB},
1574 .link_layer = IB_LINK_LAYER_INFINIBAND
1578 static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
1579 struct ib_flow_attr *flow_attr)
1583 const struct default_rules *pdefault_rules = default_table;
1584 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
1586 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
1587 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
1588 memset(&field_types, 0, sizeof(field_types));
1590 if (link_layer != pdefault_rules->link_layer)
1593 ib_flow = flow_attr + 1;
1594 /* we assume the specs are sorted */
1595 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
1596 j < flow_attr->num_of_specs; k++) {
1597 union ib_flow_spec *current_flow =
1598 (union ib_flow_spec *)ib_flow;
1600 /* same layer but different type */
1601 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
1602 (pdefault_rules->mandatory_fields[k] &
1603 IB_FLOW_SPEC_LAYER_MASK)) &&
1604 (current_flow->type !=
1605 pdefault_rules->mandatory_fields[k]))
1608 /* same layer, try match next one */
1609 if (current_flow->type ==
1610 pdefault_rules->mandatory_fields[k]) {
1613 ((union ib_flow_spec *)ib_flow)->size;
1617 ib_flow = flow_attr + 1;
1618 for (j = 0; j < flow_attr->num_of_specs;
1619 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
1620 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
1621 /* same layer and same type */
1622 if (((union ib_flow_spec *)ib_flow)->type ==
1623 pdefault_rules->mandatory_not_fields[k])
1632 static int __mlx4_ib_create_default_rules(
1633 struct mlx4_ib_dev *mdev,
1635 const struct default_rules *pdefault_rules,
1636 struct _rule_hw *mlx4_spec) {
1640 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
1642 union ib_flow_spec ib_spec;
1643 switch (pdefault_rules->rules_create_list[i]) {
1647 case IB_FLOW_SPEC_IB:
1648 ib_spec.type = IB_FLOW_SPEC_IB;
1649 ib_spec.size = sizeof(struct ib_flow_spec_ib);
1656 /* We must put empty rule, qpn is being ignored */
1657 ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
1660 pr_info("invalid parsing\n");
1664 mlx4_spec = (void *)mlx4_spec + ret;
1670 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1672 enum mlx4_net_trans_promisc_mode flow_type,
1678 struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1679 struct mlx4_cmd_mailbox *mailbox;
1680 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
1683 static const u16 __mlx4_domain[] = {
1684 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
1685 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
1686 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
1687 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
1690 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1691 pr_err("Invalid priority value %d\n", flow_attr->priority);
1695 if (domain >= IB_FLOW_DOMAIN_NUM) {
1696 pr_err("Invalid domain value %d\n", domain);
1700 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1703 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1704 if (IS_ERR(mailbox))
1705 return PTR_ERR(mailbox);
1706 ctrl = mailbox->buf;
1708 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
1709 flow_attr->priority);
1710 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1711 ctrl->port = flow_attr->port;
1712 ctrl->qpn = cpu_to_be32(qp->qp_num);
1714 ib_flow = flow_attr + 1;
1715 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
1716 /* Add default flows */
1717 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1718 if (default_flow >= 0) {
1719 ret = __mlx4_ib_create_default_rules(
1720 mdev, qp, default_table + default_flow,
1721 mailbox->buf + size);
1723 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1728 for (i = 0; i < flow_attr->num_of_specs; i++) {
1729 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1730 mailbox->buf + size);
1732 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1735 ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1739 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR &&
1740 flow_attr->num_of_specs == 1) {
1741 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1);
1742 enum ib_flow_spec_type header_spec =
1743 ((union ib_flow_spec *)(flow_attr + 1))->type;
1745 if (header_spec == IB_FLOW_SPEC_ETH)
1746 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
1749 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1750 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
1753 pr_err("mcg table is full. Fail to register network rule.\n");
1754 else if (ret == -ENXIO)
1755 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1757 pr_err("Invalid argument. Fail to register network rule.\n");
1759 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1763 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1766 err = mlx4_cmd(dev, reg_id, 0, 0,
1767 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1770 pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1775 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1779 union ib_flow_spec *ib_spec;
1780 struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1783 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
1784 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
1785 return 0; /* do nothing */
1787 ib_flow = flow_attr + 1;
1788 ib_spec = (union ib_flow_spec *)ib_flow;
1790 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1791 return 0; /* do nothing */
1793 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1794 flow_attr->port, qp->qp_num,
1795 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1800 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
1801 struct ib_flow_attr *flow_attr,
1802 enum mlx4_net_trans_promisc_mode *type)
1806 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
1807 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
1808 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
1812 if (flow_attr->num_of_specs == 0) {
1813 type[0] = MLX4_FS_MC_SNIFFER;
1814 type[1] = MLX4_FS_UC_SNIFFER;
1816 union ib_flow_spec *ib_spec;
1818 ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1819 if (ib_spec->type != IB_FLOW_SPEC_ETH)
1822 /* if all is zero than MC and UC */
1823 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
1824 type[0] = MLX4_FS_MC_SNIFFER;
1825 type[1] = MLX4_FS_UC_SNIFFER;
1827 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
1828 ib_spec->eth.mask.dst_mac[1],
1829 ib_spec->eth.mask.dst_mac[2],
1830 ib_spec->eth.mask.dst_mac[3],
1831 ib_spec->eth.mask.dst_mac[4],
1832 ib_spec->eth.mask.dst_mac[5]};
1834 /* Above xor was only on MC bit, non empty mask is valid
1835 * only if this bit is set and rest are zero.
1837 if (!is_zero_ether_addr(&mac[0]))
1840 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
1841 type[0] = MLX4_FS_MC_SNIFFER;
1843 type[0] = MLX4_FS_UC_SNIFFER;
1850 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1851 struct ib_flow_attr *flow_attr,
1854 int err = 0, i = 0, j = 0;
1855 struct mlx4_ib_flow *mflow;
1856 enum mlx4_net_trans_promisc_mode type[2];
1857 struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1858 int is_bonded = mlx4_is_bonded(dev);
1860 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
1861 return ERR_PTR(-EINVAL);
1863 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
1864 (flow_attr->type != IB_FLOW_ATTR_NORMAL))
1865 return ERR_PTR(-EOPNOTSUPP);
1867 memset(type, 0, sizeof(type));
1869 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1875 switch (flow_attr->type) {
1876 case IB_FLOW_ATTR_NORMAL:
1877 /* If dont trap flag (continue match) is set, under specific
1878 * condition traffic be replicated to given qp,
1879 * without stealing it
1881 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
1882 err = mlx4_ib_add_dont_trap_rule(dev,
1888 type[0] = MLX4_FS_REGULAR;
1892 case IB_FLOW_ATTR_ALL_DEFAULT:
1893 type[0] = MLX4_FS_ALL_DEFAULT;
1896 case IB_FLOW_ATTR_MC_DEFAULT:
1897 type[0] = MLX4_FS_MC_DEFAULT;
1900 case IB_FLOW_ATTR_SNIFFER:
1901 type[0] = MLX4_FS_MIRROR_RX_PORT;
1902 type[1] = MLX4_FS_MIRROR_SX_PORT;
1910 while (i < ARRAY_SIZE(type) && type[i]) {
1911 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
1912 &mflow->reg_id[i].id);
1914 goto err_create_flow;
1916 /* Application always sees one port so the mirror rule
1917 * must be on port #2
1919 flow_attr->port = 2;
1920 err = __mlx4_ib_create_flow(qp, flow_attr,
1922 &mflow->reg_id[j].mirror);
1923 flow_attr->port = 1;
1925 goto err_create_flow;
1932 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1933 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1934 &mflow->reg_id[i].id);
1936 goto err_create_flow;
1939 flow_attr->port = 2;
1940 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1941 &mflow->reg_id[j].mirror);
1942 flow_attr->port = 1;
1944 goto err_create_flow;
1947 /* function to create mirror rule */
1951 return &mflow->ibflow;
1955 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1956 mflow->reg_id[i].id);
1961 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1962 mflow->reg_id[j].mirror);
1967 return ERR_PTR(err);
1970 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1974 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1975 struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1977 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
1978 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
1981 if (mflow->reg_id[i].mirror) {
1982 err = __mlx4_ib_destroy_flow(mdev->dev,
1983 mflow->reg_id[i].mirror);
1994 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1997 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1998 struct mlx4_dev *dev = mdev->dev;
1999 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2000 struct mlx4_ib_steering *ib_steering = NULL;
2001 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
2002 struct mlx4_flow_reg_id reg_id;
2004 if (mdev->dev->caps.steering_mode ==
2005 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2006 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
2011 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
2013 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
2016 pr_err("multicast attach op failed, err %d\n", err);
2021 if (mlx4_is_bonded(dev)) {
2022 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
2023 (mqp->port == 1) ? 2 : 1,
2025 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
2026 prot, ®_id.mirror);
2031 err = add_gid_entry(ibqp, gid);
2036 memcpy(ib_steering->gid.raw, gid->raw, 16);
2037 ib_steering->reg_id = reg_id;
2038 mutex_lock(&mqp->mutex);
2039 list_add(&ib_steering->list, &mqp->steering_rules);
2040 mutex_unlock(&mqp->mutex);
2045 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2048 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2049 prot, reg_id.mirror);
2056 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
2058 struct mlx4_ib_gid_entry *ge;
2059 struct mlx4_ib_gid_entry *tmp;
2060 struct mlx4_ib_gid_entry *ret = NULL;
2062 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
2063 if (!memcmp(raw, ge->gid.raw, 16)) {
2072 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2075 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2076 struct mlx4_dev *dev = mdev->dev;
2077 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2078 struct net_device *ndev;
2079 struct mlx4_ib_gid_entry *ge;
2080 struct mlx4_flow_reg_id reg_id = {0, 0};
2081 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
2083 if (mdev->dev->caps.steering_mode ==
2084 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2085 struct mlx4_ib_steering *ib_steering;
2087 mutex_lock(&mqp->mutex);
2088 list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
2089 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
2090 list_del(&ib_steering->list);
2094 mutex_unlock(&mqp->mutex);
2095 if (&ib_steering->list == &mqp->steering_rules) {
2096 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
2099 reg_id = ib_steering->reg_id;
2103 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2108 if (mlx4_is_bonded(dev)) {
2109 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2110 prot, reg_id.mirror);
2115 mutex_lock(&mqp->mutex);
2116 ge = find_gid_entry(mqp, gid->raw);
2118 spin_lock_bh(&mdev->iboe.lock);
2119 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
2122 spin_unlock_bh(&mdev->iboe.lock);
2125 list_del(&ge->list);
2128 pr_warn("could not find mgid entry\n");
2130 mutex_unlock(&mqp->mutex);
2135 static int init_node_data(struct mlx4_ib_dev *dev)
2137 struct ib_smp *in_mad = NULL;
2138 struct ib_smp *out_mad = NULL;
2139 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
2142 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
2143 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
2144 if (!in_mad || !out_mad)
2147 init_query_mad(in_mad);
2148 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
2149 if (mlx4_is_master(dev->dev))
2150 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
2152 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2156 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
2158 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
2160 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2164 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
2165 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
2173 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2176 struct mlx4_ib_dev *dev =
2177 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2178 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
2181 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2184 struct mlx4_ib_dev *dev =
2185 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2186 return sprintf(buf, "%x\n", dev->dev->rev_id);
2189 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2192 struct mlx4_ib_dev *dev =
2193 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2194 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
2195 dev->dev->board_id);
2198 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2199 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2200 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2202 static struct device_attribute *mlx4_class_attributes[] = {
2208 struct diag_counter {
2213 #define DIAG_COUNTER(_name, _offset) \
2214 { .name = #_name, .offset = _offset }
2216 static const struct diag_counter diag_basic[] = {
2217 DIAG_COUNTER(rq_num_lle, 0x00),
2218 DIAG_COUNTER(sq_num_lle, 0x04),
2219 DIAG_COUNTER(rq_num_lqpoe, 0x08),
2220 DIAG_COUNTER(sq_num_lqpoe, 0x0C),
2221 DIAG_COUNTER(rq_num_lpe, 0x18),
2222 DIAG_COUNTER(sq_num_lpe, 0x1C),
2223 DIAG_COUNTER(rq_num_wrfe, 0x20),
2224 DIAG_COUNTER(sq_num_wrfe, 0x24),
2225 DIAG_COUNTER(sq_num_mwbe, 0x2C),
2226 DIAG_COUNTER(sq_num_bre, 0x34),
2227 DIAG_COUNTER(sq_num_rire, 0x44),
2228 DIAG_COUNTER(rq_num_rire, 0x48),
2229 DIAG_COUNTER(sq_num_rae, 0x4C),
2230 DIAG_COUNTER(rq_num_rae, 0x50),
2231 DIAG_COUNTER(sq_num_roe, 0x54),
2232 DIAG_COUNTER(sq_num_tree, 0x5C),
2233 DIAG_COUNTER(sq_num_rree, 0x64),
2234 DIAG_COUNTER(rq_num_rnr, 0x68),
2235 DIAG_COUNTER(sq_num_rnr, 0x6C),
2236 DIAG_COUNTER(rq_num_oos, 0x100),
2237 DIAG_COUNTER(sq_num_oos, 0x104),
2240 static const struct diag_counter diag_ext[] = {
2241 DIAG_COUNTER(rq_num_dup, 0x130),
2242 DIAG_COUNTER(sq_num_to, 0x134),
2245 static const struct diag_counter diag_device_only[] = {
2246 DIAG_COUNTER(num_cqovf, 0x1A0),
2247 DIAG_COUNTER(rq_num_udsdprd, 0x118),
2250 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
2253 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2254 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2256 if (!diag[!!port_num].name)
2259 return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
2260 diag[!!port_num].num_counters,
2261 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2264 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
2265 struct rdma_hw_stats *stats,
2268 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2269 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2270 u32 hw_value[ARRAY_SIZE(diag_device_only) +
2271 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
2275 ret = mlx4_query_diag_counters(dev->dev,
2276 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
2277 diag[!!port].offset, hw_value,
2278 diag[!!port].num_counters, port);
2283 for (i = 0; i < diag[!!port].num_counters; i++)
2284 stats->value[i] = hw_value[i];
2286 return diag[!!port].num_counters;
2289 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
2297 num_counters = ARRAY_SIZE(diag_basic);
2299 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
2300 num_counters += ARRAY_SIZE(diag_ext);
2303 num_counters += ARRAY_SIZE(diag_device_only);
2305 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
2309 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
2313 *num = num_counters;
2322 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
2330 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
2331 name[i] = diag_basic[i].name;
2332 offset[i] = diag_basic[i].offset;
2335 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
2336 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
2337 name[j] = diag_ext[i].name;
2338 offset[j] = diag_ext[i].offset;
2343 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
2344 name[j] = diag_device_only[i].name;
2345 offset[j] = diag_device_only[i].offset;
2350 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
2352 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
2355 bool per_port = !!(ibdev->dev->caps.flags2 &
2356 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
2358 if (mlx4_is_slave(ibdev->dev))
2361 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2362 /* i == 1 means we are building port counters */
2366 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
2368 &diag[i].num_counters, i);
2372 mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
2376 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats;
2377 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats;
2383 kfree(diag[i - 1].name);
2384 kfree(diag[i - 1].offset);
2390 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
2394 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2395 kfree(ibdev->diag_counters[i].offset);
2396 kfree(ibdev->diag_counters[i].name);
2400 #define MLX4_IB_INVALID_MAC ((u64)-1)
2401 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
2402 struct net_device *dev,
2406 u64 release_mac = MLX4_IB_INVALID_MAC;
2407 struct mlx4_ib_qp *qp;
2409 read_lock(&dev_base_lock);
2410 new_smac = mlx4_mac_to_u64(dev->dev_addr);
2411 read_unlock(&dev_base_lock);
2413 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
2415 /* no need for update QP1 and mac registration in non-SRIOV */
2416 if (!mlx4_is_mfunc(ibdev->dev))
2419 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
2420 qp = ibdev->qp1_proxy[port - 1];
2424 struct mlx4_update_qp_params update_params;
2426 mutex_lock(&qp->mutex);
2427 old_smac = qp->pri.smac;
2428 if (new_smac == old_smac)
2431 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
2433 if (new_smac_index < 0)
2436 update_params.smac_index = new_smac_index;
2437 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
2439 release_mac = new_smac;
2442 /* if old port was zero, no mac was yet registered for this QP */
2443 if (qp->pri.smac_port)
2444 release_mac = old_smac;
2445 qp->pri.smac = new_smac;
2446 qp->pri.smac_port = port;
2447 qp->pri.smac_index = new_smac_index;
2451 if (release_mac != MLX4_IB_INVALID_MAC)
2452 mlx4_unregister_mac(ibdev->dev, port, release_mac);
2454 mutex_unlock(&qp->mutex);
2455 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
2458 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
2459 struct net_device *dev,
2460 unsigned long event)
2463 struct mlx4_ib_iboe *iboe;
2464 int update_qps_port = -1;
2469 iboe = &ibdev->iboe;
2471 spin_lock_bh(&iboe->lock);
2472 mlx4_foreach_ib_transport_port(port, ibdev->dev) {
2474 iboe->netdevs[port - 1] =
2475 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
2477 if (dev == iboe->netdevs[port - 1] &&
2478 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
2479 event == NETDEV_UP || event == NETDEV_CHANGE))
2480 update_qps_port = port;
2483 spin_unlock_bh(&iboe->lock);
2485 if (update_qps_port > 0)
2486 mlx4_ib_update_qps(ibdev, dev, update_qps_port);
2489 static int mlx4_ib_netdev_event(struct notifier_block *this,
2490 unsigned long event, void *ptr)
2492 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2493 struct mlx4_ib_dev *ibdev;
2495 if (!net_eq(dev_net(dev), &init_net))
2498 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
2499 mlx4_ib_scan_netdevs(ibdev, dev, event);
2504 static void init_pkeys(struct mlx4_ib_dev *ibdev)
2510 if (mlx4_is_master(ibdev->dev)) {
2511 for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
2513 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2515 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2517 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
2518 /* master has the identity virt2phys pkey mapping */
2519 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
2520 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
2521 mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
2522 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
2526 /* initialize pkey cache */
2527 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2529 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2531 ibdev->pkeys.phys_pkey_cache[port-1][i] =
2537 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2539 int i, j, eq = 0, total_eqs = 0;
2541 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
2542 sizeof(ibdev->eq_table[0]), GFP_KERNEL);
2543 if (!ibdev->eq_table)
2546 for (i = 1; i <= dev->caps.num_ports; i++) {
2547 for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
2549 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
2551 ibdev->eq_table[eq] = total_eqs;
2552 if (!mlx4_assign_eq(dev, i,
2553 &ibdev->eq_table[eq]))
2556 ibdev->eq_table[eq] = -1;
2560 for (i = eq; i < dev->caps.num_comp_vectors;
2561 ibdev->eq_table[i++] = -1)
2564 /* Advertise the new number of EQs to clients */
2565 ibdev->ib_dev.num_comp_vectors = eq;
2568 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2571 int total_eqs = ibdev->ib_dev.num_comp_vectors;
2573 /* no eqs were allocated */
2574 if (!ibdev->eq_table)
2577 /* Reset the advertised EQ number */
2578 ibdev->ib_dev.num_comp_vectors = 0;
2580 for (i = 0; i < total_eqs; i++)
2581 mlx4_release_eq(dev, ibdev->eq_table[i]);
2583 kfree(ibdev->eq_table);
2584 ibdev->eq_table = NULL;
2587 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
2588 struct ib_port_immutable *immutable)
2590 struct ib_port_attr attr;
2591 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
2594 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
2595 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
2596 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2598 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
2599 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
2600 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
2601 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
2602 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2603 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET;
2604 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE |
2605 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP))
2606 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2609 err = ib_query_port(ibdev, port_num, &attr);
2613 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2614 immutable->gid_tbl_len = attr.gid_tbl_len;
2619 static void get_fw_ver_str(struct ib_device *device, char *str)
2621 struct mlx4_ib_dev *dev =
2622 container_of(device, struct mlx4_ib_dev, ib_dev);
2623 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d",
2624 (int) (dev->dev->caps.fw_ver >> 32),
2625 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
2626 (int) dev->dev->caps.fw_ver & 0xffff);
2629 static void *mlx4_ib_add(struct mlx4_dev *dev)
2631 struct mlx4_ib_dev *ibdev;
2635 struct mlx4_ib_iboe *iboe;
2636 int ib_num_ports = 0;
2637 int num_req_counters;
2640 struct counter_index *new_counter_index = NULL;
2642 pr_info_once("%s", mlx4_ib_version);
2645 mlx4_foreach_ib_transport_port(i, dev)
2648 /* No point in registering a device with no ports... */
2652 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
2654 dev_err(&dev->persist->pdev->dev,
2655 "Device struct alloc failed\n");
2659 iboe = &ibdev->iboe;
2661 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2664 if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2667 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2669 if (!ibdev->uar_map)
2671 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
2674 ibdev->bond_next_port = 0;
2676 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
2677 ibdev->ib_dev.owner = THIS_MODULE;
2678 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
2679 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
2680 ibdev->num_ports = num_ports;
2681 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
2682 1 : ibdev->num_ports;
2683 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
2684 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev;
2685 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
2686 ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
2687 ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
2689 if (dev->caps.userspace_caps)
2690 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
2692 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2694 ibdev->ib_dev.uverbs_cmd_mask =
2695 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2696 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2697 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2698 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2699 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2700 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2701 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2702 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2703 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2704 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2705 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2706 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2707 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2708 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2709 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2710 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2711 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2712 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2713 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2714 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2715 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2716 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2717 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2718 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2720 ibdev->ib_dev.query_device = mlx4_ib_query_device;
2721 ibdev->ib_dev.query_port = mlx4_ib_query_port;
2722 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
2723 ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
2724 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
2725 ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
2726 ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
2727 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
2728 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
2729 ibdev->ib_dev.mmap = mlx4_ib_mmap;
2730 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
2731 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
2732 ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
2733 ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
2734 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
2735 ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
2736 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
2737 ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
2738 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
2739 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
2740 ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
2741 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
2742 ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
2743 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
2744 ibdev->ib_dev.post_send = mlx4_ib_post_send;
2745 ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
2746 ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
2747 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
2748 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
2749 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
2750 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
2751 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
2752 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
2753 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
2754 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
2755 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
2756 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
2757 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
2758 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
2759 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
2760 ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
2761 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
2762 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str;
2763 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
2765 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2766 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
2768 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
2769 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) ==
2770 IB_LINK_LAYER_ETHERNET) ||
2771 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) ==
2772 IB_LINK_LAYER_ETHERNET))) {
2773 ibdev->ib_dev.create_wq = mlx4_ib_create_wq;
2774 ibdev->ib_dev.modify_wq = mlx4_ib_modify_wq;
2775 ibdev->ib_dev.destroy_wq = mlx4_ib_destroy_wq;
2776 ibdev->ib_dev.create_rwq_ind_table =
2777 mlx4_ib_create_rwq_ind_table;
2778 ibdev->ib_dev.destroy_rwq_ind_table =
2779 mlx4_ib_destroy_rwq_ind_table;
2780 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2781 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
2782 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
2783 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
2784 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
2785 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
2788 if (!mlx4_is_slave(ibdev->dev)) {
2789 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
2790 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
2791 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
2792 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
2795 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2796 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2797 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
2798 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
2800 ibdev->ib_dev.uverbs_cmd_mask |=
2801 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2802 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2805 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2806 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
2807 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
2808 ibdev->ib_dev.uverbs_cmd_mask |=
2809 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2810 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2813 if (check_flow_steering_support(dev)) {
2814 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
2815 ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
2816 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
2818 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2819 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2820 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2823 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2824 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2825 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2826 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2828 mlx4_ib_alloc_eqs(dev, ibdev);
2830 spin_lock_init(&iboe->lock);
2832 if (init_node_data(ibdev))
2834 mlx4_init_sl2vl_tbl(ibdev);
2836 for (i = 0; i < ibdev->num_ports; ++i) {
2837 mutex_init(&ibdev->counters_table[i].mutex);
2838 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
2841 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
2842 for (i = 0; i < num_req_counters; ++i) {
2843 mutex_init(&ibdev->qp1_proxy_lock[i]);
2845 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2846 IB_LINK_LAYER_ETHERNET) {
2847 err = mlx4_counter_alloc(ibdev->dev, &counter_index,
2848 MLX4_RES_USAGE_DRIVER);
2849 /* if failed to allocate a new counter, use default */
2852 mlx4_get_default_counter_index(dev,
2856 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
2857 counter_index = mlx4_get_default_counter_index(dev,
2860 new_counter_index = kmalloc(sizeof(*new_counter_index),
2862 if (!new_counter_index) {
2864 mlx4_counter_free(ibdev->dev, counter_index);
2867 new_counter_index->index = counter_index;
2868 new_counter_index->allocated = allocated;
2869 list_add_tail(&new_counter_index->list,
2870 &ibdev->counters_table[i].counters_list);
2871 ibdev->counters_table[i].default_counter = counter_index;
2872 pr_info("counter index %d for port %d allocated %d\n",
2873 counter_index, i + 1, allocated);
2875 if (mlx4_is_bonded(dev))
2876 for (i = 1; i < ibdev->num_ports ; ++i) {
2878 kmalloc(sizeof(struct counter_index),
2880 if (!new_counter_index)
2882 new_counter_index->index = counter_index;
2883 new_counter_index->allocated = 0;
2884 list_add_tail(&new_counter_index->list,
2885 &ibdev->counters_table[i].counters_list);
2886 ibdev->counters_table[i].default_counter =
2890 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2893 spin_lock_init(&ibdev->sm_lock);
2894 mutex_init(&ibdev->cap_mask_mutex);
2895 INIT_LIST_HEAD(&ibdev->qp_list);
2896 spin_lock_init(&ibdev->reset_flow_resource_lock);
2898 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2900 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2901 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2902 MLX4_IB_UC_STEER_QPN_ALIGN,
2903 &ibdev->steer_qpn_base, 0,
2904 MLX4_RES_USAGE_DRIVER);
2908 ibdev->ib_uc_qpns_bitmap =
2909 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
2912 if (!ibdev->ib_uc_qpns_bitmap)
2913 goto err_steer_qp_release;
2915 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
2916 bitmap_zero(ibdev->ib_uc_qpns_bitmap,
2917 ibdev->steer_qpn_count);
2918 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2919 dev, ibdev->steer_qpn_base,
2920 ibdev->steer_qpn_base +
2921 ibdev->steer_qpn_count - 1);
2923 goto err_steer_free_bitmap;
2925 bitmap_fill(ibdev->ib_uc_qpns_bitmap,
2926 ibdev->steer_qpn_count);
2930 for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
2931 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
2933 if (mlx4_ib_alloc_diag_counters(ibdev))
2934 goto err_steer_free_bitmap;
2936 if (ib_register_device(&ibdev->ib_dev, NULL))
2937 goto err_diag_counters;
2939 if (mlx4_ib_mad_init(ibdev))
2942 if (mlx4_ib_init_sriov(ibdev))
2945 if (!iboe->nb.notifier_call) {
2946 iboe->nb.notifier_call = mlx4_ib_netdev_event;
2947 err = register_netdevice_notifier(&iboe->nb);
2949 iboe->nb.notifier_call = NULL;
2953 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2954 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
2959 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
2960 if (device_create_file(&ibdev->ib_dev.dev,
2961 mlx4_class_attributes[j]))
2965 ibdev->ib_active = true;
2966 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2967 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
2970 if (mlx4_is_mfunc(ibdev->dev))
2973 /* create paravirt contexts for any VFs which are active */
2974 if (mlx4_is_master(ibdev->dev)) {
2975 for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2976 if (j == mlx4_master_func_num(ibdev->dev))
2978 if (mlx4_is_slave_active(ibdev->dev, j))
2979 do_slave_init(ibdev, j, 1);
2985 if (ibdev->iboe.nb.notifier_call) {
2986 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2987 pr_warn("failure unregistering notifier\n");
2988 ibdev->iboe.nb.notifier_call = NULL;
2990 flush_workqueue(wq);
2992 mlx4_ib_close_sriov(ibdev);
2995 mlx4_ib_mad_cleanup(ibdev);
2998 ib_unregister_device(&ibdev->ib_dev);
3001 mlx4_ib_diag_cleanup(ibdev);
3003 err_steer_free_bitmap:
3004 kfree(ibdev->ib_uc_qpns_bitmap);
3006 err_steer_qp_release:
3007 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
3008 ibdev->steer_qpn_count);
3010 for (i = 0; i < ibdev->num_ports; ++i)
3011 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
3014 mlx4_ib_free_eqs(dev, ibdev);
3015 iounmap(ibdev->uar_map);
3018 mlx4_uar_free(dev, &ibdev->priv_uar);
3021 mlx4_pd_free(dev, ibdev->priv_pdn);
3024 ib_dealloc_device(&ibdev->ib_dev);
3029 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
3033 WARN_ON(!dev->ib_uc_qpns_bitmap);
3035 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
3036 dev->steer_qpn_count,
3037 get_count_order(count));
3041 *qpn = dev->steer_qpn_base + offset;
3045 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
3048 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
3051 BUG_ON(qpn < dev->steer_qpn_base);
3053 bitmap_release_region(dev->ib_uc_qpns_bitmap,
3054 qpn - dev->steer_qpn_base,
3055 get_count_order(count));
3058 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
3063 struct ib_flow_attr *flow = NULL;
3064 struct ib_flow_spec_ib *ib_spec;
3067 flow_size = sizeof(struct ib_flow_attr) +
3068 sizeof(struct ib_flow_spec_ib);
3069 flow = kzalloc(flow_size, GFP_KERNEL);
3072 flow->port = mqp->port;
3073 flow->num_of_specs = 1;
3074 flow->size = flow_size;
3075 ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
3076 ib_spec->type = IB_FLOW_SPEC_IB;
3077 ib_spec->size = sizeof(struct ib_flow_spec_ib);
3078 /* Add an empty rule for IB L2 */
3079 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
3081 err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
3086 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
3092 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
3094 struct mlx4_ib_dev *ibdev = ibdev_ptr;
3098 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
3099 devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
3100 ibdev->ib_active = false;
3101 flush_workqueue(wq);
3103 mlx4_ib_close_sriov(ibdev);
3104 mlx4_ib_mad_cleanup(ibdev);
3105 ib_unregister_device(&ibdev->ib_dev);
3106 mlx4_ib_diag_cleanup(ibdev);
3107 if (ibdev->iboe.nb.notifier_call) {
3108 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
3109 pr_warn("failure unregistering notifier\n");
3110 ibdev->iboe.nb.notifier_call = NULL;
3113 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
3114 ibdev->steer_qpn_count);
3115 kfree(ibdev->ib_uc_qpns_bitmap);
3117 iounmap(ibdev->uar_map);
3118 for (p = 0; p < ibdev->num_ports; ++p)
3119 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
3121 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
3122 mlx4_CLOSE_PORT(dev, p);
3124 mlx4_ib_free_eqs(dev, ibdev);
3126 mlx4_uar_free(dev, &ibdev->priv_uar);
3127 mlx4_pd_free(dev, ibdev->priv_pdn);
3128 ib_dealloc_device(&ibdev->ib_dev);
3131 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
3133 struct mlx4_ib_demux_work **dm = NULL;
3134 struct mlx4_dev *dev = ibdev->dev;
3136 unsigned long flags;
3137 struct mlx4_active_ports actv_ports;
3139 unsigned int first_port;
3141 if (!mlx4_is_master(dev))
3144 actv_ports = mlx4_get_active_ports(dev, slave);
3145 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
3146 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
3148 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
3152 for (i = 0; i < ports; i++) {
3153 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
3159 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
3160 dm[i]->port = first_port + i + 1;
3161 dm[i]->slave = slave;
3162 dm[i]->do_init = do_init;
3165 /* initialize or tear down tunnel QPs for the slave */
3166 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
3167 if (!ibdev->sriov.is_going_down) {
3168 for (i = 0; i < ports; i++)
3169 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
3170 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3172 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3173 for (i = 0; i < ports; i++)
3181 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
3183 struct mlx4_ib_qp *mqp;
3184 unsigned long flags_qp;
3185 unsigned long flags_cq;
3186 struct mlx4_ib_cq *send_mcq, *recv_mcq;
3187 struct list_head cq_notify_list;
3188 struct mlx4_cq *mcq;
3189 unsigned long flags;
3191 pr_warn("mlx4_ib_handle_catas_error was started\n");
3192 INIT_LIST_HEAD(&cq_notify_list);
3194 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3195 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3197 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3198 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3199 if (mqp->sq.tail != mqp->sq.head) {
3200 send_mcq = to_mcq(mqp->ibqp.send_cq);
3201 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3202 if (send_mcq->mcq.comp &&
3203 mqp->ibqp.send_cq->comp_handler) {
3204 if (!send_mcq->mcq.reset_notify_added) {
3205 send_mcq->mcq.reset_notify_added = 1;
3206 list_add_tail(&send_mcq->mcq.reset_notify,
3210 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3212 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3213 /* Now, handle the QP's receive queue */
3214 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3215 /* no handling is needed for SRQ */
3216 if (!mqp->ibqp.srq) {
3217 if (mqp->rq.tail != mqp->rq.head) {
3218 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3219 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3220 if (recv_mcq->mcq.comp &&
3221 mqp->ibqp.recv_cq->comp_handler) {
3222 if (!recv_mcq->mcq.reset_notify_added) {
3223 recv_mcq->mcq.reset_notify_added = 1;
3224 list_add_tail(&recv_mcq->mcq.reset_notify,
3228 spin_unlock_irqrestore(&recv_mcq->lock,
3232 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3235 list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
3238 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3239 pr_warn("mlx4_ib_handle_catas_error ended\n");
3242 static void handle_bonded_port_state_event(struct work_struct *work)
3244 struct ib_event_work *ew =
3245 container_of(work, struct ib_event_work, work);
3246 struct mlx4_ib_dev *ibdev = ew->ib_dev;
3247 enum ib_port_state bonded_port_state = IB_PORT_NOP;
3249 struct ib_event ibev;
3252 spin_lock_bh(&ibdev->iboe.lock);
3253 for (i = 0; i < MLX4_MAX_PORTS; ++i) {
3254 struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
3255 enum ib_port_state curr_port_state;
3261 (netif_running(curr_netdev) &&
3262 netif_carrier_ok(curr_netdev)) ?
3263 IB_PORT_ACTIVE : IB_PORT_DOWN;
3265 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
3266 curr_port_state : IB_PORT_ACTIVE;
3268 spin_unlock_bh(&ibdev->iboe.lock);
3270 ibev.device = &ibdev->ib_dev;
3271 ibev.element.port_num = 1;
3272 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
3273 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3275 ib_dispatch_event(&ibev);
3278 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
3283 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
3285 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
3289 atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
3292 static void ib_sl2vl_update_work(struct work_struct *work)
3294 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
3295 struct mlx4_ib_dev *mdev = ew->ib_dev;
3296 int port = ew->port;
3298 mlx4_ib_sl2vl_update(mdev, port);
3303 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
3306 struct ib_event_work *ew;
3308 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3310 INIT_WORK(&ew->work, ib_sl2vl_update_work);
3313 queue_work(wq, &ew->work);
3317 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
3318 enum mlx4_dev_event event, unsigned long param)
3320 struct ib_event ibev;
3321 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
3322 struct mlx4_eqe *eqe = NULL;
3323 struct ib_event_work *ew;
3326 if (mlx4_is_bonded(dev) &&
3327 ((event == MLX4_DEV_EVENT_PORT_UP) ||
3328 (event == MLX4_DEV_EVENT_PORT_DOWN))) {
3329 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3332 INIT_WORK(&ew->work, handle_bonded_port_state_event);
3334 queue_work(wq, &ew->work);
3338 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
3339 eqe = (struct mlx4_eqe *)param;
3344 case MLX4_DEV_EVENT_PORT_UP:
3345 if (p > ibdev->num_ports)
3347 if (!mlx4_is_slave(dev) &&
3348 rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
3349 IB_LINK_LAYER_INFINIBAND) {
3350 if (mlx4_is_master(dev))
3351 mlx4_ib_invalidate_all_guid_record(ibdev, p);
3352 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
3353 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
3354 mlx4_sched_ib_sl2vl_update_work(ibdev, p);
3356 ibev.event = IB_EVENT_PORT_ACTIVE;
3359 case MLX4_DEV_EVENT_PORT_DOWN:
3360 if (p > ibdev->num_ports)
3362 ibev.event = IB_EVENT_PORT_ERR;
3365 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3366 ibdev->ib_active = false;
3367 ibev.event = IB_EVENT_DEVICE_FATAL;
3368 mlx4_ib_handle_catas_error(ibdev);
3371 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
3372 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
3376 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
3377 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
3379 /* need to queue only for port owner, which uses GEN_EQE */
3380 if (mlx4_is_master(dev))
3381 queue_work(wq, &ew->work);
3383 handle_port_mgmt_change_event(&ew->work);
3386 case MLX4_DEV_EVENT_SLAVE_INIT:
3387 /* here, p is the slave id */
3388 do_slave_init(ibdev, p, 1);
3389 if (mlx4_is_master(dev)) {
3392 for (i = 1; i <= ibdev->num_ports; i++) {
3393 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3394 == IB_LINK_LAYER_INFINIBAND)
3395 mlx4_ib_slave_alias_guid_event(ibdev,
3402 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
3403 if (mlx4_is_master(dev)) {
3406 for (i = 1; i <= ibdev->num_ports; i++) {
3407 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3408 == IB_LINK_LAYER_INFINIBAND)
3409 mlx4_ib_slave_alias_guid_event(ibdev,
3414 /* here, p is the slave id */
3415 do_slave_init(ibdev, p, 0);
3422 ibev.device = ibdev_ptr;
3423 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
3425 ib_dispatch_event(&ibev);
3428 static struct mlx4_interface mlx4_ib_interface = {
3430 .remove = mlx4_ib_remove,
3431 .event = mlx4_ib_event,
3432 .protocol = MLX4_PROT_IB_IPV6,
3433 .flags = MLX4_INTFF_BONDING
3436 static int __init mlx4_ib_init(void)
3440 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
3444 err = mlx4_ib_mcg_init();
3448 err = mlx4_register_interface(&mlx4_ib_interface);
3455 mlx4_ib_mcg_destroy();
3458 destroy_workqueue(wq);
3462 static void __exit mlx4_ib_cleanup(void)
3464 mlx4_unregister_interface(&mlx4_ib_interface);
3465 mlx4_ib_mcg_destroy();
3466 destroy_workqueue(wq);
3469 module_init(mlx4_ib_init);
3470 module_exit(mlx4_ib_cleanup);