2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38 #include <linux/netdevice.h>
39 #include <linux/inetdevice.h>
40 #include <linux/rtnetlink.h>
41 #include <linux/if_vlan.h>
43 #include <net/addrconf.h>
44 #include <net/devlink.h>
46 #include <rdma/ib_smi.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/ib_addr.h>
49 #include <rdma/ib_cache.h>
51 #include <net/bonding.h>
53 #include <linux/mlx4/driver.h>
54 #include <linux/mlx4/cmd.h>
55 #include <linux/mlx4/qp.h>
58 #include <rdma/mlx4-abi.h>
60 #define DRV_NAME MLX4_IB_DRV_NAME
61 #define DRV_VERSION "2.2-1"
62 #define DRV_RELDATE "Feb 2014"
64 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
65 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
66 #define MLX4_IB_CARD_REV_A0 0xA0
68 MODULE_AUTHOR("Roland Dreier");
69 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
70 MODULE_LICENSE("Dual BSD/GPL");
71 MODULE_VERSION(DRV_VERSION);
73 int mlx4_ib_sm_guid_assign = 0;
74 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
75 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
77 static const char mlx4_ib_version[] =
78 DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
79 DRV_VERSION " (" DRV_RELDATE ")\n";
81 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
83 static struct workqueue_struct *wq;
85 static void init_query_mad(struct ib_smp *mad)
87 mad->base_version = 1;
88 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
89 mad->class_version = 1;
90 mad->method = IB_MGMT_METHOD_GET;
93 static int check_flow_steering_support(struct mlx4_dev *dev)
95 int eth_num_ports = 0;
98 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
102 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
104 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
106 dmfs &= (!ib_num_ports ||
107 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
109 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
110 if (ib_num_ports && mlx4_is_mfunc(dev)) {
111 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
118 static int num_ib_ports(struct mlx4_dev *dev)
123 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
129 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
131 struct mlx4_ib_dev *ibdev = to_mdev(device);
132 struct net_device *dev;
135 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
138 if (mlx4_is_bonded(ibdev->dev)) {
139 struct net_device *upper = NULL;
141 upper = netdev_master_upper_dev_get_rcu(dev);
143 struct net_device *active;
145 active = bond_option_active_slave_get_rcu(netdev_priv(upper));
158 static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
159 struct mlx4_ib_dev *ibdev,
162 struct mlx4_cmd_mailbox *mailbox;
164 struct mlx4_dev *dev = ibdev->dev;
166 union ib_gid *gid_tbl;
168 mailbox = mlx4_alloc_cmd_mailbox(dev);
172 gid_tbl = mailbox->buf;
174 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
175 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
177 err = mlx4_cmd(dev, mailbox->dma,
178 MLX4_SET_PORT_GID_TABLE << 8 | port_num,
179 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
181 if (mlx4_is_bonded(dev))
182 err += mlx4_cmd(dev, mailbox->dma,
183 MLX4_SET_PORT_GID_TABLE << 8 | 2,
184 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
187 mlx4_free_cmd_mailbox(dev, mailbox);
191 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
192 struct mlx4_ib_dev *ibdev,
195 struct mlx4_cmd_mailbox *mailbox;
197 struct mlx4_dev *dev = ibdev->dev;
208 mailbox = mlx4_alloc_cmd_mailbox(dev);
212 gid_tbl = mailbox->buf;
213 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
214 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
215 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
216 gid_tbl[i].version = 2;
217 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
220 memset(&gid_tbl[i].gid, 0, 12);
224 err = mlx4_cmd(dev, mailbox->dma,
225 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
226 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
228 if (mlx4_is_bonded(dev))
229 err += mlx4_cmd(dev, mailbox->dma,
230 MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
231 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
234 mlx4_free_cmd_mailbox(dev, mailbox);
238 static int mlx4_ib_update_gids(struct gid_entry *gids,
239 struct mlx4_ib_dev *ibdev,
242 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
243 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
245 return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
248 static int mlx4_ib_add_gid(struct ib_device *device,
251 const union ib_gid *gid,
252 const struct ib_gid_attr *attr,
255 struct mlx4_ib_dev *ibdev = to_mdev(device);
256 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
257 struct mlx4_port_gid_table *port_gid_table;
258 int free = -1, found = -1;
262 struct gid_entry *gids = NULL;
264 if (!rdma_cap_roce_gid_table(device, port_num))
267 if (port_num > MLX4_MAX_PORTS)
273 port_gid_table = &iboe->gids[port_num - 1];
274 spin_lock_bh(&iboe->lock);
275 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
276 if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) &&
277 (port_gid_table->gids[i].gid_type == attr->gid_type)) {
281 if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid)))
282 free = i; /* HW has space */
289 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
290 if (!port_gid_table->gids[free].ctx) {
293 *context = port_gid_table->gids[free].ctx;
294 memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid));
295 port_gid_table->gids[free].gid_type = attr->gid_type;
296 port_gid_table->gids[free].ctx->real_index = free;
297 port_gid_table->gids[free].ctx->refcount = 1;
302 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
306 if (!ret && hw_update) {
307 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
311 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
312 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
313 gids[i].gid_type = port_gid_table->gids[i].gid_type;
317 spin_unlock_bh(&iboe->lock);
319 if (!ret && hw_update) {
320 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
327 static int mlx4_ib_del_gid(struct ib_device *device,
332 struct gid_cache_context *ctx = *context;
333 struct mlx4_ib_dev *ibdev = to_mdev(device);
334 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
335 struct mlx4_port_gid_table *port_gid_table;
338 struct gid_entry *gids = NULL;
340 if (!rdma_cap_roce_gid_table(device, port_num))
343 if (port_num > MLX4_MAX_PORTS)
346 port_gid_table = &iboe->gids[port_num - 1];
347 spin_lock_bh(&iboe->lock);
350 if (!ctx->refcount) {
351 unsigned int real_index = ctx->real_index;
353 memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid));
354 kfree(port_gid_table->gids[real_index].ctx);
355 port_gid_table->gids[real_index].ctx = NULL;
359 if (!ret && hw_update) {
362 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
366 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++)
367 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
370 spin_unlock_bh(&iboe->lock);
372 if (!ret && hw_update) {
373 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
379 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
380 u8 port_num, int index)
382 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
383 struct gid_cache_context *ctx = NULL;
385 struct mlx4_port_gid_table *port_gid_table;
386 int real_index = -EINVAL;
390 struct ib_gid_attr attr;
392 if (port_num > MLX4_MAX_PORTS)
395 if (mlx4_is_bonded(ibdev->dev))
398 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
401 ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr);
408 if (!memcmp(&gid, &zgid, sizeof(gid)))
411 spin_lock_irqsave(&iboe->lock, flags);
412 port_gid_table = &iboe->gids[port_num - 1];
414 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
415 if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) &&
416 attr.gid_type == port_gid_table->gids[i].gid_type) {
417 ctx = port_gid_table->gids[i].ctx;
421 real_index = ctx->real_index;
422 spin_unlock_irqrestore(&iboe->lock, flags);
426 static int mlx4_ib_query_device(struct ib_device *ibdev,
427 struct ib_device_attr *props,
428 struct ib_udata *uhw)
430 struct mlx4_ib_dev *dev = to_mdev(ibdev);
431 struct ib_smp *in_mad = NULL;
432 struct ib_smp *out_mad = NULL;
435 struct mlx4_uverbs_ex_query_device cmd;
436 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
437 struct mlx4_clock_params clock_params;
440 if (uhw->inlen < sizeof(cmd))
443 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
454 resp.response_length = offsetof(typeof(resp), response_length) +
455 sizeof(resp.response_length);
456 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
457 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
458 if (!in_mad || !out_mad)
461 init_query_mad(in_mad);
462 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
464 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
465 1, NULL, NULL, in_mad, out_mad);
469 memset(props, 0, sizeof *props);
471 have_ib_ports = num_ib_ports(dev->dev);
473 props->fw_ver = dev->dev->caps.fw_ver;
474 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
475 IB_DEVICE_PORT_ACTIVE_EVENT |
476 IB_DEVICE_SYS_IMAGE_GUID |
477 IB_DEVICE_RC_RNR_NAK_GEN |
478 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
479 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
480 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
481 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
482 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
483 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
484 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
485 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
486 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
487 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
488 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
489 if (dev->dev->caps.max_gso_sz &&
490 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
491 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
492 props->device_cap_flags |= IB_DEVICE_UD_TSO;
493 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
494 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
495 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
496 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
497 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
498 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
499 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
500 props->device_cap_flags |= IB_DEVICE_XRC;
501 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
502 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
503 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
504 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
505 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
507 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
509 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
510 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
512 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
514 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
516 props->vendor_part_id = dev->dev->persist->pdev->device;
517 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
518 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
520 props->max_mr_size = ~0ull;
521 props->page_size_cap = dev->dev->caps.page_size_cap;
522 props->max_qp = dev->dev->quotas.qp;
523 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
524 props->max_sge = min(dev->dev->caps.max_sq_sg,
525 dev->dev->caps.max_rq_sg);
526 props->max_sge_rd = MLX4_MAX_SGE_RD;
527 props->max_cq = dev->dev->quotas.cq;
528 props->max_cqe = dev->dev->caps.max_cqes;
529 props->max_mr = dev->dev->quotas.mpt;
530 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
531 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
532 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
533 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
534 props->max_srq = dev->dev->quotas.srq;
535 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
536 props->max_srq_sge = dev->dev->caps.max_srq_sge;
537 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
538 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
539 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
540 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
541 props->masked_atomic_cap = props->atomic_cap;
542 props->max_pkeys = dev->dev->caps.pkey_table_len[1];
543 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
544 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
545 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
546 props->max_mcast_grp;
547 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
548 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
549 props->timestamp_mask = 0xFFFFFFFFFFFFULL;
550 props->max_ah = INT_MAX;
552 if (!mlx4_is_slave(dev->dev))
553 err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
555 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
556 resp.response_length += sizeof(resp.hca_core_clock_offset);
557 if (!err && !mlx4_is_slave(dev->dev)) {
558 resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP;
559 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
564 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
575 static enum rdma_link_layer
576 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
578 struct mlx4_dev *dev = to_mdev(device)->dev;
580 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
581 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
584 static int ib_link_query_port(struct ib_device *ibdev, u8 port,
585 struct ib_port_attr *props, int netw_view)
587 struct ib_smp *in_mad = NULL;
588 struct ib_smp *out_mad = NULL;
589 int ext_active_speed;
590 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
593 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
594 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
595 if (!in_mad || !out_mad)
598 init_query_mad(in_mad);
599 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
600 in_mad->attr_mod = cpu_to_be32(port);
602 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
603 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
605 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
611 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
612 props->lmc = out_mad->data[34] & 0x7;
613 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
614 props->sm_sl = out_mad->data[36] & 0xf;
615 props->state = out_mad->data[32] & 0xf;
616 props->phys_state = out_mad->data[33] >> 4;
617 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
619 props->gid_tbl_len = out_mad->data[50];
621 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
622 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
623 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
624 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
625 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
626 props->active_width = out_mad->data[31] & 0xf;
627 props->active_speed = out_mad->data[35] >> 4;
628 props->max_mtu = out_mad->data[41] & 0xf;
629 props->active_mtu = out_mad->data[36] >> 4;
630 props->subnet_timeout = out_mad->data[51] & 0x1f;
631 props->max_vl_num = out_mad->data[37] >> 4;
632 props->init_type_reply = out_mad->data[41] >> 4;
634 /* Check if extended speeds (EDR/FDR/...) are supported */
635 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
636 ext_active_speed = out_mad->data[62] >> 4;
638 switch (ext_active_speed) {
640 props->active_speed = IB_SPEED_FDR;
643 props->active_speed = IB_SPEED_EDR;
648 /* If reported active speed is QDR, check if is FDR-10 */
649 if (props->active_speed == IB_SPEED_QDR) {
650 init_query_mad(in_mad);
651 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
652 in_mad->attr_mod = cpu_to_be32(port);
654 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
655 NULL, NULL, in_mad, out_mad);
659 /* Checking LinkSpeedActive for FDR-10 */
660 if (out_mad->data[15] & 0x1)
661 props->active_speed = IB_SPEED_FDR10;
664 /* Avoid wrong speed value returned by FW if the IB link is down. */
665 if (props->state == IB_PORT_DOWN)
666 props->active_speed = IB_SPEED_SDR;
674 static u8 state_to_phys_state(enum ib_port_state state)
676 return state == IB_PORT_ACTIVE ? 5 : 3;
679 static int eth_link_query_port(struct ib_device *ibdev, u8 port,
680 struct ib_port_attr *props, int netw_view)
683 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
684 struct mlx4_ib_iboe *iboe = &mdev->iboe;
685 struct net_device *ndev;
687 struct mlx4_cmd_mailbox *mailbox;
689 int is_bonded = mlx4_is_bonded(mdev->dev);
691 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
693 return PTR_ERR(mailbox);
695 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
696 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
701 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
702 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
703 IB_WIDTH_4X : IB_WIDTH_1X;
704 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
705 IB_SPEED_FDR : IB_SPEED_QDR;
706 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
707 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
708 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
709 props->pkey_tbl_len = 1;
710 props->max_mtu = IB_MTU_4096;
711 props->max_vl_num = 2;
712 props->state = IB_PORT_DOWN;
713 props->phys_state = state_to_phys_state(props->state);
714 props->active_mtu = IB_MTU_256;
715 spin_lock_bh(&iboe->lock);
716 ndev = iboe->netdevs[port - 1];
717 if (ndev && is_bonded) {
718 rcu_read_lock(); /* required to get upper dev */
719 ndev = netdev_master_upper_dev_get_rcu(ndev);
725 tmp = iboe_get_mtu(ndev->mtu);
726 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
728 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
729 IB_PORT_ACTIVE : IB_PORT_DOWN;
730 props->phys_state = state_to_phys_state(props->state);
732 spin_unlock_bh(&iboe->lock);
734 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
738 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
739 struct ib_port_attr *props, int netw_view)
743 memset(props, 0, sizeof *props);
745 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
746 ib_link_query_port(ibdev, port, props, netw_view) :
747 eth_link_query_port(ibdev, port, props, netw_view);
752 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
753 struct ib_port_attr *props)
755 /* returns host view */
756 return __mlx4_ib_query_port(ibdev, port, props, 0);
759 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
760 union ib_gid *gid, int netw_view)
762 struct ib_smp *in_mad = NULL;
763 struct ib_smp *out_mad = NULL;
765 struct mlx4_ib_dev *dev = to_mdev(ibdev);
767 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
769 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
770 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
771 if (!in_mad || !out_mad)
774 init_query_mad(in_mad);
775 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
776 in_mad->attr_mod = cpu_to_be32(port);
778 if (mlx4_is_mfunc(dev->dev) && netw_view)
779 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
781 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
785 memcpy(gid->raw, out_mad->data + 8, 8);
787 if (mlx4_is_mfunc(dev->dev) && !netw_view) {
789 /* For any index > 0, return the null guid */
796 init_query_mad(in_mad);
797 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
798 in_mad->attr_mod = cpu_to_be32(index / 8);
800 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
801 NULL, NULL, in_mad, out_mad);
805 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
809 memset(gid->raw + 8, 0, 8);
815 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
820 if (rdma_protocol_ib(ibdev, port))
821 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
823 if (!rdma_protocol_roce(ibdev, port))
826 if (!rdma_cap_roce_gid_table(ibdev, port))
829 ret = ib_get_cached_gid(ibdev, port, index, gid, NULL);
830 if (ret == -EAGAIN) {
831 memcpy(gid, &zgid, sizeof(*gid));
838 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
840 union sl2vl_tbl_to_u64 sl2vl64;
841 struct ib_smp *in_mad = NULL;
842 struct ib_smp *out_mad = NULL;
843 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
847 if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
852 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
853 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
854 if (!in_mad || !out_mad)
857 init_query_mad(in_mad);
858 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
859 in_mad->attr_mod = 0;
861 if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
862 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
864 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
869 for (jj = 0; jj < 8; jj++)
870 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
871 *sl2vl_tbl = sl2vl64.sl64;
879 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
885 for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
886 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
888 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
890 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
894 atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
898 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
899 u16 *pkey, int netw_view)
901 struct ib_smp *in_mad = NULL;
902 struct ib_smp *out_mad = NULL;
903 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
906 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
907 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
908 if (!in_mad || !out_mad)
911 init_query_mad(in_mad);
912 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
913 in_mad->attr_mod = cpu_to_be32(index / 32);
915 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
916 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
918 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
923 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
931 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
933 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
936 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
937 struct ib_device_modify *props)
939 struct mlx4_cmd_mailbox *mailbox;
942 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
945 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
948 if (mlx4_is_slave(to_mdev(ibdev)->dev))
951 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
952 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
953 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
956 * If possible, pass node desc to FW, so it can generate
957 * a 144 trap. If cmd fails, just ignore.
959 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
963 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
964 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
965 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
967 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
972 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
975 struct mlx4_cmd_mailbox *mailbox;
978 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
980 return PTR_ERR(mailbox);
982 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
983 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
984 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
986 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
987 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
990 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
991 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
994 mlx4_free_cmd_mailbox(dev->dev, mailbox);
998 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
999 struct ib_port_modify *props)
1001 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
1002 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
1003 struct ib_port_attr attr;
1007 /* return OK if this is RoCE. CM calls ib_modify_port() regardless
1008 * of whether port link layer is ETH or IB. For ETH ports, qkey
1009 * violations and port capabilities are not meaningful.
1014 mutex_lock(&mdev->cap_mask_mutex);
1016 err = mlx4_ib_query_port(ibdev, port, &attr);
1020 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
1021 ~props->clr_port_cap_mask;
1023 err = mlx4_ib_SET_PORT(mdev, port,
1024 !!(mask & IB_PORT_RESET_QKEY_CNTR),
1028 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
1032 static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
1033 struct ib_udata *udata)
1035 struct mlx4_ib_dev *dev = to_mdev(ibdev);
1036 struct mlx4_ib_ucontext *context;
1037 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
1038 struct mlx4_ib_alloc_ucontext_resp resp;
1041 if (!dev->ib_active)
1042 return ERR_PTR(-EAGAIN);
1044 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
1045 resp_v3.qp_tab_size = dev->dev->caps.num_qps;
1046 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
1047 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1049 resp.dev_caps = dev->dev->caps.userspace_caps;
1050 resp.qp_tab_size = dev->dev->caps.num_qps;
1051 resp.bf_reg_size = dev->dev->caps.bf_reg_size;
1052 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1053 resp.cqe_size = dev->dev->caps.cqe_size;
1056 context = kzalloc(sizeof(*context), GFP_KERNEL);
1058 return ERR_PTR(-ENOMEM);
1060 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
1063 return ERR_PTR(err);
1066 INIT_LIST_HEAD(&context->db_page_list);
1067 mutex_init(&context->db_page_mutex);
1069 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
1070 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
1072 err = ib_copy_to_udata(udata, &resp, sizeof(resp));
1075 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
1077 return ERR_PTR(-EFAULT);
1080 return &context->ibucontext;
1083 static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1085 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1087 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
1093 static void mlx4_ib_vma_open(struct vm_area_struct *area)
1095 /* vma_open is called when a new VMA is created on top of our VMA.
1096 * This is done through either mremap flow or split_vma (usually due
1097 * to mlock, madvise, munmap, etc.). We do not support a clone of the
1098 * vma, as this VMA is strongly hardware related. Therefore we set the
1099 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1100 * calling us again and trying to do incorrect actions. We assume that
1101 * the original vma size is exactly a single page that there will be no
1102 * "splitting" operations on.
1104 area->vm_ops = NULL;
1107 static void mlx4_ib_vma_close(struct vm_area_struct *area)
1109 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
1111 /* It's guaranteed that all VMAs opened on a FD are closed before the
1112 * file itself is closed, therefore no sync is needed with the regular
1113 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
1114 * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
1115 * The close operation is usually called under mm->mmap_sem except when
1116 * process is exiting. The exiting case is handled explicitly as part
1117 * of mlx4_ib_disassociate_ucontext.
1119 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
1120 area->vm_private_data;
1122 /* set the vma context pointer to null in the mlx4_ib driver's private
1123 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
1125 mlx4_ib_vma_priv_data->vma = NULL;
1128 static const struct vm_operations_struct mlx4_ib_vm_ops = {
1129 .open = mlx4_ib_vma_open,
1130 .close = mlx4_ib_vma_close
1133 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1137 struct vm_area_struct *vma;
1138 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1139 struct task_struct *owning_process = NULL;
1140 struct mm_struct *owning_mm = NULL;
1142 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1143 if (!owning_process)
1146 owning_mm = get_task_mm(owning_process);
1148 pr_info("no mm, disassociate ucontext is pending task termination\n");
1150 /* make sure that task is dead before returning, it may
1151 * prevent a rare case of module down in parallel to a
1152 * call to mlx4_ib_vma_close.
1154 put_task_struct(owning_process);
1156 owning_process = get_pid_task(ibcontext->tgid,
1158 if (!owning_process ||
1159 owning_process->state == TASK_DEAD) {
1160 pr_info("disassociate ucontext done, task was terminated\n");
1161 /* in case task was dead need to release the task struct */
1163 put_task_struct(owning_process);
1169 /* need to protect from a race on closing the vma as part of
1170 * mlx4_ib_vma_close().
1172 down_read(&owning_mm->mmap_sem);
1173 for (i = 0; i < HW_BAR_COUNT; i++) {
1174 vma = context->hw_bar_info[i].vma;
1178 ret = zap_vma_ptes(context->hw_bar_info[i].vma,
1179 context->hw_bar_info[i].vma->vm_start,
1182 pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret);
1186 /* context going to be destroyed, should not access ops any more */
1187 context->hw_bar_info[i].vma->vm_ops = NULL;
1190 up_read(&owning_mm->mmap_sem);
1192 put_task_struct(owning_process);
1195 static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
1196 struct mlx4_ib_vma_private_data *vma_private_data)
1198 vma_private_data->vma = vma;
1199 vma->vm_private_data = vma_private_data;
1200 vma->vm_ops = &mlx4_ib_vm_ops;
1203 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
1205 struct mlx4_ib_dev *dev = to_mdev(context->device);
1206 struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
1208 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1211 if (vma->vm_pgoff == 0) {
1212 /* We prevent double mmaping on same context */
1213 if (mucontext->hw_bar_info[HW_BAR_DB].vma)
1216 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1218 if (io_remap_pfn_range(vma, vma->vm_start,
1219 to_mucontext(context)->uar.pfn,
1220 PAGE_SIZE, vma->vm_page_prot))
1223 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
1225 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
1226 /* We prevent double mmaping on same context */
1227 if (mucontext->hw_bar_info[HW_BAR_BF].vma)
1230 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1232 if (io_remap_pfn_range(vma, vma->vm_start,
1233 to_mucontext(context)->uar.pfn +
1234 dev->dev->caps.num_uars,
1235 PAGE_SIZE, vma->vm_page_prot))
1238 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
1240 } else if (vma->vm_pgoff == 3) {
1241 struct mlx4_clock_params params;
1244 /* We prevent double mmaping on same context */
1245 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
1248 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms);
1253 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1254 if (io_remap_pfn_range(vma, vma->vm_start,
1255 (pci_resource_start(dev->dev->persist->pdev,
1259 PAGE_SIZE, vma->vm_page_prot))
1262 mlx4_ib_set_vma_data(vma,
1263 &mucontext->hw_bar_info[HW_BAR_CLOCK]);
1271 static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
1272 struct ib_ucontext *context,
1273 struct ib_udata *udata)
1275 struct mlx4_ib_pd *pd;
1278 pd = kmalloc(sizeof *pd, GFP_KERNEL);
1280 return ERR_PTR(-ENOMEM);
1282 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
1285 return ERR_PTR(err);
1289 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
1290 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
1292 return ERR_PTR(-EFAULT);
1298 static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
1300 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
1306 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
1307 struct ib_ucontext *context,
1308 struct ib_udata *udata)
1310 struct mlx4_ib_xrcd *xrcd;
1311 struct ib_cq_init_attr cq_attr = {};
1314 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1315 return ERR_PTR(-ENOSYS);
1317 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
1319 return ERR_PTR(-ENOMEM);
1321 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
1325 xrcd->pd = ib_alloc_pd(ibdev, 0);
1326 if (IS_ERR(xrcd->pd)) {
1327 err = PTR_ERR(xrcd->pd);
1332 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
1333 if (IS_ERR(xrcd->cq)) {
1334 err = PTR_ERR(xrcd->cq);
1338 return &xrcd->ibxrcd;
1341 ib_dealloc_pd(xrcd->pd);
1343 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
1346 return ERR_PTR(err);
1349 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
1351 ib_destroy_cq(to_mxrcd(xrcd)->cq);
1352 ib_dealloc_pd(to_mxrcd(xrcd)->pd);
1353 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
1359 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
1361 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1362 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1363 struct mlx4_ib_gid_entry *ge;
1365 ge = kzalloc(sizeof *ge, GFP_KERNEL);
1370 if (mlx4_ib_add_mc(mdev, mqp, gid)) {
1371 ge->port = mqp->port;
1375 mutex_lock(&mqp->mutex);
1376 list_add_tail(&ge->list, &mqp->gid_list);
1377 mutex_unlock(&mqp->mutex);
1382 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
1383 struct mlx4_ib_counters *ctr_table)
1385 struct counter_index *counter, *tmp_count;
1387 mutex_lock(&ctr_table->mutex);
1388 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
1390 if (counter->allocated)
1391 mlx4_counter_free(ibdev->dev, counter->index);
1392 list_del(&counter->list);
1395 mutex_unlock(&ctr_table->mutex);
1398 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
1401 struct net_device *ndev;
1407 spin_lock_bh(&mdev->iboe.lock);
1408 ndev = mdev->iboe.netdevs[mqp->port - 1];
1411 spin_unlock_bh(&mdev->iboe.lock);
1421 struct mlx4_ib_steering {
1422 struct list_head list;
1423 struct mlx4_flow_reg_id reg_id;
1427 #define LAST_ETH_FIELD vlan_tag
1428 #define LAST_IB_FIELD sl
1429 #define LAST_IPV4_FIELD dst_ip
1430 #define LAST_TCP_UDP_FIELD src_port
1432 /* Field is the last supported field */
1433 #define FIELDS_NOT_SUPPORTED(filter, field)\
1434 memchr_inv((void *)&filter.field +\
1435 sizeof(filter.field), 0,\
1437 offsetof(typeof(filter), field) -\
1438 sizeof(filter.field))
1440 static int parse_flow_attr(struct mlx4_dev *dev,
1442 union ib_flow_spec *ib_spec,
1443 struct _rule_hw *mlx4_spec)
1445 enum mlx4_net_trans_rule_id type;
1447 switch (ib_spec->type) {
1448 case IB_FLOW_SPEC_ETH:
1449 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1452 type = MLX4_NET_TRANS_RULE_ID_ETH;
1453 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
1455 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
1457 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
1458 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
1460 case IB_FLOW_SPEC_IB:
1461 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
1464 type = MLX4_NET_TRANS_RULE_ID_IB;
1465 mlx4_spec->ib.l3_qpn =
1466 cpu_to_be32(qp_num);
1467 mlx4_spec->ib.qpn_mask =
1468 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
1472 case IB_FLOW_SPEC_IPV4:
1473 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1476 type = MLX4_NET_TRANS_RULE_ID_IPV4;
1477 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
1478 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
1479 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
1480 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
1483 case IB_FLOW_SPEC_TCP:
1484 case IB_FLOW_SPEC_UDP:
1485 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
1488 type = ib_spec->type == IB_FLOW_SPEC_TCP ?
1489 MLX4_NET_TRANS_RULE_ID_TCP :
1490 MLX4_NET_TRANS_RULE_ID_UDP;
1491 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
1492 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
1493 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
1494 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
1500 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
1501 mlx4_hw_rule_sz(dev, type) < 0)
1503 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
1504 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
1505 return mlx4_hw_rule_sz(dev, type);
1508 struct default_rules {
1509 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1510 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1511 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
1514 static const struct default_rules default_table[] = {
1516 .mandatory_fields = {IB_FLOW_SPEC_IPV4},
1517 .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
1518 .rules_create_list = {IB_FLOW_SPEC_IB},
1519 .link_layer = IB_LINK_LAYER_INFINIBAND
1523 static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
1524 struct ib_flow_attr *flow_attr)
1528 const struct default_rules *pdefault_rules = default_table;
1529 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
1531 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
1532 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
1533 memset(&field_types, 0, sizeof(field_types));
1535 if (link_layer != pdefault_rules->link_layer)
1538 ib_flow = flow_attr + 1;
1539 /* we assume the specs are sorted */
1540 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
1541 j < flow_attr->num_of_specs; k++) {
1542 union ib_flow_spec *current_flow =
1543 (union ib_flow_spec *)ib_flow;
1545 /* same layer but different type */
1546 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
1547 (pdefault_rules->mandatory_fields[k] &
1548 IB_FLOW_SPEC_LAYER_MASK)) &&
1549 (current_flow->type !=
1550 pdefault_rules->mandatory_fields[k]))
1553 /* same layer, try match next one */
1554 if (current_flow->type ==
1555 pdefault_rules->mandatory_fields[k]) {
1558 ((union ib_flow_spec *)ib_flow)->size;
1562 ib_flow = flow_attr + 1;
1563 for (j = 0; j < flow_attr->num_of_specs;
1564 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
1565 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
1566 /* same layer and same type */
1567 if (((union ib_flow_spec *)ib_flow)->type ==
1568 pdefault_rules->mandatory_not_fields[k])
1577 static int __mlx4_ib_create_default_rules(
1578 struct mlx4_ib_dev *mdev,
1580 const struct default_rules *pdefault_rules,
1581 struct _rule_hw *mlx4_spec) {
1585 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
1587 union ib_flow_spec ib_spec;
1588 switch (pdefault_rules->rules_create_list[i]) {
1592 case IB_FLOW_SPEC_IB:
1593 ib_spec.type = IB_FLOW_SPEC_IB;
1594 ib_spec.size = sizeof(struct ib_flow_spec_ib);
1601 /* We must put empty rule, qpn is being ignored */
1602 ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
1605 pr_info("invalid parsing\n");
1609 mlx4_spec = (void *)mlx4_spec + ret;
1615 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1617 enum mlx4_net_trans_promisc_mode flow_type,
1623 struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1624 struct mlx4_cmd_mailbox *mailbox;
1625 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
1628 static const u16 __mlx4_domain[] = {
1629 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
1630 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
1631 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
1632 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
1635 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1636 pr_err("Invalid priority value %d\n", flow_attr->priority);
1640 if (domain >= IB_FLOW_DOMAIN_NUM) {
1641 pr_err("Invalid domain value %d\n", domain);
1645 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1648 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1649 if (IS_ERR(mailbox))
1650 return PTR_ERR(mailbox);
1651 ctrl = mailbox->buf;
1653 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
1654 flow_attr->priority);
1655 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1656 ctrl->port = flow_attr->port;
1657 ctrl->qpn = cpu_to_be32(qp->qp_num);
1659 ib_flow = flow_attr + 1;
1660 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
1661 /* Add default flows */
1662 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1663 if (default_flow >= 0) {
1664 ret = __mlx4_ib_create_default_rules(
1665 mdev, qp, default_table + default_flow,
1666 mailbox->buf + size);
1668 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1673 for (i = 0; i < flow_attr->num_of_specs; i++) {
1674 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1675 mailbox->buf + size);
1677 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1680 ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1684 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1685 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
1688 pr_err("mcg table is full. Fail to register network rule.\n");
1689 else if (ret == -ENXIO)
1690 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1692 pr_err("Invalid argument. Fail to register network rule.\n");
1694 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1698 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1701 err = mlx4_cmd(dev, reg_id, 0, 0,
1702 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1705 pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1710 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1714 union ib_flow_spec *ib_spec;
1715 struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1718 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
1719 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
1720 return 0; /* do nothing */
1722 ib_flow = flow_attr + 1;
1723 ib_spec = (union ib_flow_spec *)ib_flow;
1725 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1726 return 0; /* do nothing */
1728 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1729 flow_attr->port, qp->qp_num,
1730 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1735 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
1736 struct ib_flow_attr *flow_attr,
1737 enum mlx4_net_trans_promisc_mode *type)
1741 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
1742 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
1743 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
1747 if (flow_attr->num_of_specs == 0) {
1748 type[0] = MLX4_FS_MC_SNIFFER;
1749 type[1] = MLX4_FS_UC_SNIFFER;
1751 union ib_flow_spec *ib_spec;
1753 ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1754 if (ib_spec->type != IB_FLOW_SPEC_ETH)
1757 /* if all is zero than MC and UC */
1758 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
1759 type[0] = MLX4_FS_MC_SNIFFER;
1760 type[1] = MLX4_FS_UC_SNIFFER;
1762 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
1763 ib_spec->eth.mask.dst_mac[1],
1764 ib_spec->eth.mask.dst_mac[2],
1765 ib_spec->eth.mask.dst_mac[3],
1766 ib_spec->eth.mask.dst_mac[4],
1767 ib_spec->eth.mask.dst_mac[5]};
1769 /* Above xor was only on MC bit, non empty mask is valid
1770 * only if this bit is set and rest are zero.
1772 if (!is_zero_ether_addr(&mac[0]))
1775 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
1776 type[0] = MLX4_FS_MC_SNIFFER;
1778 type[0] = MLX4_FS_UC_SNIFFER;
1785 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1786 struct ib_flow_attr *flow_attr,
1789 int err = 0, i = 0, j = 0;
1790 struct mlx4_ib_flow *mflow;
1791 enum mlx4_net_trans_promisc_mode type[2];
1792 struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1793 int is_bonded = mlx4_is_bonded(dev);
1795 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
1796 return ERR_PTR(-EINVAL);
1798 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
1799 (flow_attr->type != IB_FLOW_ATTR_NORMAL))
1800 return ERR_PTR(-EOPNOTSUPP);
1802 memset(type, 0, sizeof(type));
1804 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1810 switch (flow_attr->type) {
1811 case IB_FLOW_ATTR_NORMAL:
1812 /* If dont trap flag (continue match) is set, under specific
1813 * condition traffic be replicated to given qp,
1814 * without stealing it
1816 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
1817 err = mlx4_ib_add_dont_trap_rule(dev,
1823 type[0] = MLX4_FS_REGULAR;
1827 case IB_FLOW_ATTR_ALL_DEFAULT:
1828 type[0] = MLX4_FS_ALL_DEFAULT;
1831 case IB_FLOW_ATTR_MC_DEFAULT:
1832 type[0] = MLX4_FS_MC_DEFAULT;
1835 case IB_FLOW_ATTR_SNIFFER:
1836 type[0] = MLX4_FS_MIRROR_RX_PORT;
1837 type[1] = MLX4_FS_MIRROR_SX_PORT;
1845 while (i < ARRAY_SIZE(type) && type[i]) {
1846 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
1847 &mflow->reg_id[i].id);
1849 goto err_create_flow;
1851 /* Application always sees one port so the mirror rule
1852 * must be on port #2
1854 flow_attr->port = 2;
1855 err = __mlx4_ib_create_flow(qp, flow_attr,
1857 &mflow->reg_id[j].mirror);
1858 flow_attr->port = 1;
1860 goto err_create_flow;
1867 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1868 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1869 &mflow->reg_id[i].id);
1871 goto err_create_flow;
1874 flow_attr->port = 2;
1875 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1876 &mflow->reg_id[j].mirror);
1877 flow_attr->port = 1;
1879 goto err_create_flow;
1882 /* function to create mirror rule */
1886 return &mflow->ibflow;
1890 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1891 mflow->reg_id[i].id);
1896 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1897 mflow->reg_id[j].mirror);
1902 return ERR_PTR(err);
1905 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1909 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1910 struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1912 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
1913 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
1916 if (mflow->reg_id[i].mirror) {
1917 err = __mlx4_ib_destroy_flow(mdev->dev,
1918 mflow->reg_id[i].mirror);
1929 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1932 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1933 struct mlx4_dev *dev = mdev->dev;
1934 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1935 struct mlx4_ib_steering *ib_steering = NULL;
1936 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
1937 struct mlx4_flow_reg_id reg_id;
1939 if (mdev->dev->caps.steering_mode ==
1940 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1941 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
1946 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
1948 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1951 pr_err("multicast attach op failed, err %d\n", err);
1956 if (mlx4_is_bonded(dev)) {
1957 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
1958 (mqp->port == 1) ? 2 : 1,
1960 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1961 prot, ®_id.mirror);
1966 err = add_gid_entry(ibqp, gid);
1971 memcpy(ib_steering->gid.raw, gid->raw, 16);
1972 ib_steering->reg_id = reg_id;
1973 mutex_lock(&mqp->mutex);
1974 list_add(&ib_steering->list, &mqp->steering_rules);
1975 mutex_unlock(&mqp->mutex);
1980 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1983 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1984 prot, reg_id.mirror);
1991 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
1993 struct mlx4_ib_gid_entry *ge;
1994 struct mlx4_ib_gid_entry *tmp;
1995 struct mlx4_ib_gid_entry *ret = NULL;
1997 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1998 if (!memcmp(raw, ge->gid.raw, 16)) {
2007 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2010 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2011 struct mlx4_dev *dev = mdev->dev;
2012 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2013 struct net_device *ndev;
2014 struct mlx4_ib_gid_entry *ge;
2015 struct mlx4_flow_reg_id reg_id = {0, 0};
2016 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
2018 if (mdev->dev->caps.steering_mode ==
2019 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2020 struct mlx4_ib_steering *ib_steering;
2022 mutex_lock(&mqp->mutex);
2023 list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
2024 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
2025 list_del(&ib_steering->list);
2029 mutex_unlock(&mqp->mutex);
2030 if (&ib_steering->list == &mqp->steering_rules) {
2031 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
2034 reg_id = ib_steering->reg_id;
2038 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2043 if (mlx4_is_bonded(dev)) {
2044 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2045 prot, reg_id.mirror);
2050 mutex_lock(&mqp->mutex);
2051 ge = find_gid_entry(mqp, gid->raw);
2053 spin_lock_bh(&mdev->iboe.lock);
2054 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
2057 spin_unlock_bh(&mdev->iboe.lock);
2060 list_del(&ge->list);
2063 pr_warn("could not find mgid entry\n");
2065 mutex_unlock(&mqp->mutex);
2070 static int init_node_data(struct mlx4_ib_dev *dev)
2072 struct ib_smp *in_mad = NULL;
2073 struct ib_smp *out_mad = NULL;
2074 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
2077 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
2078 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
2079 if (!in_mad || !out_mad)
2082 init_query_mad(in_mad);
2083 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
2084 if (mlx4_is_master(dev->dev))
2085 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
2087 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2091 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
2093 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
2095 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2099 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
2100 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
2108 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2111 struct mlx4_ib_dev *dev =
2112 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2113 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
2116 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2119 struct mlx4_ib_dev *dev =
2120 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2121 return sprintf(buf, "%x\n", dev->dev->rev_id);
2124 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2127 struct mlx4_ib_dev *dev =
2128 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2129 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
2130 dev->dev->board_id);
2133 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2134 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2135 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2137 static struct device_attribute *mlx4_class_attributes[] = {
2143 struct diag_counter {
2148 #define DIAG_COUNTER(_name, _offset) \
2149 { .name = #_name, .offset = _offset }
2151 static const struct diag_counter diag_basic[] = {
2152 DIAG_COUNTER(rq_num_lle, 0x00),
2153 DIAG_COUNTER(sq_num_lle, 0x04),
2154 DIAG_COUNTER(rq_num_lqpoe, 0x08),
2155 DIAG_COUNTER(sq_num_lqpoe, 0x0C),
2156 DIAG_COUNTER(rq_num_lpe, 0x18),
2157 DIAG_COUNTER(sq_num_lpe, 0x1C),
2158 DIAG_COUNTER(rq_num_wrfe, 0x20),
2159 DIAG_COUNTER(sq_num_wrfe, 0x24),
2160 DIAG_COUNTER(sq_num_mwbe, 0x2C),
2161 DIAG_COUNTER(sq_num_bre, 0x34),
2162 DIAG_COUNTER(sq_num_rire, 0x44),
2163 DIAG_COUNTER(rq_num_rire, 0x48),
2164 DIAG_COUNTER(sq_num_rae, 0x4C),
2165 DIAG_COUNTER(rq_num_rae, 0x50),
2166 DIAG_COUNTER(sq_num_roe, 0x54),
2167 DIAG_COUNTER(sq_num_tree, 0x5C),
2168 DIAG_COUNTER(sq_num_rree, 0x64),
2169 DIAG_COUNTER(rq_num_rnr, 0x68),
2170 DIAG_COUNTER(sq_num_rnr, 0x6C),
2171 DIAG_COUNTER(rq_num_oos, 0x100),
2172 DIAG_COUNTER(sq_num_oos, 0x104),
2175 static const struct diag_counter diag_ext[] = {
2176 DIAG_COUNTER(rq_num_dup, 0x130),
2177 DIAG_COUNTER(sq_num_to, 0x134),
2180 static const struct diag_counter diag_device_only[] = {
2181 DIAG_COUNTER(num_cqovf, 0x1A0),
2182 DIAG_COUNTER(rq_num_udsdprd, 0x118),
2185 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
2188 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2189 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2191 if (!diag[!!port_num].name)
2194 return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
2195 diag[!!port_num].num_counters,
2196 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2199 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
2200 struct rdma_hw_stats *stats,
2203 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2204 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2205 u32 hw_value[ARRAY_SIZE(diag_device_only) +
2206 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
2210 ret = mlx4_query_diag_counters(dev->dev,
2211 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
2212 diag[!!port].offset, hw_value,
2213 diag[!!port].num_counters, port);
2218 for (i = 0; i < diag[!!port].num_counters; i++)
2219 stats->value[i] = hw_value[i];
2221 return diag[!!port].num_counters;
2224 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
2232 num_counters = ARRAY_SIZE(diag_basic);
2234 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
2235 num_counters += ARRAY_SIZE(diag_ext);
2238 num_counters += ARRAY_SIZE(diag_device_only);
2240 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
2244 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
2248 *num = num_counters;
2257 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
2265 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
2266 name[i] = diag_basic[i].name;
2267 offset[i] = diag_basic[i].offset;
2270 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
2271 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
2272 name[j] = diag_ext[i].name;
2273 offset[j] = diag_ext[i].offset;
2278 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
2279 name[j] = diag_device_only[i].name;
2280 offset[j] = diag_device_only[i].offset;
2285 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
2287 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
2290 bool per_port = !!(ibdev->dev->caps.flags2 &
2291 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
2293 if (mlx4_is_slave(ibdev->dev))
2296 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2297 /* i == 1 means we are building port counters */
2301 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
2303 &diag[i].num_counters, i);
2307 mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
2311 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats;
2312 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats;
2318 kfree(diag[i - 1].name);
2319 kfree(diag[i - 1].offset);
2325 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
2329 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2330 kfree(ibdev->diag_counters[i].offset);
2331 kfree(ibdev->diag_counters[i].name);
2335 #define MLX4_IB_INVALID_MAC ((u64)-1)
2336 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
2337 struct net_device *dev,
2341 u64 release_mac = MLX4_IB_INVALID_MAC;
2342 struct mlx4_ib_qp *qp;
2344 read_lock(&dev_base_lock);
2345 new_smac = mlx4_mac_to_u64(dev->dev_addr);
2346 read_unlock(&dev_base_lock);
2348 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
2350 /* no need for update QP1 and mac registration in non-SRIOV */
2351 if (!mlx4_is_mfunc(ibdev->dev))
2354 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
2355 qp = ibdev->qp1_proxy[port - 1];
2359 struct mlx4_update_qp_params update_params;
2361 mutex_lock(&qp->mutex);
2362 old_smac = qp->pri.smac;
2363 if (new_smac == old_smac)
2366 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
2368 if (new_smac_index < 0)
2371 update_params.smac_index = new_smac_index;
2372 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
2374 release_mac = new_smac;
2377 /* if old port was zero, no mac was yet registered for this QP */
2378 if (qp->pri.smac_port)
2379 release_mac = old_smac;
2380 qp->pri.smac = new_smac;
2381 qp->pri.smac_port = port;
2382 qp->pri.smac_index = new_smac_index;
2386 if (release_mac != MLX4_IB_INVALID_MAC)
2387 mlx4_unregister_mac(ibdev->dev, port, release_mac);
2389 mutex_unlock(&qp->mutex);
2390 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
2393 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
2394 struct net_device *dev,
2395 unsigned long event)
2398 struct mlx4_ib_iboe *iboe;
2399 int update_qps_port = -1;
2404 iboe = &ibdev->iboe;
2406 spin_lock_bh(&iboe->lock);
2407 mlx4_foreach_ib_transport_port(port, ibdev->dev) {
2409 iboe->netdevs[port - 1] =
2410 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
2412 if (dev == iboe->netdevs[port - 1] &&
2413 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
2414 event == NETDEV_UP || event == NETDEV_CHANGE))
2415 update_qps_port = port;
2418 spin_unlock_bh(&iboe->lock);
2420 if (update_qps_port > 0)
2421 mlx4_ib_update_qps(ibdev, dev, update_qps_port);
2424 static int mlx4_ib_netdev_event(struct notifier_block *this,
2425 unsigned long event, void *ptr)
2427 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2428 struct mlx4_ib_dev *ibdev;
2430 if (!net_eq(dev_net(dev), &init_net))
2433 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
2434 mlx4_ib_scan_netdevs(ibdev, dev, event);
2439 static void init_pkeys(struct mlx4_ib_dev *ibdev)
2445 if (mlx4_is_master(ibdev->dev)) {
2446 for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
2448 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2450 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2452 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
2453 /* master has the identity virt2phys pkey mapping */
2454 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
2455 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
2456 mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
2457 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
2461 /* initialize pkey cache */
2462 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2464 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2466 ibdev->pkeys.phys_pkey_cache[port-1][i] =
2472 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2474 int i, j, eq = 0, total_eqs = 0;
2476 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
2477 sizeof(ibdev->eq_table[0]), GFP_KERNEL);
2478 if (!ibdev->eq_table)
2481 for (i = 1; i <= dev->caps.num_ports; i++) {
2482 for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
2484 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
2486 ibdev->eq_table[eq] = total_eqs;
2487 if (!mlx4_assign_eq(dev, i,
2488 &ibdev->eq_table[eq]))
2491 ibdev->eq_table[eq] = -1;
2495 for (i = eq; i < dev->caps.num_comp_vectors;
2496 ibdev->eq_table[i++] = -1)
2499 /* Advertise the new number of EQs to clients */
2500 ibdev->ib_dev.num_comp_vectors = eq;
2503 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2506 int total_eqs = ibdev->ib_dev.num_comp_vectors;
2508 /* no eqs were allocated */
2509 if (!ibdev->eq_table)
2512 /* Reset the advertised EQ number */
2513 ibdev->ib_dev.num_comp_vectors = 0;
2515 for (i = 0; i < total_eqs; i++)
2516 mlx4_release_eq(dev, ibdev->eq_table[i]);
2518 kfree(ibdev->eq_table);
2519 ibdev->eq_table = NULL;
2522 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
2523 struct ib_port_immutable *immutable)
2525 struct ib_port_attr attr;
2526 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
2529 err = mlx4_ib_query_port(ibdev, port_num, &attr);
2533 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2534 immutable->gid_tbl_len = attr.gid_tbl_len;
2536 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
2537 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
2539 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
2540 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
2541 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
2542 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
2543 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2546 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2551 static void get_fw_ver_str(struct ib_device *device, char *str,
2554 struct mlx4_ib_dev *dev =
2555 container_of(device, struct mlx4_ib_dev, ib_dev);
2556 snprintf(str, str_len, "%d.%d.%d",
2557 (int) (dev->dev->caps.fw_ver >> 32),
2558 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
2559 (int) dev->dev->caps.fw_ver & 0xffff);
2562 static void *mlx4_ib_add(struct mlx4_dev *dev)
2564 struct mlx4_ib_dev *ibdev;
2568 struct mlx4_ib_iboe *iboe;
2569 int ib_num_ports = 0;
2570 int num_req_counters;
2573 struct counter_index *new_counter_index = NULL;
2575 pr_info_once("%s", mlx4_ib_version);
2578 mlx4_foreach_ib_transport_port(i, dev)
2581 /* No point in registering a device with no ports... */
2585 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
2587 dev_err(&dev->persist->pdev->dev,
2588 "Device struct alloc failed\n");
2592 iboe = &ibdev->iboe;
2594 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2597 if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2600 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2602 if (!ibdev->uar_map)
2604 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
2607 ibdev->bond_next_port = 0;
2609 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
2610 ibdev->ib_dev.owner = THIS_MODULE;
2611 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
2612 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
2613 ibdev->num_ports = num_ports;
2614 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
2615 1 : ibdev->num_ports;
2616 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
2617 ibdev->ib_dev.dma_device = &dev->persist->pdev->dev;
2618 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
2619 ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
2620 ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
2622 if (dev->caps.userspace_caps)
2623 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
2625 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2627 ibdev->ib_dev.uverbs_cmd_mask =
2628 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2629 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2630 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2631 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2632 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2633 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2634 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2635 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2636 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2637 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2638 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2639 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2640 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2641 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2642 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2643 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2644 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2645 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2646 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2647 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2648 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2649 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2650 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2651 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2653 ibdev->ib_dev.query_device = mlx4_ib_query_device;
2654 ibdev->ib_dev.query_port = mlx4_ib_query_port;
2655 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
2656 ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
2657 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
2658 ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
2659 ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
2660 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
2661 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
2662 ibdev->ib_dev.mmap = mlx4_ib_mmap;
2663 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
2664 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
2665 ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
2666 ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
2667 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
2668 ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
2669 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
2670 ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
2671 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
2672 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
2673 ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
2674 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
2675 ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
2676 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
2677 ibdev->ib_dev.post_send = mlx4_ib_post_send;
2678 ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
2679 ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
2680 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
2681 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
2682 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
2683 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
2684 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
2685 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
2686 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
2687 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
2688 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
2689 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
2690 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
2691 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
2692 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
2693 ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
2694 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
2695 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str;
2696 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
2698 if (!mlx4_is_slave(ibdev->dev)) {
2699 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
2700 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
2701 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
2702 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
2705 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2706 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2707 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
2708 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
2710 ibdev->ib_dev.uverbs_cmd_mask |=
2711 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2712 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2715 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2716 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
2717 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
2718 ibdev->ib_dev.uverbs_cmd_mask |=
2719 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2720 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2723 if (check_flow_steering_support(dev)) {
2724 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
2725 ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
2726 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
2728 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2729 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2730 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2733 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2734 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2735 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2736 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2738 mlx4_ib_alloc_eqs(dev, ibdev);
2740 spin_lock_init(&iboe->lock);
2742 if (init_node_data(ibdev))
2744 mlx4_init_sl2vl_tbl(ibdev);
2746 for (i = 0; i < ibdev->num_ports; ++i) {
2747 mutex_init(&ibdev->counters_table[i].mutex);
2748 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
2751 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
2752 for (i = 0; i < num_req_counters; ++i) {
2753 mutex_init(&ibdev->qp1_proxy_lock[i]);
2755 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2756 IB_LINK_LAYER_ETHERNET) {
2757 err = mlx4_counter_alloc(ibdev->dev, &counter_index);
2758 /* if failed to allocate a new counter, use default */
2761 mlx4_get_default_counter_index(dev,
2765 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
2766 counter_index = mlx4_get_default_counter_index(dev,
2769 new_counter_index = kmalloc(sizeof(*new_counter_index),
2771 if (!new_counter_index) {
2773 mlx4_counter_free(ibdev->dev, counter_index);
2776 new_counter_index->index = counter_index;
2777 new_counter_index->allocated = allocated;
2778 list_add_tail(&new_counter_index->list,
2779 &ibdev->counters_table[i].counters_list);
2780 ibdev->counters_table[i].default_counter = counter_index;
2781 pr_info("counter index %d for port %d allocated %d\n",
2782 counter_index, i + 1, allocated);
2784 if (mlx4_is_bonded(dev))
2785 for (i = 1; i < ibdev->num_ports ; ++i) {
2787 kmalloc(sizeof(struct counter_index),
2789 if (!new_counter_index)
2791 new_counter_index->index = counter_index;
2792 new_counter_index->allocated = 0;
2793 list_add_tail(&new_counter_index->list,
2794 &ibdev->counters_table[i].counters_list);
2795 ibdev->counters_table[i].default_counter =
2799 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2802 spin_lock_init(&ibdev->sm_lock);
2803 mutex_init(&ibdev->cap_mask_mutex);
2804 INIT_LIST_HEAD(&ibdev->qp_list);
2805 spin_lock_init(&ibdev->reset_flow_resource_lock);
2807 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2809 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2810 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2811 MLX4_IB_UC_STEER_QPN_ALIGN,
2812 &ibdev->steer_qpn_base, 0);
2816 ibdev->ib_uc_qpns_bitmap =
2817 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
2820 if (!ibdev->ib_uc_qpns_bitmap) {
2821 dev_err(&dev->persist->pdev->dev,
2822 "bit map alloc failed\n");
2823 goto err_steer_qp_release;
2826 bitmap_zero(ibdev->ib_uc_qpns_bitmap, ibdev->steer_qpn_count);
2828 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2829 dev, ibdev->steer_qpn_base,
2830 ibdev->steer_qpn_base +
2831 ibdev->steer_qpn_count - 1);
2833 goto err_steer_free_bitmap;
2836 for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
2837 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
2839 if (mlx4_ib_alloc_diag_counters(ibdev))
2840 goto err_steer_free_bitmap;
2842 if (ib_register_device(&ibdev->ib_dev, NULL))
2843 goto err_diag_counters;
2845 if (mlx4_ib_mad_init(ibdev))
2848 if (mlx4_ib_init_sriov(ibdev))
2851 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE ||
2852 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2853 if (!iboe->nb.notifier_call) {
2854 iboe->nb.notifier_call = mlx4_ib_netdev_event;
2855 err = register_netdevice_notifier(&iboe->nb);
2857 iboe->nb.notifier_call = NULL;
2861 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2862 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
2869 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
2870 if (device_create_file(&ibdev->ib_dev.dev,
2871 mlx4_class_attributes[j]))
2875 ibdev->ib_active = true;
2876 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2877 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
2880 if (mlx4_is_mfunc(ibdev->dev))
2883 /* create paravirt contexts for any VFs which are active */
2884 if (mlx4_is_master(ibdev->dev)) {
2885 for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2886 if (j == mlx4_master_func_num(ibdev->dev))
2888 if (mlx4_is_slave_active(ibdev->dev, j))
2889 do_slave_init(ibdev, j, 1);
2895 if (ibdev->iboe.nb.notifier_call) {
2896 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2897 pr_warn("failure unregistering notifier\n");
2898 ibdev->iboe.nb.notifier_call = NULL;
2900 flush_workqueue(wq);
2902 mlx4_ib_close_sriov(ibdev);
2905 mlx4_ib_mad_cleanup(ibdev);
2908 ib_unregister_device(&ibdev->ib_dev);
2911 mlx4_ib_diag_cleanup(ibdev);
2913 err_steer_free_bitmap:
2914 kfree(ibdev->ib_uc_qpns_bitmap);
2916 err_steer_qp_release:
2917 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
2918 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2919 ibdev->steer_qpn_count);
2921 for (i = 0; i < ibdev->num_ports; ++i)
2922 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
2925 iounmap(ibdev->uar_map);
2928 mlx4_uar_free(dev, &ibdev->priv_uar);
2931 mlx4_pd_free(dev, ibdev->priv_pdn);
2934 ib_dealloc_device(&ibdev->ib_dev);
2939 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
2943 WARN_ON(!dev->ib_uc_qpns_bitmap);
2945 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
2946 dev->steer_qpn_count,
2947 get_count_order(count));
2951 *qpn = dev->steer_qpn_base + offset;
2955 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
2958 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
2961 BUG_ON(qpn < dev->steer_qpn_base);
2963 bitmap_release_region(dev->ib_uc_qpns_bitmap,
2964 qpn - dev->steer_qpn_base,
2965 get_count_order(count));
2968 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
2973 struct ib_flow_attr *flow = NULL;
2974 struct ib_flow_spec_ib *ib_spec;
2977 flow_size = sizeof(struct ib_flow_attr) +
2978 sizeof(struct ib_flow_spec_ib);
2979 flow = kzalloc(flow_size, GFP_KERNEL);
2982 flow->port = mqp->port;
2983 flow->num_of_specs = 1;
2984 flow->size = flow_size;
2985 ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
2986 ib_spec->type = IB_FLOW_SPEC_IB;
2987 ib_spec->size = sizeof(struct ib_flow_spec_ib);
2988 /* Add an empty rule for IB L2 */
2989 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
2991 err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
2996 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
3002 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
3004 struct mlx4_ib_dev *ibdev = ibdev_ptr;
3008 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
3009 devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
3010 ibdev->ib_active = false;
3011 flush_workqueue(wq);
3013 mlx4_ib_close_sriov(ibdev);
3014 mlx4_ib_mad_cleanup(ibdev);
3015 ib_unregister_device(&ibdev->ib_dev);
3016 mlx4_ib_diag_cleanup(ibdev);
3017 if (ibdev->iboe.nb.notifier_call) {
3018 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
3019 pr_warn("failure unregistering notifier\n");
3020 ibdev->iboe.nb.notifier_call = NULL;
3023 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) {
3024 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
3025 ibdev->steer_qpn_count);
3026 kfree(ibdev->ib_uc_qpns_bitmap);
3029 iounmap(ibdev->uar_map);
3030 for (p = 0; p < ibdev->num_ports; ++p)
3031 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
3033 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
3034 mlx4_CLOSE_PORT(dev, p);
3036 mlx4_ib_free_eqs(dev, ibdev);
3038 mlx4_uar_free(dev, &ibdev->priv_uar);
3039 mlx4_pd_free(dev, ibdev->priv_pdn);
3040 ib_dealloc_device(&ibdev->ib_dev);
3043 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
3045 struct mlx4_ib_demux_work **dm = NULL;
3046 struct mlx4_dev *dev = ibdev->dev;
3048 unsigned long flags;
3049 struct mlx4_active_ports actv_ports;
3051 unsigned int first_port;
3053 if (!mlx4_is_master(dev))
3056 actv_ports = mlx4_get_active_ports(dev, slave);
3057 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
3058 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
3060 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
3062 pr_err("failed to allocate memory for tunneling qp update\n");
3066 for (i = 0; i < ports; i++) {
3067 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
3069 pr_err("failed to allocate memory for tunneling qp update work struct\n");
3074 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
3075 dm[i]->port = first_port + i + 1;
3076 dm[i]->slave = slave;
3077 dm[i]->do_init = do_init;
3080 /* initialize or tear down tunnel QPs for the slave */
3081 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
3082 if (!ibdev->sriov.is_going_down) {
3083 for (i = 0; i < ports; i++)
3084 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
3085 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3087 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3088 for (i = 0; i < ports; i++)
3096 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
3098 struct mlx4_ib_qp *mqp;
3099 unsigned long flags_qp;
3100 unsigned long flags_cq;
3101 struct mlx4_ib_cq *send_mcq, *recv_mcq;
3102 struct list_head cq_notify_list;
3103 struct mlx4_cq *mcq;
3104 unsigned long flags;
3106 pr_warn("mlx4_ib_handle_catas_error was started\n");
3107 INIT_LIST_HEAD(&cq_notify_list);
3109 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3110 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3112 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3113 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3114 if (mqp->sq.tail != mqp->sq.head) {
3115 send_mcq = to_mcq(mqp->ibqp.send_cq);
3116 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3117 if (send_mcq->mcq.comp &&
3118 mqp->ibqp.send_cq->comp_handler) {
3119 if (!send_mcq->mcq.reset_notify_added) {
3120 send_mcq->mcq.reset_notify_added = 1;
3121 list_add_tail(&send_mcq->mcq.reset_notify,
3125 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3127 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3128 /* Now, handle the QP's receive queue */
3129 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3130 /* no handling is needed for SRQ */
3131 if (!mqp->ibqp.srq) {
3132 if (mqp->rq.tail != mqp->rq.head) {
3133 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3134 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3135 if (recv_mcq->mcq.comp &&
3136 mqp->ibqp.recv_cq->comp_handler) {
3137 if (!recv_mcq->mcq.reset_notify_added) {
3138 recv_mcq->mcq.reset_notify_added = 1;
3139 list_add_tail(&recv_mcq->mcq.reset_notify,
3143 spin_unlock_irqrestore(&recv_mcq->lock,
3147 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3150 list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
3153 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3154 pr_warn("mlx4_ib_handle_catas_error ended\n");
3157 static void handle_bonded_port_state_event(struct work_struct *work)
3159 struct ib_event_work *ew =
3160 container_of(work, struct ib_event_work, work);
3161 struct mlx4_ib_dev *ibdev = ew->ib_dev;
3162 enum ib_port_state bonded_port_state = IB_PORT_NOP;
3164 struct ib_event ibev;
3167 spin_lock_bh(&ibdev->iboe.lock);
3168 for (i = 0; i < MLX4_MAX_PORTS; ++i) {
3169 struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
3170 enum ib_port_state curr_port_state;
3176 (netif_running(curr_netdev) &&
3177 netif_carrier_ok(curr_netdev)) ?
3178 IB_PORT_ACTIVE : IB_PORT_DOWN;
3180 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
3181 curr_port_state : IB_PORT_ACTIVE;
3183 spin_unlock_bh(&ibdev->iboe.lock);
3185 ibev.device = &ibdev->ib_dev;
3186 ibev.element.port_num = 1;
3187 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
3188 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3190 ib_dispatch_event(&ibev);
3193 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
3198 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
3200 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
3204 atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
3207 static void ib_sl2vl_update_work(struct work_struct *work)
3209 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
3210 struct mlx4_ib_dev *mdev = ew->ib_dev;
3211 int port = ew->port;
3213 mlx4_ib_sl2vl_update(mdev, port);
3218 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
3221 struct ib_event_work *ew;
3223 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3225 INIT_WORK(&ew->work, ib_sl2vl_update_work);
3228 queue_work(wq, &ew->work);
3230 pr_err("failed to allocate memory for sl2vl update work\n");
3234 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
3235 enum mlx4_dev_event event, unsigned long param)
3237 struct ib_event ibev;
3238 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
3239 struct mlx4_eqe *eqe = NULL;
3240 struct ib_event_work *ew;
3243 if (mlx4_is_bonded(dev) &&
3244 ((event == MLX4_DEV_EVENT_PORT_UP) ||
3245 (event == MLX4_DEV_EVENT_PORT_DOWN))) {
3246 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3249 INIT_WORK(&ew->work, handle_bonded_port_state_event);
3251 queue_work(wq, &ew->work);
3255 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
3256 eqe = (struct mlx4_eqe *)param;
3261 case MLX4_DEV_EVENT_PORT_UP:
3262 if (p > ibdev->num_ports)
3264 if (!mlx4_is_slave(dev) &&
3265 rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
3266 IB_LINK_LAYER_INFINIBAND) {
3267 if (mlx4_is_master(dev))
3268 mlx4_ib_invalidate_all_guid_record(ibdev, p);
3269 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
3270 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
3271 mlx4_sched_ib_sl2vl_update_work(ibdev, p);
3273 ibev.event = IB_EVENT_PORT_ACTIVE;
3276 case MLX4_DEV_EVENT_PORT_DOWN:
3277 if (p > ibdev->num_ports)
3279 ibev.event = IB_EVENT_PORT_ERR;
3282 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3283 ibdev->ib_active = false;
3284 ibev.event = IB_EVENT_DEVICE_FATAL;
3285 mlx4_ib_handle_catas_error(ibdev);
3288 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
3289 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
3291 pr_err("failed to allocate memory for events work\n");
3295 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
3296 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
3298 /* need to queue only for port owner, which uses GEN_EQE */
3299 if (mlx4_is_master(dev))
3300 queue_work(wq, &ew->work);
3302 handle_port_mgmt_change_event(&ew->work);
3305 case MLX4_DEV_EVENT_SLAVE_INIT:
3306 /* here, p is the slave id */
3307 do_slave_init(ibdev, p, 1);
3308 if (mlx4_is_master(dev)) {
3311 for (i = 1; i <= ibdev->num_ports; i++) {
3312 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3313 == IB_LINK_LAYER_INFINIBAND)
3314 mlx4_ib_slave_alias_guid_event(ibdev,
3321 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
3322 if (mlx4_is_master(dev)) {
3325 for (i = 1; i <= ibdev->num_ports; i++) {
3326 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3327 == IB_LINK_LAYER_INFINIBAND)
3328 mlx4_ib_slave_alias_guid_event(ibdev,
3333 /* here, p is the slave id */
3334 do_slave_init(ibdev, p, 0);
3341 ibev.device = ibdev_ptr;
3342 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
3344 ib_dispatch_event(&ibev);
3347 static struct mlx4_interface mlx4_ib_interface = {
3349 .remove = mlx4_ib_remove,
3350 .event = mlx4_ib_event,
3351 .protocol = MLX4_PROT_IB_IPV6,
3352 .flags = MLX4_INTFF_BONDING
3355 static int __init mlx4_ib_init(void)
3359 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
3363 err = mlx4_ib_mcg_init();
3367 err = mlx4_register_interface(&mlx4_ib_interface);
3374 mlx4_ib_mcg_destroy();
3377 destroy_workqueue(wq);
3381 static void __exit mlx4_ib_cleanup(void)
3383 mlx4_unregister_interface(&mlx4_ib_interface);
3384 mlx4_ib_mcg_destroy();
3385 destroy_workqueue(wq);
3388 module_init(mlx4_ib_init);
3389 module_exit(mlx4_ib_cleanup);