2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/acpi.h>
34 #include <linux/of_platform.h>
35 #include <linux/module.h>
36 #include <rdma/ib_addr.h>
37 #include <rdma/ib_smi.h>
38 #include <rdma/ib_user_verbs.h>
39 #include <rdma/ib_cache.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include <rdma/hns-abi.h>
43 #include "hns_roce_hem.h"
46 * hns_get_gid_index - Get gid index.
47 * @hr_dev: pointer to structure hns_roce_dev.
48 * @port: port, value range: 0 ~ MAX
49 * @gid_index: gid_index, value range: 0 ~ MAX
51 * N ports shared gids, allocation method as follow:
52 * GID[0][0], GID[1][0],.....GID[N - 1][0],
53 * GID[0][0], GID[1][0],.....GID[N - 1][0],
56 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
58 return gid_index * hr_dev->caps.num_ports + port;
60 EXPORT_SYMBOL_GPL(hns_get_gid_index);
62 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
67 if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM))
70 for (i = 0; i < MAC_ADDR_OCTET_NUM; i++)
71 hr_dev->dev_addr[port][i] = addr[i];
73 phy_port = hr_dev->iboe.phy_port[port];
74 return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
77 static int hns_roce_add_gid(const union ib_gid *gid,
78 const struct ib_gid_attr *attr, void **context)
80 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
81 u8 port = attr->port_num - 1;
85 if (port >= hr_dev->caps.num_ports)
88 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
90 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index,
91 (union ib_gid *)gid, attr);
93 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
98 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
100 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
101 struct ib_gid_attr zattr = { };
102 union ib_gid zgid = { {0} };
103 u8 port = attr->port_num - 1;
107 if (port >= hr_dev->caps.num_ports)
110 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
112 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr);
114 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
119 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
122 struct device *dev = hr_dev->dev;
123 struct net_device *netdev;
126 netdev = hr_dev->iboe.netdevs[port];
128 dev_err(dev, "port(%d) can't find netdev\n", port);
135 case NETDEV_REGISTER:
136 case NETDEV_CHANGEADDR:
137 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
141 * In v1 engine, only support all ports closed together.
145 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
152 static int hns_roce_netdev_event(struct notifier_block *self,
153 unsigned long event, void *ptr)
155 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
156 struct hns_roce_ib_iboe *iboe = NULL;
157 struct hns_roce_dev *hr_dev = NULL;
161 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
162 iboe = &hr_dev->iboe;
164 for (port = 0; port < hr_dev->caps.num_ports; port++) {
165 if (dev == iboe->netdevs[port]) {
166 ret = handle_en_event(hr_dev, port, event);
176 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
181 for (i = 0; i < hr_dev->caps.num_ports; i++) {
182 if (hr_dev->hw->set_mtu)
183 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
184 hr_dev->caps.max_mtu);
185 ret = hns_roce_set_mac(hr_dev, i,
186 hr_dev->iboe.netdevs[i]->dev_addr);
194 static int hns_roce_query_device(struct ib_device *ib_dev,
195 struct ib_device_attr *props,
196 struct ib_udata *uhw)
198 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
200 memset(props, 0, sizeof(*props));
202 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
203 props->max_mr_size = (u64)(~(0ULL));
204 props->page_size_cap = hr_dev->caps.page_size_cap;
205 props->vendor_id = hr_dev->vendor_id;
206 props->vendor_part_id = hr_dev->vendor_part_id;
207 props->hw_ver = hr_dev->hw_rev;
208 props->max_qp = hr_dev->caps.num_qps;
209 props->max_qp_wr = hr_dev->caps.max_wqes;
210 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
211 IB_DEVICE_RC_RNR_NAK_GEN;
212 props->max_sge = max(hr_dev->caps.max_sq_sg, hr_dev->caps.max_rq_sg);
213 props->max_sge_rd = 1;
214 props->max_cq = hr_dev->caps.num_cqs;
215 props->max_cqe = hr_dev->caps.max_cqes;
216 props->max_mr = hr_dev->caps.num_mtpts;
217 props->max_pd = hr_dev->caps.num_pds;
218 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
219 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
220 props->atomic_cap = IB_ATOMIC_NONE;
221 props->max_pkeys = 1;
222 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
227 static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev,
230 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
231 struct net_device *ndev;
233 if (port_num < 1 || port_num > hr_dev->caps.num_ports)
238 ndev = hr_dev->iboe.netdevs[port_num - 1];
246 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
247 struct ib_port_attr *props)
249 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
250 struct device *dev = hr_dev->dev;
251 struct net_device *net_dev;
256 assert(port_num > 0);
259 /* props being zeroed by the caller, avoid zeroing it here */
261 props->max_mtu = hr_dev->caps.max_mtu;
262 props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
263 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
264 IB_PORT_VENDOR_CLASS_SUP |
265 IB_PORT_BOOT_MGMT_SUP;
266 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
267 props->pkey_tbl_len = 1;
268 props->active_width = IB_WIDTH_4X;
269 props->active_speed = 1;
271 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
273 net_dev = hr_dev->iboe.netdevs[port];
275 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
276 dev_err(dev, "find netdev %d failed!\r\n", port);
280 mtu = iboe_get_mtu(net_dev->mtu);
281 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
282 props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
283 IB_PORT_ACTIVE : IB_PORT_DOWN;
284 props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3;
286 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
291 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
294 return IB_LINK_LAYER_ETHERNET;
297 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
305 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
306 struct ib_device_modify *props)
310 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
313 if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
314 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
315 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
316 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
322 static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
323 struct ib_port_modify *props)
328 static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev,
329 struct ib_udata *udata)
332 struct hns_roce_ucontext *context;
333 struct hns_roce_ib_alloc_ucontext_resp resp = {};
334 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
336 resp.qp_tab_size = hr_dev->caps.num_qps;
338 context = kmalloc(sizeof(*context), GFP_KERNEL);
340 return ERR_PTR(-ENOMEM);
342 ret = hns_roce_uar_alloc(hr_dev, &context->uar);
344 goto error_fail_uar_alloc;
346 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
347 INIT_LIST_HEAD(&context->page_list);
348 mutex_init(&context->page_mutex);
351 ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
353 goto error_fail_copy_to_udata;
355 return &context->ibucontext;
357 error_fail_copy_to_udata:
358 hns_roce_uar_free(hr_dev, &context->uar);
360 error_fail_uar_alloc:
366 static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
368 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
370 hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
376 static int hns_roce_mmap(struct ib_ucontext *context,
377 struct vm_area_struct *vma)
379 struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
381 if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0)
384 if (vma->vm_pgoff == 0) {
385 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
386 if (io_remap_pfn_range(vma, vma->vm_start,
387 to_hr_ucontext(context)->uar.pfn,
388 PAGE_SIZE, vma->vm_page_prot))
390 } else if (vma->vm_pgoff == 1 && hr_dev->tptr_dma_addr &&
392 /* vm_pgoff: 1 -- TPTR */
393 if (io_remap_pfn_range(vma, vma->vm_start,
394 hr_dev->tptr_dma_addr >> PAGE_SHIFT,
404 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
405 struct ib_port_immutable *immutable)
407 struct ib_port_attr attr;
410 ret = ib_query_port(ib_dev, port_num, &attr);
414 immutable->pkey_tbl_len = attr.pkey_tbl_len;
415 immutable->gid_tbl_len = attr.gid_tbl_len;
417 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
418 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
419 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
420 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
425 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
427 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
429 unregister_netdevice_notifier(&iboe->nb);
430 ib_unregister_device(&hr_dev->ib_dev);
433 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
436 struct hns_roce_ib_iboe *iboe = NULL;
437 struct ib_device *ib_dev = NULL;
438 struct device *dev = hr_dev->dev;
440 iboe = &hr_dev->iboe;
441 spin_lock_init(&iboe->lock);
443 ib_dev = &hr_dev->ib_dev;
444 strlcpy(ib_dev->name, "hns_%d", IB_DEVICE_NAME_MAX);
446 ib_dev->owner = THIS_MODULE;
447 ib_dev->node_type = RDMA_NODE_IB_CA;
448 ib_dev->dev.parent = dev;
450 ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
451 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
452 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
453 ib_dev->uverbs_abi_ver = 1;
454 ib_dev->uverbs_cmd_mask =
455 (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
456 (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
457 (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
458 (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
459 (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
460 (1ULL << IB_USER_VERBS_CMD_REG_MR) |
461 (1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
462 (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
463 (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
464 (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
465 (1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
466 (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
467 (1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
468 (1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
470 /* HCA||device||port */
471 ib_dev->modify_device = hns_roce_modify_device;
472 ib_dev->query_device = hns_roce_query_device;
473 ib_dev->query_port = hns_roce_query_port;
474 ib_dev->modify_port = hns_roce_modify_port;
475 ib_dev->get_link_layer = hns_roce_get_link_layer;
476 ib_dev->get_netdev = hns_roce_get_netdev;
477 ib_dev->add_gid = hns_roce_add_gid;
478 ib_dev->del_gid = hns_roce_del_gid;
479 ib_dev->query_pkey = hns_roce_query_pkey;
480 ib_dev->alloc_ucontext = hns_roce_alloc_ucontext;
481 ib_dev->dealloc_ucontext = hns_roce_dealloc_ucontext;
482 ib_dev->mmap = hns_roce_mmap;
485 ib_dev->alloc_pd = hns_roce_alloc_pd;
486 ib_dev->dealloc_pd = hns_roce_dealloc_pd;
489 ib_dev->create_ah = hns_roce_create_ah;
490 ib_dev->query_ah = hns_roce_query_ah;
491 ib_dev->destroy_ah = hns_roce_destroy_ah;
494 ib_dev->create_qp = hns_roce_create_qp;
495 ib_dev->modify_qp = hns_roce_modify_qp;
496 ib_dev->query_qp = hr_dev->hw->query_qp;
497 ib_dev->destroy_qp = hr_dev->hw->destroy_qp;
498 ib_dev->post_send = hr_dev->hw->post_send;
499 ib_dev->post_recv = hr_dev->hw->post_recv;
502 ib_dev->create_cq = hns_roce_ib_create_cq;
503 ib_dev->modify_cq = hr_dev->hw->modify_cq;
504 ib_dev->destroy_cq = hns_roce_ib_destroy_cq;
505 ib_dev->req_notify_cq = hr_dev->hw->req_notify_cq;
506 ib_dev->poll_cq = hr_dev->hw->poll_cq;
509 ib_dev->get_dma_mr = hns_roce_get_dma_mr;
510 ib_dev->reg_user_mr = hns_roce_reg_user_mr;
511 ib_dev->dereg_mr = hns_roce_dereg_mr;
512 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) {
513 ib_dev->rereg_user_mr = hns_roce_rereg_user_mr;
514 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR);
518 ib_dev->get_port_immutable = hns_roce_port_immutable;
520 ib_dev->driver_id = RDMA_DRIVER_HNS;
521 ret = ib_register_device(ib_dev, NULL);
523 dev_err(dev, "ib_register_device failed!\n");
527 ret = hns_roce_setup_mtu_mac(hr_dev);
529 dev_err(dev, "setup_mtu_mac failed!\n");
530 goto error_failed_setup_mtu_mac;
533 iboe->nb.notifier_call = hns_roce_netdev_event;
534 ret = register_netdevice_notifier(&iboe->nb);
536 dev_err(dev, "register_netdevice_notifier failed!\n");
537 goto error_failed_setup_mtu_mac;
542 error_failed_setup_mtu_mac:
543 ib_unregister_device(ib_dev);
548 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
551 struct device *dev = hr_dev->dev;
553 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
554 HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
555 hr_dev->caps.num_mtt_segs, 1);
557 dev_err(dev, "Failed to init MTT context memory, aborting.\n");
561 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) {
562 ret = hns_roce_init_hem_table(hr_dev,
563 &hr_dev->mr_table.mtt_cqe_table,
564 HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz,
565 hr_dev->caps.num_cqe_segs, 1);
567 dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n");
572 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
573 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
574 hr_dev->caps.num_mtpts, 1);
576 dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
580 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
581 HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
582 hr_dev->caps.num_qps, 1);
584 dev_err(dev, "Failed to init QP context memory, aborting.\n");
588 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
590 hr_dev->caps.irrl_entry_sz *
591 hr_dev->caps.max_qp_init_rdma,
592 hr_dev->caps.num_qps, 1);
594 dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
598 if (hr_dev->caps.trrl_entry_sz) {
599 ret = hns_roce_init_hem_table(hr_dev,
600 &hr_dev->qp_table.trrl_table,
602 hr_dev->caps.trrl_entry_sz *
603 hr_dev->caps.max_qp_dest_rdma,
604 hr_dev->caps.num_qps, 1);
607 "Failed to init trrl_table memory, aborting.\n");
612 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
613 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
614 hr_dev->caps.num_cqs, 1);
616 dev_err(dev, "Failed to init CQ context memory, aborting.\n");
623 if (hr_dev->caps.trrl_entry_sz)
624 hns_roce_cleanup_hem_table(hr_dev,
625 &hr_dev->qp_table.trrl_table);
628 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
631 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
634 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
637 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
638 hns_roce_cleanup_hem_table(hr_dev,
639 &hr_dev->mr_table.mtt_cqe_table);
642 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
648 * hns_roce_setup_hca - setup host channel adapter
649 * @hr_dev: pointer to hns roce device
652 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
655 struct device *dev = hr_dev->dev;
657 spin_lock_init(&hr_dev->sm_lock);
658 spin_lock_init(&hr_dev->bt_cmd_lock);
660 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
661 INIT_LIST_HEAD(&hr_dev->pgdir_list);
662 mutex_init(&hr_dev->pgdir_mutex);
665 ret = hns_roce_init_uar_table(hr_dev);
667 dev_err(dev, "Failed to initialize uar table. aborting\n");
671 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
673 dev_err(dev, "Failed to allocate priv_uar.\n");
674 goto err_uar_table_free;
677 ret = hns_roce_init_pd_table(hr_dev);
679 dev_err(dev, "Failed to init protected domain table.\n");
680 goto err_uar_alloc_free;
683 ret = hns_roce_init_mr_table(hr_dev);
685 dev_err(dev, "Failed to init memory region table.\n");
686 goto err_pd_table_free;
689 ret = hns_roce_init_cq_table(hr_dev);
691 dev_err(dev, "Failed to init completion queue table.\n");
692 goto err_mr_table_free;
695 ret = hns_roce_init_qp_table(hr_dev);
697 dev_err(dev, "Failed to init queue pair table.\n");
698 goto err_cq_table_free;
704 hns_roce_cleanup_cq_table(hr_dev);
707 hns_roce_cleanup_mr_table(hr_dev);
710 hns_roce_cleanup_pd_table(hr_dev);
713 hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
716 hns_roce_cleanup_uar_table(hr_dev);
720 int hns_roce_init(struct hns_roce_dev *hr_dev)
723 struct device *dev = hr_dev->dev;
725 if (hr_dev->hw->reset) {
726 ret = hr_dev->hw->reset(hr_dev, true);
728 dev_err(dev, "Reset RoCE engine failed!\n");
733 if (hr_dev->hw->cmq_init) {
734 ret = hr_dev->hw->cmq_init(hr_dev);
736 dev_err(dev, "Init RoCE Command Queue failed!\n");
737 goto error_failed_cmq_init;
741 ret = hr_dev->hw->hw_profile(hr_dev);
743 dev_err(dev, "Get RoCE engine profile failed!\n");
744 goto error_failed_cmd_init;
747 ret = hns_roce_cmd_init(hr_dev);
749 dev_err(dev, "cmd init failed!\n");
750 goto error_failed_cmd_init;
753 ret = hr_dev->hw->init_eq(hr_dev);
755 dev_err(dev, "eq init failed!\n");
756 goto error_failed_eq_table;
759 if (hr_dev->cmd_mod) {
760 ret = hns_roce_cmd_use_events(hr_dev);
762 dev_err(dev, "Switch to event-driven cmd failed!\n");
763 goto error_failed_use_event;
767 ret = hns_roce_init_hem(hr_dev);
769 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
770 goto error_failed_init_hem;
773 ret = hns_roce_setup_hca(hr_dev);
775 dev_err(dev, "setup hca failed!\n");
776 goto error_failed_setup_hca;
779 if (hr_dev->hw->hw_init) {
780 ret = hr_dev->hw->hw_init(hr_dev);
782 dev_err(dev, "hw_init failed!\n");
783 goto error_failed_engine_init;
787 ret = hns_roce_register_device(hr_dev);
789 goto error_failed_register_device;
793 error_failed_register_device:
794 if (hr_dev->hw->hw_exit)
795 hr_dev->hw->hw_exit(hr_dev);
797 error_failed_engine_init:
798 hns_roce_cleanup_bitmap(hr_dev);
800 error_failed_setup_hca:
801 hns_roce_cleanup_hem(hr_dev);
803 error_failed_init_hem:
805 hns_roce_cmd_use_polling(hr_dev);
807 error_failed_use_event:
808 hr_dev->hw->cleanup_eq(hr_dev);
810 error_failed_eq_table:
811 hns_roce_cmd_cleanup(hr_dev);
813 error_failed_cmd_init:
814 if (hr_dev->hw->cmq_exit)
815 hr_dev->hw->cmq_exit(hr_dev);
817 error_failed_cmq_init:
818 if (hr_dev->hw->reset) {
819 ret = hr_dev->hw->reset(hr_dev, false);
821 dev_err(dev, "Dereset RoCE engine failed!\n");
826 EXPORT_SYMBOL_GPL(hns_roce_init);
828 void hns_roce_exit(struct hns_roce_dev *hr_dev)
830 hns_roce_unregister_device(hr_dev);
831 if (hr_dev->hw->hw_exit)
832 hr_dev->hw->hw_exit(hr_dev);
833 hns_roce_cleanup_bitmap(hr_dev);
834 hns_roce_cleanup_hem(hr_dev);
837 hns_roce_cmd_use_polling(hr_dev);
839 hr_dev->hw->cleanup_eq(hr_dev);
840 hns_roce_cmd_cleanup(hr_dev);
841 if (hr_dev->hw->cmq_exit)
842 hr_dev->hw->cmq_exit(hr_dev);
843 if (hr_dev->hw->reset)
844 hr_dev->hw->reset(hr_dev, false);
846 EXPORT_SYMBOL_GPL(hns_roce_exit);
848 MODULE_LICENSE("Dual BSD/GPL");
849 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
850 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
851 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
852 MODULE_DESCRIPTION("HNS RoCE Driver");