drivers/infiniband/hw/hns/hns_roce_device.h

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _HNS_ROCE_DEVICE_H
  34 #define _HNS_ROCE_DEVICE_H
  35
  36 #include <rdma/ib_verbs.h>
  37 #include <rdma/hns-abi.h>
  38
  39 #define DRV_NAME "hns_roce"
  40
  41 #define PCI_REVISION_ID_HIP08                   0x21
  42 #define PCI_REVISION_ID_HIP09                   0x30
  43
  44 #define HNS_ROCE_HW_VER1        ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
  45
  46 #define HNS_ROCE_MAX_MSG_LEN                    0x80000000
  47
  48 #define HNS_ROCE_IB_MIN_SQ_STRIDE               6
  49
  50 #define BA_BYTE_LEN                             8
  51
  52 /* Hardware specification only for v1 engine */
  53 #define HNS_ROCE_MIN_CQE_NUM                    0x40
  54 #define HNS_ROCE_MIN_WQE_NUM                    0x20
  55 #define HNS_ROCE_MIN_SRQ_WQE_NUM                1
  56
  57 /* Hardware specification only for v1 engine */
  58 #define HNS_ROCE_MAX_INNER_MTPT_NUM             0x7
  59 #define HNS_ROCE_MAX_MTPT_PBL_NUM               0x100000
  60
  61 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS        20
  62 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT   \
  63         (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
  64 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT             0x2
  65 #define HNS_ROCE_MIN_CQE_CNT                    16
  66
  67 #define HNS_ROCE_RESERVED_SGE                   1
  68
  69 #define HNS_ROCE_MAX_IRQ_NUM                    128
  70
  71 #define HNS_ROCE_SGE_IN_WQE                     2
  72 #define HNS_ROCE_SGE_SHIFT                      4
  73
  74 #define EQ_ENABLE                               1
  75 #define EQ_DISABLE                              0
  76
  77 #define HNS_ROCE_CEQ                            0
  78 #define HNS_ROCE_AEQ                            1
  79
  80 #define HNS_ROCE_CEQE_SIZE 0x4
  81 #define HNS_ROCE_AEQE_SIZE 0x10
  82
  83 #define HNS_ROCE_V3_EQE_SIZE 0x40
  84
  85 #define HNS_ROCE_V2_CQE_SIZE 32
  86 #define HNS_ROCE_V3_CQE_SIZE 64
  87
  88 #define HNS_ROCE_V2_QPC_SZ 256
  89 #define HNS_ROCE_V3_QPC_SZ 512
  90
  91 #define HNS_ROCE_MAX_PORTS                      6
  92 #define HNS_ROCE_GID_SIZE                       16
  93 #define HNS_ROCE_SGE_SIZE                       16
  94 #define HNS_ROCE_DWQE_SIZE                      65536
  95
  96 #define HNS_ROCE_HOP_NUM_0                      0xff
  97
  98 #define MR_TYPE_MR                              0x00
  99 #define MR_TYPE_FRMR                            0x01
 100 #define MR_TYPE_DMA                             0x03
 101
 102 #define HNS_ROCE_FRMR_MAX_PA                    512
 103
 104 #define PKEY_ID                                 0xffff
 105 #define GUID_LEN                                8
 106 #define NODE_DESC_SIZE                          64
 107 #define DB_REG_OFFSET                           0x1000
 108
 109 /* Configure to HW for PAGE_SIZE larger than 4KB */
 110 #define PG_SHIFT_OFFSET                         (PAGE_SHIFT - 12)
 111
 112 #define PAGES_SHIFT_8                           8
 113 #define PAGES_SHIFT_16                          16
 114 #define PAGES_SHIFT_24                          24
 115 #define PAGES_SHIFT_32                          32
 116
 117 #define HNS_ROCE_IDX_QUE_ENTRY_SZ               4
 118 #define SRQ_DB_REG                              0x230
 119
 120 #define HNS_ROCE_QP_BANK_NUM 8
 121 #define HNS_ROCE_CQ_BANK_NUM 4
 122
 123 #define CQ_BANKID_SHIFT 2
 124
 125 /* The chip implementation of the consumer index is calculated
 126  * according to twice the actual EQ depth
 127  */
 128 #define EQ_DEPTH_COEFF                          2
 129
 130 enum {
 131         SERV_TYPE_RC,
 132         SERV_TYPE_UC,
 133         SERV_TYPE_RD,
 134         SERV_TYPE_UD,
 135         SERV_TYPE_XRC = 5,
 136 };
 137
 138 enum hns_roce_qp_state {
 139         HNS_ROCE_QP_STATE_RST,
 140         HNS_ROCE_QP_STATE_INIT,
 141         HNS_ROCE_QP_STATE_RTR,
 142         HNS_ROCE_QP_STATE_RTS,
 143         HNS_ROCE_QP_STATE_SQD,
 144         HNS_ROCE_QP_STATE_ERR,
 145         HNS_ROCE_QP_NUM_STATE,
 146 };
 147
 148 enum hns_roce_event {
 149         HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
 150         HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
 151         HNS_ROCE_EVENT_TYPE_COMM_EST                  = 0x03,
 152         HNS_ROCE_EVENT_TYPE_SQ_DRAINED                = 0x04,
 153         HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR            = 0x05,
 154         HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR    = 0x06,
 155         HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR     = 0x07,
 156         HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH           = 0x08,
 157         HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH        = 0x09,
 158         HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR           = 0x0a,
 159         HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR           = 0x0b,
 160         HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW               = 0x0c,
 161         HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID             = 0x0d,
 162         HNS_ROCE_EVENT_TYPE_PORT_CHANGE               = 0x0f,
 163         /* 0x10 and 0x11 is unused in currently application case */
 164         HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,
 165         HNS_ROCE_EVENT_TYPE_MB                        = 0x13,
 166         HNS_ROCE_EVENT_TYPE_FLR                       = 0x15,
 167         HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION            = 0x16,
 168         HNS_ROCE_EVENT_TYPE_INVALID_XRCETH            = 0x17,
 169 };
 170
 171 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12
 172
 173 enum {
 174         HNS_ROCE_CAP_FLAG_REREG_MR              = BIT(0),
 175         HNS_ROCE_CAP_FLAG_ROCE_V1_V2            = BIT(1),
 176         HNS_ROCE_CAP_FLAG_RQ_INLINE             = BIT(2),
 177         HNS_ROCE_CAP_FLAG_CQ_RECORD_DB          = BIT(3),
 178         HNS_ROCE_CAP_FLAG_QP_RECORD_DB          = BIT(4),
 179         HNS_ROCE_CAP_FLAG_SRQ                   = BIT(5),
 180         HNS_ROCE_CAP_FLAG_XRC                   = BIT(6),
 181         HNS_ROCE_CAP_FLAG_MW                    = BIT(7),
 182         HNS_ROCE_CAP_FLAG_FRMR                  = BIT(8),
 183         HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL          = BIT(9),
 184         HNS_ROCE_CAP_FLAG_ATOMIC                = BIT(10),
 185         HNS_ROCE_CAP_FLAG_SDI_MODE              = BIT(14),
 186         HNS_ROCE_CAP_FLAG_STASH                 = BIT(17),
 187 };
 188
 189 #define HNS_ROCE_DB_TYPE_COUNT                  2
 190 #define HNS_ROCE_DB_UNIT_SIZE                   4
 191
 192 enum {
 193         HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
 194 };
 195
 196 enum hns_roce_reset_stage {
 197         HNS_ROCE_STATE_NON_RST,
 198         HNS_ROCE_STATE_RST_BEF_DOWN,
 199         HNS_ROCE_STATE_RST_DOWN,
 200         HNS_ROCE_STATE_RST_UNINIT,
 201         HNS_ROCE_STATE_RST_INIT,
 202         HNS_ROCE_STATE_RST_INITED,
 203 };
 204
 205 enum hns_roce_instance_state {
 206         HNS_ROCE_STATE_NON_INIT,
 207         HNS_ROCE_STATE_INIT,
 208         HNS_ROCE_STATE_INITED,
 209         HNS_ROCE_STATE_UNINIT,
 210 };
 211
 212 enum {
 213         HNS_ROCE_RST_DIRECT_RETURN              = 0,
 214 };
 215
 216 #define HNS_ROCE_CMD_SUCCESS                    1
 217
 218 /* The minimum page size is 4K for hardware */
 219 #define HNS_HW_PAGE_SHIFT                       12
 220 #define HNS_HW_PAGE_SIZE                        (1 << HNS_HW_PAGE_SHIFT)
 221
 222 struct hns_roce_uar {
 223         u64             pfn;
 224         unsigned long   index;
 225         unsigned long   logic_idx;
 226 };
 227
 228 enum hns_roce_mmap_type {
 229         HNS_ROCE_MMAP_TYPE_DB = 1,
 230         HNS_ROCE_MMAP_TYPE_TPTR,
 231 };
 232
 233 struct hns_user_mmap_entry {
 234         struct rdma_user_mmap_entry rdma_entry;
 235         enum hns_roce_mmap_type mmap_type;
 236         u64 address;
 237 };
 238
 239 struct hns_roce_ucontext {
 240         struct ib_ucontext      ibucontext;
 241         struct hns_roce_uar     uar;
 242         struct list_head        page_list;
 243         struct mutex            page_mutex;
 244         struct hns_user_mmap_entry *db_mmap_entry;
 245         struct hns_user_mmap_entry *tptr_mmap_entry;
 246 };
 247
 248 struct hns_roce_pd {
 249         struct ib_pd            ibpd;
 250         unsigned long           pdn;
 251 };
 252
 253 struct hns_roce_xrcd {
 254         struct ib_xrcd ibxrcd;
 255         u32 xrcdn;
 256 };
 257
 258 struct hns_roce_bitmap {
 259         /* Bitmap Traversal last a bit which is 1 */
 260         unsigned long           last;
 261         unsigned long           top;
 262         unsigned long           max;
 263         unsigned long           reserved_top;
 264         unsigned long           mask;
 265         spinlock_t              lock;
 266         unsigned long           *table;
 267 };
 268
 269 struct hns_roce_ida {
 270         struct ida ida;
 271         u32 min; /* Lowest ID to allocate.  */
 272         u32 max; /* Highest ID to allocate. */
 273 };
 274
 275 /* For Hardware Entry Memory */
 276 struct hns_roce_hem_table {
 277         /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
 278         u32             type;
 279         /* HEM array elment num */
 280         unsigned long   num_hem;
 281         /* Single obj size */
 282         unsigned long   obj_size;
 283         unsigned long   table_chunk_size;
 284         int             lowmem;
 285         struct mutex    mutex;
 286         struct hns_roce_hem **hem;
 287         u64             **bt_l1;
 288         dma_addr_t      *bt_l1_dma_addr;
 289         u64             **bt_l0;
 290         dma_addr_t      *bt_l0_dma_addr;
 291 };
 292
 293 struct hns_roce_buf_region {
 294         u32 offset; /* page offset */
 295         u32 count; /* page count */
 296         int hopnum; /* addressing hop num */
 297 };
 298
 299 #define HNS_ROCE_MAX_BT_REGION  3
 300 #define HNS_ROCE_MAX_BT_LEVEL   3
 301 struct hns_roce_hem_list {
 302         struct list_head root_bt;
 303         /* link all bt dma mem by hop config */
 304         struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
 305         struct list_head btm_bt; /* link all bottom bt in @mid_bt */
 306         dma_addr_t root_ba; /* pointer to the root ba table */
 307 };
 308
 309 struct hns_roce_buf_attr {
 310         struct {
 311                 size_t  size;  /* region size */
 312                 int     hopnum; /* multi-hop addressing hop num */
 313         } region[HNS_ROCE_MAX_BT_REGION];
 314         unsigned int region_count; /* valid region count */
 315         unsigned int page_shift;  /* buffer page shift */
 316         unsigned int user_access; /* umem access flag */
 317         bool mtt_only; /* only alloc buffer-required MTT memory */
 318 };
 319
 320 struct hns_roce_hem_cfg {
 321         dma_addr_t      root_ba; /* root BA table's address */
 322         bool            is_direct; /* addressing without BA table */
 323         unsigned int    ba_pg_shift; /* BA table page shift */
 324         unsigned int    buf_pg_shift; /* buffer page shift */
 325         unsigned int    buf_pg_count;  /* buffer page count */
 326         struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
 327         unsigned int    region_count;
 328 };
 329
 330 /* memory translate region */
 331 struct hns_roce_mtr {
 332         struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
 333         struct ib_umem          *umem; /* user space buffer */
 334         struct hns_roce_buf     *kmem; /* kernel space buffer */
 335         struct hns_roce_hem_cfg  hem_cfg; /* config for hardware addressing */
 336 };
 337
 338 struct hns_roce_mw {
 339         struct ib_mw            ibmw;
 340         u32                     pdn;
 341         u32                     rkey;
 342         int                     enabled; /* MW's active status */
 343         u32                     pbl_hop_num;
 344         u32                     pbl_ba_pg_sz;
 345         u32                     pbl_buf_pg_sz;
 346 };
 347
 348 /* Only support 4K page size for mr register */
 349 #define MR_SIZE_4K 0
 350
 351 struct hns_roce_mr {
 352         struct ib_mr            ibmr;
 353         u64                     iova; /* MR's virtual original addr */
 354         u64                     size; /* Address range of MR */
 355         u32                     key; /* Key of MR */
 356         u32                     pd;   /* PD num of MR */
 357         u32                     access; /* Access permission of MR */
 358         int                     enabled; /* MR's active status */
 359         int                     type;   /* MR's register type */
 360         u32                     pbl_hop_num;    /* multi-hop number */
 361         struct hns_roce_mtr     pbl_mtr;
 362         u32                     npages;
 363         dma_addr_t              *page_list;
 364 };
 365
 366 struct hns_roce_mr_table {
 367         struct hns_roce_ida mtpt_ida;
 368         struct hns_roce_hem_table       mtpt_table;
 369 };
 370
 371 struct hns_roce_wq {
 372         u64             *wrid;     /* Work request ID */
 373         spinlock_t      lock;
 374         u32             wqe_cnt;  /* WQE num */
 375         u32             max_gs;
 376         u32             rsv_sge;
 377         int             offset;
 378         int             wqe_shift;      /* WQE size */
 379         u32             head;
 380         u32             tail;
 381         void __iomem    *db_reg;
 382 };
 383
 384 struct hns_roce_sge {
 385         unsigned int    sge_cnt;        /* SGE num */
 386         int             offset;
 387         int             sge_shift;      /* SGE size */
 388 };
 389
 390 struct hns_roce_buf_list {
 391         void            *buf;
 392         dma_addr_t      map;
 393 };
 394
 395 /*
 396  * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
 397  * dma address range.
 398  *
 399  * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
 400  *
 401  * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
 402  * the allocated size is smaller than the required size.
 403  */
 404 enum {
 405         HNS_ROCE_BUF_DIRECT = BIT(0),
 406         HNS_ROCE_BUF_NOSLEEP = BIT(1),
 407         HNS_ROCE_BUF_NOFAIL = BIT(2),
 408 };
 409
 410 struct hns_roce_buf {
 411         struct hns_roce_buf_list        *trunk_list;
 412         u32                             ntrunks;
 413         u32                             npages;
 414         unsigned int                    trunk_shift;
 415         unsigned int                    page_shift;
 416 };
 417
 418 struct hns_roce_db_pgdir {
 419         struct list_head        list;
 420         DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
 421         DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
 422         unsigned long           *bits[HNS_ROCE_DB_TYPE_COUNT];
 423         u32                     *page;
 424         dma_addr_t              db_dma;
 425 };
 426
 427 struct hns_roce_user_db_page {
 428         struct list_head        list;
 429         struct ib_umem          *umem;
 430         unsigned long           user_virt;
 431         refcount_t              refcount;
 432 };
 433
 434 struct hns_roce_db {
 435         u32             *db_record;
 436         union {
 437                 struct hns_roce_db_pgdir *pgdir;
 438                 struct hns_roce_user_db_page *user_page;
 439         } u;
 440         dma_addr_t      dma;
 441         void            *virt_addr;
 442         unsigned long   index;
 443         unsigned long   order;
 444 };
 445
 446 struct hns_roce_cq {
 447         struct ib_cq                    ib_cq;
 448         struct hns_roce_mtr             mtr;
 449         struct hns_roce_db              db;
 450         u32                             flags;
 451         spinlock_t                      lock;
 452         u32                             cq_depth;
 453         u32                             cons_index;
 454         u32                             *set_ci_db;
 455         void __iomem                    *db_reg;
 456         u16                             *tptr_addr;
 457         int                             arm_sn;
 458         int                             cqe_size;
 459         unsigned long                   cqn;
 460         u32                             vector;
 461         refcount_t                      refcount;
 462         struct completion               free;
 463         struct list_head                sq_list; /* all qps on this send cq */
 464         struct list_head                rq_list; /* all qps on this recv cq */
 465         int                             is_armed; /* cq is armed */
 466         struct list_head                node; /* all armed cqs are on a list */
 467 };
 468
 469 struct hns_roce_idx_que {
 470         struct hns_roce_mtr             mtr;
 471         int                             entry_shift;
 472         unsigned long                   *bitmap;
 473         u32                             head;
 474         u32                             tail;
 475 };
 476
 477 struct hns_roce_srq {
 478         struct ib_srq           ibsrq;
 479         unsigned long           srqn;
 480         u32                     wqe_cnt;
 481         int                     max_gs;
 482         u32                     rsv_sge;
 483         int                     wqe_shift;
 484         u32                     cqn;
 485         u32                     xrcdn;
 486         void __iomem            *db_reg;
 487
 488         refcount_t              refcount;
 489         struct completion       free;
 490
 491         struct hns_roce_mtr     buf_mtr;
 492
 493         u64                    *wrid;
 494         struct hns_roce_idx_que idx_que;
 495         spinlock_t              lock;
 496         struct mutex            mutex;
 497         void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
 498 };
 499
 500 struct hns_roce_uar_table {
 501         struct hns_roce_bitmap bitmap;
 502 };
 503
 504 struct hns_roce_bank {
 505         struct ida ida;
 506         u32 inuse; /* Number of IDs allocated */
 507         u32 min; /* Lowest ID to allocate.  */
 508         u32 max; /* Highest ID to allocate. */
 509         u32 next; /* Next ID to allocate. */
 510 };
 511
 512 struct hns_roce_idx_table {
 513         u32 *spare_idx;
 514         u32 head;
 515         u32 tail;
 516 };
 517
 518 struct hns_roce_qp_table {
 519         struct hns_roce_hem_table       qp_table;
 520         struct hns_roce_hem_table       irrl_table;
 521         struct hns_roce_hem_table       trrl_table;
 522         struct hns_roce_hem_table       sccc_table;
 523         struct mutex                    scc_mutex;
 524         struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
 525         struct mutex bank_mutex;
 526         struct hns_roce_idx_table       idx_table;
 527 };
 528
 529 struct hns_roce_cq_table {
 530         struct xarray                   array;
 531         struct hns_roce_hem_table       table;
 532         struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
 533         struct mutex                    bank_mutex;
 534 };
 535
 536 struct hns_roce_srq_table {
 537         struct hns_roce_ida             srq_ida;
 538         struct xarray                   xa;
 539         struct hns_roce_hem_table       table;
 540 };
 541
 542 struct hns_roce_raq_table {
 543         struct hns_roce_buf_list        *e_raq_buf;
 544 };
 545
 546 struct hns_roce_av {
 547         u8 port;
 548         u8 gid_index;
 549         u8 stat_rate;
 550         u8 hop_limit;
 551         u32 flowlabel;
 552         u16 udp_sport;
 553         u8 sl;
 554         u8 tclass;
 555         u8 dgid[HNS_ROCE_GID_SIZE];
 556         u8 mac[ETH_ALEN];
 557         u16 vlan_id;
 558         u8 vlan_en;
 559 };
 560
 561 struct hns_roce_ah {
 562         struct ib_ah            ibah;
 563         struct hns_roce_av      av;
 564 };
 565
 566 struct hns_roce_cmd_context {
 567         struct completion       done;
 568         int                     result;
 569         int                     next;
 570         u64                     out_param;
 571         u16                     token;
 572         u16                     busy;
 573 };
 574
 575 struct hns_roce_cmdq {
 576         struct dma_pool         *pool;
 577         struct semaphore        poll_sem;
 578         /*
 579          * Event mode: cmd register mutex protection,
 580          * ensure to not exceed max_cmds and user use limit region
 581          */
 582         struct semaphore        event_sem;
 583         int                     max_cmds;
 584         spinlock_t              context_lock;
 585         int                     free_head;
 586         struct hns_roce_cmd_context *context;
 587         /*
 588          * Process whether use event mode, init default non-zero
 589          * After the event queue of cmd event ready,
 590          * can switch into event mode
 591          * close device, switch into poll mode(non event mode)
 592          */
 593         u8                      use_events;
 594 };
 595
 596 struct hns_roce_cmd_mailbox {
 597         void                   *buf;
 598         dma_addr_t              dma;
 599 };
 600
 601 struct hns_roce_dev;
 602
 603 struct hns_roce_rinl_sge {
 604         void                    *addr;
 605         u32                     len;
 606 };
 607
 608 struct hns_roce_rinl_wqe {
 609         struct hns_roce_rinl_sge *sg_list;
 610         u32                      sge_cnt;
 611 };
 612
 613 struct hns_roce_rinl_buf {
 614         struct hns_roce_rinl_wqe *wqe_list;
 615         u32                      wqe_cnt;
 616 };
 617
 618 enum {
 619         HNS_ROCE_FLUSH_FLAG = 0,
 620 };
 621
 622 struct hns_roce_work {
 623         struct hns_roce_dev *hr_dev;
 624         struct work_struct work;
 625         int event_type;
 626         int sub_type;
 627         u32 queue_num;
 628 };
 629
 630 enum {
 631         HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5),
 632 };
 633
 634 struct hns_roce_qp {
 635         struct ib_qp            ibqp;
 636         struct hns_roce_wq      rq;
 637         struct hns_roce_db      rdb;
 638         struct hns_roce_db      sdb;
 639         unsigned long           en_flags;
 640         u32                     doorbell_qpn;
 641         enum ib_sig_type        sq_signal_bits;
 642         struct hns_roce_wq      sq;
 643
 644         struct hns_roce_mtr     mtr;
 645
 646         u32                     buff_size;
 647         struct mutex            mutex;
 648         u8                      port;
 649         u8                      phy_port;
 650         u8                      sl;
 651         u8                      resp_depth;
 652         u8                      state;
 653         u32                     access_flags;
 654         u32                     atomic_rd_en;
 655         u32                     pkey_index;
 656         u32                     qkey;
 657         void                    (*event)(struct hns_roce_qp *qp,
 658                                          enum hns_roce_event event_type);
 659         unsigned long           qpn;
 660
 661         u32                     xrcdn;
 662
 663         refcount_t              refcount;
 664         struct completion       free;
 665
 666         struct hns_roce_sge     sge;
 667         u32                     next_sge;
 668         enum ib_mtu             path_mtu;
 669         u32                     max_inline_data;
 670
 671         /* 0: flush needed, 1: unneeded */
 672         unsigned long           flush_flag;
 673         struct hns_roce_work    flush_work;
 674         struct hns_roce_rinl_buf rq_inl_buf;
 675         struct list_head        node;           /* all qps are on a list */
 676         struct list_head        rq_node;        /* all recv qps are on a list */
 677         struct list_head        sq_node;        /* all send qps are on a list */
 678 };
 679
 680 struct hns_roce_ib_iboe {
 681         spinlock_t              lock;
 682         struct net_device      *netdevs[HNS_ROCE_MAX_PORTS];
 683         struct notifier_block   nb;
 684         u8                      phy_port[HNS_ROCE_MAX_PORTS];
 685 };
 686
 687 enum {
 688         HNS_ROCE_EQ_STAT_INVALID  = 0,
 689         HNS_ROCE_EQ_STAT_VALID    = 2,
 690 };
 691
 692 struct hns_roce_ceqe {
 693         __le32  comp;
 694         __le32  rsv[15];
 695 };
 696
 697 struct hns_roce_aeqe {
 698         __le32 asyn;
 699         union {
 700                 struct {
 701                         __le32 num;
 702                         u32 rsv0;
 703                         u32 rsv1;
 704                 } queue_event;
 705
 706                 struct {
 707                         __le64  out_param;
 708                         __le16  token;
 709                         u8      status;
 710                         u8      rsv0;
 711                 } __packed cmd;
 712          } event;
 713         __le32 rsv[12];
 714 };
 715
 716 struct hns_roce_eq {
 717         struct hns_roce_dev             *hr_dev;
 718         void __iomem                    *db_reg;
 719
 720         int                             type_flag; /* Aeq:1 ceq:0 */
 721         int                             eqn;
 722         u32                             entries;
 723         u32                             log_entries;
 724         int                             eqe_size;
 725         int                             irq;
 726         int                             log_page_size;
 727         u32                             cons_index;
 728         struct hns_roce_buf_list        *buf_list;
 729         int                             over_ignore;
 730         int                             coalesce;
 731         int                             arm_st;
 732         int                             hop_num;
 733         struct hns_roce_mtr             mtr;
 734         u16                             eq_max_cnt;
 735         u32                             eq_period;
 736         int                             shift;
 737         int                             event_type;
 738         int                             sub_type;
 739 };
 740
 741 struct hns_roce_eq_table {
 742         struct hns_roce_eq      *eq;
 743         void __iomem            **eqc_base; /* only for hw v1 */
 744 };
 745
 746 enum cong_type {
 747         CONG_TYPE_DCQCN,
 748         CONG_TYPE_LDCP,
 749         CONG_TYPE_HC3,
 750         CONG_TYPE_DIP,
 751 };
 752
 753 struct hns_roce_caps {
 754         u64             fw_ver;
 755         u8              num_ports;
 756         int             gid_table_len[HNS_ROCE_MAX_PORTS];
 757         int             pkey_table_len[HNS_ROCE_MAX_PORTS];
 758         int             local_ca_ack_delay;
 759         int             num_uars;
 760         u32             phy_num_uars;
 761         u32             max_sq_sg;
 762         u32             max_sq_inline;
 763         u32             max_rq_sg;
 764         u32             max_extend_sg;
 765         u32             num_qps;
 766         u32             num_pi_qps;
 767         u32             reserved_qps;
 768         int             num_qpc_timer;
 769         int             num_cqc_timer;
 770         int             num_srqs;
 771         u32             max_wqes;
 772         u32             max_srq_wrs;
 773         u32             max_srq_sges;
 774         u32             max_sq_desc_sz;
 775         u32             max_rq_desc_sz;
 776         u32             max_srq_desc_sz;
 777         int             max_qp_init_rdma;
 778         int             max_qp_dest_rdma;
 779         u32             num_cqs;
 780         u32             max_cqes;
 781         u32             min_cqes;
 782         u32             min_wqes;
 783         u32             reserved_cqs;
 784         int             reserved_srqs;
 785         int             num_aeq_vectors;
 786         int             num_comp_vectors;
 787         int             num_other_vectors;
 788         u32             num_mtpts;
 789         u32             num_mtt_segs;
 790         u32             num_srqwqe_segs;
 791         u32             num_idx_segs;
 792         int             reserved_mrws;
 793         int             reserved_uars;
 794         int             num_pds;
 795         int             reserved_pds;
 796         u32             num_xrcds;
 797         u32             reserved_xrcds;
 798         u32             mtt_entry_sz;
 799         u32             cqe_sz;
 800         u32             page_size_cap;
 801         u32             reserved_lkey;
 802         int             mtpt_entry_sz;
 803         int             qpc_sz;
 804         int             irrl_entry_sz;
 805         int             trrl_entry_sz;
 806         int             cqc_entry_sz;
 807         int             sccc_sz;
 808         int             qpc_timer_entry_sz;
 809         int             cqc_timer_entry_sz;
 810         int             srqc_entry_sz;
 811         int             idx_entry_sz;
 812         u32             pbl_ba_pg_sz;
 813         u32             pbl_buf_pg_sz;
 814         u32             pbl_hop_num;
 815         int             aeqe_depth;
 816         int             ceqe_depth;
 817         u32             aeqe_size;
 818         u32             ceqe_size;
 819         enum ib_mtu     max_mtu;
 820         u32             qpc_bt_num;
 821         u32             qpc_timer_bt_num;
 822         u32             srqc_bt_num;
 823         u32             cqc_bt_num;
 824         u32             cqc_timer_bt_num;
 825         u32             mpt_bt_num;
 826         u32             eqc_bt_num;
 827         u32             smac_bt_num;
 828         u32             sgid_bt_num;
 829         u32             sccc_bt_num;
 830         u32             gmv_bt_num;
 831         u32             qpc_ba_pg_sz;
 832         u32             qpc_buf_pg_sz;
 833         u32             qpc_hop_num;
 834         u32             srqc_ba_pg_sz;
 835         u32             srqc_buf_pg_sz;
 836         u32             srqc_hop_num;
 837         u32             cqc_ba_pg_sz;
 838         u32             cqc_buf_pg_sz;
 839         u32             cqc_hop_num;
 840         u32             mpt_ba_pg_sz;
 841         u32             mpt_buf_pg_sz;
 842         u32             mpt_hop_num;
 843         u32             mtt_ba_pg_sz;
 844         u32             mtt_buf_pg_sz;
 845         u32             mtt_hop_num;
 846         u32             wqe_sq_hop_num;
 847         u32             wqe_sge_hop_num;
 848         u32             wqe_rq_hop_num;
 849         u32             sccc_ba_pg_sz;
 850         u32             sccc_buf_pg_sz;
 851         u32             sccc_hop_num;
 852         u32             qpc_timer_ba_pg_sz;
 853         u32             qpc_timer_buf_pg_sz;
 854         u32             qpc_timer_hop_num;
 855         u32             cqc_timer_ba_pg_sz;
 856         u32             cqc_timer_buf_pg_sz;
 857         u32             cqc_timer_hop_num;
 858         u32             cqe_ba_pg_sz;   /* page_size = 4K*(2^cqe_ba_pg_sz) */
 859         u32             cqe_buf_pg_sz;
 860         u32             cqe_hop_num;
 861         u32             srqwqe_ba_pg_sz;
 862         u32             srqwqe_buf_pg_sz;
 863         u32             srqwqe_hop_num;
 864         u32             idx_ba_pg_sz;
 865         u32             idx_buf_pg_sz;
 866         u32             idx_hop_num;
 867         u32             eqe_ba_pg_sz;
 868         u32             eqe_buf_pg_sz;
 869         u32             eqe_hop_num;
 870         u32             gmv_entry_num;
 871         u32             gmv_entry_sz;
 872         u32             gmv_ba_pg_sz;
 873         u32             gmv_buf_pg_sz;
 874         u32             gmv_hop_num;
 875         u32             sl_num;
 876         u32             llm_buf_pg_sz;
 877         u32             chunk_sz;       /* chunk size in non multihop mode */
 878         u64             flags;
 879         u16             default_ceq_max_cnt;
 880         u16             default_ceq_period;
 881         u16             default_aeq_max_cnt;
 882         u16             default_aeq_period;
 883         u16             default_aeq_arm_st;
 884         u16             default_ceq_arm_st;
 885         enum cong_type  cong_type;
 886 };
 887
 888 struct hns_roce_dfx_hw {
 889         int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
 890                               int *buffer);
 891 };
 892
 893 enum hns_roce_device_state {
 894         HNS_ROCE_DEVICE_STATE_INITED,
 895         HNS_ROCE_DEVICE_STATE_RST_DOWN,
 896         HNS_ROCE_DEVICE_STATE_UNINIT,
 897 };
 898
 899 struct hns_roce_hw {
 900         int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
 901         int (*cmq_init)(struct hns_roce_dev *hr_dev);
 902         void (*cmq_exit)(struct hns_roce_dev *hr_dev);
 903         int (*hw_profile)(struct hns_roce_dev *hr_dev);
 904         int (*hw_init)(struct hns_roce_dev *hr_dev);
 905         void (*hw_exit)(struct hns_roce_dev *hr_dev);
 906         int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
 907                          u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
 908                          u16 token, int event);
 909         int (*poll_mbox_done)(struct hns_roce_dev *hr_dev,
 910                               unsigned int timeout);
 911         bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy);
 912         int (*set_gid)(struct hns_roce_dev *hr_dev, u32 port, int gid_index,
 913                        const union ib_gid *gid, const struct ib_gid_attr *attr);
 914         int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port,
 915                        const u8 *addr);
 916         void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
 917                         enum ib_mtu mtu);
 918         int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
 919                           struct hns_roce_mr *mr, unsigned long mtpt_idx);
 920         int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
 921                                 struct hns_roce_mr *mr, int flags,
 922                                 void *mb_buf);
 923         int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
 924                                struct hns_roce_mr *mr);
 925         int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
 926         void (*write_cqc)(struct hns_roce_dev *hr_dev,
 927                           struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
 928                           dma_addr_t dma_handle);
 929         int (*set_hem)(struct hns_roce_dev *hr_dev,
 930                        struct hns_roce_hem_table *table, int obj, int step_idx);
 931         int (*clear_hem)(struct hns_roce_dev *hr_dev,
 932                          struct hns_roce_hem_table *table, int obj,
 933                          int step_idx);
 934         int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
 935                          int attr_mask, enum ib_qp_state cur_state,
 936                          enum ib_qp_state new_state);
 937         int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
 938                          struct hns_roce_qp *hr_qp);
 939         int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
 940                         struct ib_udata *udata);
 941         int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
 942         int (*init_eq)(struct hns_roce_dev *hr_dev);
 943         void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
 944         int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
 945         const struct ib_device_ops *hns_roce_dev_ops;
 946         const struct ib_device_ops *hns_roce_dev_srq_ops;
 947 };
 948
 949 struct hns_roce_dev {
 950         struct ib_device        ib_dev;
 951         struct platform_device  *pdev;
 952         struct pci_dev          *pci_dev;
 953         struct device           *dev;
 954         struct hns_roce_uar     priv_uar;
 955         const char              *irq_names[HNS_ROCE_MAX_IRQ_NUM];
 956         spinlock_t              sm_lock;
 957         spinlock_t              bt_cmd_lock;
 958         bool                    active;
 959         bool                    is_reset;
 960         bool                    dis_db;
 961         unsigned long           reset_cnt;
 962         struct hns_roce_ib_iboe iboe;
 963         enum hns_roce_device_state state;
 964         struct list_head        qp_list; /* list of all qps on this dev */
 965         spinlock_t              qp_list_lock; /* protect qp_list */
 966         struct list_head        dip_list; /* list of all dest ips on this dev */
 967         spinlock_t              dip_list_lock; /* protect dip_list */
 968
 969         struct list_head        pgdir_list;
 970         struct mutex            pgdir_mutex;
 971         int                     irq[HNS_ROCE_MAX_IRQ_NUM];
 972         u8 __iomem              *reg_base;
 973         void __iomem            *mem_base;
 974         struct hns_roce_caps    caps;
 975         struct xarray           qp_table_xa;
 976
 977         unsigned char   dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
 978         u64                     sys_image_guid;
 979         u32                     vendor_id;
 980         u32                     vendor_part_id;
 981         u32                     hw_rev;
 982         void __iomem            *priv_addr;
 983
 984         struct hns_roce_cmdq    cmd;
 985         struct hns_roce_ida pd_ida;
 986         struct hns_roce_ida xrcd_ida;
 987         struct hns_roce_ida uar_ida;
 988         struct hns_roce_mr_table  mr_table;
 989         struct hns_roce_cq_table  cq_table;
 990         struct hns_roce_srq_table srq_table;
 991         struct hns_roce_qp_table  qp_table;
 992         struct hns_roce_eq_table  eq_table;
 993         struct hns_roce_hem_table  qpc_timer_table;
 994         struct hns_roce_hem_table  cqc_timer_table;
 995         /* GMV is the memory area that the driver allocates for the hardware
 996          * to store SGID, SMAC and VLAN information.
 997          */
 998         struct hns_roce_hem_table  gmv_table;
 999
1000         int                     cmd_mod;
1001         int                     loop_idc;
1002         u32                     sdb_offset;
1003         u32                     odb_offset;
1004         dma_addr_t              tptr_dma_addr;  /* only for hw v1 */
1005         u32                     tptr_size;      /* only for hw v1 */
1006         const struct hns_roce_hw *hw;
1007         void                    *priv;
1008         struct workqueue_struct *irq_workq;
1009         const struct hns_roce_dfx_hw *dfx;
1010         u32 func_num;
1011         u32 is_vf;
1012         u32 cong_algo_tmpl_id;
1013 };
1014
1015 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
1016 {
1017         return container_of(ib_dev, struct hns_roce_dev, ib_dev);
1018 }
1019
1020 static inline struct hns_roce_ucontext
1021                         *to_hr_ucontext(struct ib_ucontext *ibucontext)
1022 {
1023         return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1024 }
1025
1026 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1027 {
1028         return container_of(ibpd, struct hns_roce_pd, ibpd);
1029 }
1030
1031 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd)
1032 {
1033         return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd);
1034 }
1035
1036 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1037 {
1038         return container_of(ibah, struct hns_roce_ah, ibah);
1039 }
1040
1041 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1042 {
1043         return container_of(ibmr, struct hns_roce_mr, ibmr);
1044 }
1045
1046 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1047 {
1048         return container_of(ibmw, struct hns_roce_mw, ibmw);
1049 }
1050
1051 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1052 {
1053         return container_of(ibqp, struct hns_roce_qp, ibqp);
1054 }
1055
1056 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1057 {
1058         return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1059 }
1060
1061 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1062 {
1063         return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1064 }
1065
1066 static inline struct hns_user_mmap_entry *
1067 to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry)
1068 {
1069         return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry);
1070 }
1071
1072 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1073 {
1074         writeq(*(u64 *)val, dest);
1075 }
1076
1077 static inline struct hns_roce_qp
1078         *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1079 {
1080         return xa_load(&hr_dev->qp_table_xa, qpn);
1081 }
1082
1083 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
1084                                         unsigned int offset)
1085 {
1086         return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1087                         (offset & ((1 << buf->trunk_shift) - 1));
1088 }
1089
1090 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf,
1091                                                unsigned int offset)
1092 {
1093         return buf->trunk_list[offset >> buf->trunk_shift].map +
1094                         (offset & ((1 << buf->trunk_shift) - 1));
1095 }
1096
1097 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
1098 {
1099         return hns_roce_buf_dma_addr(buf, idx << buf->page_shift);
1100 }
1101
1102 #define hr_hw_page_align(x)             ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1103
1104 static inline u64 to_hr_hw_page_addr(u64 addr)
1105 {
1106         return addr >> HNS_HW_PAGE_SHIFT;
1107 }
1108
1109 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1110 {
1111         return page_shift - HNS_HW_PAGE_SHIFT;
1112 }
1113
1114 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1115 {
1116         if (count > 0)
1117                 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1118
1119         return 0;
1120 }
1121
1122 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1123 {
1124         return hr_hw_page_align(count << buf_shift);
1125 }
1126
1127 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1128 {
1129         return hr_hw_page_align(count << buf_shift) >> buf_shift;
1130 }
1131
1132 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1133 {
1134         if (!count)
1135                 return 0;
1136
1137         return ilog2(to_hr_hem_entries_count(count, buf_shift));
1138 }
1139
1140 #define DSCP_SHIFT 2
1141
1142 static inline u8 get_tclass(const struct ib_global_route *grh)
1143 {
1144         return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
1145                grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
1146 }
1147
1148 void hns_roce_init_uar_table(struct hns_roce_dev *dev);
1149 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1150
1151 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1152 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1153 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1154                         u64 out_param);
1155 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1156 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1157
1158 /* hns roce hw need current block and next block addr from mtt */
1159 #define MTT_MIN_COUNT    2
1160 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1161                       int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1162 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1163                         struct hns_roce_buf_attr *buf_attr,
1164                         unsigned int page_shift, struct ib_udata *udata,
1165                         unsigned long user_addr);
1166 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1167                           struct hns_roce_mtr *mtr);
1168 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1169                      dma_addr_t *pages, unsigned int page_cnt);
1170
1171 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1172 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1173 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1174 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1175 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1176 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev);
1177
1178 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1179 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1180 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1181
1182 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1183
1184 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1185                        struct ib_udata *udata);
1186 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1187 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1188 {
1189         return 0;
1190 }
1191
1192 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1193 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1194
1195 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1196 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1197                                    u64 virt_addr, int access_flags,
1198                                    struct ib_udata *udata);
1199 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
1200                                      u64 length, u64 virt_addr,
1201                                      int mr_access_flags, struct ib_pd *pd,
1202                                      struct ib_udata *udata);
1203 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1204                                 u32 max_num_sg);
1205 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1206                        unsigned int *sg_offset);
1207 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1208 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
1209                             struct hns_roce_cmd_mailbox *mailbox,
1210                             unsigned long mpt_index);
1211 unsigned long key_to_hw_index(u32 key);
1212
1213 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1214 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1215
1216 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1217 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1218                                         u32 page_shift, u32 flags);
1219
1220 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1221                            int buf_cnt, struct hns_roce_buf *buf,
1222                            unsigned int page_shift);
1223 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1224                            int buf_cnt, struct ib_umem *umem,
1225                            unsigned int page_shift);
1226
1227 int hns_roce_create_srq(struct ib_srq *srq,
1228                         struct ib_srq_init_attr *srq_init_attr,
1229                         struct ib_udata *udata);
1230 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1231                         enum ib_srq_attr_mask srq_attr_mask,
1232                         struct ib_udata *udata);
1233 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1234
1235 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1236 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1237
1238 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr,
1239                        struct ib_udata *udata);
1240 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1241                        int attr_mask, struct ib_udata *udata);
1242 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1243 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1244 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1245 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
1246 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1247                           struct ib_cq *ib_cq);
1248 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1249 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1250                        struct hns_roce_cq *recv_cq);
1251 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1252                          struct hns_roce_cq *recv_cq);
1253 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1254 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1255                          struct ib_udata *udata);
1256 __be32 send_ieth(const struct ib_send_wr *wr);
1257 int to_hr_qp_type(int qp_type);
1258
1259 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1260                        struct ib_udata *udata);
1261
1262 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1263 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt,
1264                          struct hns_roce_db *db);
1265 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1266                             struct hns_roce_db *db);
1267 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1268                       int order);
1269 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1270
1271 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1272 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1273 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp);
1274 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1275 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1276 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index);
1277 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1278 int hns_roce_init(struct hns_roce_dev *hr_dev);
1279 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1280 int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
1281                                struct ib_cq *ib_cq);
1282 struct hns_user_mmap_entry *
1283 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
1284                                 size_t length,
1285                                 enum hns_roce_mmap_type mmap_type);
1286 #endif /* _HNS_ROCE_DEVICE_H */