drivers/infiniband/hw/hns/hns_roce_device.h

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _HNS_ROCE_DEVICE_H
  34 #define _HNS_ROCE_DEVICE_H
  35
  36 #include <rdma/ib_verbs.h>
  37
  38 #define DRV_NAME "hns_roce"
  39
  40 /* hip08 is a pci device */
  41 #define PCI_REVISION_ID_HIP08                   0x21
  42
  43 #define HNS_ROCE_HW_VER1        ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
  44
  45 #define HNS_ROCE_MAX_MSG_LEN                    0x80000000
  46
  47 #define HNS_ROCE_IB_MIN_SQ_STRIDE               6
  48
  49 #define HNS_ROCE_BA_SIZE                        (32 * 4096)
  50
  51 #define BA_BYTE_LEN                             8
  52
  53 /* Hardware specification only for v1 engine */
  54 #define HNS_ROCE_MIN_CQE_NUM                    0x40
  55 #define HNS_ROCE_MIN_WQE_NUM                    0x20
  56
  57 /* Hardware specification only for v1 engine */
  58 #define HNS_ROCE_MAX_INNER_MTPT_NUM             0x7
  59 #define HNS_ROCE_MAX_MTPT_PBL_NUM               0x100000
  60 #define HNS_ROCE_MAX_SGE_NUM                    2
  61
  62 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS        20
  63 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT   \
  64         (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
  65 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT             0x2
  66 #define HNS_ROCE_MIN_CQE_CNT                    16
  67
  68 #define HNS_ROCE_RESERVED_SGE                   1
  69
  70 #define HNS_ROCE_MAX_IRQ_NUM                    128
  71
  72 #define HNS_ROCE_SGE_IN_WQE                     2
  73 #define HNS_ROCE_SGE_SHIFT                      4
  74
  75 #define EQ_ENABLE                               1
  76 #define EQ_DISABLE                              0
  77
  78 #define HNS_ROCE_CEQ                            0
  79 #define HNS_ROCE_AEQ                            1
  80
  81 #define HNS_ROCE_CEQ_ENTRY_SIZE                 0x4
  82 #define HNS_ROCE_AEQ_ENTRY_SIZE                 0x10
  83
  84 #define HNS_ROCE_SL_SHIFT                       28
  85 #define HNS_ROCE_TCLASS_SHIFT                   20
  86 #define HNS_ROCE_FLOW_LABEL_MASK                0xfffff
  87
  88 #define HNS_ROCE_MAX_PORTS                      6
  89 #define HNS_ROCE_MAX_GID_NUM                    16
  90 #define HNS_ROCE_GID_SIZE                       16
  91 #define HNS_ROCE_SGE_SIZE                       16
  92
  93 #define HNS_ROCE_HOP_NUM_0                      0xff
  94
  95 #define BITMAP_NO_RR                            0
  96 #define BITMAP_RR                               1
  97
  98 #define MR_TYPE_MR                              0x00
  99 #define MR_TYPE_FRMR                            0x01
 100 #define MR_TYPE_DMA                             0x03
 101
 102 #define HNS_ROCE_FRMR_MAX_PA                    512
 103
 104 #define PKEY_ID                                 0xffff
 105 #define GUID_LEN                                8
 106 #define NODE_DESC_SIZE                          64
 107 #define DB_REG_OFFSET                           0x1000
 108
 109 /* Configure to HW for PAGE_SIZE larger than 4KB */
 110 #define PG_SHIFT_OFFSET                         (PAGE_SHIFT - 12)
 111
 112 #define PAGES_SHIFT_8                           8
 113 #define PAGES_SHIFT_16                          16
 114 #define PAGES_SHIFT_24                          24
 115 #define PAGES_SHIFT_32                          32
 116
 117 #define HNS_ROCE_PCI_BAR_NUM                    2
 118
 119 #define HNS_ROCE_IDX_QUE_ENTRY_SZ               4
 120 #define SRQ_DB_REG                              0x230
 121
 122 /* The chip implementation of the consumer index is calculated
 123  * according to twice the actual EQ depth
 124  */
 125 #define EQ_DEPTH_COEFF                          2
 126
 127 enum {
 128         SERV_TYPE_RC,
 129         SERV_TYPE_UC,
 130         SERV_TYPE_RD,
 131         SERV_TYPE_UD,
 132 };
 133
 134 enum {
 135         HNS_ROCE_QP_CAP_RQ_RECORD_DB = BIT(0),
 136         HNS_ROCE_QP_CAP_SQ_RECORD_DB = BIT(1),
 137 };
 138
 139 enum hns_roce_cq_flags {
 140         HNS_ROCE_CQ_FLAG_RECORD_DB = BIT(0),
 141 };
 142
 143 enum hns_roce_qp_state {
 144         HNS_ROCE_QP_STATE_RST,
 145         HNS_ROCE_QP_STATE_INIT,
 146         HNS_ROCE_QP_STATE_RTR,
 147         HNS_ROCE_QP_STATE_RTS,
 148         HNS_ROCE_QP_STATE_SQD,
 149         HNS_ROCE_QP_STATE_ERR,
 150         HNS_ROCE_QP_NUM_STATE,
 151 };
 152
 153 enum hns_roce_event {
 154         HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
 155         HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
 156         HNS_ROCE_EVENT_TYPE_COMM_EST                  = 0x03,
 157         HNS_ROCE_EVENT_TYPE_SQ_DRAINED                = 0x04,
 158         HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR            = 0x05,
 159         HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR    = 0x06,
 160         HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR     = 0x07,
 161         HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH           = 0x08,
 162         HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH        = 0x09,
 163         HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR           = 0x0a,
 164         HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR           = 0x0b,
 165         HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW               = 0x0c,
 166         HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID             = 0x0d,
 167         HNS_ROCE_EVENT_TYPE_PORT_CHANGE               = 0x0f,
 168         /* 0x10 and 0x11 is unused in currently application case */
 169         HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,
 170         HNS_ROCE_EVENT_TYPE_MB                        = 0x13,
 171         HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW              = 0x14,
 172         HNS_ROCE_EVENT_TYPE_FLR                       = 0x15,
 173 };
 174
 175 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
 176 enum {
 177         HNS_ROCE_LWQCE_QPC_ERROR                = 1,
 178         HNS_ROCE_LWQCE_MTU_ERROR                = 2,
 179         HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR        = 3,
 180         HNS_ROCE_LWQCE_WQE_ADDR_ERROR           = 4,
 181         HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR       = 5,
 182         HNS_ROCE_LWQCE_SL_ERROR                 = 6,
 183         HNS_ROCE_LWQCE_PORT_ERROR               = 7,
 184 };
 185
 186 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
 187 enum {
 188         HNS_ROCE_LAVWQE_R_KEY_VIOLATION         = 1,
 189         HNS_ROCE_LAVWQE_LENGTH_ERROR            = 2,
 190         HNS_ROCE_LAVWQE_VA_ERROR                = 3,
 191         HNS_ROCE_LAVWQE_PD_ERROR                = 4,
 192         HNS_ROCE_LAVWQE_RW_ACC_ERROR            = 5,
 193         HNS_ROCE_LAVWQE_KEY_STATE_ERROR         = 6,
 194         HNS_ROCE_LAVWQE_MR_OPERATION_ERROR      = 7,
 195 };
 196
 197 /* DOORBELL overflow subtype */
 198 enum {
 199         HNS_ROCE_DB_SUBTYPE_SDB_OVF             = 1,
 200         HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF         = 2,
 201         HNS_ROCE_DB_SUBTYPE_ODB_OVF             = 3,
 202         HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF         = 4,
 203         HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP         = 5,
 204         HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP         = 6,
 205 };
 206
 207 enum {
 208         /* RQ&SRQ related operations */
 209         HNS_ROCE_OPCODE_SEND_DATA_RECEIVE       = 0x06,
 210         HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE   = 0x07,
 211 };
 212
 213 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12
 214
 215 enum {
 216         HNS_ROCE_CAP_FLAG_REREG_MR              = BIT(0),
 217         HNS_ROCE_CAP_FLAG_ROCE_V1_V2            = BIT(1),
 218         HNS_ROCE_CAP_FLAG_RQ_INLINE             = BIT(2),
 219         HNS_ROCE_CAP_FLAG_RECORD_DB             = BIT(3),
 220         HNS_ROCE_CAP_FLAG_SQ_RECORD_DB          = BIT(4),
 221         HNS_ROCE_CAP_FLAG_SRQ                   = BIT(5),
 222         HNS_ROCE_CAP_FLAG_MW                    = BIT(7),
 223         HNS_ROCE_CAP_FLAG_FRMR                  = BIT(8),
 224         HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL          = BIT(9),
 225         HNS_ROCE_CAP_FLAG_ATOMIC                = BIT(10),
 226 };
 227
 228 #define HNS_ROCE_DB_TYPE_COUNT                  2
 229 #define HNS_ROCE_DB_UNIT_SIZE                   4
 230
 231 enum {
 232         HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
 233 };
 234
 235 enum hns_roce_reset_stage {
 236         HNS_ROCE_STATE_NON_RST,
 237         HNS_ROCE_STATE_RST_BEF_DOWN,
 238         HNS_ROCE_STATE_RST_DOWN,
 239         HNS_ROCE_STATE_RST_UNINIT,
 240         HNS_ROCE_STATE_RST_INIT,
 241         HNS_ROCE_STATE_RST_INITED,
 242 };
 243
 244 enum hns_roce_instance_state {
 245         HNS_ROCE_STATE_NON_INIT,
 246         HNS_ROCE_STATE_INIT,
 247         HNS_ROCE_STATE_INITED,
 248         HNS_ROCE_STATE_UNINIT,
 249 };
 250
 251 enum {
 252         HNS_ROCE_RST_DIRECT_RETURN              = 0,
 253 };
 254
 255 enum {
 256         CMD_RST_PRC_OTHERS,
 257         CMD_RST_PRC_SUCCESS,
 258         CMD_RST_PRC_EBUSY,
 259 };
 260
 261 #define HNS_ROCE_CMD_SUCCESS                    1
 262
 263 #define HNS_ROCE_PORT_DOWN                      0
 264 #define HNS_ROCE_PORT_UP                        1
 265
 266 /* The minimum page size is 4K for hardware */
 267 #define HNS_HW_PAGE_SHIFT                       12
 268 #define HNS_HW_PAGE_SIZE                        (1 << HNS_HW_PAGE_SHIFT)
 269
 270 /* The minimum page count for hardware access page directly. */
 271 #define HNS_HW_DIRECT_PAGE_COUNT 2
 272
 273 struct hns_roce_uar {
 274         u64             pfn;
 275         unsigned long   index;
 276         unsigned long   logic_idx;
 277 };
 278
 279 struct hns_roce_ucontext {
 280         struct ib_ucontext      ibucontext;
 281         struct hns_roce_uar     uar;
 282         struct list_head        page_list;
 283         struct mutex            page_mutex;
 284 };
 285
 286 struct hns_roce_pd {
 287         struct ib_pd            ibpd;
 288         unsigned long           pdn;
 289 };
 290
 291 struct hns_roce_bitmap {
 292         /* Bitmap Traversal last a bit which is 1 */
 293         unsigned long           last;
 294         unsigned long           top;
 295         unsigned long           max;
 296         unsigned long           reserved_top;
 297         unsigned long           mask;
 298         spinlock_t              lock;
 299         unsigned long           *table;
 300 };
 301
 302 /* For Hardware Entry Memory */
 303 struct hns_roce_hem_table {
 304         /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
 305         u32             type;
 306         /* HEM array elment num */
 307         unsigned long   num_hem;
 308         /* HEM entry record obj total num */
 309         unsigned long   num_obj;
 310         /* Single obj size */
 311         unsigned long   obj_size;
 312         unsigned long   table_chunk_size;
 313         int             lowmem;
 314         struct mutex    mutex;
 315         struct hns_roce_hem **hem;
 316         u64             **bt_l1;
 317         dma_addr_t      *bt_l1_dma_addr;
 318         u64             **bt_l0;
 319         dma_addr_t      *bt_l0_dma_addr;
 320 };
 321
 322 struct hns_roce_buf_region {
 323         int offset; /* page offset */
 324         u32 count; /* page count */
 325         int hopnum; /* addressing hop num */
 326 };
 327
 328 #define HNS_ROCE_MAX_BT_REGION  3
 329 #define HNS_ROCE_MAX_BT_LEVEL   3
 330 struct hns_roce_hem_list {
 331         struct list_head root_bt;
 332         /* link all bt dma mem by hop config */
 333         struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
 334         struct list_head btm_bt; /* link all bottom bt in @mid_bt */
 335         dma_addr_t root_ba; /* pointer to the root ba table */
 336 };
 337
 338 struct hns_roce_buf_attr {
 339         struct {
 340                 size_t  size;  /* region size */
 341                 int     hopnum; /* multi-hop addressing hop num */
 342         } region[HNS_ROCE_MAX_BT_REGION];
 343         int region_count; /* valid region count */
 344         unsigned int page_shift;  /* buffer page shift */
 345         bool fixed_page; /* decide page shift is fixed-size or maximum size */
 346         int user_access; /* umem access flag */
 347         bool mtt_only; /* only alloc buffer-required MTT memory */
 348 };
 349
 350 struct hns_roce_hem_cfg {
 351         dma_addr_t      root_ba; /* root BA table's address */
 352         bool            is_direct; /* addressing without BA table */
 353         unsigned int    ba_pg_shift; /* BA table page shift */
 354         unsigned int    buf_pg_shift; /* buffer page shift */
 355         unsigned int    buf_pg_count;  /* buffer page count */
 356         struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
 357         int             region_count;
 358 };
 359
 360 /* memory translate region */
 361 struct hns_roce_mtr {
 362         struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
 363         struct ib_umem          *umem; /* user space buffer */
 364         struct hns_roce_buf     *kmem; /* kernel space buffer */
 365         struct hns_roce_hem_cfg  hem_cfg; /* config for hardware addressing */
 366 };
 367
 368 struct hns_roce_mw {
 369         struct ib_mw            ibmw;
 370         u32                     pdn;
 371         u32                     rkey;
 372         int                     enabled; /* MW's active status */
 373         u32                     pbl_hop_num;
 374         u32                     pbl_ba_pg_sz;
 375         u32                     pbl_buf_pg_sz;
 376 };
 377
 378 /* Only support 4K page size for mr register */
 379 #define MR_SIZE_4K 0
 380
 381 struct hns_roce_mr {
 382         struct ib_mr            ibmr;
 383         u64                     iova; /* MR's virtual orignal addr */
 384         u64                     size; /* Address range of MR */
 385         u32                     key; /* Key of MR */
 386         u32                     pd;   /* PD num of MR */
 387         u32                     access; /* Access permission of MR */
 388         int                     enabled; /* MR's active status */
 389         int                     type;   /* MR's register type */
 390         u32                     pbl_hop_num;    /* multi-hop number */
 391         struct hns_roce_mtr     pbl_mtr;
 392         u32                     npages;
 393         dma_addr_t              *page_list;
 394 };
 395
 396 struct hns_roce_mr_table {
 397         struct hns_roce_bitmap          mtpt_bitmap;
 398         struct hns_roce_hem_table       mtpt_table;
 399 };
 400
 401 struct hns_roce_wq {
 402         u64             *wrid;     /* Work request ID */
 403         spinlock_t      lock;
 404         u32             wqe_cnt;  /* WQE num */
 405         int             max_gs;
 406         int             offset;
 407         int             wqe_shift;      /* WQE size */
 408         u32             head;
 409         u32             tail;
 410         void __iomem    *db_reg_l;
 411 };
 412
 413 struct hns_roce_sge {
 414         unsigned int    sge_cnt;        /* SGE num */
 415         int             offset;
 416         int             sge_shift;      /* SGE size */
 417 };
 418
 419 struct hns_roce_buf_list {
 420         void            *buf;
 421         dma_addr_t      map;
 422 };
 423
 424 struct hns_roce_buf {
 425         struct hns_roce_buf_list        direct;
 426         struct hns_roce_buf_list        *page_list;
 427         u32                             npages;
 428         u32                             size;
 429         unsigned int                    page_shift;
 430 };
 431
 432 struct hns_roce_db_pgdir {
 433         struct list_head        list;
 434         DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
 435         DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
 436         unsigned long           *bits[HNS_ROCE_DB_TYPE_COUNT];
 437         u32                     *page;
 438         dma_addr_t              db_dma;
 439 };
 440
 441 struct hns_roce_user_db_page {
 442         struct list_head        list;
 443         struct ib_umem          *umem;
 444         unsigned long           user_virt;
 445         refcount_t              refcount;
 446 };
 447
 448 struct hns_roce_db {
 449         u32             *db_record;
 450         union {
 451                 struct hns_roce_db_pgdir *pgdir;
 452                 struct hns_roce_user_db_page *user_page;
 453         } u;
 454         dma_addr_t      dma;
 455         void            *virt_addr;
 456         int             index;
 457         int             order;
 458 };
 459
 460 struct hns_roce_cq {
 461         struct ib_cq                    ib_cq;
 462         struct hns_roce_mtr             mtr;
 463         struct hns_roce_db              db;
 464         u32                             flags;
 465         spinlock_t                      lock;
 466         u32                             cq_depth;
 467         u32                             cons_index;
 468         u32                             *set_ci_db;
 469         void __iomem                    *cq_db_l;
 470         u16                             *tptr_addr;
 471         int                             arm_sn;
 472         unsigned long                   cqn;
 473         u32                             vector;
 474         atomic_t                        refcount;
 475         struct completion               free;
 476         struct list_head                sq_list; /* all qps on this send cq */
 477         struct list_head                rq_list; /* all qps on this recv cq */
 478         int                             is_armed; /* cq is armed */
 479         struct list_head                node; /* all armed cqs are on a list */
 480 };
 481
 482 struct hns_roce_idx_que {
 483         struct hns_roce_mtr             mtr;
 484         int                             entry_shift;
 485         unsigned long                   *bitmap;
 486 };
 487
 488 struct hns_roce_srq {
 489         struct ib_srq           ibsrq;
 490         unsigned long           srqn;
 491         u32                     wqe_cnt;
 492         int                     max_gs;
 493         int                     wqe_shift;
 494         void __iomem            *db_reg_l;
 495
 496         atomic_t                refcount;
 497         struct completion       free;
 498
 499         struct hns_roce_mtr     buf_mtr;
 500
 501         u64                    *wrid;
 502         struct hns_roce_idx_que idx_que;
 503         spinlock_t              lock;
 504         int                     head;
 505         int                     tail;
 506         struct mutex            mutex;
 507         void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
 508 };
 509
 510 struct hns_roce_uar_table {
 511         struct hns_roce_bitmap bitmap;
 512 };
 513
 514 struct hns_roce_qp_table {
 515         struct hns_roce_bitmap          bitmap;
 516         struct hns_roce_hem_table       qp_table;
 517         struct hns_roce_hem_table       irrl_table;
 518         struct hns_roce_hem_table       trrl_table;
 519         struct hns_roce_hem_table       sccc_table;
 520         struct mutex                    scc_mutex;
 521 };
 522
 523 struct hns_roce_cq_table {
 524         struct hns_roce_bitmap          bitmap;
 525         struct xarray                   array;
 526         struct hns_roce_hem_table       table;
 527 };
 528
 529 struct hns_roce_srq_table {
 530         struct hns_roce_bitmap          bitmap;
 531         struct xarray                   xa;
 532         struct hns_roce_hem_table       table;
 533 };
 534
 535 struct hns_roce_raq_table {
 536         struct hns_roce_buf_list        *e_raq_buf;
 537 };
 538
 539 struct hns_roce_av {
 540         u8          port;
 541         u8          gid_index;
 542         u8          stat_rate;
 543         u8          hop_limit;
 544         u32         flowlabel;
 545         u8          sl;
 546         u8          tclass;
 547         u8          dgid[HNS_ROCE_GID_SIZE];
 548         u8          mac[ETH_ALEN];
 549         u16         vlan_id;
 550         bool        vlan_en;
 551 };
 552
 553 struct hns_roce_ah {
 554         struct ib_ah            ibah;
 555         struct hns_roce_av      av;
 556 };
 557
 558 struct hns_roce_cmd_context {
 559         struct completion       done;
 560         int                     result;
 561         int                     next;
 562         u64                     out_param;
 563         u16                     token;
 564 };
 565
 566 struct hns_roce_cmdq {
 567         struct dma_pool         *pool;
 568         struct mutex            hcr_mutex;
 569         struct semaphore        poll_sem;
 570         /*
 571          * Event mode: cmd register mutex protection,
 572          * ensure to not exceed max_cmds and user use limit region
 573          */
 574         struct semaphore        event_sem;
 575         int                     max_cmds;
 576         spinlock_t              context_lock;
 577         int                     free_head;
 578         struct hns_roce_cmd_context *context;
 579         /*
 580          * Result of get integer part
 581          * which max_comds compute according a power of 2
 582          */
 583         u16                     token_mask;
 584         /*
 585          * Process whether use event mode, init default non-zero
 586          * After the event queue of cmd event ready,
 587          * can switch into event mode
 588          * close device, switch into poll mode(non event mode)
 589          */
 590         u8                      use_events;
 591 };
 592
 593 struct hns_roce_cmd_mailbox {
 594         void                   *buf;
 595         dma_addr_t              dma;
 596 };
 597
 598 struct hns_roce_dev;
 599
 600 struct hns_roce_rinl_sge {
 601         void                    *addr;
 602         u32                     len;
 603 };
 604
 605 struct hns_roce_rinl_wqe {
 606         struct hns_roce_rinl_sge *sg_list;
 607         u32                      sge_cnt;
 608 };
 609
 610 struct hns_roce_rinl_buf {
 611         struct hns_roce_rinl_wqe *wqe_list;
 612         u32                      wqe_cnt;
 613 };
 614
 615 enum {
 616         HNS_ROCE_FLUSH_FLAG = 0,
 617 };
 618
 619 struct hns_roce_work {
 620         struct hns_roce_dev *hr_dev;
 621         struct work_struct work;
 622         u32 qpn;
 623         u32 cqn;
 624         int event_type;
 625         int sub_type;
 626 };
 627
 628 struct hns_roce_qp {
 629         struct ib_qp            ibqp;
 630         struct hns_roce_wq      rq;
 631         struct hns_roce_db      rdb;
 632         struct hns_roce_db      sdb;
 633         unsigned long           en_flags;
 634         u32                     doorbell_qpn;
 635         u32                     sq_signal_bits;
 636         struct hns_roce_wq      sq;
 637
 638         struct hns_roce_mtr     mtr;
 639
 640         u32                     buff_size;
 641         struct mutex            mutex;
 642         u8                      port;
 643         u8                      phy_port;
 644         u8                      sl;
 645         u8                      resp_depth;
 646         u8                      state;
 647         u32                     access_flags;
 648         u32                     atomic_rd_en;
 649         u32                     pkey_index;
 650         u32                     qkey;
 651         void                    (*event)(struct hns_roce_qp *qp,
 652                                          enum hns_roce_event event_type);
 653         unsigned long           qpn;
 654
 655         atomic_t                refcount;
 656         struct completion       free;
 657
 658         struct hns_roce_sge     sge;
 659         u32                     next_sge;
 660
 661         /* 0: flush needed, 1: unneeded */
 662         unsigned long           flush_flag;
 663         struct hns_roce_work    flush_work;
 664         struct hns_roce_rinl_buf rq_inl_buf;
 665         struct list_head        node;           /* all qps are on a list */
 666         struct list_head        rq_node;        /* all recv qps are on a list */
 667         struct list_head        sq_node;        /* all send qps are on a list */
 668 };
 669
 670 struct hns_roce_ib_iboe {
 671         spinlock_t              lock;
 672         struct net_device      *netdevs[HNS_ROCE_MAX_PORTS];
 673         struct notifier_block   nb;
 674         u8                      phy_port[HNS_ROCE_MAX_PORTS];
 675 };
 676
 677 enum {
 678         HNS_ROCE_EQ_STAT_INVALID  = 0,
 679         HNS_ROCE_EQ_STAT_VALID    = 2,
 680 };
 681
 682 struct hns_roce_ceqe {
 683         __le32                  comp;
 684 };
 685
 686 struct hns_roce_aeqe {
 687         __le32 asyn;
 688         union {
 689                 struct {
 690                         __le32 qp;
 691                         u32 rsv0;
 692                         u32 rsv1;
 693                 } qp_event;
 694
 695                 struct {
 696                         __le32 srq;
 697                         u32 rsv0;
 698                         u32 rsv1;
 699                 } srq_event;
 700
 701                 struct {
 702                         __le32 cq;
 703                         u32 rsv0;
 704                         u32 rsv1;
 705                 } cq_event;
 706
 707                 struct {
 708                         __le32 ceqe;
 709                         u32 rsv0;
 710                         u32 rsv1;
 711                 } ce_event;
 712
 713                 struct {
 714                         __le64  out_param;
 715                         __le16  token;
 716                         u8      status;
 717                         u8      rsv0;
 718                 } __packed cmd;
 719          } event;
 720 };
 721
 722 struct hns_roce_eq {
 723         struct hns_roce_dev             *hr_dev;
 724         void __iomem                    *doorbell;
 725
 726         int                             type_flag; /* Aeq:1 ceq:0 */
 727         int                             eqn;
 728         u32                             entries;
 729         int                             log_entries;
 730         int                             eqe_size;
 731         int                             irq;
 732         int                             log_page_size;
 733         int                             cons_index;
 734         struct hns_roce_buf_list        *buf_list;
 735         int                             over_ignore;
 736         int                             coalesce;
 737         int                             arm_st;
 738         int                             hop_num;
 739         struct hns_roce_mtr             mtr;
 740         u16                             eq_max_cnt;
 741         int                             eq_period;
 742         int                             shift;
 743         int                             event_type;
 744         int                             sub_type;
 745 };
 746
 747 struct hns_roce_eq_table {
 748         struct hns_roce_eq      *eq;
 749         void __iomem            **eqc_base; /* only for hw v1 */
 750 };
 751
 752 struct hns_roce_caps {
 753         u64             fw_ver;
 754         u8              num_ports;
 755         int             gid_table_len[HNS_ROCE_MAX_PORTS];
 756         int             pkey_table_len[HNS_ROCE_MAX_PORTS];
 757         int             local_ca_ack_delay;
 758         int             num_uars;
 759         u32             phy_num_uars;
 760         u32             max_sq_sg;
 761         u32             max_sq_inline;
 762         u32             max_rq_sg;
 763         u32             max_extend_sg;
 764         int             num_qps;
 765         int             reserved_qps;
 766         int             num_qpc_timer;
 767         int             num_cqc_timer;
 768         int             num_srqs;
 769         u32             max_wqes;
 770         u32             max_srq_wrs;
 771         u32             max_srq_sges;
 772         u32             max_sq_desc_sz;
 773         u32             max_rq_desc_sz;
 774         u32             max_srq_desc_sz;
 775         int             max_qp_init_rdma;
 776         int             max_qp_dest_rdma;
 777         int             num_cqs;
 778         u32             max_cqes;
 779         u32             min_cqes;
 780         u32             min_wqes;
 781         int             reserved_cqs;
 782         int             reserved_srqs;
 783         int             num_aeq_vectors;
 784         int             num_comp_vectors;
 785         int             num_other_vectors;
 786         int             num_mtpts;
 787         u32             num_mtt_segs;
 788         u32             num_cqe_segs;
 789         u32             num_srqwqe_segs;
 790         u32             num_idx_segs;
 791         int             reserved_mrws;
 792         int             reserved_uars;
 793         int             num_pds;
 794         int             reserved_pds;
 795         u32             mtt_entry_sz;
 796         u32             cq_entry_sz;
 797         u32             page_size_cap;
 798         u32             reserved_lkey;
 799         int             mtpt_entry_sz;
 800         int             qpc_entry_sz;
 801         int             irrl_entry_sz;
 802         int             trrl_entry_sz;
 803         int             cqc_entry_sz;
 804         int             sccc_entry_sz;
 805         int             qpc_timer_entry_sz;
 806         int             cqc_timer_entry_sz;
 807         int             srqc_entry_sz;
 808         int             idx_entry_sz;
 809         u32             pbl_ba_pg_sz;
 810         u32             pbl_buf_pg_sz;
 811         u32             pbl_hop_num;
 812         int             aeqe_depth;
 813         int             ceqe_depth;
 814         enum ib_mtu     max_mtu;
 815         u32             qpc_bt_num;
 816         u32             qpc_timer_bt_num;
 817         u32             srqc_bt_num;
 818         u32             cqc_bt_num;
 819         u32             cqc_timer_bt_num;
 820         u32             mpt_bt_num;
 821         u32             sccc_bt_num;
 822         u32             qpc_ba_pg_sz;
 823         u32             qpc_buf_pg_sz;
 824         u32             qpc_hop_num;
 825         u32             srqc_ba_pg_sz;
 826         u32             srqc_buf_pg_sz;
 827         u32             srqc_hop_num;
 828         u32             cqc_ba_pg_sz;
 829         u32             cqc_buf_pg_sz;
 830         u32             cqc_hop_num;
 831         u32             mpt_ba_pg_sz;
 832         u32             mpt_buf_pg_sz;
 833         u32             mpt_hop_num;
 834         u32             mtt_ba_pg_sz;
 835         u32             mtt_buf_pg_sz;
 836         u32             mtt_hop_num;
 837         u32             wqe_sq_hop_num;
 838         u32             wqe_sge_hop_num;
 839         u32             wqe_rq_hop_num;
 840         u32             sccc_ba_pg_sz;
 841         u32             sccc_buf_pg_sz;
 842         u32             sccc_hop_num;
 843         u32             qpc_timer_ba_pg_sz;
 844         u32             qpc_timer_buf_pg_sz;
 845         u32             qpc_timer_hop_num;
 846         u32             cqc_timer_ba_pg_sz;
 847         u32             cqc_timer_buf_pg_sz;
 848         u32             cqc_timer_hop_num;
 849         u32             cqe_ba_pg_sz;   /* page_size = 4K*(2^cqe_ba_pg_sz) */
 850         u32             cqe_buf_pg_sz;
 851         u32             cqe_hop_num;
 852         u32             srqwqe_ba_pg_sz;
 853         u32             srqwqe_buf_pg_sz;
 854         u32             srqwqe_hop_num;
 855         u32             idx_ba_pg_sz;
 856         u32             idx_buf_pg_sz;
 857         u32             idx_hop_num;
 858         u32             eqe_ba_pg_sz;
 859         u32             eqe_buf_pg_sz;
 860         u32             eqe_hop_num;
 861         u32             sl_num;
 862         u32             tsq_buf_pg_sz;
 863         u32             tpq_buf_pg_sz;
 864         u32             chunk_sz;       /* chunk size in non multihop mode */
 865         u64             flags;
 866         u16             default_ceq_max_cnt;
 867         u16             default_ceq_period;
 868         u16             default_aeq_max_cnt;
 869         u16             default_aeq_period;
 870         u16             default_aeq_arm_st;
 871         u16             default_ceq_arm_st;
 872 };
 873
 874 struct hns_roce_dfx_hw {
 875         int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
 876                               int *buffer);
 877 };
 878
 879 enum hns_roce_device_state {
 880         HNS_ROCE_DEVICE_STATE_INITED,
 881         HNS_ROCE_DEVICE_STATE_RST_DOWN,
 882         HNS_ROCE_DEVICE_STATE_UNINIT,
 883 };
 884
 885 struct hns_roce_hw {
 886         int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
 887         int (*cmq_init)(struct hns_roce_dev *hr_dev);
 888         void (*cmq_exit)(struct hns_roce_dev *hr_dev);
 889         int (*hw_profile)(struct hns_roce_dev *hr_dev);
 890         int (*hw_init)(struct hns_roce_dev *hr_dev);
 891         void (*hw_exit)(struct hns_roce_dev *hr_dev);
 892         int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
 893                          u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
 894                          u16 token, int event);
 895         int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
 896         int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev);
 897         int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
 898                        const union ib_gid *gid, const struct ib_gid_attr *attr);
 899         int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
 900         void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
 901                         enum ib_mtu mtu);
 902         int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
 903                           struct hns_roce_mr *mr, unsigned long mtpt_idx);
 904         int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
 905                                 struct hns_roce_mr *mr, int flags, u32 pdn,
 906                                 int mr_access_flags, u64 iova, u64 size,
 907                                 void *mb_buf);
 908         int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
 909                                struct hns_roce_mr *mr);
 910         int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
 911         void (*write_cqc)(struct hns_roce_dev *hr_dev,
 912                           struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
 913                           dma_addr_t dma_handle);
 914         int (*set_hem)(struct hns_roce_dev *hr_dev,
 915                        struct hns_roce_hem_table *table, int obj, int step_idx);
 916         int (*clear_hem)(struct hns_roce_dev *hr_dev,
 917                          struct hns_roce_hem_table *table, int obj,
 918                          int step_idx);
 919         int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
 920                         int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
 921         int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
 922                          int attr_mask, enum ib_qp_state cur_state,
 923                          enum ib_qp_state new_state);
 924         int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata);
 925         int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
 926                          struct hns_roce_qp *hr_qp);
 927         int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 928                          const struct ib_send_wr **bad_wr);
 929         int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr,
 930                          const struct ib_recv_wr **bad_recv_wr);
 931         int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 932         int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 933         int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
 934                         struct ib_udata *udata);
 935         void (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
 936         int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
 937         int (*init_eq)(struct hns_roce_dev *hr_dev);
 938         void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
 939         void (*write_srqc)(struct hns_roce_dev *hr_dev,
 940                            struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn,
 941                            void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx,
 942                            dma_addr_t dma_handle_wqe,
 943                            dma_addr_t dma_handle_idx);
 944         int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
 945                        enum ib_srq_attr_mask srq_attr_mask,
 946                        struct ib_udata *udata);
 947         int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr);
 948         int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
 949                              const struct ib_recv_wr **bad_wr);
 950         const struct ib_device_ops *hns_roce_dev_ops;
 951         const struct ib_device_ops *hns_roce_dev_srq_ops;
 952 };
 953
 954 struct hns_roce_dev {
 955         struct ib_device        ib_dev;
 956         struct platform_device  *pdev;
 957         struct pci_dev          *pci_dev;
 958         struct device           *dev;
 959         struct hns_roce_uar     priv_uar;
 960         const char              *irq_names[HNS_ROCE_MAX_IRQ_NUM];
 961         spinlock_t              sm_lock;
 962         spinlock_t              bt_cmd_lock;
 963         bool                    active;
 964         bool                    is_reset;
 965         bool                    dis_db;
 966         unsigned long           reset_cnt;
 967         struct hns_roce_ib_iboe iboe;
 968         enum hns_roce_device_state state;
 969         struct list_head        qp_list; /* list of all qps on this dev */
 970         spinlock_t              qp_list_lock; /* protect qp_list */
 971
 972         struct list_head        pgdir_list;
 973         struct mutex            pgdir_mutex;
 974         int                     irq[HNS_ROCE_MAX_IRQ_NUM];
 975         u8 __iomem              *reg_base;
 976         struct hns_roce_caps    caps;
 977         struct xarray           qp_table_xa;
 978
 979         unsigned char   dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
 980         u64                     sys_image_guid;
 981         u32                     vendor_id;
 982         u32                     vendor_part_id;
 983         u32                     hw_rev;
 984         void __iomem            *priv_addr;
 985
 986         struct hns_roce_cmdq    cmd;
 987         struct hns_roce_bitmap    pd_bitmap;
 988         struct hns_roce_uar_table uar_table;
 989         struct hns_roce_mr_table  mr_table;
 990         struct hns_roce_cq_table  cq_table;
 991         struct hns_roce_srq_table srq_table;
 992         struct hns_roce_qp_table  qp_table;
 993         struct hns_roce_eq_table  eq_table;
 994         struct hns_roce_hem_table  qpc_timer_table;
 995         struct hns_roce_hem_table  cqc_timer_table;
 996
 997         int                     cmd_mod;
 998         int                     loop_idc;
 999         u32                     sdb_offset;
1000         u32                     odb_offset;
1001         dma_addr_t              tptr_dma_addr;  /* only for hw v1 */
1002         u32                     tptr_size;      /* only for hw v1 */
1003         const struct hns_roce_hw *hw;
1004         void                    *priv;
1005         struct workqueue_struct *irq_workq;
1006         const struct hns_roce_dfx_hw *dfx;
1007 };
1008
1009 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
1010 {
1011         return container_of(ib_dev, struct hns_roce_dev, ib_dev);
1012 }
1013
1014 static inline struct hns_roce_ucontext
1015                         *to_hr_ucontext(struct ib_ucontext *ibucontext)
1016 {
1017         return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1018 }
1019
1020 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1021 {
1022         return container_of(ibpd, struct hns_roce_pd, ibpd);
1023 }
1024
1025 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1026 {
1027         return container_of(ibah, struct hns_roce_ah, ibah);
1028 }
1029
1030 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1031 {
1032         return container_of(ibmr, struct hns_roce_mr, ibmr);
1033 }
1034
1035 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1036 {
1037         return container_of(ibmw, struct hns_roce_mw, ibmw);
1038 }
1039
1040 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1041 {
1042         return container_of(ibqp, struct hns_roce_qp, ibqp);
1043 }
1044
1045 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1046 {
1047         return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1048 }
1049
1050 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1051 {
1052         return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1053 }
1054
1055 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1056 {
1057         __raw_writeq(*(u64 *) val, dest);
1058 }
1059
1060 static inline struct hns_roce_qp
1061         *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1062 {
1063         return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1));
1064 }
1065
1066 static inline bool hns_roce_buf_is_direct(struct hns_roce_buf *buf)
1067 {
1068         if (buf->page_list)
1069                 return false;
1070
1071         return true;
1072 }
1073
1074 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
1075 {
1076         if (hns_roce_buf_is_direct(buf))
1077                 return (char *)(buf->direct.buf) + (offset & (buf->size - 1));
1078
1079         return (char *)(buf->page_list[offset >> buf->page_shift].buf) +
1080                (offset & ((1 << buf->page_shift) - 1));
1081 }
1082
1083 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, int idx)
1084 {
1085         if (hns_roce_buf_is_direct(buf))
1086                 return buf->direct.map + ((dma_addr_t)idx << buf->page_shift);
1087         else
1088                 return buf->page_list[idx].map;
1089 }
1090
1091 #define hr_hw_page_align(x)             ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1092
1093 static inline u64 to_hr_hw_page_addr(u64 addr)
1094 {
1095         return addr >> HNS_HW_PAGE_SHIFT;
1096 }
1097
1098 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1099 {
1100         return page_shift - HNS_HW_PAGE_SHIFT;
1101 }
1102
1103 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1104 {
1105         if (count > 0)
1106                 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1107
1108         return 0;
1109 }
1110
1111 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1112 {
1113         return hr_hw_page_align(count << buf_shift);
1114 }
1115
1116 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1117 {
1118         return hr_hw_page_align(count << buf_shift) >> buf_shift;
1119 }
1120
1121 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1122 {
1123         if (!count)
1124                 return 0;
1125
1126         return ilog2(to_hr_hem_entries_count(count, buf_shift));
1127 }
1128
1129 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
1130 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1131 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1132 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
1133
1134 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1135 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1136 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1137                         u64 out_param);
1138 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1139 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1140
1141 /* hns roce hw need current block and next block addr from mtt */
1142 #define MTT_MIN_COUNT    2
1143 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1144                       int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1145 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1146                         struct hns_roce_buf_attr *buf_attr,
1147                         unsigned int page_shift, struct ib_udata *udata,
1148                         unsigned long user_addr);
1149 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1150                           struct hns_roce_mtr *mtr);
1151 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1152                      dma_addr_t *pages, int page_cnt);
1153
1154 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1155 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1156 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1157 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1158 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1159
1160 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
1161 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
1162 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1163 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1164 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1165 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev);
1166
1167 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
1168 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
1169                          int rr);
1170 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
1171                          u32 reserved_bot, u32 resetrved_top);
1172 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
1173 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1174 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
1175                                 int align, unsigned long *obj);
1176 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
1177                                 unsigned long obj, int cnt,
1178                                 int rr);
1179
1180 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1181                        struct ib_udata *udata);
1182 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1183 void hns_roce_destroy_ah(struct ib_ah *ah, u32 flags);
1184
1185 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1186 void hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1187
1188 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1189 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1190                                    u64 virt_addr, int access_flags,
1191                                    struct ib_udata *udata);
1192 int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length,
1193                            u64 virt_addr, int mr_access_flags, struct ib_pd *pd,
1194                            struct ib_udata *udata);
1195 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1196                                 u32 max_num_sg);
1197 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1198                        unsigned int *sg_offset);
1199 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1200 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
1201                             struct hns_roce_cmd_mailbox *mailbox,
1202                             unsigned long mpt_index);
1203 unsigned long key_to_hw_index(u32 key);
1204
1205 struct ib_mw *hns_roce_alloc_mw(struct ib_pd *pd, enum ib_mw_type,
1206                                 struct ib_udata *udata);
1207 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1208
1209 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1210 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
1211                        struct hns_roce_buf *buf, u32 page_shift);
1212
1213 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1214                            int buf_cnt, int start, struct hns_roce_buf *buf);
1215 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1216                            int buf_cnt, int start, struct ib_umem *umem,
1217                            unsigned int page_shift);
1218
1219 int hns_roce_create_srq(struct ib_srq *srq,
1220                         struct ib_srq_init_attr *srq_init_attr,
1221                         struct ib_udata *udata);
1222 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1223                         enum ib_srq_attr_mask srq_attr_mask,
1224                         struct ib_udata *udata);
1225 void hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1226
1227 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
1228                                  struct ib_qp_init_attr *init_attr,
1229                                  struct ib_udata *udata);
1230 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1231                        int attr_mask, struct ib_udata *udata);
1232 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1233 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
1234 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n);
1235 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n);
1236 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
1237                           struct ib_cq *ib_cq);
1238 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1239 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1240                        struct hns_roce_cq *recv_cq);
1241 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1242                          struct hns_roce_cq *recv_cq);
1243 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1244 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1245                          struct ib_udata *udata);
1246 __be32 send_ieth(const struct ib_send_wr *wr);
1247 int to_hr_qp_type(int qp_type);
1248
1249 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1250                        struct ib_udata *udata);
1251
1252 void hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1253 int hns_roce_db_map_user(struct hns_roce_ucontext *context,
1254                          struct ib_udata *udata, unsigned long virt,
1255                          struct hns_roce_db *db);
1256 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1257                             struct hns_roce_db *db);
1258 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1259                       int order);
1260 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1261
1262 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1263 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1264 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1265 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1266 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
1267 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1268 int hns_roce_init(struct hns_roce_dev *hr_dev);
1269 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1270
1271 int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
1272                                struct ib_cq *ib_cq);
1273 #endif /* _HNS_ROCE_DEVICE_H */