drivers/infiniband/hw/hns/hns_roce_device.h

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _HNS_ROCE_DEVICE_H
  34 #define _HNS_ROCE_DEVICE_H
  35
  36 #include <rdma/ib_verbs.h>
  37
  38 #define DRV_NAME "hns_roce"
  39
  40 #define PCI_REVISION_ID_HIP08                   0x21
  41 #define PCI_REVISION_ID_HIP09                   0x30
  42
  43 #define HNS_ROCE_HW_VER1        ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
  44
  45 #define HNS_ROCE_MAX_MSG_LEN                    0x80000000
  46
  47 #define HNS_ROCE_IB_MIN_SQ_STRIDE               6
  48
  49 #define HNS_ROCE_BA_SIZE                        (32 * 4096)
  50
  51 #define BA_BYTE_LEN                             8
  52
  53 /* Hardware specification only for v1 engine */
  54 #define HNS_ROCE_MIN_CQE_NUM                    0x40
  55 #define HNS_ROCE_MIN_WQE_NUM                    0x20
  56
  57 /* Hardware specification only for v1 engine */
  58 #define HNS_ROCE_MAX_INNER_MTPT_NUM             0x7
  59 #define HNS_ROCE_MAX_MTPT_PBL_NUM               0x100000
  60
  61 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS        20
  62 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT   \
  63         (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
  64 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT             0x2
  65 #define HNS_ROCE_MIN_CQE_CNT                    16
  66
  67 #define HNS_ROCE_MAX_IRQ_NUM                    128
  68
  69 #define HNS_ROCE_SGE_IN_WQE                     2
  70 #define HNS_ROCE_SGE_SHIFT                      4
  71
  72 #define EQ_ENABLE                               1
  73 #define EQ_DISABLE                              0
  74
  75 #define HNS_ROCE_CEQ                            0
  76 #define HNS_ROCE_AEQ                            1
  77
  78 #define HNS_ROCE_CEQE_SIZE 0x4
  79 #define HNS_ROCE_AEQE_SIZE 0x10
  80
  81 #define HNS_ROCE_V3_EQE_SIZE 0x40
  82
  83 #define HNS_ROCE_V2_CQE_SIZE 32
  84 #define HNS_ROCE_V3_CQE_SIZE 64
  85
  86 #define HNS_ROCE_V2_QPC_SZ 256
  87 #define HNS_ROCE_V3_QPC_SZ 512
  88
  89 #define HNS_ROCE_MAX_PORTS                      6
  90 #define HNS_ROCE_GID_SIZE                       16
  91 #define HNS_ROCE_SGE_SIZE                       16
  92
  93 #define HNS_ROCE_HOP_NUM_0                      0xff
  94
  95 #define BITMAP_NO_RR                            0
  96 #define BITMAP_RR                               1
  97
  98 #define MR_TYPE_MR                              0x00
  99 #define MR_TYPE_FRMR                            0x01
 100 #define MR_TYPE_DMA                             0x03
 101
 102 #define HNS_ROCE_FRMR_MAX_PA                    512
 103
 104 #define PKEY_ID                                 0xffff
 105 #define GUID_LEN                                8
 106 #define NODE_DESC_SIZE                          64
 107 #define DB_REG_OFFSET                           0x1000
 108
 109 /* Configure to HW for PAGE_SIZE larger than 4KB */
 110 #define PG_SHIFT_OFFSET                         (PAGE_SHIFT - 12)
 111
 112 #define PAGES_SHIFT_8                           8
 113 #define PAGES_SHIFT_16                          16
 114 #define PAGES_SHIFT_24                          24
 115 #define PAGES_SHIFT_32                          32
 116
 117 #define HNS_ROCE_IDX_QUE_ENTRY_SZ               4
 118 #define SRQ_DB_REG                              0x230
 119
 120 #define HNS_ROCE_QP_BANK_NUM 8
 121
 122 /* The chip implementation of the consumer index is calculated
 123  * according to twice the actual EQ depth
 124  */
 125 #define EQ_DEPTH_COEFF                          2
 126
 127 enum {
 128         SERV_TYPE_RC,
 129         SERV_TYPE_UC,
 130         SERV_TYPE_RD,
 131         SERV_TYPE_UD,
 132 };
 133
 134 enum hns_roce_qp_caps {
 135         HNS_ROCE_QP_CAP_RQ_RECORD_DB = BIT(0),
 136         HNS_ROCE_QP_CAP_SQ_RECORD_DB = BIT(1),
 137         HNS_ROCE_QP_CAP_OWNER_DB = BIT(2),
 138 };
 139
 140 enum hns_roce_cq_flags {
 141         HNS_ROCE_CQ_FLAG_RECORD_DB = BIT(0),
 142 };
 143
 144 enum hns_roce_qp_state {
 145         HNS_ROCE_QP_STATE_RST,
 146         HNS_ROCE_QP_STATE_INIT,
 147         HNS_ROCE_QP_STATE_RTR,
 148         HNS_ROCE_QP_STATE_RTS,
 149         HNS_ROCE_QP_STATE_SQD,
 150         HNS_ROCE_QP_STATE_ERR,
 151         HNS_ROCE_QP_NUM_STATE,
 152 };
 153
 154 enum hns_roce_event {
 155         HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
 156         HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
 157         HNS_ROCE_EVENT_TYPE_COMM_EST                  = 0x03,
 158         HNS_ROCE_EVENT_TYPE_SQ_DRAINED                = 0x04,
 159         HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR            = 0x05,
 160         HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR    = 0x06,
 161         HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR     = 0x07,
 162         HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH           = 0x08,
 163         HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH        = 0x09,
 164         HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR           = 0x0a,
 165         HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR           = 0x0b,
 166         HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW               = 0x0c,
 167         HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID             = 0x0d,
 168         HNS_ROCE_EVENT_TYPE_PORT_CHANGE               = 0x0f,
 169         /* 0x10 and 0x11 is unused in currently application case */
 170         HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,
 171         HNS_ROCE_EVENT_TYPE_MB                        = 0x13,
 172         HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW              = 0x14,
 173         HNS_ROCE_EVENT_TYPE_FLR                       = 0x15,
 174 };
 175
 176 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
 177 enum {
 178         HNS_ROCE_LWQCE_QPC_ERROR                = 1,
 179         HNS_ROCE_LWQCE_MTU_ERROR                = 2,
 180         HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR        = 3,
 181         HNS_ROCE_LWQCE_WQE_ADDR_ERROR           = 4,
 182         HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR       = 5,
 183         HNS_ROCE_LWQCE_SL_ERROR                 = 6,
 184         HNS_ROCE_LWQCE_PORT_ERROR               = 7,
 185 };
 186
 187 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
 188 enum {
 189         HNS_ROCE_LAVWQE_R_KEY_VIOLATION         = 1,
 190         HNS_ROCE_LAVWQE_LENGTH_ERROR            = 2,
 191         HNS_ROCE_LAVWQE_VA_ERROR                = 3,
 192         HNS_ROCE_LAVWQE_PD_ERROR                = 4,
 193         HNS_ROCE_LAVWQE_RW_ACC_ERROR            = 5,
 194         HNS_ROCE_LAVWQE_KEY_STATE_ERROR         = 6,
 195         HNS_ROCE_LAVWQE_MR_OPERATION_ERROR      = 7,
 196 };
 197
 198 /* DOORBELL overflow subtype */
 199 enum {
 200         HNS_ROCE_DB_SUBTYPE_SDB_OVF             = 1,
 201         HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF         = 2,
 202         HNS_ROCE_DB_SUBTYPE_ODB_OVF             = 3,
 203         HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF         = 4,
 204         HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP         = 5,
 205         HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP         = 6,
 206 };
 207
 208 enum {
 209         /* RQ&SRQ related operations */
 210         HNS_ROCE_OPCODE_SEND_DATA_RECEIVE       = 0x06,
 211         HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE   = 0x07,
 212 };
 213
 214 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12
 215
 216 enum {
 217         HNS_ROCE_CAP_FLAG_REREG_MR              = BIT(0),
 218         HNS_ROCE_CAP_FLAG_ROCE_V1_V2            = BIT(1),
 219         HNS_ROCE_CAP_FLAG_RQ_INLINE             = BIT(2),
 220         HNS_ROCE_CAP_FLAG_RECORD_DB             = BIT(3),
 221         HNS_ROCE_CAP_FLAG_SQ_RECORD_DB          = BIT(4),
 222         HNS_ROCE_CAP_FLAG_SRQ                   = BIT(5),
 223         HNS_ROCE_CAP_FLAG_MW                    = BIT(7),
 224         HNS_ROCE_CAP_FLAG_FRMR                  = BIT(8),
 225         HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL          = BIT(9),
 226         HNS_ROCE_CAP_FLAG_ATOMIC                = BIT(10),
 227         HNS_ROCE_CAP_FLAG_SDI_MODE              = BIT(14),
 228 };
 229
 230 #define HNS_ROCE_DB_TYPE_COUNT                  2
 231 #define HNS_ROCE_DB_UNIT_SIZE                   4
 232
 233 enum {
 234         HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
 235 };
 236
 237 enum hns_roce_reset_stage {
 238         HNS_ROCE_STATE_NON_RST,
 239         HNS_ROCE_STATE_RST_BEF_DOWN,
 240         HNS_ROCE_STATE_RST_DOWN,
 241         HNS_ROCE_STATE_RST_UNINIT,
 242         HNS_ROCE_STATE_RST_INIT,
 243         HNS_ROCE_STATE_RST_INITED,
 244 };
 245
 246 enum hns_roce_instance_state {
 247         HNS_ROCE_STATE_NON_INIT,
 248         HNS_ROCE_STATE_INIT,
 249         HNS_ROCE_STATE_INITED,
 250         HNS_ROCE_STATE_UNINIT,
 251 };
 252
 253 enum {
 254         HNS_ROCE_RST_DIRECT_RETURN              = 0,
 255 };
 256
 257 enum {
 258         CMD_RST_PRC_OTHERS,
 259         CMD_RST_PRC_SUCCESS,
 260         CMD_RST_PRC_EBUSY,
 261 };
 262
 263 #define HNS_ROCE_CMD_SUCCESS                    1
 264
 265 #define HNS_ROCE_PORT_DOWN                      0
 266 #define HNS_ROCE_PORT_UP                        1
 267
 268 /* The minimum page size is 4K for hardware */
 269 #define HNS_HW_PAGE_SHIFT                       12
 270 #define HNS_HW_PAGE_SIZE                        (1 << HNS_HW_PAGE_SHIFT)
 271
 272 struct hns_roce_uar {
 273         u64             pfn;
 274         unsigned long   index;
 275         unsigned long   logic_idx;
 276 };
 277
 278 struct hns_roce_ucontext {
 279         struct ib_ucontext      ibucontext;
 280         struct hns_roce_uar     uar;
 281         struct list_head        page_list;
 282         struct mutex            page_mutex;
 283 };
 284
 285 struct hns_roce_pd {
 286         struct ib_pd            ibpd;
 287         unsigned long           pdn;
 288 };
 289
 290 struct hns_roce_bitmap {
 291         /* Bitmap Traversal last a bit which is 1 */
 292         unsigned long           last;
 293         unsigned long           top;
 294         unsigned long           max;
 295         unsigned long           reserved_top;
 296         unsigned long           mask;
 297         spinlock_t              lock;
 298         unsigned long           *table;
 299 };
 300
 301 /* For Hardware Entry Memory */
 302 struct hns_roce_hem_table {
 303         /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
 304         u32             type;
 305         /* HEM array elment num */
 306         unsigned long   num_hem;
 307         /* HEM entry record obj total num */
 308         unsigned long   num_obj;
 309         /* Single obj size */
 310         unsigned long   obj_size;
 311         unsigned long   table_chunk_size;
 312         int             lowmem;
 313         struct mutex    mutex;
 314         struct hns_roce_hem **hem;
 315         u64             **bt_l1;
 316         dma_addr_t      *bt_l1_dma_addr;
 317         u64             **bt_l0;
 318         dma_addr_t      *bt_l0_dma_addr;
 319 };
 320
 321 struct hns_roce_buf_region {
 322         int offset; /* page offset */
 323         u32 count; /* page count */
 324         int hopnum; /* addressing hop num */
 325 };
 326
 327 #define HNS_ROCE_MAX_BT_REGION  3
 328 #define HNS_ROCE_MAX_BT_LEVEL   3
 329 struct hns_roce_hem_list {
 330         struct list_head root_bt;
 331         /* link all bt dma mem by hop config */
 332         struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
 333         struct list_head btm_bt; /* link all bottom bt in @mid_bt */
 334         dma_addr_t root_ba; /* pointer to the root ba table */
 335 };
 336
 337 struct hns_roce_buf_attr {
 338         struct {
 339                 size_t  size;  /* region size */
 340                 int     hopnum; /* multi-hop addressing hop num */
 341         } region[HNS_ROCE_MAX_BT_REGION];
 342         int region_count; /* valid region count */
 343         unsigned int page_shift;  /* buffer page shift */
 344         bool fixed_page; /* decide page shift is fixed-size or maximum size */
 345         int user_access; /* umem access flag */
 346         bool mtt_only; /* only alloc buffer-required MTT memory */
 347 };
 348
 349 struct hns_roce_hem_cfg {
 350         dma_addr_t      root_ba; /* root BA table's address */
 351         bool            is_direct; /* addressing without BA table */
 352         unsigned int    ba_pg_shift; /* BA table page shift */
 353         unsigned int    buf_pg_shift; /* buffer page shift */
 354         unsigned int    buf_pg_count;  /* buffer page count */
 355         struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
 356         int             region_count;
 357 };
 358
 359 /* memory translate region */
 360 struct hns_roce_mtr {
 361         struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
 362         struct ib_umem          *umem; /* user space buffer */
 363         struct hns_roce_buf     *kmem; /* kernel space buffer */
 364         struct hns_roce_hem_cfg  hem_cfg; /* config for hardware addressing */
 365 };
 366
 367 struct hns_roce_mw {
 368         struct ib_mw            ibmw;
 369         u32                     pdn;
 370         u32                     rkey;
 371         int                     enabled; /* MW's active status */
 372         u32                     pbl_hop_num;
 373         u32                     pbl_ba_pg_sz;
 374         u32                     pbl_buf_pg_sz;
 375 };
 376
 377 /* Only support 4K page size for mr register */
 378 #define MR_SIZE_4K 0
 379
 380 struct hns_roce_mr {
 381         struct ib_mr            ibmr;
 382         u64                     iova; /* MR's virtual orignal addr */
 383         u64                     size; /* Address range of MR */
 384         u32                     key; /* Key of MR */
 385         u32                     pd;   /* PD num of MR */
 386         u32                     access; /* Access permission of MR */
 387         int                     enabled; /* MR's active status */
 388         int                     type;   /* MR's register type */
 389         u32                     pbl_hop_num;    /* multi-hop number */
 390         struct hns_roce_mtr     pbl_mtr;
 391         u32                     npages;
 392         dma_addr_t              *page_list;
 393 };
 394
 395 struct hns_roce_mr_table {
 396         struct hns_roce_bitmap          mtpt_bitmap;
 397         struct hns_roce_hem_table       mtpt_table;
 398 };
 399
 400 struct hns_roce_wq {
 401         u64             *wrid;     /* Work request ID */
 402         spinlock_t      lock;
 403         u32             wqe_cnt;  /* WQE num */
 404         int             max_gs;
 405         int             offset;
 406         int             wqe_shift;      /* WQE size */
 407         u32             head;
 408         u32             tail;
 409         void __iomem    *db_reg_l;
 410 };
 411
 412 struct hns_roce_sge {
 413         unsigned int    sge_cnt;        /* SGE num */
 414         int             offset;
 415         int             sge_shift;      /* SGE size */
 416 };
 417
 418 struct hns_roce_buf_list {
 419         void            *buf;
 420         dma_addr_t      map;
 421 };
 422
 423 /*
 424  * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
 425  * dma address range.
 426  *
 427  * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
 428  *
 429  * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
 430  * the allocated size is smaller than the required size.
 431  */
 432 enum {
 433         HNS_ROCE_BUF_DIRECT = BIT(0),
 434         HNS_ROCE_BUF_NOSLEEP = BIT(1),
 435         HNS_ROCE_BUF_NOFAIL = BIT(2),
 436 };
 437
 438 struct hns_roce_buf {
 439         struct hns_roce_buf_list        *trunk_list;
 440         u32                             ntrunks;
 441         u32                             npages;
 442         unsigned int                    trunk_shift;
 443         unsigned int                    page_shift;
 444 };
 445
 446 struct hns_roce_db_pgdir {
 447         struct list_head        list;
 448         DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
 449         DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
 450         unsigned long           *bits[HNS_ROCE_DB_TYPE_COUNT];
 451         u32                     *page;
 452         dma_addr_t              db_dma;
 453 };
 454
 455 struct hns_roce_user_db_page {
 456         struct list_head        list;
 457         struct ib_umem          *umem;
 458         unsigned long           user_virt;
 459         refcount_t              refcount;
 460 };
 461
 462 struct hns_roce_db {
 463         u32             *db_record;
 464         union {
 465                 struct hns_roce_db_pgdir *pgdir;
 466                 struct hns_roce_user_db_page *user_page;
 467         } u;
 468         dma_addr_t      dma;
 469         void            *virt_addr;
 470         int             index;
 471         int             order;
 472 };
 473
 474 struct hns_roce_cq {
 475         struct ib_cq                    ib_cq;
 476         struct hns_roce_mtr             mtr;
 477         struct hns_roce_db              db;
 478         u32                             flags;
 479         spinlock_t                      lock;
 480         u32                             cq_depth;
 481         u32                             cons_index;
 482         u32                             *set_ci_db;
 483         void __iomem                    *cq_db_l;
 484         u16                             *tptr_addr;
 485         int                             arm_sn;
 486         int                             cqe_size;
 487         unsigned long                   cqn;
 488         u32                             vector;
 489         atomic_t                        refcount;
 490         struct completion               free;
 491         struct list_head                sq_list; /* all qps on this send cq */
 492         struct list_head                rq_list; /* all qps on this recv cq */
 493         int                             is_armed; /* cq is armed */
 494         struct list_head                node; /* all armed cqs are on a list */
 495 };
 496
 497 struct hns_roce_idx_que {
 498         struct hns_roce_mtr             mtr;
 499         int                             entry_shift;
 500         unsigned long                   *bitmap;
 501 };
 502
 503 struct hns_roce_srq {
 504         struct ib_srq           ibsrq;
 505         unsigned long           srqn;
 506         u32                     wqe_cnt;
 507         int                     max_gs;
 508         int                     wqe_shift;
 509         void __iomem            *db_reg_l;
 510
 511         atomic_t                refcount;
 512         struct completion       free;
 513
 514         struct hns_roce_mtr     buf_mtr;
 515
 516         u64                    *wrid;
 517         struct hns_roce_idx_que idx_que;
 518         spinlock_t              lock;
 519         int                     head;
 520         int                     tail;
 521         struct mutex            mutex;
 522         void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
 523 };
 524
 525 struct hns_roce_uar_table {
 526         struct hns_roce_bitmap bitmap;
 527 };
 528
 529 struct hns_roce_bank {
 530         struct ida ida;
 531         u32 inuse; /* Number of IDs allocated */
 532         u32 min; /* Lowest ID to allocate.  */
 533         u32 max; /* Highest ID to allocate. */
 534         u32 next; /* Next ID to allocate. */
 535 };
 536
 537 struct hns_roce_qp_table {
 538         struct hns_roce_hem_table       qp_table;
 539         struct hns_roce_hem_table       irrl_table;
 540         struct hns_roce_hem_table       trrl_table;
 541         struct hns_roce_hem_table       sccc_table;
 542         struct mutex                    scc_mutex;
 543         struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
 544         spinlock_t bank_lock;
 545 };
 546
 547 struct hns_roce_cq_table {
 548         struct hns_roce_bitmap          bitmap;
 549         struct xarray                   array;
 550         struct hns_roce_hem_table       table;
 551 };
 552
 553 struct hns_roce_srq_table {
 554         struct hns_roce_bitmap          bitmap;
 555         struct xarray                   xa;
 556         struct hns_roce_hem_table       table;
 557 };
 558
 559 struct hns_roce_raq_table {
 560         struct hns_roce_buf_list        *e_raq_buf;
 561 };
 562
 563 struct hns_roce_av {
 564         u8 port;
 565         u8 gid_index;
 566         u8 stat_rate;
 567         u8 hop_limit;
 568         u32 flowlabel;
 569         u16 udp_sport;
 570         u8 sl;
 571         u8 tclass;
 572         u8 dgid[HNS_ROCE_GID_SIZE];
 573         u8 mac[ETH_ALEN];
 574         u16 vlan_id;
 575         u8 vlan_en;
 576 };
 577
 578 struct hns_roce_ah {
 579         struct ib_ah            ibah;
 580         struct hns_roce_av      av;
 581 };
 582
 583 struct hns_roce_cmd_context {
 584         struct completion       done;
 585         int                     result;
 586         int                     next;
 587         u64                     out_param;
 588         u16                     token;
 589 };
 590
 591 struct hns_roce_cmdq {
 592         struct dma_pool         *pool;
 593         struct mutex            hcr_mutex;
 594         struct semaphore        poll_sem;
 595         /*
 596          * Event mode: cmd register mutex protection,
 597          * ensure to not exceed max_cmds and user use limit region
 598          */
 599         struct semaphore        event_sem;
 600         int                     max_cmds;
 601         spinlock_t              context_lock;
 602         int                     free_head;
 603         struct hns_roce_cmd_context *context;
 604         /*
 605          * Result of get integer part
 606          * which max_comds compute according a power of 2
 607          */
 608         u16                     token_mask;
 609         /*
 610          * Process whether use event mode, init default non-zero
 611          * After the event queue of cmd event ready,
 612          * can switch into event mode
 613          * close device, switch into poll mode(non event mode)
 614          */
 615         u8                      use_events;
 616 };
 617
 618 struct hns_roce_cmd_mailbox {
 619         void                   *buf;
 620         dma_addr_t              dma;
 621 };
 622
 623 struct hns_roce_dev;
 624
 625 struct hns_roce_rinl_sge {
 626         void                    *addr;
 627         u32                     len;
 628 };
 629
 630 struct hns_roce_rinl_wqe {
 631         struct hns_roce_rinl_sge *sg_list;
 632         u32                      sge_cnt;
 633 };
 634
 635 struct hns_roce_rinl_buf {
 636         struct hns_roce_rinl_wqe *wqe_list;
 637         u32                      wqe_cnt;
 638 };
 639
 640 enum {
 641         HNS_ROCE_FLUSH_FLAG = 0,
 642 };
 643
 644 struct hns_roce_work {
 645         struct hns_roce_dev *hr_dev;
 646         struct work_struct work;
 647         u32 qpn;
 648         u32 cqn;
 649         int event_type;
 650         int sub_type;
 651 };
 652
 653 struct hns_roce_qp {
 654         struct ib_qp            ibqp;
 655         struct hns_roce_wq      rq;
 656         struct hns_roce_db      rdb;
 657         struct hns_roce_db      sdb;
 658         unsigned long           en_flags;
 659         u32                     doorbell_qpn;
 660         u32                     sq_signal_bits;
 661         struct hns_roce_wq      sq;
 662
 663         struct hns_roce_mtr     mtr;
 664
 665         u32                     buff_size;
 666         struct mutex            mutex;
 667         u8                      port;
 668         u8                      phy_port;
 669         u8                      sl;
 670         u8                      resp_depth;
 671         u8                      state;
 672         u32                     access_flags;
 673         u32                     atomic_rd_en;
 674         u32                     pkey_index;
 675         u32                     qkey;
 676         void                    (*event)(struct hns_roce_qp *qp,
 677                                          enum hns_roce_event event_type);
 678         unsigned long           qpn;
 679
 680         atomic_t                refcount;
 681         struct completion       free;
 682
 683         struct hns_roce_sge     sge;
 684         u32                     next_sge;
 685         enum ib_mtu             path_mtu;
 686         u32                     max_inline_data;
 687
 688         /* 0: flush needed, 1: unneeded */
 689         unsigned long           flush_flag;
 690         struct hns_roce_work    flush_work;
 691         struct hns_roce_rinl_buf rq_inl_buf;
 692         struct list_head        node;           /* all qps are on a list */
 693         struct list_head        rq_node;        /* all recv qps are on a list */
 694         struct list_head        sq_node;        /* all send qps are on a list */
 695 };
 696
 697 struct hns_roce_ib_iboe {
 698         spinlock_t              lock;
 699         struct net_device      *netdevs[HNS_ROCE_MAX_PORTS];
 700         struct notifier_block   nb;
 701         u8                      phy_port[HNS_ROCE_MAX_PORTS];
 702 };
 703
 704 enum {
 705         HNS_ROCE_EQ_STAT_INVALID  = 0,
 706         HNS_ROCE_EQ_STAT_VALID    = 2,
 707 };
 708
 709 struct hns_roce_ceqe {
 710         __le32  comp;
 711         __le32  rsv[15];
 712 };
 713
 714 struct hns_roce_aeqe {
 715         __le32 asyn;
 716         union {
 717                 struct {
 718                         __le32 qp;
 719                         u32 rsv0;
 720                         u32 rsv1;
 721                 } qp_event;
 722
 723                 struct {
 724                         __le32 srq;
 725                         u32 rsv0;
 726                         u32 rsv1;
 727                 } srq_event;
 728
 729                 struct {
 730                         __le32 cq;
 731                         u32 rsv0;
 732                         u32 rsv1;
 733                 } cq_event;
 734
 735                 struct {
 736                         __le32 ceqe;
 737                         u32 rsv0;
 738                         u32 rsv1;
 739                 } ce_event;
 740
 741                 struct {
 742                         __le64  out_param;
 743                         __le16  token;
 744                         u8      status;
 745                         u8      rsv0;
 746                 } __packed cmd;
 747          } event;
 748         __le32 rsv[12];
 749 };
 750
 751 struct hns_roce_eq {
 752         struct hns_roce_dev             *hr_dev;
 753         void __iomem                    *doorbell;
 754
 755         int                             type_flag; /* Aeq:1 ceq:0 */
 756         int                             eqn;
 757         u32                             entries;
 758         int                             log_entries;
 759         int                             eqe_size;
 760         int                             irq;
 761         int                             log_page_size;
 762         int                             cons_index;
 763         struct hns_roce_buf_list        *buf_list;
 764         int                             over_ignore;
 765         int                             coalesce;
 766         int                             arm_st;
 767         int                             hop_num;
 768         struct hns_roce_mtr             mtr;
 769         u16                             eq_max_cnt;
 770         int                             eq_period;
 771         int                             shift;
 772         int                             event_type;
 773         int                             sub_type;
 774 };
 775
 776 struct hns_roce_eq_table {
 777         struct hns_roce_eq      *eq;
 778         void __iomem            **eqc_base; /* only for hw v1 */
 779 };
 780
 781 struct hns_roce_caps {
 782         u64             fw_ver;
 783         u8              num_ports;
 784         int             gid_table_len[HNS_ROCE_MAX_PORTS];
 785         int             pkey_table_len[HNS_ROCE_MAX_PORTS];
 786         int             local_ca_ack_delay;
 787         int             num_uars;
 788         u32             phy_num_uars;
 789         u32             max_sq_sg;
 790         u32             max_sq_inline;
 791         u32             max_rq_sg;
 792         u32             max_extend_sg;
 793         int             num_qps;
 794         u32             reserved_qps;
 795         int             num_qpc_timer;
 796         int             num_cqc_timer;
 797         int             num_srqs;
 798         u32             max_wqes;
 799         u32             max_srq_wrs;
 800         u32             max_srq_sges;
 801         u32             max_sq_desc_sz;
 802         u32             max_rq_desc_sz;
 803         u32             max_srq_desc_sz;
 804         int             max_qp_init_rdma;
 805         int             max_qp_dest_rdma;
 806         int             num_cqs;
 807         u32             max_cqes;
 808         u32             min_cqes;
 809         u32             min_wqes;
 810         int             reserved_cqs;
 811         int             reserved_srqs;
 812         int             num_aeq_vectors;
 813         int             num_comp_vectors;
 814         int             num_other_vectors;
 815         int             num_mtpts;
 816         u32             num_mtt_segs;
 817         u32             num_cqe_segs;
 818         u32             num_srqwqe_segs;
 819         u32             num_idx_segs;
 820         int             reserved_mrws;
 821         int             reserved_uars;
 822         int             num_pds;
 823         int             reserved_pds;
 824         u32             mtt_entry_sz;
 825         u32             cqe_sz;
 826         u32             page_size_cap;
 827         u32             reserved_lkey;
 828         int             mtpt_entry_sz;
 829         int             qpc_sz;
 830         int             irrl_entry_sz;
 831         int             trrl_entry_sz;
 832         int             cqc_entry_sz;
 833         int             sccc_sz;
 834         int             qpc_timer_entry_sz;
 835         int             cqc_timer_entry_sz;
 836         int             srqc_entry_sz;
 837         int             idx_entry_sz;
 838         u32             pbl_ba_pg_sz;
 839         u32             pbl_buf_pg_sz;
 840         u32             pbl_hop_num;
 841         int             aeqe_depth;
 842         int             ceqe_depth;
 843         u32             aeqe_size;
 844         u32             ceqe_size;
 845         enum ib_mtu     max_mtu;
 846         u32             qpc_bt_num;
 847         u32             qpc_timer_bt_num;
 848         u32             srqc_bt_num;
 849         u32             cqc_bt_num;
 850         u32             cqc_timer_bt_num;
 851         u32             mpt_bt_num;
 852         u32             sccc_bt_num;
 853         u32             gmv_bt_num;
 854         u32             qpc_ba_pg_sz;
 855         u32             qpc_buf_pg_sz;
 856         u32             qpc_hop_num;
 857         u32             srqc_ba_pg_sz;
 858         u32             srqc_buf_pg_sz;
 859         u32             srqc_hop_num;
 860         u32             cqc_ba_pg_sz;
 861         u32             cqc_buf_pg_sz;
 862         u32             cqc_hop_num;
 863         u32             mpt_ba_pg_sz;
 864         u32             mpt_buf_pg_sz;
 865         u32             mpt_hop_num;
 866         u32             mtt_ba_pg_sz;
 867         u32             mtt_buf_pg_sz;
 868         u32             mtt_hop_num;
 869         u32             wqe_sq_hop_num;
 870         u32             wqe_sge_hop_num;
 871         u32             wqe_rq_hop_num;
 872         u32             sccc_ba_pg_sz;
 873         u32             sccc_buf_pg_sz;
 874         u32             sccc_hop_num;
 875         u32             qpc_timer_ba_pg_sz;
 876         u32             qpc_timer_buf_pg_sz;
 877         u32             qpc_timer_hop_num;
 878         u32             cqc_timer_ba_pg_sz;
 879         u32             cqc_timer_buf_pg_sz;
 880         u32             cqc_timer_hop_num;
 881         u32             cqe_ba_pg_sz;   /* page_size = 4K*(2^cqe_ba_pg_sz) */
 882         u32             cqe_buf_pg_sz;
 883         u32             cqe_hop_num;
 884         u32             srqwqe_ba_pg_sz;
 885         u32             srqwqe_buf_pg_sz;
 886         u32             srqwqe_hop_num;
 887         u32             idx_ba_pg_sz;
 888         u32             idx_buf_pg_sz;
 889         u32             idx_hop_num;
 890         u32             eqe_ba_pg_sz;
 891         u32             eqe_buf_pg_sz;
 892         u32             eqe_hop_num;
 893         u32             gmv_entry_num;
 894         u32             gmv_entry_sz;
 895         u32             gmv_ba_pg_sz;
 896         u32             gmv_buf_pg_sz;
 897         u32             gmv_hop_num;
 898         u32             sl_num;
 899         u32             tsq_buf_pg_sz;
 900         u32             tpq_buf_pg_sz;
 901         u32             chunk_sz;       /* chunk size in non multihop mode */
 902         u64             flags;
 903         u16             default_ceq_max_cnt;
 904         u16             default_ceq_period;
 905         u16             default_aeq_max_cnt;
 906         u16             default_aeq_period;
 907         u16             default_aeq_arm_st;
 908         u16             default_ceq_arm_st;
 909 };
 910
 911 struct hns_roce_dfx_hw {
 912         int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
 913                               int *buffer);
 914 };
 915
 916 enum hns_roce_device_state {
 917         HNS_ROCE_DEVICE_STATE_INITED,
 918         HNS_ROCE_DEVICE_STATE_RST_DOWN,
 919         HNS_ROCE_DEVICE_STATE_UNINIT,
 920 };
 921
 922 struct hns_roce_hw {
 923         int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
 924         int (*cmq_init)(struct hns_roce_dev *hr_dev);
 925         void (*cmq_exit)(struct hns_roce_dev *hr_dev);
 926         int (*hw_profile)(struct hns_roce_dev *hr_dev);
 927         int (*hw_init)(struct hns_roce_dev *hr_dev);
 928         void (*hw_exit)(struct hns_roce_dev *hr_dev);
 929         int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
 930                          u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
 931                          u16 token, int event);
 932         int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
 933         int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev);
 934         int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
 935                        const union ib_gid *gid, const struct ib_gid_attr *attr);
 936         int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
 937         void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
 938                         enum ib_mtu mtu);
 939         int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
 940                           struct hns_roce_mr *mr, unsigned long mtpt_idx);
 941         int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
 942                                 struct hns_roce_mr *mr, int flags, u32 pdn,
 943                                 int mr_access_flags, u64 iova, u64 size,
 944                                 void *mb_buf);
 945         int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
 946                                struct hns_roce_mr *mr);
 947         int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
 948         void (*write_cqc)(struct hns_roce_dev *hr_dev,
 949                           struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
 950                           dma_addr_t dma_handle);
 951         int (*set_hem)(struct hns_roce_dev *hr_dev,
 952                        struct hns_roce_hem_table *table, int obj, int step_idx);
 953         int (*clear_hem)(struct hns_roce_dev *hr_dev,
 954                          struct hns_roce_hem_table *table, int obj,
 955                          int step_idx);
 956         int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
 957                         int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
 958         int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
 959                          int attr_mask, enum ib_qp_state cur_state,
 960                          enum ib_qp_state new_state);
 961         int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata);
 962         int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
 963                          struct hns_roce_qp *hr_qp);
 964         int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 965                          const struct ib_send_wr **bad_wr);
 966         int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr,
 967                          const struct ib_recv_wr **bad_recv_wr);
 968         int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 969         int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 970         int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
 971                         struct ib_udata *udata);
 972         int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
 973         int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
 974         int (*init_eq)(struct hns_roce_dev *hr_dev);
 975         void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
 976         void (*write_srqc)(struct hns_roce_dev *hr_dev,
 977                            struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn,
 978                            void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx,
 979                            dma_addr_t dma_handle_wqe,
 980                            dma_addr_t dma_handle_idx);
 981         int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
 982                        enum ib_srq_attr_mask srq_attr_mask,
 983                        struct ib_udata *udata);
 984         int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr);
 985         int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
 986                              const struct ib_recv_wr **bad_wr);
 987         const struct ib_device_ops *hns_roce_dev_ops;
 988         const struct ib_device_ops *hns_roce_dev_srq_ops;
 989 };
 990
 991 struct hns_roce_dev {
 992         struct ib_device        ib_dev;
 993         struct platform_device  *pdev;
 994         struct pci_dev          *pci_dev;
 995         struct device           *dev;
 996         struct hns_roce_uar     priv_uar;
 997         const char              *irq_names[HNS_ROCE_MAX_IRQ_NUM];
 998         spinlock_t              sm_lock;
 999         spinlock_t              bt_cmd_lock;
1000         bool                    active;
1001         bool                    is_reset;
1002         bool                    dis_db;
1003         unsigned long           reset_cnt;
1004         struct hns_roce_ib_iboe iboe;
1005         enum hns_roce_device_state state;
1006         struct list_head        qp_list; /* list of all qps on this dev */
1007         spinlock_t              qp_list_lock; /* protect qp_list */
1008
1009         struct list_head        pgdir_list;
1010         struct mutex            pgdir_mutex;
1011         int                     irq[HNS_ROCE_MAX_IRQ_NUM];
1012         u8 __iomem              *reg_base;
1013         struct hns_roce_caps    caps;
1014         struct xarray           qp_table_xa;
1015
1016         unsigned char   dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
1017         u64                     sys_image_guid;
1018         u32                     vendor_id;
1019         u32                     vendor_part_id;
1020         u32                     hw_rev;
1021         void __iomem            *priv_addr;
1022
1023         struct hns_roce_cmdq    cmd;
1024         struct hns_roce_bitmap    pd_bitmap;
1025         struct hns_roce_uar_table uar_table;
1026         struct hns_roce_mr_table  mr_table;
1027         struct hns_roce_cq_table  cq_table;
1028         struct hns_roce_srq_table srq_table;
1029         struct hns_roce_qp_table  qp_table;
1030         struct hns_roce_eq_table  eq_table;
1031         struct hns_roce_hem_table  qpc_timer_table;
1032         struct hns_roce_hem_table  cqc_timer_table;
1033         /* GMV is the memory area that the driver allocates for the hardware
1034          * to store SGID, SMAC and VLAN information.
1035          */
1036         struct hns_roce_hem_table  gmv_table;
1037
1038         int                     cmd_mod;
1039         int                     loop_idc;
1040         u32                     sdb_offset;
1041         u32                     odb_offset;
1042         dma_addr_t              tptr_dma_addr;  /* only for hw v1 */
1043         u32                     tptr_size;      /* only for hw v1 */
1044         const struct hns_roce_hw *hw;
1045         void                    *priv;
1046         struct workqueue_struct *irq_workq;
1047         const struct hns_roce_dfx_hw *dfx;
1048 };
1049
1050 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
1051 {
1052         return container_of(ib_dev, struct hns_roce_dev, ib_dev);
1053 }
1054
1055 static inline struct hns_roce_ucontext
1056                         *to_hr_ucontext(struct ib_ucontext *ibucontext)
1057 {
1058         return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1059 }
1060
1061 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1062 {
1063         return container_of(ibpd, struct hns_roce_pd, ibpd);
1064 }
1065
1066 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1067 {
1068         return container_of(ibah, struct hns_roce_ah, ibah);
1069 }
1070
1071 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1072 {
1073         return container_of(ibmr, struct hns_roce_mr, ibmr);
1074 }
1075
1076 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1077 {
1078         return container_of(ibmw, struct hns_roce_mw, ibmw);
1079 }
1080
1081 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1082 {
1083         return container_of(ibqp, struct hns_roce_qp, ibqp);
1084 }
1085
1086 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1087 {
1088         return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1089 }
1090
1091 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1092 {
1093         return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1094 }
1095
1096 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1097 {
1098         __raw_writeq(*(u64 *) val, dest);
1099 }
1100
1101 static inline struct hns_roce_qp
1102         *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1103 {
1104         return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1));
1105 }
1106
1107 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
1108 {
1109         return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1110                         (offset & ((1 << buf->trunk_shift) - 1));
1111 }
1112
1113 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, int idx)
1114 {
1115         int offset = idx << buf->page_shift;
1116
1117         return buf->trunk_list[offset >> buf->trunk_shift].map +
1118                         (offset & ((1 << buf->trunk_shift) - 1));
1119 }
1120
1121 #define hr_hw_page_align(x)             ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1122
1123 static inline u64 to_hr_hw_page_addr(u64 addr)
1124 {
1125         return addr >> HNS_HW_PAGE_SHIFT;
1126 }
1127
1128 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1129 {
1130         return page_shift - HNS_HW_PAGE_SHIFT;
1131 }
1132
1133 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1134 {
1135         if (count > 0)
1136                 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1137
1138         return 0;
1139 }
1140
1141 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1142 {
1143         return hr_hw_page_align(count << buf_shift);
1144 }
1145
1146 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1147 {
1148         return hr_hw_page_align(count << buf_shift) >> buf_shift;
1149 }
1150
1151 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1152 {
1153         if (!count)
1154                 return 0;
1155
1156         return ilog2(to_hr_hem_entries_count(count, buf_shift));
1157 }
1158
1159 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
1160 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1161 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1162 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
1163
1164 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1165 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1166 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1167                         u64 out_param);
1168 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1169 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1170
1171 /* hns roce hw need current block and next block addr from mtt */
1172 #define MTT_MIN_COUNT    2
1173 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1174                       int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1175 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1176                         struct hns_roce_buf_attr *buf_attr,
1177                         unsigned int page_shift, struct ib_udata *udata,
1178                         unsigned long user_addr);
1179 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1180                           struct hns_roce_mtr *mtr);
1181 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1182                      dma_addr_t *pages, int page_cnt);
1183
1184 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1185 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1186 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1187 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1188 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1189
1190 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
1191 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
1192 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1193 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1194 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1195 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev);
1196
1197 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
1198 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
1199                          int rr);
1200 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
1201                          u32 reserved_bot, u32 resetrved_top);
1202 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
1203 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1204 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
1205                                 int align, unsigned long *obj);
1206 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
1207                                 unsigned long obj, int cnt,
1208                                 int rr);
1209
1210 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1211                        struct ib_udata *udata);
1212 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1213 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1214 {
1215         return 0;
1216 }
1217
1218 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1219 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1220
1221 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1222 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1223                                    u64 virt_addr, int access_flags,
1224                                    struct ib_udata *udata);
1225 int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length,
1226                            u64 virt_addr, int mr_access_flags, struct ib_pd *pd,
1227                            struct ib_udata *udata);
1228 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1229                                 u32 max_num_sg);
1230 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1231                        unsigned int *sg_offset);
1232 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1233 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
1234                             struct hns_roce_cmd_mailbox *mailbox,
1235                             unsigned long mpt_index);
1236 unsigned long key_to_hw_index(u32 key);
1237
1238 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1239 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1240
1241 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1242 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1243                                         u32 page_shift, u32 flags);
1244
1245 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1246                            int buf_cnt, int start, struct hns_roce_buf *buf);
1247 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1248                            int buf_cnt, int start, struct ib_umem *umem,
1249                            unsigned int page_shift);
1250
1251 int hns_roce_create_srq(struct ib_srq *srq,
1252                         struct ib_srq_init_attr *srq_init_attr,
1253                         struct ib_udata *udata);
1254 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1255                         enum ib_srq_attr_mask srq_attr_mask,
1256                         struct ib_udata *udata);
1257 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1258
1259 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
1260                                  struct ib_qp_init_attr *init_attr,
1261                                  struct ib_udata *udata);
1262 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1263                        int attr_mask, struct ib_udata *udata);
1264 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1265 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
1266 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n);
1267 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n);
1268 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
1269                           struct ib_cq *ib_cq);
1270 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1271 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1272                        struct hns_roce_cq *recv_cq);
1273 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1274                          struct hns_roce_cq *recv_cq);
1275 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1276 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1277                          struct ib_udata *udata);
1278 __be32 send_ieth(const struct ib_send_wr *wr);
1279 int to_hr_qp_type(int qp_type);
1280
1281 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1282                        struct ib_udata *udata);
1283
1284 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1285 int hns_roce_db_map_user(struct hns_roce_ucontext *context,
1286                          struct ib_udata *udata, unsigned long virt,
1287                          struct hns_roce_db *db);
1288 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1289                             struct hns_roce_db *db);
1290 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1291                       int order);
1292 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1293
1294 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1295 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1296 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1297 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1298 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
1299 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1300 int hns_roce_init(struct hns_roce_dev *hr_dev);
1301 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1302
1303 int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
1304                                struct ib_cq *ib_cq);
1305 #endif /* _HNS_ROCE_DEVICE_H */