drivers/infiniband/hw/hns/hns_roce_device.h

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _HNS_ROCE_DEVICE_H
  34 #define _HNS_ROCE_DEVICE_H
  35
  36 #include <rdma/ib_verbs.h>
  37
  38 #define DRV_NAME "hns_roce"
  39
  40 #define HNS_ROCE_HW_VER1        ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
  41
  42 #define MAC_ADDR_OCTET_NUM                      6
  43 #define HNS_ROCE_MAX_MSG_LEN                    0x80000000
  44
  45 #define HNS_ROCE_ALOGN_UP(a, b) ((((a) + (b) - 1) / (b)) * (b))
  46
  47 #define HNS_ROCE_IB_MIN_SQ_STRIDE               6
  48
  49 #define HNS_ROCE_BA_SIZE                        (32 * 4096)
  50
  51 /* Hardware specification only for v1 engine */
  52 #define HNS_ROCE_MIN_CQE_NUM                    0x40
  53 #define HNS_ROCE_MIN_WQE_NUM                    0x20
  54
  55 /* Hardware specification only for v1 engine */
  56 #define HNS_ROCE_MAX_INNER_MTPT_NUM             0x7
  57 #define HNS_ROCE_MAX_MTPT_PBL_NUM               0x100000
  58
  59 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS        20
  60 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT   \
  61         (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
  62 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT             0x2
  63 #define HNS_ROCE_MIN_CQE_CNT                    16
  64
  65 #define HNS_ROCE_MAX_IRQ_NUM                    34
  66
  67 #define HNS_ROCE_COMP_VEC_NUM                   32
  68
  69 #define HNS_ROCE_AEQE_VEC_NUM                   1
  70 #define HNS_ROCE_AEQE_OF_VEC_NUM                1
  71
  72 /* 4G/4K = 1M */
  73 #define HNS_ROCE_SL_SHIFT                       28
  74 #define HNS_ROCE_TCLASS_SHIFT                   20
  75 #define HNS_ROCE_FLOW_LABLE_MASK                0xfffff
  76
  77 #define HNS_ROCE_MAX_PORTS                      6
  78 #define HNS_ROCE_MAX_GID_NUM                    16
  79 #define HNS_ROCE_GID_SIZE                       16
  80
  81 #define HNS_ROCE_HOP_NUM_0                      0xff
  82
  83 #define BITMAP_NO_RR                            0
  84 #define BITMAP_RR                               1
  85
  86 #define MR_TYPE_MR                              0x00
  87 #define MR_TYPE_DMA                             0x03
  88
  89 #define PKEY_ID                                 0xffff
  90 #define GUID_LEN                                8
  91 #define NODE_DESC_SIZE                          64
  92 #define DB_REG_OFFSET                           0x1000
  93
  94 #define SERV_TYPE_RC                            0
  95 #define SERV_TYPE_RD                            1
  96 #define SERV_TYPE_UC                            2
  97 #define SERV_TYPE_UD                            3
  98
  99 #define PAGES_SHIFT_8                           8
 100 #define PAGES_SHIFT_16                          16
 101 #define PAGES_SHIFT_24                          24
 102 #define PAGES_SHIFT_32                          32
 103
 104 enum hns_roce_qp_state {
 105         HNS_ROCE_QP_STATE_RST,
 106         HNS_ROCE_QP_STATE_INIT,
 107         HNS_ROCE_QP_STATE_RTR,
 108         HNS_ROCE_QP_STATE_RTS,
 109         HNS_ROCE_QP_STATE_SQD,
 110         HNS_ROCE_QP_STATE_ERR,
 111         HNS_ROCE_QP_NUM_STATE,
 112 };
 113
 114 enum hns_roce_event {
 115         HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
 116         HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
 117         HNS_ROCE_EVENT_TYPE_COMM_EST                  = 0x03,
 118         HNS_ROCE_EVENT_TYPE_SQ_DRAINED                = 0x04,
 119         HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR            = 0x05,
 120         HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR    = 0x06,
 121         HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR     = 0x07,
 122         HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH           = 0x08,
 123         HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH        = 0x09,
 124         HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR           = 0x0a,
 125         HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR           = 0x0b,
 126         HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW               = 0x0c,
 127         HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID             = 0x0d,
 128         HNS_ROCE_EVENT_TYPE_PORT_CHANGE               = 0x0f,
 129         /* 0x10 and 0x11 is unused in currently application case */
 130         HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,
 131         HNS_ROCE_EVENT_TYPE_MB                        = 0x13,
 132         HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW              = 0x14,
 133 };
 134
 135 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
 136 enum {
 137         HNS_ROCE_LWQCE_QPC_ERROR                = 1,
 138         HNS_ROCE_LWQCE_MTU_ERROR                = 2,
 139         HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR        = 3,
 140         HNS_ROCE_LWQCE_WQE_ADDR_ERROR           = 4,
 141         HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR       = 5,
 142         HNS_ROCE_LWQCE_SL_ERROR                 = 6,
 143         HNS_ROCE_LWQCE_PORT_ERROR               = 7,
 144 };
 145
 146 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
 147 enum {
 148         HNS_ROCE_LAVWQE_R_KEY_VIOLATION         = 1,
 149         HNS_ROCE_LAVWQE_LENGTH_ERROR            = 2,
 150         HNS_ROCE_LAVWQE_VA_ERROR                = 3,
 151         HNS_ROCE_LAVWQE_PD_ERROR                = 4,
 152         HNS_ROCE_LAVWQE_RW_ACC_ERROR            = 5,
 153         HNS_ROCE_LAVWQE_KEY_STATE_ERROR         = 6,
 154         HNS_ROCE_LAVWQE_MR_OPERATION_ERROR      = 7,
 155 };
 156
 157 /* DOORBELL overflow subtype */
 158 enum {
 159         HNS_ROCE_DB_SUBTYPE_SDB_OVF             = 1,
 160         HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF         = 2,
 161         HNS_ROCE_DB_SUBTYPE_ODB_OVF             = 3,
 162         HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF         = 4,
 163         HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP         = 5,
 164         HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP         = 6,
 165 };
 166
 167 enum {
 168         /* RQ&SRQ related operations */
 169         HNS_ROCE_OPCODE_SEND_DATA_RECEIVE       = 0x06,
 170         HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE   = 0x07,
 171 };
 172
 173 enum hns_roce_mtt_type {
 174         MTT_TYPE_WQE = 0,
 175         MTT_TYPE_CQE,
 176 };
 177
 178 #define HNS_ROCE_CMD_SUCCESS                    1
 179
 180 #define HNS_ROCE_PORT_DOWN                      0
 181 #define HNS_ROCE_PORT_UP                        1
 182
 183 #define HNS_ROCE_MTT_ENTRY_PER_SEG              8
 184
 185 #define PAGE_ADDR_SHIFT                         12
 186
 187 struct hns_roce_uar {
 188         u64             pfn;
 189         unsigned long   index;
 190 };
 191
 192 struct hns_roce_ucontext {
 193         struct ib_ucontext      ibucontext;
 194         struct hns_roce_uar     uar;
 195 };
 196
 197 struct hns_roce_pd {
 198         struct ib_pd            ibpd;
 199         unsigned long           pdn;
 200 };
 201
 202 struct hns_roce_bitmap {
 203         /* Bitmap Traversal last a bit which is 1 */
 204         unsigned long           last;
 205         unsigned long           top;
 206         unsigned long           max;
 207         unsigned long           reserved_top;
 208         unsigned long           mask;
 209         spinlock_t              lock;
 210         unsigned long           *table;
 211 };
 212
 213 /* Order bitmap length -- bit num compute formula: 1 << (max_order - order) */
 214 /* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */
 215 /* Every bit repesent to a partner free/used status in bitmap */
 216 /*
 217  * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1
 218  * Bit = 1 represent to idle and available; bit = 0: not available
 219  */
 220 struct hns_roce_buddy {
 221         /* Members point to every order level bitmap */
 222         unsigned long **bits;
 223         /* Represent to avail bits of the order level bitmap */
 224         u32            *num_free;
 225         int             max_order;
 226         spinlock_t      lock;
 227 };
 228
 229 /* For Hardware Entry Memory */
 230 struct hns_roce_hem_table {
 231         /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
 232         u32             type;
 233         /* HEM array elment num */
 234         unsigned long   num_hem;
 235         /* HEM entry record obj total num */
 236         unsigned long   num_obj;
 237         /*Single obj size */
 238         unsigned long   obj_size;
 239         int             lowmem;
 240         struct mutex    mutex;
 241         struct hns_roce_hem **hem;
 242         u64             **bt_l1;
 243         dma_addr_t      *bt_l1_dma_addr;
 244         u64             **bt_l0;
 245         dma_addr_t      *bt_l0_dma_addr;
 246 };
 247
 248 struct hns_roce_mtt {
 249         unsigned long           first_seg;
 250         int                     order;
 251         int                     page_shift;
 252         enum hns_roce_mtt_type  mtt_type;
 253 };
 254
 255 /* Only support 4K page size for mr register */
 256 #define MR_SIZE_4K 0
 257
 258 struct hns_roce_mr {
 259         struct ib_mr            ibmr;
 260         struct ib_umem          *umem;
 261         u64                     iova; /* MR's virtual orignal addr */
 262         u64                     size; /* Address range of MR */
 263         u32                     key; /* Key of MR */
 264         u32                     pd;   /* PD num of MR */
 265         u32                     access;/* Access permission of MR */
 266         int                     enabled; /* MR's active status */
 267         int                     type;   /* MR's register type */
 268         u64                     *pbl_buf;/* MR's PBL space */
 269         dma_addr_t              pbl_dma_addr;   /* MR's PBL space PA */
 270         u32                     pbl_size;/* PA number in the PBL */
 271         u64                     pbl_ba;/* page table address */
 272         u32                     l0_chunk_last_num;/* L0 last number */
 273         u32                     l1_chunk_last_num;/* L1 last number */
 274         u64                     **pbl_bt_l2;/* PBL BT L2 */
 275         u64                     **pbl_bt_l1;/* PBL BT L1 */
 276         u64                     *pbl_bt_l0;/* PBL BT L0 */
 277         dma_addr_t              *pbl_l2_dma_addr;/* PBL BT L2 dma addr */
 278         dma_addr_t              *pbl_l1_dma_addr;/* PBL BT L1 dma addr */
 279         dma_addr_t              pbl_l0_dma_addr;/* PBL BT L0 dma addr */
 280         u32                     pbl_ba_pg_sz;/* BT chunk page size */
 281         u32                     pbl_buf_pg_sz;/* buf chunk page size */
 282         u32                     pbl_hop_num;/* multi-hop number */
 283 };
 284
 285 struct hns_roce_mr_table {
 286         struct hns_roce_bitmap          mtpt_bitmap;
 287         struct hns_roce_buddy           mtt_buddy;
 288         struct hns_roce_hem_table       mtt_table;
 289         struct hns_roce_hem_table       mtpt_table;
 290         struct hns_roce_buddy           mtt_cqe_buddy;
 291         struct hns_roce_hem_table       mtt_cqe_table;
 292 };
 293
 294 struct hns_roce_wq {
 295         u64             *wrid;     /* Work request ID */
 296         spinlock_t      lock;
 297         int             wqe_cnt;  /* WQE num */
 298         u32             max_post;
 299         int             max_gs;
 300         int             offset;
 301         int             wqe_shift;/* WQE size */
 302         u32             head;
 303         u32             tail;
 304         void __iomem    *db_reg_l;
 305 };
 306
 307 struct hns_roce_buf_list {
 308         void            *buf;
 309         dma_addr_t      map;
 310 };
 311
 312 struct hns_roce_buf {
 313         struct hns_roce_buf_list        direct;
 314         struct hns_roce_buf_list        *page_list;
 315         int                             nbufs;
 316         u32                             npages;
 317         int                             page_shift;
 318 };
 319
 320 struct hns_roce_cq_buf {
 321         struct hns_roce_buf hr_buf;
 322         struct hns_roce_mtt hr_mtt;
 323 };
 324
 325 struct hns_roce_cq {
 326         struct ib_cq                    ib_cq;
 327         struct hns_roce_cq_buf          hr_buf;
 328         spinlock_t                      lock;
 329         struct ib_umem                  *umem;
 330         void (*comp)(struct hns_roce_cq *);
 331         void (*event)(struct hns_roce_cq *, enum hns_roce_event);
 332
 333         struct hns_roce_uar             *uar;
 334         u32                             cq_depth;
 335         u32                             cons_index;
 336         void __iomem                    *cq_db_l;
 337         u16                             *tptr_addr;
 338         unsigned long                   cqn;
 339         u32                             vector;
 340         atomic_t                        refcount;
 341         struct completion               free;
 342 };
 343
 344 struct hns_roce_srq {
 345         struct ib_srq           ibsrq;
 346         int                     srqn;
 347 };
 348
 349 struct hns_roce_uar_table {
 350         struct hns_roce_bitmap bitmap;
 351 };
 352
 353 struct hns_roce_qp_table {
 354         struct hns_roce_bitmap          bitmap;
 355         spinlock_t                      lock;
 356         struct hns_roce_hem_table       qp_table;
 357         struct hns_roce_hem_table       irrl_table;
 358 };
 359
 360 struct hns_roce_cq_table {
 361         struct hns_roce_bitmap          bitmap;
 362         spinlock_t                      lock;
 363         struct radix_tree_root          tree;
 364         struct hns_roce_hem_table       table;
 365 };
 366
 367 struct hns_roce_raq_table {
 368         struct hns_roce_buf_list        *e_raq_buf;
 369 };
 370
 371 struct hns_roce_av {
 372         __le32      port_pd;
 373         u8          gid_index;
 374         u8          stat_rate;
 375         u8          hop_limit;
 376         __le32      sl_tclass_flowlabel;
 377         u8          dgid[HNS_ROCE_GID_SIZE];
 378         u8          mac[6];
 379         __le16      vlan;
 380 };
 381
 382 struct hns_roce_ah {
 383         struct ib_ah            ibah;
 384         struct hns_roce_av      av;
 385 };
 386
 387 struct hns_roce_cmd_context {
 388         struct completion       done;
 389         int                     result;
 390         int                     next;
 391         u64                     out_param;
 392         u16                     token;
 393 };
 394
 395 struct hns_roce_cmdq {
 396         struct dma_pool         *pool;
 397         struct mutex            hcr_mutex;
 398         struct semaphore        poll_sem;
 399         /*
 400          * Event mode: cmd register mutex protection,
 401          * ensure to not exceed max_cmds and user use limit region
 402          */
 403         struct semaphore        event_sem;
 404         int                     max_cmds;
 405         spinlock_t              context_lock;
 406         int                     free_head;
 407         struct hns_roce_cmd_context *context;
 408         /*
 409          * Result of get integer part
 410          * which max_comds compute according a power of 2
 411          */
 412         u16                     token_mask;
 413         /*
 414          * Process whether use event mode, init default non-zero
 415          * After the event queue of cmd event ready,
 416          * can switch into event mode
 417          * close device, switch into poll mode(non event mode)
 418          */
 419         u8                      use_events;
 420         u8                      toggle;
 421 };
 422
 423 struct hns_roce_cmd_mailbox {
 424         void                   *buf;
 425         dma_addr_t              dma;
 426 };
 427
 428 struct hns_roce_dev;
 429
 430 struct hns_roce_qp {
 431         struct ib_qp            ibqp;
 432         struct hns_roce_buf     hr_buf;
 433         struct hns_roce_wq      rq;
 434         __le64                  doorbell_qpn;
 435         __le32                  sq_signal_bits;
 436         u32                     sq_next_wqe;
 437         int                     sq_max_wqes_per_wr;
 438         int                     sq_spare_wqes;
 439         struct hns_roce_wq      sq;
 440
 441         struct ib_umem          *umem;
 442         struct hns_roce_mtt     mtt;
 443         u32                     buff_size;
 444         struct mutex            mutex;
 445         u8                      port;
 446         u8                      phy_port;
 447         u8                      sl;
 448         u8                      resp_depth;
 449         u8                      state;
 450         u32                     access_flags;
 451         u32                     pkey_index;
 452         void                    (*event)(struct hns_roce_qp *,
 453                                          enum hns_roce_event);
 454         unsigned long           qpn;
 455
 456         atomic_t                refcount;
 457         struct completion       free;
 458 };
 459
 460 struct hns_roce_sqp {
 461         struct hns_roce_qp      hr_qp;
 462 };
 463
 464 struct hns_roce_ib_iboe {
 465         spinlock_t              lock;
 466         struct net_device      *netdevs[HNS_ROCE_MAX_PORTS];
 467         struct notifier_block   nb;
 468         struct notifier_block   nb_inet;
 469         u8                      phy_port[HNS_ROCE_MAX_PORTS];
 470 };
 471
 472 struct hns_roce_eq {
 473         struct hns_roce_dev             *hr_dev;
 474         void __iomem                    *doorbell;
 475
 476         int                             type_flag;/* Aeq:1 ceq:0 */
 477         int                             eqn;
 478         u32                             entries;
 479         int                             log_entries;
 480         int                             eqe_size;
 481         int                             irq;
 482         int                             log_page_size;
 483         int                             cons_index;
 484         struct hns_roce_buf_list        *buf_list;
 485 };
 486
 487 struct hns_roce_eq_table {
 488         struct hns_roce_eq      *eq;
 489         void __iomem            **eqc_base;
 490 };
 491
 492 struct hns_roce_caps {
 493         u8              num_ports;
 494         int             gid_table_len[HNS_ROCE_MAX_PORTS];
 495         int             pkey_table_len[HNS_ROCE_MAX_PORTS];
 496         int             local_ca_ack_delay;
 497         int             num_uars;
 498         u32             phy_num_uars;
 499         u32             max_sq_sg;      /* 2 */
 500         u32             max_sq_inline;  /* 32 */
 501         u32             max_rq_sg;      /* 2 */
 502         int             num_qps;        /* 256k */
 503         u32             max_wqes;       /* 16k */
 504         u32             max_sq_desc_sz; /* 64 */
 505         u32             max_rq_desc_sz; /* 64 */
 506         u32             max_srq_desc_sz;
 507         int             max_qp_init_rdma;
 508         int             max_qp_dest_rdma;
 509         int             num_cqs;
 510         int             max_cqes;
 511         int             reserved_cqs;
 512         int             num_aeq_vectors;        /* 1 */
 513         int             num_comp_vectors;       /* 32 ceq */
 514         int             num_other_vectors;
 515         int             num_mtpts;
 516         u32             num_mtt_segs;
 517         u32             num_cqe_segs;
 518         int             reserved_mrws;
 519         int             reserved_uars;
 520         int             num_pds;
 521         int             reserved_pds;
 522         u32             mtt_entry_sz;
 523         u32             cq_entry_sz;
 524         u32             page_size_cap;
 525         u32             reserved_lkey;
 526         int             mtpt_entry_sz;
 527         int             qpc_entry_sz;
 528         int             irrl_entry_sz;
 529         int             cqc_entry_sz;
 530         u32             pbl_ba_pg_sz;
 531         u32             pbl_buf_pg_sz;
 532         u32             pbl_hop_num;
 533         int             aeqe_depth;
 534         int             ceqe_depth[HNS_ROCE_COMP_VEC_NUM];
 535         enum ib_mtu     max_mtu;
 536         u32             qpc_bt_num;
 537         u32             srqc_bt_num;
 538         u32             cqc_bt_num;
 539         u32             mpt_bt_num;
 540         u32             qpc_ba_pg_sz;
 541         u32             qpc_buf_pg_sz;
 542         u32             qpc_hop_num;
 543         u32             srqc_ba_pg_sz;
 544         u32             srqc_buf_pg_sz;
 545         u32             srqc_hop_num;
 546         u32             cqc_ba_pg_sz;
 547         u32             cqc_buf_pg_sz;
 548         u32             cqc_hop_num;
 549         u32             mpt_ba_pg_sz;
 550         u32             mpt_buf_pg_sz;
 551         u32             mpt_hop_num;
 552         u32             mtt_ba_pg_sz;
 553         u32             mtt_buf_pg_sz;
 554         u32             mtt_hop_num;
 555         u32             cqe_ba_pg_sz;
 556         u32             cqe_buf_pg_sz;
 557         u32             cqe_hop_num;
 558 };
 559
 560 struct hns_roce_hw {
 561         int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
 562         int (*cmq_init)(struct hns_roce_dev *hr_dev);
 563         void (*cmq_exit)(struct hns_roce_dev *hr_dev);
 564         int (*hw_profile)(struct hns_roce_dev *hr_dev);
 565         int (*hw_init)(struct hns_roce_dev *hr_dev);
 566         void (*hw_exit)(struct hns_roce_dev *hr_dev);
 567         int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
 568                          u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
 569                          u16 token, int event);
 570         int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
 571         void (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
 572                         union ib_gid *gid);
 573         void (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
 574         void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
 575                         enum ib_mtu mtu);
 576         int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr,
 577                           unsigned long mtpt_idx);
 578         void (*write_cqc)(struct hns_roce_dev *hr_dev,
 579                           struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
 580                           dma_addr_t dma_handle, int nent, u32 vector);
 581         int (*set_hem)(struct hns_roce_dev *hr_dev,
 582                        struct hns_roce_hem_table *table, int obj, int step_idx);
 583         int (*clear_hem)(struct hns_roce_dev *hr_dev,
 584                          struct hns_roce_hem_table *table, int obj,
 585                          int step_idx);
 586         int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
 587                         int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
 588         int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
 589                          int attr_mask, enum ib_qp_state cur_state,
 590                          enum ib_qp_state new_state);
 591         int (*destroy_qp)(struct ib_qp *ibqp);
 592         int (*post_send)(struct ib_qp *ibqp, struct ib_send_wr *wr,
 593                          struct ib_send_wr **bad_wr);
 594         int (*post_recv)(struct ib_qp *qp, struct ib_recv_wr *recv_wr,
 595                          struct ib_recv_wr **bad_recv_wr);
 596         int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 597         int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 598         int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr);
 599         int (*destroy_cq)(struct ib_cq *ibcq);
 600 };
 601
 602 struct hns_roce_dev {
 603         struct ib_device        ib_dev;
 604         struct platform_device  *pdev;
 605         struct pci_dev          *pci_dev;
 606         struct device           *dev;
 607         struct hns_roce_uar     priv_uar;
 608         const char              *irq_names[HNS_ROCE_MAX_IRQ_NUM];
 609         spinlock_t              sm_lock;
 610         spinlock_t              bt_cmd_lock;
 611         struct hns_roce_ib_iboe iboe;
 612
 613         int                     irq[HNS_ROCE_MAX_IRQ_NUM];
 614         u8 __iomem              *reg_base;
 615         struct hns_roce_caps    caps;
 616         struct radix_tree_root  qp_table_tree;
 617
 618         unsigned char   dev_addr[HNS_ROCE_MAX_PORTS][MAC_ADDR_OCTET_NUM];
 619         u64                     sys_image_guid;
 620         u32                     vendor_id;
 621         u32                     vendor_part_id;
 622         u32                     hw_rev;
 623         void __iomem            *priv_addr;
 624
 625         struct hns_roce_cmdq    cmd;
 626         struct hns_roce_bitmap    pd_bitmap;
 627         struct hns_roce_uar_table uar_table;
 628         struct hns_roce_mr_table  mr_table;
 629         struct hns_roce_cq_table  cq_table;
 630         struct hns_roce_qp_table  qp_table;
 631         struct hns_roce_eq_table  eq_table;
 632
 633         int                     cmd_mod;
 634         int                     loop_idc;
 635         dma_addr_t              tptr_dma_addr; /*only for hw v1*/
 636         u32                     tptr_size; /*only for hw v1*/
 637         const struct hns_roce_hw *hw;
 638         void                    *priv;
 639 };
 640
 641 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
 642 {
 643         return container_of(ib_dev, struct hns_roce_dev, ib_dev);
 644 }
 645
 646 static inline struct hns_roce_ucontext
 647                         *to_hr_ucontext(struct ib_ucontext *ibucontext)
 648 {
 649         return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
 650 }
 651
 652 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
 653 {
 654         return container_of(ibpd, struct hns_roce_pd, ibpd);
 655 }
 656
 657 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
 658 {
 659         return container_of(ibah, struct hns_roce_ah, ibah);
 660 }
 661
 662 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
 663 {
 664         return container_of(ibmr, struct hns_roce_mr, ibmr);
 665 }
 666
 667 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
 668 {
 669         return container_of(ibqp, struct hns_roce_qp, ibqp);
 670 }
 671
 672 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
 673 {
 674         return container_of(ib_cq, struct hns_roce_cq, ib_cq);
 675 }
 676
 677 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
 678 {
 679         return container_of(ibsrq, struct hns_roce_srq, ibsrq);
 680 }
 681
 682 static inline struct hns_roce_sqp *hr_to_hr_sqp(struct hns_roce_qp *hr_qp)
 683 {
 684         return container_of(hr_qp, struct hns_roce_sqp, hr_qp);
 685 }
 686
 687 static inline void hns_roce_write64_k(__be32 val[2], void __iomem *dest)
 688 {
 689         __raw_writeq(*(u64 *) val, dest);
 690 }
 691
 692 static inline struct hns_roce_qp
 693         *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
 694 {
 695         return radix_tree_lookup(&hr_dev->qp_table_tree,
 696                                  qpn & (hr_dev->caps.num_qps - 1));
 697 }
 698
 699 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
 700 {
 701         u32 bits_per_long_val = BITS_PER_LONG;
 702
 703         if (bits_per_long_val == 64 || buf->nbufs == 1)
 704                 return (char *)(buf->direct.buf) + offset;
 705         else
 706                 return (char *)(buf->page_list[offset >> PAGE_SHIFT].buf) +
 707                        (offset & (PAGE_SIZE - 1));
 708 }
 709
 710 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
 711 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
 712 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
 713 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
 714
 715 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
 716 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
 717 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
 718                         u64 out_param);
 719 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
 720 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
 721
 722 int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift,
 723                       struct hns_roce_mtt *mtt);
 724 void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev,
 725                           struct hns_roce_mtt *mtt);
 726 int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev,
 727                            struct hns_roce_mtt *mtt, struct hns_roce_buf *buf);
 728
 729 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
 730 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
 731 int hns_roce_init_eq_table(struct hns_roce_dev *hr_dev);
 732 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
 733 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
 734
 735 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
 736 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
 737 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
 738 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
 739 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
 740
 741 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
 742 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
 743                          int rr);
 744 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
 745                          u32 reserved_bot, u32 resetrved_top);
 746 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
 747 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
 748 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
 749                                 int align, unsigned long *obj);
 750 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
 751                                 unsigned long obj, int cnt,
 752                                 int rr);
 753
 754 struct ib_ah *hns_roce_create_ah(struct ib_pd *pd,
 755                                  struct rdma_ah_attr *ah_attr,
 756                                  struct ib_udata *udata);
 757 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
 758 int hns_roce_destroy_ah(struct ib_ah *ah);
 759
 760 struct ib_pd *hns_roce_alloc_pd(struct ib_device *ib_dev,
 761                                 struct ib_ucontext *context,
 762                                 struct ib_udata *udata);
 763 int hns_roce_dealloc_pd(struct ib_pd *pd);
 764
 765 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
 766 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
 767                                    u64 virt_addr, int access_flags,
 768                                    struct ib_udata *udata);
 769 int hns_roce_dereg_mr(struct ib_mr *ibmr);
 770 int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev,
 771                        struct hns_roce_cmd_mailbox *mailbox,
 772                        unsigned long mpt_index);
 773 unsigned long key_to_hw_index(u32 key);
 774
 775 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size,
 776                        struct hns_roce_buf *buf);
 777 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
 778                        struct hns_roce_buf *buf);
 779
 780 int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev,
 781                                struct hns_roce_mtt *mtt, struct ib_umem *umem);
 782
 783 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
 784                                  struct ib_qp_init_attr *init_attr,
 785                                  struct ib_udata *udata);
 786 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 787                        int attr_mask, struct ib_udata *udata);
 788 void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
 789 void *get_send_wqe(struct hns_roce_qp *hr_qp, int n);
 790 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
 791                           struct ib_cq *ib_cq);
 792 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
 793 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
 794                        struct hns_roce_cq *recv_cq);
 795 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
 796                          struct hns_roce_cq *recv_cq);
 797 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
 798 void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
 799 void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
 800                                int cnt);
 801 __be32 send_ieth(struct ib_send_wr *wr);
 802 int to_hr_qp_type(int qp_type);
 803
 804 struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
 805                                     const struct ib_cq_init_attr *attr,
 806                                     struct ib_ucontext *context,
 807                                     struct ib_udata *udata);
 808
 809 int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq);
 810 void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq);
 811
 812 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
 813 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
 814 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
 815 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
 816 int hns_roce_init(struct hns_roce_dev *hr_dev);
 817 void hns_roce_exit(struct hns_roce_dev *hr_dev);
 818
 819 #endif /* _HNS_ROCE_DEVICE_H */