2 * Copyright (c) 2016 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _HNS_ROCE_DEVICE_H
34 #define _HNS_ROCE_DEVICE_H
36 #include <rdma/ib_verbs.h>
38 #define DRV_NAME "hns_roce"
40 /* hip08 is a pci device */
41 #define PCI_REVISION_ID_HIP08 0x21
43 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
45 #define HNS_ROCE_MAX_MSG_LEN 0x80000000
47 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6
49 #define HNS_ROCE_BA_SIZE (32 * 4096)
53 /* Hardware specification only for v1 engine */
54 #define HNS_ROCE_MIN_CQE_NUM 0x40
55 #define HNS_ROCE_MIN_WQE_NUM 0x20
57 /* Hardware specification only for v1 engine */
58 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7
59 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000
60 #define HNS_ROCE_MAX_SGE_NUM 2
62 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20
63 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \
64 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
65 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2
66 #define HNS_ROCE_MIN_CQE_CNT 16
68 #define HNS_ROCE_MAX_IRQ_NUM 128
70 #define HNS_ROCE_SGE_IN_WQE 2
71 #define HNS_ROCE_SGE_SHIFT 4
76 #define HNS_ROCE_CEQ 0
77 #define HNS_ROCE_AEQ 1
79 #define HNS_ROCE_CEQ_ENTRY_SIZE 0x4
80 #define HNS_ROCE_AEQ_ENTRY_SIZE 0x10
82 #define HNS_ROCE_SL_SHIFT 28
83 #define HNS_ROCE_TCLASS_SHIFT 20
84 #define HNS_ROCE_FLOW_LABEL_MASK 0xfffff
86 #define HNS_ROCE_MAX_PORTS 6
87 #define HNS_ROCE_MAX_GID_NUM 16
88 #define HNS_ROCE_GID_SIZE 16
89 #define HNS_ROCE_SGE_SIZE 16
91 #define HNS_ROCE_HOP_NUM_0 0xff
93 #define BITMAP_NO_RR 0
96 #define MR_TYPE_MR 0x00
97 #define MR_TYPE_FRMR 0x01
98 #define MR_TYPE_DMA 0x03
100 #define HNS_ROCE_FRMR_MAX_PA 512
102 #define PKEY_ID 0xffff
104 #define NODE_DESC_SIZE 64
105 #define DB_REG_OFFSET 0x1000
107 /* Configure to HW for PAGE_SIZE larger than 4KB */
108 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12)
110 #define PAGES_SHIFT_8 8
111 #define PAGES_SHIFT_16 16
112 #define PAGES_SHIFT_24 24
113 #define PAGES_SHIFT_32 32
115 #define HNS_ROCE_PCI_BAR_NUM 2
117 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4
118 #define SRQ_DB_REG 0x230
120 /* The chip implementation of the consumer index is calculated
121 * according to twice the actual EQ depth
123 #define EQ_DEPTH_COEFF 2
133 HNS_ROCE_QP_CAP_RQ_RECORD_DB = BIT(0),
134 HNS_ROCE_QP_CAP_SQ_RECORD_DB = BIT(1),
137 enum hns_roce_cq_flags {
138 HNS_ROCE_CQ_FLAG_RECORD_DB = BIT(0),
141 enum hns_roce_qp_state {
142 HNS_ROCE_QP_STATE_RST,
143 HNS_ROCE_QP_STATE_INIT,
144 HNS_ROCE_QP_STATE_RTR,
145 HNS_ROCE_QP_STATE_RTS,
146 HNS_ROCE_QP_STATE_SQD,
147 HNS_ROCE_QP_STATE_ERR,
148 HNS_ROCE_QP_NUM_STATE,
151 enum hns_roce_event {
152 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01,
153 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02,
154 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03,
155 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04,
156 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
157 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06,
158 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07,
159 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08,
160 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09,
161 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a,
162 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b,
163 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c,
164 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d,
165 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f,
166 /* 0x10 and 0x11 is unused in currently application case */
167 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12,
168 HNS_ROCE_EVENT_TYPE_MB = 0x13,
169 HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW = 0x14,
170 HNS_ROCE_EVENT_TYPE_FLR = 0x15,
173 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
175 HNS_ROCE_LWQCE_QPC_ERROR = 1,
176 HNS_ROCE_LWQCE_MTU_ERROR = 2,
177 HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3,
178 HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4,
179 HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5,
180 HNS_ROCE_LWQCE_SL_ERROR = 6,
181 HNS_ROCE_LWQCE_PORT_ERROR = 7,
184 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
186 HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1,
187 HNS_ROCE_LAVWQE_LENGTH_ERROR = 2,
188 HNS_ROCE_LAVWQE_VA_ERROR = 3,
189 HNS_ROCE_LAVWQE_PD_ERROR = 4,
190 HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5,
191 HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6,
192 HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7,
195 /* DOORBELL overflow subtype */
197 HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1,
198 HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2,
199 HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3,
200 HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4,
201 HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5,
202 HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6,
206 /* RQ&SRQ related operations */
207 HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06,
208 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07,
211 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12
214 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0),
215 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1),
216 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2),
217 HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3),
218 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4),
219 HNS_ROCE_CAP_FLAG_SRQ = BIT(5),
220 HNS_ROCE_CAP_FLAG_MW = BIT(7),
221 HNS_ROCE_CAP_FLAG_FRMR = BIT(8),
222 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9),
223 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10),
226 #define HNS_ROCE_DB_TYPE_COUNT 2
227 #define HNS_ROCE_DB_UNIT_SIZE 4
230 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
233 enum hns_roce_reset_stage {
234 HNS_ROCE_STATE_NON_RST,
235 HNS_ROCE_STATE_RST_BEF_DOWN,
236 HNS_ROCE_STATE_RST_DOWN,
237 HNS_ROCE_STATE_RST_UNINIT,
238 HNS_ROCE_STATE_RST_INIT,
239 HNS_ROCE_STATE_RST_INITED,
242 enum hns_roce_instance_state {
243 HNS_ROCE_STATE_NON_INIT,
245 HNS_ROCE_STATE_INITED,
246 HNS_ROCE_STATE_UNINIT,
250 HNS_ROCE_RST_DIRECT_RETURN = 0,
259 #define HNS_ROCE_CMD_SUCCESS 1
261 #define HNS_ROCE_PORT_DOWN 0
262 #define HNS_ROCE_PORT_UP 1
264 /* The minimum page size is 4K for hardware */
265 #define HNS_HW_PAGE_SHIFT 12
266 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT)
268 /* The minimum page count for hardware access page directly. */
269 #define HNS_HW_DIRECT_PAGE_COUNT 2
271 struct hns_roce_uar {
274 unsigned long logic_idx;
277 struct hns_roce_ucontext {
278 struct ib_ucontext ibucontext;
279 struct hns_roce_uar uar;
280 struct list_head page_list;
281 struct mutex page_mutex;
289 struct hns_roce_bitmap {
290 /* Bitmap Traversal last a bit which is 1 */
294 unsigned long reserved_top;
297 unsigned long *table;
300 /* For Hardware Entry Memory */
301 struct hns_roce_hem_table {
302 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
304 /* HEM array elment num */
305 unsigned long num_hem;
306 /* HEM entry record obj total num */
307 unsigned long num_obj;
308 /* Single obj size */
309 unsigned long obj_size;
310 unsigned long table_chunk_size;
313 struct hns_roce_hem **hem;
315 dma_addr_t *bt_l1_dma_addr;
317 dma_addr_t *bt_l0_dma_addr;
320 struct hns_roce_buf_region {
321 int offset; /* page offset */
322 u32 count; /* page count */
323 int hopnum; /* addressing hop num */
326 #define HNS_ROCE_MAX_BT_REGION 3
327 #define HNS_ROCE_MAX_BT_LEVEL 3
328 struct hns_roce_hem_list {
329 struct list_head root_bt;
330 /* link all bt dma mem by hop config */
331 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
332 struct list_head btm_bt; /* link all bottom bt in @mid_bt */
333 dma_addr_t root_ba; /* pointer to the root ba table */
336 struct hns_roce_buf_attr {
338 size_t size; /* region size */
339 int hopnum; /* multi-hop addressing hop num */
340 } region[HNS_ROCE_MAX_BT_REGION];
341 int region_count; /* valid region count */
342 unsigned int page_shift; /* buffer page shift */
343 bool fixed_page; /* decide page shift is fixed-size or maximum size */
344 int user_access; /* umem access flag */
345 bool mtt_only; /* only alloc buffer-required MTT memory */
348 struct hns_roce_hem_cfg {
349 dma_addr_t root_ba; /* root BA table's address */
350 bool is_direct; /* addressing without BA table */
351 unsigned int ba_pg_shift; /* BA table page shift */
352 unsigned int buf_pg_shift; /* buffer page shift */
353 unsigned int buf_pg_count; /* buffer page count */
354 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
358 /* memory translate region */
359 struct hns_roce_mtr {
360 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
361 struct ib_umem *umem; /* user space buffer */
362 struct hns_roce_buf *kmem; /* kernel space buffer */
363 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */
370 int enabled; /* MW's active status */
376 /* Only support 4K page size for mr register */
381 u64 iova; /* MR's virtual orignal addr */
382 u64 size; /* Address range of MR */
383 u32 key; /* Key of MR */
384 u32 pd; /* PD num of MR */
385 u32 access; /* Access permission of MR */
386 int enabled; /* MR's active status */
387 int type; /* MR's register type */
388 u32 pbl_hop_num; /* multi-hop number */
389 struct hns_roce_mtr pbl_mtr;
391 dma_addr_t *page_list;
394 struct hns_roce_mr_table {
395 struct hns_roce_bitmap mtpt_bitmap;
396 struct hns_roce_hem_table mtpt_table;
400 u64 *wrid; /* Work request ID */
402 u32 wqe_cnt; /* WQE num */
405 int wqe_shift; /* WQE size */
408 void __iomem *db_reg_l;
411 struct hns_roce_sge {
412 unsigned int sge_cnt; /* SGE num */
414 int sge_shift; /* SGE size */
417 struct hns_roce_buf_list {
422 struct hns_roce_buf {
423 struct hns_roce_buf_list direct;
424 struct hns_roce_buf_list *page_list;
427 unsigned int page_shift;
430 struct hns_roce_db_pgdir {
431 struct list_head list;
432 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
433 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
434 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT];
439 struct hns_roce_user_db_page {
440 struct list_head list;
441 struct ib_umem *umem;
442 unsigned long user_virt;
449 struct hns_roce_db_pgdir *pgdir;
450 struct hns_roce_user_db_page *user_page;
460 struct hns_roce_mtr mtr;
461 struct hns_roce_db db;
467 void __iomem *cq_db_l;
473 struct completion free;
474 struct list_head sq_list; /* all qps on this send cq */
475 struct list_head rq_list; /* all qps on this recv cq */
476 int is_armed; /* cq is armed */
477 struct list_head node; /* all armed cqs are on a list */
480 struct hns_roce_idx_que {
481 struct hns_roce_mtr mtr;
483 unsigned long *bitmap;
486 struct hns_roce_srq {
492 void __iomem *db_reg_l;
495 struct completion free;
497 struct hns_roce_mtr buf_mtr;
500 struct hns_roce_idx_que idx_que;
505 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
508 struct hns_roce_uar_table {
509 struct hns_roce_bitmap bitmap;
512 struct hns_roce_qp_table {
513 struct hns_roce_bitmap bitmap;
514 struct hns_roce_hem_table qp_table;
515 struct hns_roce_hem_table irrl_table;
516 struct hns_roce_hem_table trrl_table;
517 struct hns_roce_hem_table sccc_table;
518 struct mutex scc_mutex;
521 struct hns_roce_cq_table {
522 struct hns_roce_bitmap bitmap;
524 struct hns_roce_hem_table table;
527 struct hns_roce_srq_table {
528 struct hns_roce_bitmap bitmap;
530 struct hns_roce_hem_table table;
533 struct hns_roce_raq_table {
534 struct hns_roce_buf_list *e_raq_buf;
545 u8 dgid[HNS_ROCE_GID_SIZE];
553 struct hns_roce_av av;
556 struct hns_roce_cmd_context {
557 struct completion done;
564 struct hns_roce_cmdq {
565 struct dma_pool *pool;
566 struct mutex hcr_mutex;
567 struct semaphore poll_sem;
569 * Event mode: cmd register mutex protection,
570 * ensure to not exceed max_cmds and user use limit region
572 struct semaphore event_sem;
574 spinlock_t context_lock;
576 struct hns_roce_cmd_context *context;
578 * Result of get integer part
579 * which max_comds compute according a power of 2
583 * Process whether use event mode, init default non-zero
584 * After the event queue of cmd event ready,
585 * can switch into event mode
586 * close device, switch into poll mode(non event mode)
591 struct hns_roce_cmd_mailbox {
598 struct hns_roce_rinl_sge {
603 struct hns_roce_rinl_wqe {
604 struct hns_roce_rinl_sge *sg_list;
608 struct hns_roce_rinl_buf {
609 struct hns_roce_rinl_wqe *wqe_list;
614 HNS_ROCE_FLUSH_FLAG = 0,
617 struct hns_roce_work {
618 struct hns_roce_dev *hr_dev;
619 struct work_struct work;
628 struct hns_roce_wq rq;
629 struct hns_roce_db rdb;
630 struct hns_roce_db sdb;
631 unsigned long en_flags;
634 struct hns_roce_wq sq;
636 struct hns_roce_mtr mtr;
649 void (*event)(struct hns_roce_qp *qp,
650 enum hns_roce_event event_type);
654 struct completion free;
656 struct hns_roce_sge sge;
659 /* 0: flush needed, 1: unneeded */
660 unsigned long flush_flag;
661 struct hns_roce_work flush_work;
662 struct hns_roce_rinl_buf rq_inl_buf;
663 struct list_head node; /* all qps are on a list */
664 struct list_head rq_node; /* all recv qps are on a list */
665 struct list_head sq_node; /* all send qps are on a list */
668 struct hns_roce_ib_iboe {
670 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
671 struct notifier_block nb;
672 u8 phy_port[HNS_ROCE_MAX_PORTS];
676 HNS_ROCE_EQ_STAT_INVALID = 0,
677 HNS_ROCE_EQ_STAT_VALID = 2,
680 struct hns_roce_ceqe {
684 struct hns_roce_aeqe {
721 struct hns_roce_dev *hr_dev;
722 void __iomem *doorbell;
724 int type_flag; /* Aeq:1 ceq:0 */
732 struct hns_roce_buf_list *buf_list;
737 struct hns_roce_mtr mtr;
745 struct hns_roce_eq_table {
746 struct hns_roce_eq *eq;
747 void __iomem **eqc_base; /* only for hw v1 */
750 struct hns_roce_caps {
753 int gid_table_len[HNS_ROCE_MAX_PORTS];
754 int pkey_table_len[HNS_ROCE_MAX_PORTS];
755 int local_ca_ack_delay;
773 int max_qp_init_rdma;
774 int max_qp_dest_rdma;
782 int num_comp_vectors;
783 int num_other_vectors;
803 int qpc_timer_entry_sz;
804 int cqc_timer_entry_sz;
814 u32 qpc_timer_bt_num;
817 u32 cqc_timer_bt_num;
841 u32 qpc_timer_ba_pg_sz;
842 u32 qpc_timer_buf_pg_sz;
843 u32 qpc_timer_hop_num;
844 u32 cqc_timer_ba_pg_sz;
845 u32 cqc_timer_buf_pg_sz;
846 u32 cqc_timer_hop_num;
847 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */
851 u32 srqwqe_buf_pg_sz;
862 u32 chunk_sz; /* chunk size in non multihop mode */
864 u16 default_ceq_max_cnt;
865 u16 default_ceq_period;
866 u16 default_aeq_max_cnt;
867 u16 default_aeq_period;
868 u16 default_aeq_arm_st;
869 u16 default_ceq_arm_st;
872 struct hns_roce_dfx_hw {
873 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
877 enum hns_roce_device_state {
878 HNS_ROCE_DEVICE_STATE_INITED,
879 HNS_ROCE_DEVICE_STATE_RST_DOWN,
880 HNS_ROCE_DEVICE_STATE_UNINIT,
884 int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
885 int (*cmq_init)(struct hns_roce_dev *hr_dev);
886 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
887 int (*hw_profile)(struct hns_roce_dev *hr_dev);
888 int (*hw_init)(struct hns_roce_dev *hr_dev);
889 void (*hw_exit)(struct hns_roce_dev *hr_dev);
890 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
891 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
892 u16 token, int event);
893 int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
894 int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev);
895 int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
896 const union ib_gid *gid, const struct ib_gid_attr *attr);
897 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
898 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
900 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
901 struct hns_roce_mr *mr, unsigned long mtpt_idx);
902 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
903 struct hns_roce_mr *mr, int flags, u32 pdn,
904 int mr_access_flags, u64 iova, u64 size,
906 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
907 struct hns_roce_mr *mr);
908 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
909 void (*write_cqc)(struct hns_roce_dev *hr_dev,
910 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
911 dma_addr_t dma_handle);
912 int (*set_hem)(struct hns_roce_dev *hr_dev,
913 struct hns_roce_hem_table *table, int obj, int step_idx);
914 int (*clear_hem)(struct hns_roce_dev *hr_dev,
915 struct hns_roce_hem_table *table, int obj,
917 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
918 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
919 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
920 int attr_mask, enum ib_qp_state cur_state,
921 enum ib_qp_state new_state);
922 int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata);
923 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
924 struct hns_roce_qp *hr_qp);
925 int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr,
926 const struct ib_send_wr **bad_wr);
927 int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr,
928 const struct ib_recv_wr **bad_recv_wr);
929 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
930 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
931 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
932 struct ib_udata *udata);
933 void (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
934 int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
935 int (*init_eq)(struct hns_roce_dev *hr_dev);
936 void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
937 void (*write_srqc)(struct hns_roce_dev *hr_dev,
938 struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn,
939 void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx,
940 dma_addr_t dma_handle_wqe,
941 dma_addr_t dma_handle_idx);
942 int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
943 enum ib_srq_attr_mask srq_attr_mask,
944 struct ib_udata *udata);
945 int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr);
946 int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
947 const struct ib_recv_wr **bad_wr);
948 const struct ib_device_ops *hns_roce_dev_ops;
949 const struct ib_device_ops *hns_roce_dev_srq_ops;
952 struct hns_roce_dev {
953 struct ib_device ib_dev;
954 struct platform_device *pdev;
955 struct pci_dev *pci_dev;
957 struct hns_roce_uar priv_uar;
958 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
960 spinlock_t bt_cmd_lock;
964 unsigned long reset_cnt;
965 struct hns_roce_ib_iboe iboe;
966 enum hns_roce_device_state state;
967 struct list_head qp_list; /* list of all qps on this dev */
968 spinlock_t qp_list_lock; /* protect qp_list */
970 struct list_head pgdir_list;
971 struct mutex pgdir_mutex;
972 int irq[HNS_ROCE_MAX_IRQ_NUM];
973 u8 __iomem *reg_base;
974 struct hns_roce_caps caps;
975 struct xarray qp_table_xa;
977 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
982 void __iomem *priv_addr;
984 struct hns_roce_cmdq cmd;
985 struct hns_roce_bitmap pd_bitmap;
986 struct hns_roce_uar_table uar_table;
987 struct hns_roce_mr_table mr_table;
988 struct hns_roce_cq_table cq_table;
989 struct hns_roce_srq_table srq_table;
990 struct hns_roce_qp_table qp_table;
991 struct hns_roce_eq_table eq_table;
992 struct hns_roce_hem_table qpc_timer_table;
993 struct hns_roce_hem_table cqc_timer_table;
999 dma_addr_t tptr_dma_addr; /* only for hw v1 */
1000 u32 tptr_size; /* only for hw v1 */
1001 const struct hns_roce_hw *hw;
1003 struct workqueue_struct *irq_workq;
1004 const struct hns_roce_dfx_hw *dfx;
1007 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
1009 return container_of(ib_dev, struct hns_roce_dev, ib_dev);
1012 static inline struct hns_roce_ucontext
1013 *to_hr_ucontext(struct ib_ucontext *ibucontext)
1015 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1018 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1020 return container_of(ibpd, struct hns_roce_pd, ibpd);
1023 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1025 return container_of(ibah, struct hns_roce_ah, ibah);
1028 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1030 return container_of(ibmr, struct hns_roce_mr, ibmr);
1033 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1035 return container_of(ibmw, struct hns_roce_mw, ibmw);
1038 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1040 return container_of(ibqp, struct hns_roce_qp, ibqp);
1043 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1045 return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1048 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1050 return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1053 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1055 __raw_writeq(*(u64 *) val, dest);
1058 static inline struct hns_roce_qp
1059 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1061 return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1));
1064 static inline bool hns_roce_buf_is_direct(struct hns_roce_buf *buf)
1072 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
1074 if (hns_roce_buf_is_direct(buf))
1075 return (char *)(buf->direct.buf) + (offset & (buf->size - 1));
1077 return (char *)(buf->page_list[offset >> buf->page_shift].buf) +
1078 (offset & ((1 << buf->page_shift) - 1));
1081 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, int idx)
1083 if (hns_roce_buf_is_direct(buf))
1084 return buf->direct.map + ((dma_addr_t)idx << buf->page_shift);
1086 return buf->page_list[idx].map;
1089 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1091 static inline u64 to_hr_hw_page_addr(u64 addr)
1093 return addr >> HNS_HW_PAGE_SHIFT;
1096 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1098 return page_shift - HNS_HW_PAGE_SHIFT;
1101 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1104 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1109 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1111 return hr_hw_page_align(count << buf_shift);
1114 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1116 return hr_hw_page_align(count << buf_shift) >> buf_shift;
1119 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1124 return ilog2(to_hr_hem_entries_count(count, buf_shift));
1127 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
1128 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1129 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1130 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
1132 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1133 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1134 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1136 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1137 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1139 /* hns roce hw need current block and next block addr from mtt */
1140 #define MTT_MIN_COUNT 2
1141 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1142 int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1143 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1144 struct hns_roce_buf_attr *buf_attr,
1145 unsigned int page_shift, struct ib_udata *udata,
1146 unsigned long user_addr);
1147 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1148 struct hns_roce_mtr *mtr);
1149 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1150 dma_addr_t *pages, int page_cnt);
1152 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1153 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1154 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1155 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1156 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1158 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
1159 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
1160 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1161 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1162 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1163 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev);
1165 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
1166 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
1168 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
1169 u32 reserved_bot, u32 resetrved_top);
1170 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
1171 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1172 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
1173 int align, unsigned long *obj);
1174 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
1175 unsigned long obj, int cnt,
1178 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1179 struct ib_udata *udata);
1180 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1181 void hns_roce_destroy_ah(struct ib_ah *ah, u32 flags);
1183 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1184 void hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1186 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1187 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1188 u64 virt_addr, int access_flags,
1189 struct ib_udata *udata);
1190 int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length,
1191 u64 virt_addr, int mr_access_flags, struct ib_pd *pd,
1192 struct ib_udata *udata);
1193 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1195 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1196 unsigned int *sg_offset);
1197 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1198 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
1199 struct hns_roce_cmd_mailbox *mailbox,
1200 unsigned long mpt_index);
1201 unsigned long key_to_hw_index(u32 key);
1203 struct ib_mw *hns_roce_alloc_mw(struct ib_pd *pd, enum ib_mw_type,
1204 struct ib_udata *udata);
1205 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1207 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1208 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
1209 struct hns_roce_buf *buf, u32 page_shift);
1211 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1212 int buf_cnt, int start, struct hns_roce_buf *buf);
1213 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1214 int buf_cnt, int start, struct ib_umem *umem,
1215 unsigned int page_shift);
1217 int hns_roce_create_srq(struct ib_srq *srq,
1218 struct ib_srq_init_attr *srq_init_attr,
1219 struct ib_udata *udata);
1220 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1221 enum ib_srq_attr_mask srq_attr_mask,
1222 struct ib_udata *udata);
1223 void hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1225 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
1226 struct ib_qp_init_attr *init_attr,
1227 struct ib_udata *udata);
1228 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1229 int attr_mask, struct ib_udata *udata);
1230 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1231 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
1232 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n);
1233 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n);
1234 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
1235 struct ib_cq *ib_cq);
1236 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1237 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1238 struct hns_roce_cq *recv_cq);
1239 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1240 struct hns_roce_cq *recv_cq);
1241 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1242 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1243 struct ib_udata *udata);
1244 __be32 send_ieth(const struct ib_send_wr *wr);
1245 int to_hr_qp_type(int qp_type);
1247 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1248 struct ib_udata *udata);
1250 void hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1251 int hns_roce_db_map_user(struct hns_roce_ucontext *context,
1252 struct ib_udata *udata, unsigned long virt,
1253 struct hns_roce_db *db);
1254 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1255 struct hns_roce_db *db);
1256 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1258 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1260 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1261 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1262 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1263 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1264 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
1265 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1266 int hns_roce_init(struct hns_roce_dev *hr_dev);
1267 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1269 int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
1270 struct ib_cq *ib_cq);
1271 #endif /* _HNS_ROCE_DEVICE_H */