drivers/infiniband/hw/hfi1/verbs.c

   1 /*
   2  * Copyright(c) 2015, 2016 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 #include <rdma/ib_mad.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <linux/io.h>
  51 #include <linux/module.h>
  52 #include <linux/utsname.h>
  53 #include <linux/rculist.h>
  54 #include <linux/mm.h>
  55 #include <linux/vmalloc.h>
  56
  57 #include "hfi.h"
  58 #include "common.h"
  59 #include "device.h"
  60 #include "trace.h"
  61 #include "qp.h"
  62 #include "verbs_txreq.h"
  63 #include "debugfs.h"
  64
  65 static unsigned int hfi1_lkey_table_size = 16;
  66 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint,
  67                    S_IRUGO);
  68 MODULE_PARM_DESC(lkey_table_size,
  69                  "LKEY table size in bits (2^n, 1 <= n <= 23)");
  70
  71 static unsigned int hfi1_max_pds = 0xFFFF;
  72 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO);
  73 MODULE_PARM_DESC(max_pds,
  74                  "Maximum number of protection domains to support");
  75
  76 static unsigned int hfi1_max_ahs = 0xFFFF;
  77 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO);
  78 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
  79
  80 unsigned int hfi1_max_cqes = 0x2FFFFF;
  81 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO);
  82 MODULE_PARM_DESC(max_cqes,
  83                  "Maximum number of completion queue entries to support");
  84
  85 unsigned int hfi1_max_cqs = 0x1FFFF;
  86 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO);
  87 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
  88
  89 unsigned int hfi1_max_qp_wrs = 0x3FFF;
  90 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO);
  91 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
  92
  93 unsigned int hfi1_max_qps = 32768;
  94 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO);
  95 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
  96
  97 unsigned int hfi1_max_sges = 0x60;
  98 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO);
  99 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
 100
 101 unsigned int hfi1_max_mcast_grps = 16384;
 102 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO);
 103 MODULE_PARM_DESC(max_mcast_grps,
 104                  "Maximum number of multicast groups to support");
 105
 106 unsigned int hfi1_max_mcast_qp_attached = 16;
 107 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached,
 108                    uint, S_IRUGO);
 109 MODULE_PARM_DESC(max_mcast_qp_attached,
 110                  "Maximum number of attached QPs to support");
 111
 112 unsigned int hfi1_max_srqs = 1024;
 113 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO);
 114 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
 115
 116 unsigned int hfi1_max_srq_sges = 128;
 117 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO);
 118 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
 119
 120 unsigned int hfi1_max_srq_wrs = 0x1FFFF;
 121 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO);
 122 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
 123
 124 unsigned short piothreshold = 256;
 125 module_param(piothreshold, ushort, S_IRUGO);
 126 MODULE_PARM_DESC(piothreshold, "size used to determine sdma vs. pio");
 127
 128 #define COPY_CACHELESS 1
 129 #define COPY_ADAPTIVE  2
 130 static unsigned int sge_copy_mode;
 131 module_param(sge_copy_mode, uint, S_IRUGO);
 132 MODULE_PARM_DESC(sge_copy_mode,
 133                  "Verbs copy mode: 0 use memcpy, 1 use cacheless copy, 2 adapt based on WSS");
 134
 135 static void verbs_sdma_complete(
 136         struct sdma_txreq *cookie,
 137         int status);
 138
 139 static int pio_wait(struct rvt_qp *qp,
 140                     struct send_context *sc,
 141                     struct hfi1_pkt_state *ps,
 142                     u32 flag);
 143
 144 /* Length of buffer to create verbs txreq cache name */
 145 #define TXREQ_NAME_LEN 24
 146
 147 static uint wss_threshold;
 148 module_param(wss_threshold, uint, S_IRUGO);
 149 MODULE_PARM_DESC(wss_threshold, "Percentage (1-100) of LLC to use as a threshold for a cacheless copy");
 150 static uint wss_clean_period = 256;
 151 module_param(wss_clean_period, uint, S_IRUGO);
 152 MODULE_PARM_DESC(wss_clean_period, "Count of verbs copies before an entry in the page copy table is cleaned");
 153
 154 /* memory working set size */
 155 struct hfi1_wss {
 156         unsigned long *entries;
 157         atomic_t total_count;
 158         atomic_t clean_counter;
 159         atomic_t clean_entry;
 160
 161         int threshold;
 162         int num_entries;
 163         long pages_mask;
 164 };
 165
 166 static struct hfi1_wss wss;
 167
 168 int hfi1_wss_init(void)
 169 {
 170         long llc_size;
 171         long llc_bits;
 172         long table_size;
 173         long table_bits;
 174
 175         /* check for a valid percent range - default to 80 if none or invalid */
 176         if (wss_threshold < 1 || wss_threshold > 100)
 177                 wss_threshold = 80;
 178         /* reject a wildly large period */
 179         if (wss_clean_period > 1000000)
 180                 wss_clean_period = 256;
 181         /* reject a zero period */
 182         if (wss_clean_period == 0)
 183                 wss_clean_period = 1;
 184
 185         /*
 186          * Calculate the table size - the next power of 2 larger than the
 187          * LLC size.  LLC size is in KiB.
 188          */
 189         llc_size = wss_llc_size() * 1024;
 190         table_size = roundup_pow_of_two(llc_size);
 191
 192         /* one bit per page in rounded up table */
 193         llc_bits = llc_size / PAGE_SIZE;
 194         table_bits = table_size / PAGE_SIZE;
 195         wss.pages_mask = table_bits - 1;
 196         wss.num_entries = table_bits / BITS_PER_LONG;
 197
 198         wss.threshold = (llc_bits * wss_threshold) / 100;
 199         if (wss.threshold == 0)
 200                 wss.threshold = 1;
 201
 202         atomic_set(&wss.clean_counter, wss_clean_period);
 203
 204         wss.entries = kcalloc(wss.num_entries, sizeof(*wss.entries),
 205                               GFP_KERNEL);
 206         if (!wss.entries) {
 207                 hfi1_wss_exit();
 208                 return -ENOMEM;
 209         }
 210
 211         return 0;
 212 }
 213
 214 void hfi1_wss_exit(void)
 215 {
 216         /* coded to handle partially initialized and repeat callers */
 217         kfree(wss.entries);
 218         wss.entries = NULL;
 219 }
 220
 221 /*
 222  * Advance the clean counter.  When the clean period has expired,
 223  * clean an entry.
 224  *
 225  * This is implemented in atomics to avoid locking.  Because multiple
 226  * variables are involved, it can be racy which can lead to slightly
 227  * inaccurate information.  Since this is only a heuristic, this is
 228  * OK.  Any innaccuracies will clean themselves out as the counter
 229  * advances.  That said, it is unlikely the entry clean operation will
 230  * race - the next possible racer will not start until the next clean
 231  * period.
 232  *
 233  * The clean counter is implemented as a decrement to zero.  When zero
 234  * is reached an entry is cleaned.
 235  */
 236 static void wss_advance_clean_counter(void)
 237 {
 238         int entry;
 239         int weight;
 240         unsigned long bits;
 241
 242         /* become the cleaner if we decrement the counter to zero */
 243         if (atomic_dec_and_test(&wss.clean_counter)) {
 244                 /*
 245                  * Set, not add, the clean period.  This avoids an issue
 246                  * where the counter could decrement below the clean period.
 247                  * Doing a set can result in lost decrements, slowing the
 248                  * clean advance.  Since this a heuristic, this possible
 249                  * slowdown is OK.
 250                  *
 251                  * An alternative is to loop, advancing the counter by a
 252                  * clean period until the result is > 0. However, this could
 253                  * lead to several threads keeping another in the clean loop.
 254                  * This could be mitigated by limiting the number of times
 255                  * we stay in the loop.
 256                  */
 257                 atomic_set(&wss.clean_counter, wss_clean_period);
 258
 259                 /*
 260                  * Uniquely grab the entry to clean and move to next.
 261                  * The current entry is always the lower bits of
 262                  * wss.clean_entry.  The table size, wss.num_entries,
 263                  * is always a power-of-2.
 264                  */
 265                 entry = (atomic_inc_return(&wss.clean_entry) - 1)
 266                         & (wss.num_entries - 1);
 267
 268                 /* clear the entry and count the bits */
 269                 bits = xchg(&wss.entries[entry], 0);
 270                 weight = hweight64((u64)bits);
 271                 /* only adjust the contended total count if needed */
 272                 if (weight)
 273                         atomic_sub(weight, &wss.total_count);
 274         }
 275 }
 276
 277 /*
 278  * Insert the given address into the working set array.
 279  */
 280 static void wss_insert(void *address)
 281 {
 282         u32 page = ((unsigned long)address >> PAGE_SHIFT) & wss.pages_mask;
 283         u32 entry = page / BITS_PER_LONG; /* assumes this ends up a shift */
 284         u32 nr = page & (BITS_PER_LONG - 1);
 285
 286         if (!test_and_set_bit(nr, &wss.entries[entry]))
 287                 atomic_inc(&wss.total_count);
 288
 289         wss_advance_clean_counter();
 290 }
 291
 292 /*
 293  * Is the working set larger than the threshold?
 294  */
 295 static inline bool wss_exceeds_threshold(void)
 296 {
 297         return atomic_read(&wss.total_count) >= wss.threshold;
 298 }
 299
 300 /*
 301  * Translate ib_wr_opcode into ib_wc_opcode.
 302  */
 303 const enum ib_wc_opcode ib_hfi1_wc_opcode[] = {
 304         [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
 305         [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
 306         [IB_WR_SEND] = IB_WC_SEND,
 307         [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
 308         [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
 309         [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
 310         [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD,
 311         [IB_WR_SEND_WITH_INV] = IB_WC_SEND,
 312         [IB_WR_LOCAL_INV] = IB_WC_LOCAL_INV,
 313         [IB_WR_REG_MR] = IB_WC_REG_MR
 314 };
 315
 316 /*
 317  * Length of header by opcode, 0 --> not supported
 318  */
 319 const u8 hdr_len_by_opcode[256] = {
 320         /* RC */
 321         [IB_OPCODE_RC_SEND_FIRST]                     = 12 + 8,
 322         [IB_OPCODE_RC_SEND_MIDDLE]                    = 12 + 8,
 323         [IB_OPCODE_RC_SEND_LAST]                      = 12 + 8,
 324         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 325         [IB_OPCODE_RC_SEND_ONLY]                      = 12 + 8,
 326         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 327         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 328         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 329         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = 12 + 8,
 330         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 331         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 332         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 333         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = 12 + 8 + 16,
 334         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = 12 + 8 + 4,
 335         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = 12 + 8,
 336         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = 12 + 8 + 4,
 337         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = 12 + 8 + 4,
 338         [IB_OPCODE_RC_ACKNOWLEDGE]                    = 12 + 8 + 4,
 339         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = 12 + 8 + 4 + 8,
 340         [IB_OPCODE_RC_COMPARE_SWAP]                   = 12 + 8 + 28,
 341         [IB_OPCODE_RC_FETCH_ADD]                      = 12 + 8 + 28,
 342         [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE]      = 12 + 8 + 4,
 343         [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE]      = 12 + 8 + 4,
 344         /* UC */
 345         [IB_OPCODE_UC_SEND_FIRST]                     = 12 + 8,
 346         [IB_OPCODE_UC_SEND_MIDDLE]                    = 12 + 8,
 347         [IB_OPCODE_UC_SEND_LAST]                      = 12 + 8,
 348         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 349         [IB_OPCODE_UC_SEND_ONLY]                      = 12 + 8,
 350         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 351         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 352         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 353         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = 12 + 8,
 354         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 355         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 356         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 357         /* UD */
 358         [IB_OPCODE_UD_SEND_ONLY]                      = 12 + 8 + 8,
 359         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 12
 360 };
 361
 362 static const opcode_handler opcode_handler_tbl[256] = {
 363         /* RC */
 364         [IB_OPCODE_RC_SEND_FIRST]                     = &hfi1_rc_rcv,
 365         [IB_OPCODE_RC_SEND_MIDDLE]                    = &hfi1_rc_rcv,
 366         [IB_OPCODE_RC_SEND_LAST]                      = &hfi1_rc_rcv,
 367         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 368         [IB_OPCODE_RC_SEND_ONLY]                      = &hfi1_rc_rcv,
 369         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 370         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = &hfi1_rc_rcv,
 371         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = &hfi1_rc_rcv,
 372         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = &hfi1_rc_rcv,
 373         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 374         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = &hfi1_rc_rcv,
 375         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 376         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = &hfi1_rc_rcv,
 377         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = &hfi1_rc_rcv,
 378         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = &hfi1_rc_rcv,
 379         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = &hfi1_rc_rcv,
 380         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = &hfi1_rc_rcv,
 381         [IB_OPCODE_RC_ACKNOWLEDGE]                    = &hfi1_rc_rcv,
 382         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = &hfi1_rc_rcv,
 383         [IB_OPCODE_RC_COMPARE_SWAP]                   = &hfi1_rc_rcv,
 384         [IB_OPCODE_RC_FETCH_ADD]                      = &hfi1_rc_rcv,
 385         [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE]      = &hfi1_rc_rcv,
 386         [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE]      = &hfi1_rc_rcv,
 387         /* UC */
 388         [IB_OPCODE_UC_SEND_FIRST]                     = &hfi1_uc_rcv,
 389         [IB_OPCODE_UC_SEND_MIDDLE]                    = &hfi1_uc_rcv,
 390         [IB_OPCODE_UC_SEND_LAST]                      = &hfi1_uc_rcv,
 391         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 392         [IB_OPCODE_UC_SEND_ONLY]                      = &hfi1_uc_rcv,
 393         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 394         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = &hfi1_uc_rcv,
 395         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = &hfi1_uc_rcv,
 396         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = &hfi1_uc_rcv,
 397         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 398         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = &hfi1_uc_rcv,
 399         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 400         /* UD */
 401         [IB_OPCODE_UD_SEND_ONLY]                      = &hfi1_ud_rcv,
 402         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_ud_rcv,
 403         /* CNP */
 404         [IB_OPCODE_CNP]                               = &hfi1_cnp_rcv
 405 };
 406
 407 #define OPMASK 0x1f
 408
 409 static const u32 pio_opmask[BIT(3)] = {
 410         /* RC */
 411         [IB_OPCODE_RC >> 5] =
 412                 BIT(RC_OP(SEND_ONLY) & OPMASK) |
 413                 BIT(RC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
 414                 BIT(RC_OP(RDMA_WRITE_ONLY) & OPMASK) |
 415                 BIT(RC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK) |
 416                 BIT(RC_OP(RDMA_READ_REQUEST) & OPMASK) |
 417                 BIT(RC_OP(ACKNOWLEDGE) & OPMASK) |
 418                 BIT(RC_OP(ATOMIC_ACKNOWLEDGE) & OPMASK) |
 419                 BIT(RC_OP(COMPARE_SWAP) & OPMASK) |
 420                 BIT(RC_OP(FETCH_ADD) & OPMASK),
 421         /* UC */
 422         [IB_OPCODE_UC >> 5] =
 423                 BIT(UC_OP(SEND_ONLY) & OPMASK) |
 424                 BIT(UC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
 425                 BIT(UC_OP(RDMA_WRITE_ONLY) & OPMASK) |
 426                 BIT(UC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK),
 427 };
 428
 429 /*
 430  * System image GUID.
 431  */
 432 __be64 ib_hfi1_sys_image_guid;
 433
 434 /**
 435  * hfi1_copy_sge - copy data to SGE memory
 436  * @ss: the SGE state
 437  * @data: the data to copy
 438  * @length: the length of the data
 439  * @release: boolean to release MR
 440  * @copy_last: do a separate copy of the last 8 bytes
 441  */
 442 void hfi1_copy_sge(
 443         struct rvt_sge_state *ss,
 444         void *data, u32 length,
 445         bool release,
 446         bool copy_last)
 447 {
 448         struct rvt_sge *sge = &ss->sge;
 449         int i;
 450         bool in_last = false;
 451         bool cacheless_copy = false;
 452
 453         if (sge_copy_mode == COPY_CACHELESS) {
 454                 cacheless_copy = length >= PAGE_SIZE;
 455         } else if (sge_copy_mode == COPY_ADAPTIVE) {
 456                 if (length >= PAGE_SIZE) {
 457                         /*
 458                          * NOTE: this *assumes*:
 459                          * o The first vaddr is the dest.
 460                          * o If multiple pages, then vaddr is sequential.
 461                          */
 462                         wss_insert(sge->vaddr);
 463                         if (length >= (2 * PAGE_SIZE))
 464                                 wss_insert(sge->vaddr + PAGE_SIZE);
 465
 466                         cacheless_copy = wss_exceeds_threshold();
 467                 } else {
 468                         wss_advance_clean_counter();
 469                 }
 470         }
 471         if (copy_last) {
 472                 if (length > 8) {
 473                         length -= 8;
 474                 } else {
 475                         copy_last = false;
 476                         in_last = true;
 477                 }
 478         }
 479
 480 again:
 481         while (length) {
 482                 u32 len = rvt_get_sge_length(sge, length);
 483
 484                 WARN_ON_ONCE(len == 0);
 485                 if (unlikely(in_last)) {
 486                         /* enforce byte transfer ordering */
 487                         for (i = 0; i < len; i++)
 488                                 ((u8 *)sge->vaddr)[i] = ((u8 *)data)[i];
 489                 } else if (cacheless_copy) {
 490                         cacheless_memcpy(sge->vaddr, data, len);
 491                 } else {
 492                         memcpy(sge->vaddr, data, len);
 493                 }
 494                 rvt_update_sge(ss, len, release);
 495                 data += len;
 496                 length -= len;
 497         }
 498
 499         if (copy_last) {
 500                 copy_last = false;
 501                 in_last = true;
 502                 length = 8;
 503                 goto again;
 504         }
 505 }
 506
 507 /*
 508  * Make sure the QP is ready and able to accept the given opcode.
 509  */
 510 static inline opcode_handler qp_ok(int opcode, struct hfi1_packet *packet)
 511 {
 512         if (!(ib_rvt_state_ops[packet->qp->state] & RVT_PROCESS_RECV_OK))
 513                 return NULL;
 514         if (((opcode & RVT_OPCODE_QP_MASK) == packet->qp->allowed_ops) ||
 515             (opcode == IB_OPCODE_CNP))
 516                 return opcode_handler_tbl[opcode];
 517
 518         return NULL;
 519 }
 520
 521 /**
 522  * hfi1_ib_rcv - process an incoming packet
 523  * @packet: data packet information
 524  *
 525  * This is called to process an incoming packet at interrupt level.
 526  *
 527  * Tlen is the length of the header + data + CRC in bytes.
 528  */
 529 void hfi1_ib_rcv(struct hfi1_packet *packet)
 530 {
 531         struct hfi1_ctxtdata *rcd = packet->rcd;
 532         struct ib_header *hdr = packet->hdr;
 533         u32 tlen = packet->tlen;
 534         struct hfi1_pportdata *ppd = rcd->ppd;
 535         struct hfi1_ibport *ibp = rcd_to_iport(rcd);
 536         struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi;
 537         opcode_handler packet_handler;
 538         unsigned long flags;
 539         u32 qp_num;
 540         int lnh;
 541         u8 opcode;
 542         u16 lid;
 543
 544         /* Check for GRH */
 545         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
 546         if (lnh == HFI1_LRH_BTH) {
 547                 packet->ohdr = &hdr->u.oth;
 548         } else if (lnh == HFI1_LRH_GRH) {
 549                 u32 vtf;
 550
 551                 packet->ohdr = &hdr->u.l.oth;
 552                 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
 553                         goto drop;
 554                 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
 555                 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
 556                         goto drop;
 557                 packet->rcv_flags |= HFI1_HAS_GRH;
 558         } else {
 559                 goto drop;
 560         }
 561
 562         trace_input_ibhdr(rcd->dd, hdr);
 563
 564         opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24);
 565         inc_opstats(tlen, &rcd->opstats->stats[opcode]);
 566
 567         /* Get the destination QP number. */
 568         qp_num = be32_to_cpu(packet->ohdr->bth[1]) & RVT_QPN_MASK;
 569         lid = be16_to_cpu(hdr->lrh[1]);
 570         if (unlikely((lid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) &&
 571                      (lid != be16_to_cpu(IB_LID_PERMISSIVE)))) {
 572                 struct rvt_mcast *mcast;
 573                 struct rvt_mcast_qp *p;
 574
 575                 if (lnh != HFI1_LRH_GRH)
 576                         goto drop;
 577                 mcast = rvt_mcast_find(&ibp->rvp, &hdr->u.l.grh.dgid);
 578                 if (!mcast)
 579                         goto drop;
 580                 list_for_each_entry_rcu(p, &mcast->qp_list, list) {
 581                         packet->qp = p->qp;
 582                         spin_lock_irqsave(&packet->qp->r_lock, flags);
 583                         packet_handler = qp_ok(opcode, packet);
 584                         if (likely(packet_handler))
 585                                 packet_handler(packet);
 586                         else
 587                                 ibp->rvp.n_pkt_drops++;
 588                         spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 589                 }
 590                 /*
 591                  * Notify rvt_multicast_detach() if it is waiting for us
 592                  * to finish.
 593                  */
 594                 if (atomic_dec_return(&mcast->refcount) <= 1)
 595                         wake_up(&mcast->wait);
 596         } else {
 597                 rcu_read_lock();
 598                 packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
 599                 if (!packet->qp) {
 600                         rcu_read_unlock();
 601                         goto drop;
 602                 }
 603                 if (unlikely(hfi1_dbg_fault_opcode(packet->qp, opcode,
 604                                                    true))) {
 605                         rcu_read_unlock();
 606                         goto drop;
 607                 }
 608                 spin_lock_irqsave(&packet->qp->r_lock, flags);
 609                 packet_handler = qp_ok(opcode, packet);
 610                 if (likely(packet_handler))
 611                         packet_handler(packet);
 612                 else
 613                         ibp->rvp.n_pkt_drops++;
 614                 spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 615                 rcu_read_unlock();
 616         }
 617         return;
 618
 619 drop:
 620         ibp->rvp.n_pkt_drops++;
 621 }
 622
 623 /*
 624  * This is called from a timer to check for QPs
 625  * which need kernel memory in order to send a packet.
 626  */
 627 static void mem_timer(unsigned long data)
 628 {
 629         struct hfi1_ibdev *dev = (struct hfi1_ibdev *)data;
 630         struct list_head *list = &dev->memwait;
 631         struct rvt_qp *qp = NULL;
 632         struct iowait *wait;
 633         unsigned long flags;
 634         struct hfi1_qp_priv *priv;
 635
 636         write_seqlock_irqsave(&dev->iowait_lock, flags);
 637         if (!list_empty(list)) {
 638                 wait = list_first_entry(list, struct iowait, list);
 639                 qp = iowait_to_qp(wait);
 640                 priv = qp->priv;
 641                 list_del_init(&priv->s_iowait.list);
 642                 priv->s_iowait.lock = NULL;
 643                 /* refcount held until actual wake up */
 644                 if (!list_empty(list))
 645                         mod_timer(&dev->mem_timer, jiffies + 1);
 646         }
 647         write_sequnlock_irqrestore(&dev->iowait_lock, flags);
 648
 649         if (qp)
 650                 hfi1_qp_wakeup(qp, RVT_S_WAIT_KMEM);
 651 }
 652
 653 /*
 654  * This is called with progress side lock held.
 655  */
 656 /* New API */
 657 static void verbs_sdma_complete(
 658         struct sdma_txreq *cookie,
 659         int status)
 660 {
 661         struct verbs_txreq *tx =
 662                 container_of(cookie, struct verbs_txreq, txreq);
 663         struct rvt_qp *qp = tx->qp;
 664
 665         spin_lock(&qp->s_lock);
 666         if (tx->wqe) {
 667                 hfi1_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
 668         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
 669                 struct ib_header *hdr;
 670
 671                 hdr = &tx->phdr.hdr;
 672                 hfi1_rc_send_complete(qp, hdr);
 673         }
 674         spin_unlock(&qp->s_lock);
 675
 676         hfi1_put_txreq(tx);
 677 }
 678
 679 static int wait_kmem(struct hfi1_ibdev *dev,
 680                      struct rvt_qp *qp,
 681                      struct hfi1_pkt_state *ps)
 682 {
 683         struct hfi1_qp_priv *priv = qp->priv;
 684         unsigned long flags;
 685         int ret = 0;
 686
 687         spin_lock_irqsave(&qp->s_lock, flags);
 688         if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
 689                 write_seqlock(&dev->iowait_lock);
 690                 list_add_tail(&ps->s_txreq->txreq.list,
 691                               &priv->s_iowait.tx_head);
 692                 if (list_empty(&priv->s_iowait.list)) {
 693                         if (list_empty(&dev->memwait))
 694                                 mod_timer(&dev->mem_timer, jiffies + 1);
 695                         qp->s_flags |= RVT_S_WAIT_KMEM;
 696                         list_add_tail(&priv->s_iowait.list, &dev->memwait);
 697                         priv->s_iowait.lock = &dev->iowait_lock;
 698                         trace_hfi1_qpsleep(qp, RVT_S_WAIT_KMEM);
 699                         rvt_get_qp(qp);
 700                 }
 701                 write_sequnlock(&dev->iowait_lock);
 702                 qp->s_flags &= ~RVT_S_BUSY;
 703                 ret = -EBUSY;
 704         }
 705         spin_unlock_irqrestore(&qp->s_lock, flags);
 706
 707         return ret;
 708 }
 709
 710 /*
 711  * This routine calls txadds for each sg entry.
 712  *
 713  * Add failures will revert the sge cursor
 714  */
 715 static noinline int build_verbs_ulp_payload(
 716         struct sdma_engine *sde,
 717         u32 length,
 718         struct verbs_txreq *tx)
 719 {
 720         struct rvt_sge_state *ss = tx->ss;
 721         struct rvt_sge *sg_list = ss->sg_list;
 722         struct rvt_sge sge = ss->sge;
 723         u8 num_sge = ss->num_sge;
 724         u32 len;
 725         int ret = 0;
 726
 727         while (length) {
 728                 len = ss->sge.length;
 729                 if (len > length)
 730                         len = length;
 731                 if (len > ss->sge.sge_length)
 732                         len = ss->sge.sge_length;
 733                 WARN_ON_ONCE(len == 0);
 734                 ret = sdma_txadd_kvaddr(
 735                         sde->dd,
 736                         &tx->txreq,
 737                         ss->sge.vaddr,
 738                         len);
 739                 if (ret)
 740                         goto bail_txadd;
 741                 rvt_update_sge(ss, len, false);
 742                 length -= len;
 743         }
 744         return ret;
 745 bail_txadd:
 746         /* unwind cursor */
 747         ss->sge = sge;
 748         ss->num_sge = num_sge;
 749         ss->sg_list = sg_list;
 750         return ret;
 751 }
 752
 753 /*
 754  * Build the number of DMA descriptors needed to send length bytes of data.
 755  *
 756  * NOTE: DMA mapping is held in the tx until completed in the ring or
 757  *       the tx desc is freed without having been submitted to the ring
 758  *
 759  * This routine ensures all the helper routine calls succeed.
 760  */
 761 /* New API */
 762 static int build_verbs_tx_desc(
 763         struct sdma_engine *sde,
 764         u32 length,
 765         struct verbs_txreq *tx,
 766         struct hfi1_ahg_info *ahg_info,
 767         u64 pbc)
 768 {
 769         int ret = 0;
 770         struct hfi1_sdma_header *phdr = &tx->phdr;
 771         u16 hdrbytes = tx->hdr_dwords << 2;
 772
 773         if (!ahg_info->ahgcount) {
 774                 ret = sdma_txinit_ahg(
 775                         &tx->txreq,
 776                         ahg_info->tx_flags,
 777                         hdrbytes + length,
 778                         ahg_info->ahgidx,
 779                         0,
 780                         NULL,
 781                         0,
 782                         verbs_sdma_complete);
 783                 if (ret)
 784                         goto bail_txadd;
 785                 phdr->pbc = cpu_to_le64(pbc);
 786                 ret = sdma_txadd_kvaddr(
 787                         sde->dd,
 788                         &tx->txreq,
 789                         phdr,
 790                         hdrbytes);
 791                 if (ret)
 792                         goto bail_txadd;
 793         } else {
 794                 ret = sdma_txinit_ahg(
 795                         &tx->txreq,
 796                         ahg_info->tx_flags,
 797                         length,
 798                         ahg_info->ahgidx,
 799                         ahg_info->ahgcount,
 800                         ahg_info->ahgdesc,
 801                         hdrbytes,
 802                         verbs_sdma_complete);
 803                 if (ret)
 804                         goto bail_txadd;
 805         }
 806
 807         /* add the ulp payload - if any. tx->ss can be NULL for acks */
 808         if (tx->ss)
 809                 ret = build_verbs_ulp_payload(sde, length, tx);
 810 bail_txadd:
 811         return ret;
 812 }
 813
 814 int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
 815                         u64 pbc)
 816 {
 817         struct hfi1_qp_priv *priv = qp->priv;
 818         struct hfi1_ahg_info *ahg_info = priv->s_ahg;
 819         u32 hdrwords = qp->s_hdrwords;
 820         u32 len = ps->s_txreq->s_cur_size;
 821         u32 plen = hdrwords + ((len + 3) >> 2) + 2; /* includes pbc */
 822         struct hfi1_ibdev *dev = ps->dev;
 823         struct hfi1_pportdata *ppd = ps->ppd;
 824         struct verbs_txreq *tx;
 825         u64 pbc_flags = 0;
 826         u8 sc5 = priv->s_sc;
 827
 828         int ret;
 829
 830         tx = ps->s_txreq;
 831         if (!sdma_txreq_built(&tx->txreq)) {
 832                 if (likely(pbc == 0)) {
 833                         u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
 834                         /* No vl15 here */
 835                         /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
 836                         pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
 837
 838                         pbc = create_pbc(ppd,
 839                                          pbc_flags,
 840                                          qp->srate_mbps,
 841                                          vl,
 842                                          plen);
 843                 }
 844                 tx->wqe = qp->s_wqe;
 845                 ret = build_verbs_tx_desc(tx->sde, len, tx, ahg_info, pbc);
 846                 if (unlikely(ret))
 847                         goto bail_build;
 848         }
 849         ret =  sdma_send_txreq(tx->sde, &priv->s_iowait, &tx->txreq);
 850         if (unlikely(ret < 0)) {
 851                 if (ret == -ECOMM)
 852                         goto bail_ecomm;
 853                 return ret;
 854         }
 855         trace_sdma_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
 856                                 &ps->s_txreq->phdr.hdr);
 857         return ret;
 858
 859 bail_ecomm:
 860         /* The current one got "sent" */
 861         return 0;
 862 bail_build:
 863         ret = wait_kmem(dev, qp, ps);
 864         if (!ret) {
 865                 /* free txreq - bad state */
 866                 hfi1_put_txreq(ps->s_txreq);
 867                 ps->s_txreq = NULL;
 868         }
 869         return ret;
 870 }
 871
 872 /*
 873  * If we are now in the error state, return zero to flush the
 874  * send work request.
 875  */
 876 static int pio_wait(struct rvt_qp *qp,
 877                     struct send_context *sc,
 878                     struct hfi1_pkt_state *ps,
 879                     u32 flag)
 880 {
 881         struct hfi1_qp_priv *priv = qp->priv;
 882         struct hfi1_devdata *dd = sc->dd;
 883         struct hfi1_ibdev *dev = &dd->verbs_dev;
 884         unsigned long flags;
 885         int ret = 0;
 886
 887         /*
 888          * Note that as soon as want_buffer() is called and
 889          * possibly before it returns, sc_piobufavail()
 890          * could be called. Therefore, put QP on the I/O wait list before
 891          * enabling the PIO avail interrupt.
 892          */
 893         spin_lock_irqsave(&qp->s_lock, flags);
 894         if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
 895                 write_seqlock(&dev->iowait_lock);
 896                 list_add_tail(&ps->s_txreq->txreq.list,
 897                               &priv->s_iowait.tx_head);
 898                 if (list_empty(&priv->s_iowait.list)) {
 899                         struct hfi1_ibdev *dev = &dd->verbs_dev;
 900                         int was_empty;
 901
 902                         dev->n_piowait += !!(flag & RVT_S_WAIT_PIO);
 903                         dev->n_piodrain += !!(flag & RVT_S_WAIT_PIO_DRAIN);
 904                         qp->s_flags |= flag;
 905                         was_empty = list_empty(&sc->piowait);
 906                         list_add_tail(&priv->s_iowait.list, &sc->piowait);
 907                         priv->s_iowait.lock = &dev->iowait_lock;
 908                         trace_hfi1_qpsleep(qp, RVT_S_WAIT_PIO);
 909                         rvt_get_qp(qp);
 910                         /* counting: only call wantpiobuf_intr if first user */
 911                         if (was_empty)
 912                                 hfi1_sc_wantpiobuf_intr(sc, 1);
 913                 }
 914                 write_sequnlock(&dev->iowait_lock);
 915                 qp->s_flags &= ~RVT_S_BUSY;
 916                 ret = -EBUSY;
 917         }
 918         spin_unlock_irqrestore(&qp->s_lock, flags);
 919         return ret;
 920 }
 921
 922 static void verbs_pio_complete(void *arg, int code)
 923 {
 924         struct rvt_qp *qp = (struct rvt_qp *)arg;
 925         struct hfi1_qp_priv *priv = qp->priv;
 926
 927         if (iowait_pio_dec(&priv->s_iowait))
 928                 iowait_drain_wakeup(&priv->s_iowait);
 929 }
 930
 931 int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
 932                         u64 pbc)
 933 {
 934         struct hfi1_qp_priv *priv = qp->priv;
 935         u32 hdrwords = qp->s_hdrwords;
 936         struct rvt_sge_state *ss = ps->s_txreq->ss;
 937         u32 len = ps->s_txreq->s_cur_size;
 938         u32 dwords = (len + 3) >> 2;
 939         u32 plen = hdrwords + dwords + 2; /* includes pbc */
 940         struct hfi1_pportdata *ppd = ps->ppd;
 941         u32 *hdr = (u32 *)&ps->s_txreq->phdr.hdr;
 942         u64 pbc_flags = 0;
 943         u8 sc5;
 944         unsigned long flags = 0;
 945         struct send_context *sc;
 946         struct pio_buf *pbuf;
 947         int wc_status = IB_WC_SUCCESS;
 948         int ret = 0;
 949         pio_release_cb cb = NULL;
 950
 951         /* only RC/UC use complete */
 952         switch (qp->ibqp.qp_type) {
 953         case IB_QPT_RC:
 954         case IB_QPT_UC:
 955                 cb = verbs_pio_complete;
 956                 break;
 957         default:
 958                 break;
 959         }
 960
 961         /* vl15 special case taken care of in ud.c */
 962         sc5 = priv->s_sc;
 963         sc = ps->s_txreq->psc;
 964
 965         if (likely(pbc == 0)) {
 966                 u8 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
 967                 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
 968                 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
 969                 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps, vl, plen);
 970         }
 971         if (cb)
 972                 iowait_pio_inc(&priv->s_iowait);
 973         pbuf = sc_buffer_alloc(sc, plen, cb, qp);
 974         if (unlikely(!pbuf)) {
 975                 if (cb)
 976                         verbs_pio_complete(qp, 0);
 977                 if (ppd->host_link_state != HLS_UP_ACTIVE) {
 978                         /*
 979                          * If we have filled the PIO buffers to capacity and are
 980                          * not in an active state this request is not going to
 981                          * go out to so just complete it with an error or else a
 982                          * ULP or the core may be stuck waiting.
 983                          */
 984                         hfi1_cdbg(
 985                                 PIO,
 986                                 "alloc failed. state not active, completing");
 987                         wc_status = IB_WC_GENERAL_ERR;
 988                         goto pio_bail;
 989                 } else {
 990                         /*
 991                          * This is a normal occurrence. The PIO buffs are full
 992                          * up but we are still happily sending, well we could be
 993                          * so lets continue to queue the request.
 994                          */
 995                         hfi1_cdbg(PIO, "alloc failed. state active, queuing");
 996                         ret = pio_wait(qp, sc, ps, RVT_S_WAIT_PIO);
 997                         if (!ret)
 998                                 /* txreq not queued - free */
 999                                 goto bail;
1000                         /* tx consumed in wait */
1001                         return ret;
1002                 }
1003         }
1004
1005         if (len == 0) {
1006                 pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords);
1007         } else {
1008                 if (ss) {
1009                         seg_pio_copy_start(pbuf, pbc, hdr, hdrwords * 4);
1010                         while (len) {
1011                                 void *addr = ss->sge.vaddr;
1012                                 u32 slen = ss->sge.length;
1013
1014                                 if (slen > len)
1015                                         slen = len;
1016                                 rvt_update_sge(ss, slen, false);
1017                                 seg_pio_copy_mid(pbuf, addr, slen);
1018                                 len -= slen;
1019                         }
1020                         seg_pio_copy_end(pbuf);
1021                 }
1022         }
1023
1024         trace_pio_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
1025                                &ps->s_txreq->phdr.hdr);
1026
1027 pio_bail:
1028         if (qp->s_wqe) {
1029                 spin_lock_irqsave(&qp->s_lock, flags);
1030                 hfi1_send_complete(qp, qp->s_wqe, wc_status);
1031                 spin_unlock_irqrestore(&qp->s_lock, flags);
1032         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1033                 spin_lock_irqsave(&qp->s_lock, flags);
1034                 hfi1_rc_send_complete(qp, &ps->s_txreq->phdr.hdr);
1035                 spin_unlock_irqrestore(&qp->s_lock, flags);
1036         }
1037
1038         ret = 0;
1039
1040 bail:
1041         hfi1_put_txreq(ps->s_txreq);
1042         return ret;
1043 }
1044
1045 /*
1046  * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1047  * being an entry from the partition key table), return 0
1048  * otherwise. Use the matching criteria for egress partition keys
1049  * specified in the OPAv1 spec., section 9.1l.7.
1050  */
1051 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent)
1052 {
1053         u16 mkey = pkey & PKEY_LOW_15_MASK;
1054         u16 mentry = ent & PKEY_LOW_15_MASK;
1055
1056         if (mkey == mentry) {
1057                 /*
1058                  * If pkey[15] is set (full partition member),
1059                  * is bit 15 in the corresponding table element
1060                  * clear (limited member)?
1061                  */
1062                 if (pkey & PKEY_MEMBER_MASK)
1063                         return !!(ent & PKEY_MEMBER_MASK);
1064                 return 1;
1065         }
1066         return 0;
1067 }
1068
1069 /**
1070  * egress_pkey_check - check P_KEY of a packet
1071  * @ppd:    Physical IB port data
1072  * @lrh: Local route header
1073  * @bth: Base transport header
1074  * @sc5:    SC for packet
1075  * @s_pkey_index: It will be used for look up optimization for kernel contexts
1076  * only. If it is negative value, then it means user contexts is calling this
1077  * function.
1078  *
1079  * It checks if hdr's pkey is valid.
1080  *
1081  * Return: 0 on success, otherwise, 1
1082  */
1083 int egress_pkey_check(struct hfi1_pportdata *ppd, __be16 *lrh, __be32 *bth,
1084                       u8 sc5, int8_t s_pkey_index)
1085 {
1086         struct hfi1_devdata *dd;
1087         int i;
1088         u16 pkey;
1089         int is_user_ctxt_mechanism = (s_pkey_index < 0);
1090
1091         if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT))
1092                 return 0;
1093
1094         pkey = (u16)be32_to_cpu(bth[0]);
1095
1096         /* If SC15, pkey[0:14] must be 0x7fff */
1097         if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1098                 goto bad;
1099
1100         /* Is the pkey = 0x0, or 0x8000? */
1101         if ((pkey & PKEY_LOW_15_MASK) == 0)
1102                 goto bad;
1103
1104         /*
1105          * For the kernel contexts only, if a qp is passed into the function,
1106          * the most likely matching pkey has index qp->s_pkey_index
1107          */
1108         if (!is_user_ctxt_mechanism &&
1109             egress_pkey_matches_entry(pkey, ppd->pkeys[s_pkey_index])) {
1110                 return 0;
1111         }
1112
1113         for (i = 0; i < MAX_PKEY_VALUES; i++) {
1114                 if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1115                         return 0;
1116         }
1117 bad:
1118         /*
1119          * For the user-context mechanism, the P_KEY check would only happen
1120          * once per SDMA request, not once per packet.  Therefore, there's no
1121          * need to increment the counter for the user-context mechanism.
1122          */
1123         if (!is_user_ctxt_mechanism) {
1124                 incr_cntr64(&ppd->port_xmit_constraint_errors);
1125                 dd = ppd->dd;
1126                 if (!(dd->err_info_xmit_constraint.status &
1127                       OPA_EI_STATUS_SMASK)) {
1128                         u16 slid = be16_to_cpu(lrh[3]);
1129
1130                         dd->err_info_xmit_constraint.status |=
1131                                 OPA_EI_STATUS_SMASK;
1132                         dd->err_info_xmit_constraint.slid = slid;
1133                         dd->err_info_xmit_constraint.pkey = pkey;
1134                 }
1135         }
1136         return 1;
1137 }
1138
1139 /**
1140  * get_send_routine - choose an egress routine
1141  *
1142  * Choose an egress routine based on QP type
1143  * and size
1144  */
1145 static inline send_routine get_send_routine(struct rvt_qp *qp,
1146                                             struct verbs_txreq *tx)
1147 {
1148         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1149         struct hfi1_qp_priv *priv = qp->priv;
1150         struct ib_header *h = &tx->phdr.hdr;
1151
1152         if (unlikely(!(dd->flags & HFI1_HAS_SEND_DMA)))
1153                 return dd->process_pio_send;
1154         switch (qp->ibqp.qp_type) {
1155         case IB_QPT_SMI:
1156                 return dd->process_pio_send;
1157         case IB_QPT_GSI:
1158         case IB_QPT_UD:
1159                 break;
1160         case IB_QPT_UC:
1161         case IB_QPT_RC: {
1162                 u8 op = get_opcode(h);
1163
1164                 if (piothreshold &&
1165                     tx->s_cur_size <= min(piothreshold, qp->pmtu) &&
1166                     (BIT(op & OPMASK) & pio_opmask[op >> 5]) &&
1167                     iowait_sdma_pending(&priv->s_iowait) == 0 &&
1168                     !sdma_txreq_built(&tx->txreq))
1169                         return dd->process_pio_send;
1170                 break;
1171         }
1172         default:
1173                 break;
1174         }
1175         return dd->process_dma_send;
1176 }
1177
1178 /**
1179  * hfi1_verbs_send - send a packet
1180  * @qp: the QP to send on
1181  * @ps: the state of the packet to send
1182  *
1183  * Return zero if packet is sent or queued OK.
1184  * Return non-zero and clear qp->s_flags RVT_S_BUSY otherwise.
1185  */
1186 int hfi1_verbs_send(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
1187 {
1188         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1189         struct hfi1_qp_priv *priv = qp->priv;
1190         struct ib_other_headers *ohdr;
1191         struct ib_header *hdr;
1192         send_routine sr;
1193         int ret;
1194         u8 lnh;
1195
1196         hdr = &ps->s_txreq->phdr.hdr;
1197         /* locate the pkey within the headers */
1198         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
1199         if (lnh == HFI1_LRH_GRH)
1200                 ohdr = &hdr->u.l.oth;
1201         else
1202                 ohdr = &hdr->u.oth;
1203
1204         sr = get_send_routine(qp, ps->s_txreq);
1205         ret = egress_pkey_check(dd->pport,
1206                                 hdr->lrh,
1207                                 ohdr->bth,
1208                                 priv->s_sc,
1209                                 qp->s_pkey_index);
1210         if (unlikely(ret)) {
1211                 /*
1212                  * The value we are returning here does not get propagated to
1213                  * the verbs caller. Thus we need to complete the request with
1214                  * error otherwise the caller could be sitting waiting on the
1215                  * completion event. Only do this for PIO. SDMA has its own
1216                  * mechanism for handling the errors. So for SDMA we can just
1217                  * return.
1218                  */
1219                 if (sr == dd->process_pio_send) {
1220                         unsigned long flags;
1221
1222                         hfi1_cdbg(PIO, "%s() Failed. Completing with err",
1223                                   __func__);
1224                         spin_lock_irqsave(&qp->s_lock, flags);
1225                         hfi1_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
1226                         spin_unlock_irqrestore(&qp->s_lock, flags);
1227                 }
1228                 return -EINVAL;
1229         }
1230         if (sr == dd->process_dma_send && iowait_pio_pending(&priv->s_iowait))
1231                 return pio_wait(qp,
1232                                 ps->s_txreq->psc,
1233                                 ps,
1234                                 RVT_S_WAIT_PIO_DRAIN);
1235         return sr(qp, ps, 0);
1236 }
1237
1238 /**
1239  * hfi1_fill_device_attr - Fill in rvt dev info device attributes.
1240  * @dd: the device data structure
1241  */
1242 static void hfi1_fill_device_attr(struct hfi1_devdata *dd)
1243 {
1244         struct rvt_dev_info *rdi = &dd->verbs_dev.rdi;
1245         u32 ver = dd->dc8051_ver;
1246
1247         memset(&rdi->dparms.props, 0, sizeof(rdi->dparms.props));
1248
1249         rdi->dparms.props.fw_ver = ((u64)(dc8051_ver_maj(ver)) << 32) |
1250                 ((u64)(dc8051_ver_min(ver)) << 16) |
1251                 (u64)dc8051_ver_patch(ver);
1252
1253         rdi->dparms.props.device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1254                         IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1255                         IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1256                         IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE |
1257                         IB_DEVICE_MEM_MGT_EXTENSIONS;
1258         rdi->dparms.props.page_size_cap = PAGE_SIZE;
1259         rdi->dparms.props.vendor_id = dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3;
1260         rdi->dparms.props.vendor_part_id = dd->pcidev->device;
1261         rdi->dparms.props.hw_ver = dd->minrev;
1262         rdi->dparms.props.sys_image_guid = ib_hfi1_sys_image_guid;
1263         rdi->dparms.props.max_mr_size = U64_MAX;
1264         rdi->dparms.props.max_fast_reg_page_list_len = UINT_MAX;
1265         rdi->dparms.props.max_qp = hfi1_max_qps;
1266         rdi->dparms.props.max_qp_wr = hfi1_max_qp_wrs;
1267         rdi->dparms.props.max_sge = hfi1_max_sges;
1268         rdi->dparms.props.max_sge_rd = hfi1_max_sges;
1269         rdi->dparms.props.max_cq = hfi1_max_cqs;
1270         rdi->dparms.props.max_ah = hfi1_max_ahs;
1271         rdi->dparms.props.max_cqe = hfi1_max_cqes;
1272         rdi->dparms.props.max_mr = rdi->lkey_table.max;
1273         rdi->dparms.props.max_fmr = rdi->lkey_table.max;
1274         rdi->dparms.props.max_map_per_fmr = 32767;
1275         rdi->dparms.props.max_pd = hfi1_max_pds;
1276         rdi->dparms.props.max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC;
1277         rdi->dparms.props.max_qp_init_rd_atom = 255;
1278         rdi->dparms.props.max_srq = hfi1_max_srqs;
1279         rdi->dparms.props.max_srq_wr = hfi1_max_srq_wrs;
1280         rdi->dparms.props.max_srq_sge = hfi1_max_srq_sges;
1281         rdi->dparms.props.atomic_cap = IB_ATOMIC_GLOB;
1282         rdi->dparms.props.max_pkeys = hfi1_get_npkeys(dd);
1283         rdi->dparms.props.max_mcast_grp = hfi1_max_mcast_grps;
1284         rdi->dparms.props.max_mcast_qp_attach = hfi1_max_mcast_qp_attached;
1285         rdi->dparms.props.max_total_mcast_qp_attach =
1286                                         rdi->dparms.props.max_mcast_qp_attach *
1287                                         rdi->dparms.props.max_mcast_grp;
1288 }
1289
1290 static inline u16 opa_speed_to_ib(u16 in)
1291 {
1292         u16 out = 0;
1293
1294         if (in & OPA_LINK_SPEED_25G)
1295                 out |= IB_SPEED_EDR;
1296         if (in & OPA_LINK_SPEED_12_5G)
1297                 out |= IB_SPEED_FDR;
1298
1299         return out;
1300 }
1301
1302 /*
1303  * Convert a single OPA link width (no multiple flags) to an IB value.
1304  * A zero OPA link width means link down, which means the IB width value
1305  * is a don't care.
1306  */
1307 static inline u16 opa_width_to_ib(u16 in)
1308 {
1309         switch (in) {
1310         case OPA_LINK_WIDTH_1X:
1311         /* map 2x and 3x to 1x as they don't exist in IB */
1312         case OPA_LINK_WIDTH_2X:
1313         case OPA_LINK_WIDTH_3X:
1314                 return IB_WIDTH_1X;
1315         default: /* link down or unknown, return our largest width */
1316         case OPA_LINK_WIDTH_4X:
1317                 return IB_WIDTH_4X;
1318         }
1319 }
1320
1321 static int query_port(struct rvt_dev_info *rdi, u8 port_num,
1322                       struct ib_port_attr *props)
1323 {
1324         struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1325         struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1326         struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1327         u16 lid = ppd->lid;
1328
1329         /* props being zeroed by the caller, avoid zeroing it here */
1330         props->lid = lid ? lid : 0;
1331         props->lmc = ppd->lmc;
1332         /* OPA logical states match IB logical states */
1333         props->state = driver_lstate(ppd);
1334         props->phys_state = hfi1_ibphys_portstate(ppd);
1335         props->gid_tbl_len = HFI1_GUIDS_PER_PORT;
1336         props->active_width = (u8)opa_width_to_ib(ppd->link_width_active);
1337         /* see rate_show() in ib core/sysfs.c */
1338         props->active_speed = (u8)opa_speed_to_ib(ppd->link_speed_active);
1339         props->max_vl_num = ppd->vls_supported;
1340
1341         /* Once we are a "first class" citizen and have added the OPA MTUs to
1342          * the core we can advertise the larger MTU enum to the ULPs, for now
1343          * advertise only 4K.
1344          *
1345          * Those applications which are either OPA aware or pass the MTU enum
1346          * from the Path Records to us will get the new 8k MTU.  Those that
1347          * attempt to process the MTU enum may fail in various ways.
1348          */
1349         props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ?
1350                                       4096 : hfi1_max_mtu), IB_MTU_4096);
1351         props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
1352                 mtu_to_enum(ppd->ibmtu, IB_MTU_2048);
1353
1354         return 0;
1355 }
1356
1357 static int modify_device(struct ib_device *device,
1358                          int device_modify_mask,
1359                          struct ib_device_modify *device_modify)
1360 {
1361         struct hfi1_devdata *dd = dd_from_ibdev(device);
1362         unsigned i;
1363         int ret;
1364
1365         if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1366                                    IB_DEVICE_MODIFY_NODE_DESC)) {
1367                 ret = -EOPNOTSUPP;
1368                 goto bail;
1369         }
1370
1371         if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1372                 memcpy(device->node_desc, device_modify->node_desc,
1373                        IB_DEVICE_NODE_DESC_MAX);
1374                 for (i = 0; i < dd->num_pports; i++) {
1375                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1376
1377                         hfi1_node_desc_chg(ibp);
1378                 }
1379         }
1380
1381         if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1382                 ib_hfi1_sys_image_guid =
1383                         cpu_to_be64(device_modify->sys_image_guid);
1384                 for (i = 0; i < dd->num_pports; i++) {
1385                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1386
1387                         hfi1_sys_guid_chg(ibp);
1388                 }
1389         }
1390
1391         ret = 0;
1392
1393 bail:
1394         return ret;
1395 }
1396
1397 static int shut_down_port(struct rvt_dev_info *rdi, u8 port_num)
1398 {
1399         struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1400         struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1401         struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1402         int ret;
1403
1404         set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0,
1405                              OPA_LINKDOWN_REASON_UNKNOWN);
1406         ret = set_link_state(ppd, HLS_DN_DOWNDEF);
1407         return ret;
1408 }
1409
1410 static int hfi1_get_guid_be(struct rvt_dev_info *rdi, struct rvt_ibport *rvp,
1411                             int guid_index, __be64 *guid)
1412 {
1413         struct hfi1_ibport *ibp = container_of(rvp, struct hfi1_ibport, rvp);
1414
1415         if (guid_index >= HFI1_GUIDS_PER_PORT)
1416                 return -EINVAL;
1417
1418         *guid = get_sguid(ibp, guid_index);
1419         return 0;
1420 }
1421
1422 /*
1423  * convert ah port,sl to sc
1424  */
1425 u8 ah_to_sc(struct ib_device *ibdev, struct ib_ah_attr *ah)
1426 {
1427         struct hfi1_ibport *ibp = to_iport(ibdev, ah->port_num);
1428
1429         return ibp->sl_to_sc[ah->sl];
1430 }
1431
1432 static int hfi1_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1433 {
1434         struct hfi1_ibport *ibp;
1435         struct hfi1_pportdata *ppd;
1436         struct hfi1_devdata *dd;
1437         u8 sc5;
1438
1439         /* test the mapping for validity */
1440         ibp = to_iport(ibdev, ah_attr->port_num);
1441         ppd = ppd_from_ibp(ibp);
1442         sc5 = ibp->sl_to_sc[ah_attr->sl];
1443         dd = dd_from_ppd(ppd);
1444         if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf)
1445                 return -EINVAL;
1446         return 0;
1447 }
1448
1449 static void hfi1_notify_new_ah(struct ib_device *ibdev,
1450                                struct ib_ah_attr *ah_attr,
1451                                struct rvt_ah *ah)
1452 {
1453         struct hfi1_ibport *ibp;
1454         struct hfi1_pportdata *ppd;
1455         struct hfi1_devdata *dd;
1456         u8 sc5;
1457
1458         /*
1459          * Do not trust reading anything from rvt_ah at this point as it is not
1460          * done being setup. We can however modify things which we need to set.
1461          */
1462
1463         ibp = to_iport(ibdev, ah_attr->port_num);
1464         ppd = ppd_from_ibp(ibp);
1465         sc5 = ibp->sl_to_sc[ah->attr.sl];
1466         dd = dd_from_ppd(ppd);
1467         ah->vl = sc_to_vlt(dd, sc5);
1468         if (ah->vl < num_vls || ah->vl == 15)
1469                 ah->log_pmtu = ilog2(dd->vld[ah->vl].mtu);
1470 }
1471
1472 struct ib_ah *hfi1_create_qp0_ah(struct hfi1_ibport *ibp, u16 dlid)
1473 {
1474         struct ib_ah_attr attr;
1475         struct ib_ah *ah = ERR_PTR(-EINVAL);
1476         struct rvt_qp *qp0;
1477
1478         memset(&attr, 0, sizeof(attr));
1479         attr.dlid = dlid;
1480         attr.port_num = ppd_from_ibp(ibp)->port;
1481         rcu_read_lock();
1482         qp0 = rcu_dereference(ibp->rvp.qp[0]);
1483         if (qp0)
1484                 ah = ib_create_ah(qp0->ibqp.pd, &attr);
1485         rcu_read_unlock();
1486         return ah;
1487 }
1488
1489 /**
1490  * hfi1_get_npkeys - return the size of the PKEY table for context 0
1491  * @dd: the hfi1_ib device
1492  */
1493 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd)
1494 {
1495         return ARRAY_SIZE(dd->pport[0].pkeys);
1496 }
1497
1498 static void init_ibport(struct hfi1_pportdata *ppd)
1499 {
1500         struct hfi1_ibport *ibp = &ppd->ibport_data;
1501         size_t sz = ARRAY_SIZE(ibp->sl_to_sc);
1502         int i;
1503
1504         for (i = 0; i < sz; i++) {
1505                 ibp->sl_to_sc[i] = i;
1506                 ibp->sc_to_sl[i] = i;
1507         }
1508
1509         spin_lock_init(&ibp->rvp.lock);
1510         /* Set the prefix to the default value (see ch. 4.1.1) */
1511         ibp->rvp.gid_prefix = IB_DEFAULT_GID_PREFIX;
1512         ibp->rvp.sm_lid = 0;
1513         /* Below should only set bits defined in OPA PortInfo.CapabilityMask */
1514         ibp->rvp.port_cap_flags = IB_PORT_AUTO_MIGR_SUP |
1515                 IB_PORT_CAP_MASK_NOTICE_SUP;
1516         ibp->rvp.pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1517         ibp->rvp.pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1518         ibp->rvp.pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1519         ibp->rvp.pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1520         ibp->rvp.pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1521
1522         RCU_INIT_POINTER(ibp->rvp.qp[0], NULL);
1523         RCU_INIT_POINTER(ibp->rvp.qp[1], NULL);
1524 }
1525
1526 static void hfi1_get_dev_fw_str(struct ib_device *ibdev, char *str,
1527                                 size_t str_len)
1528 {
1529         struct rvt_dev_info *rdi = ib_to_rvt(ibdev);
1530         struct hfi1_ibdev *dev = dev_from_rdi(rdi);
1531         u32 ver = dd_from_dev(dev)->dc8051_ver;
1532
1533         snprintf(str, str_len, "%u.%u.%u", dc8051_ver_maj(ver),
1534                  dc8051_ver_min(ver), dc8051_ver_patch(ver));
1535 }
1536
1537 static const char * const driver_cntr_names[] = {
1538         /* must be element 0*/
1539         "DRIVER_KernIntr",
1540         "DRIVER_ErrorIntr",
1541         "DRIVER_Tx_Errs",
1542         "DRIVER_Rcv_Errs",
1543         "DRIVER_HW_Errs",
1544         "DRIVER_NoPIOBufs",
1545         "DRIVER_CtxtsOpen",
1546         "DRIVER_RcvLen_Errs",
1547         "DRIVER_EgrBufFull",
1548         "DRIVER_EgrHdrFull"
1549 };
1550
1551 static DEFINE_MUTEX(cntr_names_lock); /* protects the *_cntr_names bufers */
1552 static const char **dev_cntr_names;
1553 static const char **port_cntr_names;
1554 static int num_driver_cntrs = ARRAY_SIZE(driver_cntr_names);
1555 static int num_dev_cntrs;
1556 static int num_port_cntrs;
1557 static int cntr_names_initialized;
1558
1559 /*
1560  * Convert a list of names separated by '\n' into an array of NULL terminated
1561  * strings. Optionally some entries can be reserved in the array to hold extra
1562  * external strings.
1563  */
1564 static int init_cntr_names(const char *names_in,
1565                            const size_t names_len,
1566                            int num_extra_names,
1567                            int *num_cntrs,
1568                            const char ***cntr_names)
1569 {
1570         char *names_out, *p, **q;
1571         int i, n;
1572
1573         n = 0;
1574         for (i = 0; i < names_len; i++)
1575                 if (names_in[i] == '\n')
1576                         n++;
1577
1578         names_out = kmalloc((n + num_extra_names) * sizeof(char *) + names_len,
1579                             GFP_KERNEL);
1580         if (!names_out) {
1581                 *num_cntrs = 0;
1582                 *cntr_names = NULL;
1583                 return -ENOMEM;
1584         }
1585
1586         p = names_out + (n + num_extra_names) * sizeof(char *);
1587         memcpy(p, names_in, names_len);
1588
1589         q = (char **)names_out;
1590         for (i = 0; i < n; i++) {
1591                 q[i] = p;
1592                 p = strchr(p, '\n');
1593                 *p++ = '\0';
1594         }
1595
1596         *num_cntrs = n;
1597         *cntr_names = (const char **)names_out;
1598         return 0;
1599 }
1600
1601 static struct rdma_hw_stats *alloc_hw_stats(struct ib_device *ibdev,
1602                                             u8 port_num)
1603 {
1604         int i, err;
1605
1606         mutex_lock(&cntr_names_lock);
1607         if (!cntr_names_initialized) {
1608                 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1609
1610                 err = init_cntr_names(dd->cntrnames,
1611                                       dd->cntrnameslen,
1612                                       num_driver_cntrs,
1613                                       &num_dev_cntrs,
1614                                       &dev_cntr_names);
1615                 if (err) {
1616                         mutex_unlock(&cntr_names_lock);
1617                         return NULL;
1618                 }
1619
1620                 for (i = 0; i < num_driver_cntrs; i++)
1621                         dev_cntr_names[num_dev_cntrs + i] =
1622                                 driver_cntr_names[i];
1623
1624                 err = init_cntr_names(dd->portcntrnames,
1625                                       dd->portcntrnameslen,
1626                                       0,
1627                                       &num_port_cntrs,
1628                                       &port_cntr_names);
1629                 if (err) {
1630                         kfree(dev_cntr_names);
1631                         dev_cntr_names = NULL;
1632                         mutex_unlock(&cntr_names_lock);
1633                         return NULL;
1634                 }
1635                 cntr_names_initialized = 1;
1636         }
1637         mutex_unlock(&cntr_names_lock);
1638
1639         if (!port_num)
1640                 return rdma_alloc_hw_stats_struct(
1641                                 dev_cntr_names,
1642                                 num_dev_cntrs + num_driver_cntrs,
1643                                 RDMA_HW_STATS_DEFAULT_LIFESPAN);
1644         else
1645                 return rdma_alloc_hw_stats_struct(
1646                                 port_cntr_names,
1647                                 num_port_cntrs,
1648                                 RDMA_HW_STATS_DEFAULT_LIFESPAN);
1649 }
1650
1651 static u64 hfi1_sps_ints(void)
1652 {
1653         unsigned long flags;
1654         struct hfi1_devdata *dd;
1655         u64 sps_ints = 0;
1656
1657         spin_lock_irqsave(&hfi1_devs_lock, flags);
1658         list_for_each_entry(dd, &hfi1_dev_list, list) {
1659                 sps_ints += get_all_cpu_total(dd->int_counter);
1660         }
1661         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
1662         return sps_ints;
1663 }
1664
1665 static int get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats,
1666                         u8 port, int index)
1667 {
1668         u64 *values;
1669         int count;
1670
1671         if (!port) {
1672                 u64 *stats = (u64 *)&hfi1_stats;
1673                 int i;
1674
1675                 hfi1_read_cntrs(dd_from_ibdev(ibdev), NULL, &values);
1676                 values[num_dev_cntrs] = hfi1_sps_ints();
1677                 for (i = 1; i < num_driver_cntrs; i++)
1678                         values[num_dev_cntrs + i] = stats[i];
1679                 count = num_dev_cntrs + num_driver_cntrs;
1680         } else {
1681                 struct hfi1_ibport *ibp = to_iport(ibdev, port);
1682
1683                 hfi1_read_portcntrs(ppd_from_ibp(ibp), NULL, &values);
1684                 count = num_port_cntrs;
1685         }
1686
1687         memcpy(stats->value, values, count * sizeof(u64));
1688         return count;
1689 }
1690
1691 /**
1692  * hfi1_register_ib_device - register our device with the infiniband core
1693  * @dd: the device data structure
1694  * Return 0 if successful, errno if unsuccessful.
1695  */
1696 int hfi1_register_ib_device(struct hfi1_devdata *dd)
1697 {
1698         struct hfi1_ibdev *dev = &dd->verbs_dev;
1699         struct ib_device *ibdev = &dev->rdi.ibdev;
1700         struct hfi1_pportdata *ppd = dd->pport;
1701         struct hfi1_ibport *ibp = &ppd->ibport_data;
1702         unsigned i;
1703         int ret;
1704         size_t lcpysz = IB_DEVICE_NAME_MAX;
1705
1706         for (i = 0; i < dd->num_pports; i++)
1707                 init_ibport(ppd + i);
1708
1709         /* Only need to initialize non-zero fields. */
1710
1711         setup_timer(&dev->mem_timer, mem_timer, (unsigned long)dev);
1712
1713         seqlock_init(&dev->iowait_lock);
1714         seqlock_init(&dev->txwait_lock);
1715         INIT_LIST_HEAD(&dev->txwait);
1716         INIT_LIST_HEAD(&dev->memwait);
1717
1718         ret = verbs_txreq_init(dev);
1719         if (ret)
1720                 goto err_verbs_txreq;
1721
1722         /* Use first-port GUID as node guid */
1723         ibdev->node_guid = get_sguid(ibp, HFI1_PORT_GUID_INDEX);
1724
1725         /*
1726          * The system image GUID is supposed to be the same for all
1727          * HFIs in a single system but since there can be other
1728          * device types in the system, we can't be sure this is unique.
1729          */
1730         if (!ib_hfi1_sys_image_guid)
1731                 ib_hfi1_sys_image_guid = ibdev->node_guid;
1732         lcpysz = strlcpy(ibdev->name, class_name(), lcpysz);
1733         strlcpy(ibdev->name + lcpysz, "_%d", IB_DEVICE_NAME_MAX - lcpysz);
1734         ibdev->owner = THIS_MODULE;
1735         ibdev->phys_port_cnt = dd->num_pports;
1736         ibdev->dev.parent = &dd->pcidev->dev;
1737         ibdev->modify_device = modify_device;
1738         ibdev->alloc_hw_stats = alloc_hw_stats;
1739         ibdev->get_hw_stats = get_hw_stats;
1740
1741         /* keep process mad in the driver */
1742         ibdev->process_mad = hfi1_process_mad;
1743         ibdev->get_dev_fw_str = hfi1_get_dev_fw_str;
1744
1745         strncpy(ibdev->node_desc, init_utsname()->nodename,
1746                 sizeof(ibdev->node_desc));
1747
1748         /*
1749          * Fill in rvt info object.
1750          */
1751         dd->verbs_dev.rdi.driver_f.port_callback = hfi1_create_port_files;
1752         dd->verbs_dev.rdi.driver_f.get_card_name = get_card_name;
1753         dd->verbs_dev.rdi.driver_f.get_pci_dev = get_pci_dev;
1754         dd->verbs_dev.rdi.driver_f.check_ah = hfi1_check_ah;
1755         dd->verbs_dev.rdi.driver_f.notify_new_ah = hfi1_notify_new_ah;
1756         dd->verbs_dev.rdi.driver_f.get_guid_be = hfi1_get_guid_be;
1757         dd->verbs_dev.rdi.driver_f.query_port_state = query_port;
1758         dd->verbs_dev.rdi.driver_f.shut_down_port = shut_down_port;
1759         dd->verbs_dev.rdi.driver_f.cap_mask_chg = hfi1_cap_mask_chg;
1760         /*
1761          * Fill in rvt info device attributes.
1762          */
1763         hfi1_fill_device_attr(dd);
1764
1765         /* queue pair */
1766         dd->verbs_dev.rdi.dparms.qp_table_size = hfi1_qp_table_size;
1767         dd->verbs_dev.rdi.dparms.qpn_start = 0;
1768         dd->verbs_dev.rdi.dparms.qpn_inc = 1;
1769         dd->verbs_dev.rdi.dparms.qos_shift = dd->qos_shift;
1770         dd->verbs_dev.rdi.dparms.qpn_res_start = kdeth_qp << 16;
1771         dd->verbs_dev.rdi.dparms.qpn_res_end =
1772         dd->verbs_dev.rdi.dparms.qpn_res_start + 65535;
1773         dd->verbs_dev.rdi.dparms.max_rdma_atomic = HFI1_MAX_RDMA_ATOMIC;
1774         dd->verbs_dev.rdi.dparms.psn_mask = PSN_MASK;
1775         dd->verbs_dev.rdi.dparms.psn_shift = PSN_SHIFT;
1776         dd->verbs_dev.rdi.dparms.psn_modify_mask = PSN_MODIFY_MASK;
1777         dd->verbs_dev.rdi.dparms.core_cap_flags = RDMA_CORE_PORT_INTEL_OPA;
1778         dd->verbs_dev.rdi.dparms.max_mad_size = OPA_MGMT_MAD_SIZE;
1779
1780         dd->verbs_dev.rdi.driver_f.qp_priv_alloc = qp_priv_alloc;
1781         dd->verbs_dev.rdi.driver_f.qp_priv_free = qp_priv_free;
1782         dd->verbs_dev.rdi.driver_f.free_all_qps = free_all_qps;
1783         dd->verbs_dev.rdi.driver_f.notify_qp_reset = notify_qp_reset;
1784         dd->verbs_dev.rdi.driver_f.do_send = hfi1_do_send;
1785         dd->verbs_dev.rdi.driver_f.schedule_send = hfi1_schedule_send;
1786         dd->verbs_dev.rdi.driver_f.schedule_send_no_lock = _hfi1_schedule_send;
1787         dd->verbs_dev.rdi.driver_f.get_pmtu_from_attr = get_pmtu_from_attr;
1788         dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1789         dd->verbs_dev.rdi.driver_f.flush_qp_waiters = flush_qp_waiters;
1790         dd->verbs_dev.rdi.driver_f.stop_send_queue = stop_send_queue;
1791         dd->verbs_dev.rdi.driver_f.quiesce_qp = quiesce_qp;
1792         dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1793         dd->verbs_dev.rdi.driver_f.mtu_from_qp = mtu_from_qp;
1794         dd->verbs_dev.rdi.driver_f.mtu_to_path_mtu = mtu_to_path_mtu;
1795         dd->verbs_dev.rdi.driver_f.check_modify_qp = hfi1_check_modify_qp;
1796         dd->verbs_dev.rdi.driver_f.modify_qp = hfi1_modify_qp;
1797         dd->verbs_dev.rdi.driver_f.notify_restart_rc = hfi1_restart_rc;
1798         dd->verbs_dev.rdi.driver_f.check_send_wqe = hfi1_check_send_wqe;
1799
1800         /* completeion queue */
1801         snprintf(dd->verbs_dev.rdi.dparms.cq_name,
1802                  sizeof(dd->verbs_dev.rdi.dparms.cq_name),
1803                  "hfi1_cq%d", dd->unit);
1804         dd->verbs_dev.rdi.dparms.node = dd->node;
1805
1806         /* misc settings */
1807         dd->verbs_dev.rdi.flags = 0; /* Let rdmavt handle it all */
1808         dd->verbs_dev.rdi.dparms.lkey_table_size = hfi1_lkey_table_size;
1809         dd->verbs_dev.rdi.dparms.nports = dd->num_pports;
1810         dd->verbs_dev.rdi.dparms.npkeys = hfi1_get_npkeys(dd);
1811
1812         /* post send table */
1813         dd->verbs_dev.rdi.post_parms = hfi1_post_parms;
1814
1815         ppd = dd->pport;
1816         for (i = 0; i < dd->num_pports; i++, ppd++)
1817                 rvt_init_port(&dd->verbs_dev.rdi,
1818                               &ppd->ibport_data.rvp,
1819                               i,
1820                               ppd->pkeys);
1821
1822         ret = rvt_register_device(&dd->verbs_dev.rdi);
1823         if (ret)
1824                 goto err_verbs_txreq;
1825
1826         ret = hfi1_verbs_register_sysfs(dd);
1827         if (ret)
1828                 goto err_class;
1829
1830         return ret;
1831
1832 err_class:
1833         rvt_unregister_device(&dd->verbs_dev.rdi);
1834 err_verbs_txreq:
1835         verbs_txreq_exit(dev);
1836         dd_dev_err(dd, "cannot register verbs: %d!\n", -ret);
1837         return ret;
1838 }
1839
1840 void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
1841 {
1842         struct hfi1_ibdev *dev = &dd->verbs_dev;
1843
1844         hfi1_verbs_unregister_sysfs(dd);
1845
1846         rvt_unregister_device(&dd->verbs_dev.rdi);
1847
1848         if (!list_empty(&dev->txwait))
1849                 dd_dev_err(dd, "txwait list not empty!\n");
1850         if (!list_empty(&dev->memwait))
1851                 dd_dev_err(dd, "memwait list not empty!\n");
1852
1853         del_timer_sync(&dev->mem_timer);
1854         verbs_txreq_exit(dev);
1855
1856         mutex_lock(&cntr_names_lock);
1857         kfree(dev_cntr_names);
1858         kfree(port_cntr_names);
1859         dev_cntr_names = NULL;
1860         port_cntr_names = NULL;
1861         cntr_names_initialized = 0;
1862         mutex_unlock(&cntr_names_lock);
1863 }
1864
1865 void hfi1_cnp_rcv(struct hfi1_packet *packet)
1866 {
1867         struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd);
1868         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1869         struct ib_header *hdr = packet->hdr;
1870         struct rvt_qp *qp = packet->qp;
1871         u32 lqpn, rqpn = 0;
1872         u16 rlid = 0;
1873         u8 sl, sc5, svc_type;
1874
1875         switch (packet->qp->ibqp.qp_type) {
1876         case IB_QPT_UC:
1877                 rlid = qp->remote_ah_attr.dlid;
1878                 rqpn = qp->remote_qpn;
1879                 svc_type = IB_CC_SVCTYPE_UC;
1880                 break;
1881         case IB_QPT_RC:
1882                 rlid = qp->remote_ah_attr.dlid;
1883                 rqpn = qp->remote_qpn;
1884                 svc_type = IB_CC_SVCTYPE_RC;
1885                 break;
1886         case IB_QPT_SMI:
1887         case IB_QPT_GSI:
1888         case IB_QPT_UD:
1889                 svc_type = IB_CC_SVCTYPE_UD;
1890                 break;
1891         default:
1892                 ibp->rvp.n_pkt_drops++;
1893                 return;
1894         }
1895
1896         sc5 = hdr2sc(hdr, packet->rhf);
1897         sl = ibp->sc_to_sl[sc5];
1898         lqpn = qp->ibqp.qp_num;
1899
1900         process_becn(ppd, sl, rlid, lqpn, rqpn, svc_type);
1901 }