drivers/infiniband/hw/hfi1/verbs.c

   1 /*
   2  * Copyright(c) 2015 - 2018 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 #include <rdma/ib_mad.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <linux/io.h>
  51 #include <linux/module.h>
  52 #include <linux/utsname.h>
  53 #include <linux/rculist.h>
  54 #include <linux/mm.h>
  55 #include <linux/vmalloc.h>
  56 #include <rdma/opa_addr.h>
  57
  58 #include "hfi.h"
  59 #include "common.h"
  60 #include "device.h"
  61 #include "trace.h"
  62 #include "qp.h"
  63 #include "verbs_txreq.h"
  64 #include "debugfs.h"
  65 #include "vnic.h"
  66 #include "fault.h"
  67 #include "affinity.h"
  68
  69 static unsigned int hfi1_lkey_table_size = 16;
  70 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint,
  71                    S_IRUGO);
  72 MODULE_PARM_DESC(lkey_table_size,
  73                  "LKEY table size in bits (2^n, 1 <= n <= 23)");
  74
  75 static unsigned int hfi1_max_pds = 0xFFFF;
  76 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO);
  77 MODULE_PARM_DESC(max_pds,
  78                  "Maximum number of protection domains to support");
  79
  80 static unsigned int hfi1_max_ahs = 0xFFFF;
  81 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO);
  82 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
  83
  84 unsigned int hfi1_max_cqes = 0x2FFFFF;
  85 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO);
  86 MODULE_PARM_DESC(max_cqes,
  87                  "Maximum number of completion queue entries to support");
  88
  89 unsigned int hfi1_max_cqs = 0x1FFFF;
  90 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO);
  91 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
  92
  93 unsigned int hfi1_max_qp_wrs = 0x3FFF;
  94 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO);
  95 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
  96
  97 unsigned int hfi1_max_qps = 32768;
  98 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO);
  99 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
 100
 101 unsigned int hfi1_max_sges = 0x60;
 102 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO);
 103 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
 104
 105 unsigned int hfi1_max_mcast_grps = 16384;
 106 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO);
 107 MODULE_PARM_DESC(max_mcast_grps,
 108                  "Maximum number of multicast groups to support");
 109
 110 unsigned int hfi1_max_mcast_qp_attached = 16;
 111 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached,
 112                    uint, S_IRUGO);
 113 MODULE_PARM_DESC(max_mcast_qp_attached,
 114                  "Maximum number of attached QPs to support");
 115
 116 unsigned int hfi1_max_srqs = 1024;
 117 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO);
 118 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
 119
 120 unsigned int hfi1_max_srq_sges = 128;
 121 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO);
 122 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
 123
 124 unsigned int hfi1_max_srq_wrs = 0x1FFFF;
 125 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO);
 126 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
 127
 128 unsigned short piothreshold = 256;
 129 module_param(piothreshold, ushort, S_IRUGO);
 130 MODULE_PARM_DESC(piothreshold, "size used to determine sdma vs. pio");
 131
 132 #define COPY_CACHELESS 1
 133 #define COPY_ADAPTIVE  2
 134 static unsigned int sge_copy_mode;
 135 module_param(sge_copy_mode, uint, S_IRUGO);
 136 MODULE_PARM_DESC(sge_copy_mode,
 137                  "Verbs copy mode: 0 use memcpy, 1 use cacheless copy, 2 adapt based on WSS");
 138
 139 static void verbs_sdma_complete(
 140         struct sdma_txreq *cookie,
 141         int status);
 142
 143 static int pio_wait(struct rvt_qp *qp,
 144                     struct send_context *sc,
 145                     struct hfi1_pkt_state *ps,
 146                     u32 flag);
 147
 148 /* Length of buffer to create verbs txreq cache name */
 149 #define TXREQ_NAME_LEN 24
 150
 151 /* 16B trailing buffer */
 152 static const u8 trail_buf[MAX_16B_PADDING];
 153
 154 static uint wss_threshold;
 155 module_param(wss_threshold, uint, S_IRUGO);
 156 MODULE_PARM_DESC(wss_threshold, "Percentage (1-100) of LLC to use as a threshold for a cacheless copy");
 157 static uint wss_clean_period = 256;
 158 module_param(wss_clean_period, uint, S_IRUGO);
 159 MODULE_PARM_DESC(wss_clean_period, "Count of verbs copies before an entry in the page copy table is cleaned");
 160
 161 /* memory working set size */
 162 struct hfi1_wss {
 163         unsigned long *entries;
 164         atomic_t total_count;
 165         atomic_t clean_counter;
 166         atomic_t clean_entry;
 167
 168         int threshold;
 169         int num_entries;
 170         long pages_mask;
 171 };
 172
 173 static struct hfi1_wss wss;
 174
 175 int hfi1_wss_init(void)
 176 {
 177         long llc_size;
 178         long llc_bits;
 179         long table_size;
 180         long table_bits;
 181
 182         /* check for a valid percent range - default to 80 if none or invalid */
 183         if (wss_threshold < 1 || wss_threshold > 100)
 184                 wss_threshold = 80;
 185         /* reject a wildly large period */
 186         if (wss_clean_period > 1000000)
 187                 wss_clean_period = 256;
 188         /* reject a zero period */
 189         if (wss_clean_period == 0)
 190                 wss_clean_period = 1;
 191
 192         /*
 193          * Calculate the table size - the next power of 2 larger than the
 194          * LLC size.  LLC size is in KiB.
 195          */
 196         llc_size = wss_llc_size() * 1024;
 197         table_size = roundup_pow_of_two(llc_size);
 198
 199         /* one bit per page in rounded up table */
 200         llc_bits = llc_size / PAGE_SIZE;
 201         table_bits = table_size / PAGE_SIZE;
 202         wss.pages_mask = table_bits - 1;
 203         wss.num_entries = table_bits / BITS_PER_LONG;
 204
 205         wss.threshold = (llc_bits * wss_threshold) / 100;
 206         if (wss.threshold == 0)
 207                 wss.threshold = 1;
 208
 209         atomic_set(&wss.clean_counter, wss_clean_period);
 210
 211         wss.entries = kcalloc(wss.num_entries, sizeof(*wss.entries),
 212                               GFP_KERNEL);
 213         if (!wss.entries) {
 214                 hfi1_wss_exit();
 215                 return -ENOMEM;
 216         }
 217
 218         return 0;
 219 }
 220
 221 void hfi1_wss_exit(void)
 222 {
 223         /* coded to handle partially initialized and repeat callers */
 224         kfree(wss.entries);
 225         wss.entries = NULL;
 226 }
 227
 228 /*
 229  * Advance the clean counter.  When the clean period has expired,
 230  * clean an entry.
 231  *
 232  * This is implemented in atomics to avoid locking.  Because multiple
 233  * variables are involved, it can be racy which can lead to slightly
 234  * inaccurate information.  Since this is only a heuristic, this is
 235  * OK.  Any innaccuracies will clean themselves out as the counter
 236  * advances.  That said, it is unlikely the entry clean operation will
 237  * race - the next possible racer will not start until the next clean
 238  * period.
 239  *
 240  * The clean counter is implemented as a decrement to zero.  When zero
 241  * is reached an entry is cleaned.
 242  */
 243 static void wss_advance_clean_counter(void)
 244 {
 245         int entry;
 246         int weight;
 247         unsigned long bits;
 248
 249         /* become the cleaner if we decrement the counter to zero */
 250         if (atomic_dec_and_test(&wss.clean_counter)) {
 251                 /*
 252                  * Set, not add, the clean period.  This avoids an issue
 253                  * where the counter could decrement below the clean period.
 254                  * Doing a set can result in lost decrements, slowing the
 255                  * clean advance.  Since this a heuristic, this possible
 256                  * slowdown is OK.
 257                  *
 258                  * An alternative is to loop, advancing the counter by a
 259                  * clean period until the result is > 0. However, this could
 260                  * lead to several threads keeping another in the clean loop.
 261                  * This could be mitigated by limiting the number of times
 262                  * we stay in the loop.
 263                  */
 264                 atomic_set(&wss.clean_counter, wss_clean_period);
 265
 266                 /*
 267                  * Uniquely grab the entry to clean and move to next.
 268                  * The current entry is always the lower bits of
 269                  * wss.clean_entry.  The table size, wss.num_entries,
 270                  * is always a power-of-2.
 271                  */
 272                 entry = (atomic_inc_return(&wss.clean_entry) - 1)
 273                         & (wss.num_entries - 1);
 274
 275                 /* clear the entry and count the bits */
 276                 bits = xchg(&wss.entries[entry], 0);
 277                 weight = hweight64((u64)bits);
 278                 /* only adjust the contended total count if needed */
 279                 if (weight)
 280                         atomic_sub(weight, &wss.total_count);
 281         }
 282 }
 283
 284 /*
 285  * Insert the given address into the working set array.
 286  */
 287 static void wss_insert(void *address)
 288 {
 289         u32 page = ((unsigned long)address >> PAGE_SHIFT) & wss.pages_mask;
 290         u32 entry = page / BITS_PER_LONG; /* assumes this ends up a shift */
 291         u32 nr = page & (BITS_PER_LONG - 1);
 292
 293         if (!test_and_set_bit(nr, &wss.entries[entry]))
 294                 atomic_inc(&wss.total_count);
 295
 296         wss_advance_clean_counter();
 297 }
 298
 299 /*
 300  * Is the working set larger than the threshold?
 301  */
 302 static inline bool wss_exceeds_threshold(void)
 303 {
 304         return atomic_read(&wss.total_count) >= wss.threshold;
 305 }
 306
 307 /*
 308  * Translate ib_wr_opcode into ib_wc_opcode.
 309  */
 310 const enum ib_wc_opcode ib_hfi1_wc_opcode[] = {
 311         [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
 312         [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
 313         [IB_WR_SEND] = IB_WC_SEND,
 314         [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
 315         [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
 316         [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
 317         [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD,
 318         [IB_WR_SEND_WITH_INV] = IB_WC_SEND,
 319         [IB_WR_LOCAL_INV] = IB_WC_LOCAL_INV,
 320         [IB_WR_REG_MR] = IB_WC_REG_MR
 321 };
 322
 323 /*
 324  * Length of header by opcode, 0 --> not supported
 325  */
 326 const u8 hdr_len_by_opcode[256] = {
 327         /* RC */
 328         [IB_OPCODE_RC_SEND_FIRST]                     = 12 + 8,
 329         [IB_OPCODE_RC_SEND_MIDDLE]                    = 12 + 8,
 330         [IB_OPCODE_RC_SEND_LAST]                      = 12 + 8,
 331         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 332         [IB_OPCODE_RC_SEND_ONLY]                      = 12 + 8,
 333         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 334         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 335         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 336         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = 12 + 8,
 337         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 338         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 339         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 340         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = 12 + 8 + 16,
 341         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = 12 + 8 + 4,
 342         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = 12 + 8,
 343         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = 12 + 8 + 4,
 344         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = 12 + 8 + 4,
 345         [IB_OPCODE_RC_ACKNOWLEDGE]                    = 12 + 8 + 4,
 346         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = 12 + 8 + 4 + 8,
 347         [IB_OPCODE_RC_COMPARE_SWAP]                   = 12 + 8 + 28,
 348         [IB_OPCODE_RC_FETCH_ADD]                      = 12 + 8 + 28,
 349         [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE]      = 12 + 8 + 4,
 350         [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE]      = 12 + 8 + 4,
 351         /* UC */
 352         [IB_OPCODE_UC_SEND_FIRST]                     = 12 + 8,
 353         [IB_OPCODE_UC_SEND_MIDDLE]                    = 12 + 8,
 354         [IB_OPCODE_UC_SEND_LAST]                      = 12 + 8,
 355         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 356         [IB_OPCODE_UC_SEND_ONLY]                      = 12 + 8,
 357         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 358         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 359         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 360         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = 12 + 8,
 361         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 362         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 363         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 364         /* UD */
 365         [IB_OPCODE_UD_SEND_ONLY]                      = 12 + 8 + 8,
 366         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 12
 367 };
 368
 369 static const opcode_handler opcode_handler_tbl[256] = {
 370         /* RC */
 371         [IB_OPCODE_RC_SEND_FIRST]                     = &hfi1_rc_rcv,
 372         [IB_OPCODE_RC_SEND_MIDDLE]                    = &hfi1_rc_rcv,
 373         [IB_OPCODE_RC_SEND_LAST]                      = &hfi1_rc_rcv,
 374         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 375         [IB_OPCODE_RC_SEND_ONLY]                      = &hfi1_rc_rcv,
 376         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 377         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = &hfi1_rc_rcv,
 378         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = &hfi1_rc_rcv,
 379         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = &hfi1_rc_rcv,
 380         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 381         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = &hfi1_rc_rcv,
 382         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 383         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = &hfi1_rc_rcv,
 384         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = &hfi1_rc_rcv,
 385         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = &hfi1_rc_rcv,
 386         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = &hfi1_rc_rcv,
 387         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = &hfi1_rc_rcv,
 388         [IB_OPCODE_RC_ACKNOWLEDGE]                    = &hfi1_rc_rcv,
 389         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = &hfi1_rc_rcv,
 390         [IB_OPCODE_RC_COMPARE_SWAP]                   = &hfi1_rc_rcv,
 391         [IB_OPCODE_RC_FETCH_ADD]                      = &hfi1_rc_rcv,
 392         [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE]      = &hfi1_rc_rcv,
 393         [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE]      = &hfi1_rc_rcv,
 394         /* UC */
 395         [IB_OPCODE_UC_SEND_FIRST]                     = &hfi1_uc_rcv,
 396         [IB_OPCODE_UC_SEND_MIDDLE]                    = &hfi1_uc_rcv,
 397         [IB_OPCODE_UC_SEND_LAST]                      = &hfi1_uc_rcv,
 398         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 399         [IB_OPCODE_UC_SEND_ONLY]                      = &hfi1_uc_rcv,
 400         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 401         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = &hfi1_uc_rcv,
 402         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = &hfi1_uc_rcv,
 403         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = &hfi1_uc_rcv,
 404         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 405         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = &hfi1_uc_rcv,
 406         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 407         /* UD */
 408         [IB_OPCODE_UD_SEND_ONLY]                      = &hfi1_ud_rcv,
 409         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_ud_rcv,
 410         /* CNP */
 411         [IB_OPCODE_CNP]                               = &hfi1_cnp_rcv
 412 };
 413
 414 #define OPMASK 0x1f
 415
 416 static const u32 pio_opmask[BIT(3)] = {
 417         /* RC */
 418         [IB_OPCODE_RC >> 5] =
 419                 BIT(RC_OP(SEND_ONLY) & OPMASK) |
 420                 BIT(RC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
 421                 BIT(RC_OP(RDMA_WRITE_ONLY) & OPMASK) |
 422                 BIT(RC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK) |
 423                 BIT(RC_OP(RDMA_READ_REQUEST) & OPMASK) |
 424                 BIT(RC_OP(ACKNOWLEDGE) & OPMASK) |
 425                 BIT(RC_OP(ATOMIC_ACKNOWLEDGE) & OPMASK) |
 426                 BIT(RC_OP(COMPARE_SWAP) & OPMASK) |
 427                 BIT(RC_OP(FETCH_ADD) & OPMASK),
 428         /* UC */
 429         [IB_OPCODE_UC >> 5] =
 430                 BIT(UC_OP(SEND_ONLY) & OPMASK) |
 431                 BIT(UC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
 432                 BIT(UC_OP(RDMA_WRITE_ONLY) & OPMASK) |
 433                 BIT(UC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK),
 434 };
 435
 436 /*
 437  * System image GUID.
 438  */
 439 __be64 ib_hfi1_sys_image_guid;
 440
 441 /**
 442  * hfi1_copy_sge - copy data to SGE memory
 443  * @ss: the SGE state
 444  * @data: the data to copy
 445  * @length: the length of the data
 446  * @release: boolean to release MR
 447  * @copy_last: do a separate copy of the last 8 bytes
 448  */
 449 void hfi1_copy_sge(
 450         struct rvt_sge_state *ss,
 451         void *data, u32 length,
 452         bool release,
 453         bool copy_last)
 454 {
 455         struct rvt_sge *sge = &ss->sge;
 456         int i;
 457         bool in_last = false;
 458         bool cacheless_copy = false;
 459
 460         if (sge_copy_mode == COPY_CACHELESS) {
 461                 cacheless_copy = length >= PAGE_SIZE;
 462         } else if (sge_copy_mode == COPY_ADAPTIVE) {
 463                 if (length >= PAGE_SIZE) {
 464                         /*
 465                          * NOTE: this *assumes*:
 466                          * o The first vaddr is the dest.
 467                          * o If multiple pages, then vaddr is sequential.
 468                          */
 469                         wss_insert(sge->vaddr);
 470                         if (length >= (2 * PAGE_SIZE))
 471                                 wss_insert(sge->vaddr + PAGE_SIZE);
 472
 473                         cacheless_copy = wss_exceeds_threshold();
 474                 } else {
 475                         wss_advance_clean_counter();
 476                 }
 477         }
 478         if (copy_last) {
 479                 if (length > 8) {
 480                         length -= 8;
 481                 } else {
 482                         copy_last = false;
 483                         in_last = true;
 484                 }
 485         }
 486
 487 again:
 488         while (length) {
 489                 u32 len = rvt_get_sge_length(sge, length);
 490
 491                 WARN_ON_ONCE(len == 0);
 492                 if (unlikely(in_last)) {
 493                         /* enforce byte transfer ordering */
 494                         for (i = 0; i < len; i++)
 495                                 ((u8 *)sge->vaddr)[i] = ((u8 *)data)[i];
 496                 } else if (cacheless_copy) {
 497                         cacheless_memcpy(sge->vaddr, data, len);
 498                 } else {
 499                         memcpy(sge->vaddr, data, len);
 500                 }
 501                 rvt_update_sge(ss, len, release);
 502                 data += len;
 503                 length -= len;
 504         }
 505
 506         if (copy_last) {
 507                 copy_last = false;
 508                 in_last = true;
 509                 length = 8;
 510                 goto again;
 511         }
 512 }
 513
 514 /*
 515  * Make sure the QP is ready and able to accept the given opcode.
 516  */
 517 static inline opcode_handler qp_ok(struct hfi1_packet *packet)
 518 {
 519         if (!(ib_rvt_state_ops[packet->qp->state] & RVT_PROCESS_RECV_OK))
 520                 return NULL;
 521         if (((packet->opcode & RVT_OPCODE_QP_MASK) ==
 522              packet->qp->allowed_ops) ||
 523             (packet->opcode == IB_OPCODE_CNP))
 524                 return opcode_handler_tbl[packet->opcode];
 525
 526         return NULL;
 527 }
 528
 529 static u64 hfi1_fault_tx(struct rvt_qp *qp, u8 opcode, u64 pbc)
 530 {
 531 #ifdef CONFIG_FAULT_INJECTION
 532         if ((opcode & IB_OPCODE_MSP) == IB_OPCODE_MSP)
 533                 /*
 534                  * In order to drop non-IB traffic we
 535                  * set PbcInsertHrc to NONE (0x2).
 536                  * The packet will still be delivered
 537                  * to the receiving node but a
 538                  * KHdrHCRCErr (KDETH packet with a bad
 539                  * HCRC) will be triggered and the
 540                  * packet will not be delivered to the
 541                  * correct context.
 542                  */
 543                 pbc |= (u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT;
 544         else
 545                 /*
 546                  * In order to drop regular verbs
 547                  * traffic we set the PbcTestEbp
 548                  * flag. The packet will still be
 549                  * delivered to the receiving node but
 550                  * a 'late ebp error' will be
 551                  * triggered and will be dropped.
 552                  */
 553                 pbc |= PBC_TEST_EBP;
 554 #endif
 555         return pbc;
 556 }
 557
 558 static int hfi1_do_pkey_check(struct hfi1_packet *packet)
 559 {
 560         struct hfi1_ctxtdata *rcd = packet->rcd;
 561         struct hfi1_pportdata *ppd = rcd->ppd;
 562         struct hfi1_16b_header *hdr = packet->hdr;
 563         u16 pkey;
 564
 565         /* Pkey check needed only for bypass packets */
 566         if (packet->etype != RHF_RCV_TYPE_BYPASS)
 567                 return 0;
 568
 569         /* Perform pkey check */
 570         pkey = hfi1_16B_get_pkey(hdr);
 571         return ingress_pkey_check(ppd, pkey, packet->sc,
 572                                   packet->qp->s_pkey_index,
 573                                   packet->slid, true);
 574 }
 575
 576 static inline void hfi1_handle_packet(struct hfi1_packet *packet,
 577                                       bool is_mcast)
 578 {
 579         u32 qp_num;
 580         struct hfi1_ctxtdata *rcd = packet->rcd;
 581         struct hfi1_pportdata *ppd = rcd->ppd;
 582         struct hfi1_ibport *ibp = rcd_to_iport(rcd);
 583         struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi;
 584         opcode_handler packet_handler;
 585         unsigned long flags;
 586
 587         inc_opstats(packet->tlen, &rcd->opstats->stats[packet->opcode]);
 588
 589         if (unlikely(is_mcast)) {
 590                 struct rvt_mcast *mcast;
 591                 struct rvt_mcast_qp *p;
 592
 593                 if (!packet->grh)
 594                         goto drop;
 595                 mcast = rvt_mcast_find(&ibp->rvp,
 596                                        &packet->grh->dgid,
 597                                        opa_get_lid(packet->dlid, 9B));
 598                 if (!mcast)
 599                         goto drop;
 600                 list_for_each_entry_rcu(p, &mcast->qp_list, list) {
 601                         packet->qp = p->qp;
 602                         if (hfi1_do_pkey_check(packet))
 603                                 goto drop;
 604                         spin_lock_irqsave(&packet->qp->r_lock, flags);
 605                         packet_handler = qp_ok(packet);
 606                         if (likely(packet_handler))
 607                                 packet_handler(packet);
 608                         else
 609                                 ibp->rvp.n_pkt_drops++;
 610                         spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 611                 }
 612                 /*
 613                  * Notify rvt_multicast_detach() if it is waiting for us
 614                  * to finish.
 615                  */
 616                 if (atomic_dec_return(&mcast->refcount) <= 1)
 617                         wake_up(&mcast->wait);
 618         } else {
 619                 /* Get the destination QP number. */
 620                 qp_num = ib_bth_get_qpn(packet->ohdr);
 621                 rcu_read_lock();
 622                 packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
 623                 if (!packet->qp)
 624                         goto unlock_drop;
 625
 626                 if (hfi1_do_pkey_check(packet))
 627                         goto unlock_drop;
 628
 629                 spin_lock_irqsave(&packet->qp->r_lock, flags);
 630                 packet_handler = qp_ok(packet);
 631                 if (likely(packet_handler))
 632                         packet_handler(packet);
 633                 else
 634                         ibp->rvp.n_pkt_drops++;
 635                 spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 636                 rcu_read_unlock();
 637         }
 638         return;
 639 unlock_drop:
 640         rcu_read_unlock();
 641 drop:
 642         ibp->rvp.n_pkt_drops++;
 643 }
 644
 645 /**
 646  * hfi1_ib_rcv - process an incoming packet
 647  * @packet: data packet information
 648  *
 649  * This is called to process an incoming packet at interrupt level.
 650  */
 651 void hfi1_ib_rcv(struct hfi1_packet *packet)
 652 {
 653         struct hfi1_ctxtdata *rcd = packet->rcd;
 654
 655         trace_input_ibhdr(rcd->dd, packet, !!(rhf_dc_info(packet->rhf)));
 656         hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid));
 657 }
 658
 659 void hfi1_16B_rcv(struct hfi1_packet *packet)
 660 {
 661         struct hfi1_ctxtdata *rcd = packet->rcd;
 662
 663         trace_input_ibhdr(rcd->dd, packet, false);
 664         hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid));
 665 }
 666
 667 /*
 668  * This is called from a timer to check for QPs
 669  * which need kernel memory in order to send a packet.
 670  */
 671 static void mem_timer(struct timer_list *t)
 672 {
 673         struct hfi1_ibdev *dev = from_timer(dev, t, mem_timer);
 674         struct list_head *list = &dev->memwait;
 675         struct rvt_qp *qp = NULL;
 676         struct iowait *wait;
 677         unsigned long flags;
 678         struct hfi1_qp_priv *priv;
 679
 680         write_seqlock_irqsave(&dev->iowait_lock, flags);
 681         if (!list_empty(list)) {
 682                 wait = list_first_entry(list, struct iowait, list);
 683                 qp = iowait_to_qp(wait);
 684                 priv = qp->priv;
 685                 list_del_init(&priv->s_iowait.list);
 686                 priv->s_iowait.lock = NULL;
 687                 /* refcount held until actual wake up */
 688                 if (!list_empty(list))
 689                         mod_timer(&dev->mem_timer, jiffies + 1);
 690         }
 691         write_sequnlock_irqrestore(&dev->iowait_lock, flags);
 692
 693         if (qp)
 694                 hfi1_qp_wakeup(qp, RVT_S_WAIT_KMEM);
 695 }
 696
 697 /*
 698  * This is called with progress side lock held.
 699  */
 700 /* New API */
 701 static void verbs_sdma_complete(
 702         struct sdma_txreq *cookie,
 703         int status)
 704 {
 705         struct verbs_txreq *tx =
 706                 container_of(cookie, struct verbs_txreq, txreq);
 707         struct rvt_qp *qp = tx->qp;
 708
 709         spin_lock(&qp->s_lock);
 710         if (tx->wqe) {
 711                 hfi1_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
 712         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
 713                 struct hfi1_opa_header *hdr;
 714
 715                 hdr = &tx->phdr.hdr;
 716                 hfi1_rc_send_complete(qp, hdr);
 717         }
 718         spin_unlock(&qp->s_lock);
 719
 720         hfi1_put_txreq(tx);
 721 }
 722
 723 static int wait_kmem(struct hfi1_ibdev *dev,
 724                      struct rvt_qp *qp,
 725                      struct hfi1_pkt_state *ps)
 726 {
 727         struct hfi1_qp_priv *priv = qp->priv;
 728         unsigned long flags;
 729         int ret = 0;
 730
 731         spin_lock_irqsave(&qp->s_lock, flags);
 732         if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
 733                 write_seqlock(&dev->iowait_lock);
 734                 list_add_tail(&ps->s_txreq->txreq.list,
 735                               &priv->s_iowait.tx_head);
 736                 if (list_empty(&priv->s_iowait.list)) {
 737                         if (list_empty(&dev->memwait))
 738                                 mod_timer(&dev->mem_timer, jiffies + 1);
 739                         qp->s_flags |= RVT_S_WAIT_KMEM;
 740                         list_add_tail(&priv->s_iowait.list, &dev->memwait);
 741                         priv->s_iowait.lock = &dev->iowait_lock;
 742                         trace_hfi1_qpsleep(qp, RVT_S_WAIT_KMEM);
 743                         rvt_get_qp(qp);
 744                 }
 745                 write_sequnlock(&dev->iowait_lock);
 746                 qp->s_flags &= ~RVT_S_BUSY;
 747                 ret = -EBUSY;
 748         }
 749         spin_unlock_irqrestore(&qp->s_lock, flags);
 750
 751         return ret;
 752 }
 753
 754 /*
 755  * This routine calls txadds for each sg entry.
 756  *
 757  * Add failures will revert the sge cursor
 758  */
 759 static noinline int build_verbs_ulp_payload(
 760         struct sdma_engine *sde,
 761         u32 length,
 762         struct verbs_txreq *tx)
 763 {
 764         struct rvt_sge_state *ss = tx->ss;
 765         struct rvt_sge *sg_list = ss->sg_list;
 766         struct rvt_sge sge = ss->sge;
 767         u8 num_sge = ss->num_sge;
 768         u32 len;
 769         int ret = 0;
 770
 771         while (length) {
 772                 len = ss->sge.length;
 773                 if (len > length)
 774                         len = length;
 775                 if (len > ss->sge.sge_length)
 776                         len = ss->sge.sge_length;
 777                 WARN_ON_ONCE(len == 0);
 778                 ret = sdma_txadd_kvaddr(
 779                         sde->dd,
 780                         &tx->txreq,
 781                         ss->sge.vaddr,
 782                         len);
 783                 if (ret)
 784                         goto bail_txadd;
 785                 rvt_update_sge(ss, len, false);
 786                 length -= len;
 787         }
 788         return ret;
 789 bail_txadd:
 790         /* unwind cursor */
 791         ss->sge = sge;
 792         ss->num_sge = num_sge;
 793         ss->sg_list = sg_list;
 794         return ret;
 795 }
 796
 797 /**
 798  * update_tx_opstats - record stats by opcode
 799  * @qp; the qp
 800  * @ps: transmit packet state
 801  * @plen: the plen in dwords
 802  *
 803  * This is a routine to record the tx opstats after a
 804  * packet has been presented to the egress mechanism.
 805  */
 806 static void update_tx_opstats(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
 807                               u32 plen)
 808 {
 809 #ifdef CONFIG_DEBUG_FS
 810         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
 811         struct hfi1_opcode_stats_perctx *s = get_cpu_ptr(dd->tx_opstats);
 812
 813         inc_opstats(plen * 4, &s->stats[ps->opcode]);
 814         put_cpu_ptr(s);
 815 #endif
 816 }
 817
 818 /*
 819  * Build the number of DMA descriptors needed to send length bytes of data.
 820  *
 821  * NOTE: DMA mapping is held in the tx until completed in the ring or
 822  *       the tx desc is freed without having been submitted to the ring
 823  *
 824  * This routine ensures all the helper routine calls succeed.
 825  */
 826 /* New API */
 827 static int build_verbs_tx_desc(
 828         struct sdma_engine *sde,
 829         u32 length,
 830         struct verbs_txreq *tx,
 831         struct hfi1_ahg_info *ahg_info,
 832         u64 pbc)
 833 {
 834         int ret = 0;
 835         struct hfi1_sdma_header *phdr = &tx->phdr;
 836         u16 hdrbytes = (tx->hdr_dwords + sizeof(pbc) / 4) << 2;
 837         u8 extra_bytes = 0;
 838
 839         if (tx->phdr.hdr.hdr_type) {
 840                 /*
 841                  * hdrbytes accounts for PBC. Need to subtract 8 bytes
 842                  * before calculating padding.
 843                  */
 844                 extra_bytes = hfi1_get_16b_padding(hdrbytes - 8, length) +
 845                               (SIZE_OF_CRC << 2) + SIZE_OF_LT;
 846         }
 847         if (!ahg_info->ahgcount) {
 848                 ret = sdma_txinit_ahg(
 849                         &tx->txreq,
 850                         ahg_info->tx_flags,
 851                         hdrbytes + length +
 852                         extra_bytes,
 853                         ahg_info->ahgidx,
 854                         0,
 855                         NULL,
 856                         0,
 857                         verbs_sdma_complete);
 858                 if (ret)
 859                         goto bail_txadd;
 860                 phdr->pbc = cpu_to_le64(pbc);
 861                 ret = sdma_txadd_kvaddr(
 862                         sde->dd,
 863                         &tx->txreq,
 864                         phdr,
 865                         hdrbytes);
 866                 if (ret)
 867                         goto bail_txadd;
 868         } else {
 869                 ret = sdma_txinit_ahg(
 870                         &tx->txreq,
 871                         ahg_info->tx_flags,
 872                         length,
 873                         ahg_info->ahgidx,
 874                         ahg_info->ahgcount,
 875                         ahg_info->ahgdesc,
 876                         hdrbytes,
 877                         verbs_sdma_complete);
 878                 if (ret)
 879                         goto bail_txadd;
 880         }
 881         /* add the ulp payload - if any. tx->ss can be NULL for acks */
 882         if (tx->ss) {
 883                 ret = build_verbs_ulp_payload(sde, length, tx);
 884                 if (ret)
 885                         goto bail_txadd;
 886         }
 887
 888         /* add icrc, lt byte, and padding to flit */
 889         if (extra_bytes)
 890                 ret = sdma_txadd_kvaddr(sde->dd, &tx->txreq,
 891                                         (void *)trail_buf, extra_bytes);
 892
 893 bail_txadd:
 894         return ret;
 895 }
 896
 897 int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
 898                         u64 pbc)
 899 {
 900         struct hfi1_qp_priv *priv = qp->priv;
 901         struct hfi1_ahg_info *ahg_info = priv->s_ahg;
 902         u32 hdrwords = ps->s_txreq->hdr_dwords;
 903         u32 len = ps->s_txreq->s_cur_size;
 904         u32 plen;
 905         struct hfi1_ibdev *dev = ps->dev;
 906         struct hfi1_pportdata *ppd = ps->ppd;
 907         struct verbs_txreq *tx;
 908         u8 sc5 = priv->s_sc;
 909         int ret;
 910         u32 dwords;
 911
 912         if (ps->s_txreq->phdr.hdr.hdr_type) {
 913                 u8 extra_bytes = hfi1_get_16b_padding((hdrwords << 2), len);
 914
 915                 dwords = (len + extra_bytes + (SIZE_OF_CRC << 2) +
 916                           SIZE_OF_LT) >> 2;
 917         } else {
 918                 dwords = (len + 3) >> 2;
 919         }
 920         plen = hdrwords + dwords + sizeof(pbc) / 4;
 921
 922         tx = ps->s_txreq;
 923         if (!sdma_txreq_built(&tx->txreq)) {
 924                 if (likely(pbc == 0)) {
 925                         u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
 926
 927                         /* No vl15 here */
 928                         /* set PBC_DC_INFO bit (aka SC[4]) in pbc */
 929                         if (ps->s_txreq->phdr.hdr.hdr_type)
 930                                 pbc |= PBC_PACKET_BYPASS |
 931                                        PBC_INSERT_BYPASS_ICRC;
 932                         else
 933                                 pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT);
 934
 935                         if (unlikely(hfi1_dbg_should_fault_tx(qp, ps->opcode)))
 936                                 pbc = hfi1_fault_tx(qp, ps->opcode, pbc);
 937                         pbc = create_pbc(ppd,
 938                                          pbc,
 939                                          qp->srate_mbps,
 940                                          vl,
 941                                          plen);
 942                 }
 943                 tx->wqe = qp->s_wqe;
 944                 ret = build_verbs_tx_desc(tx->sde, len, tx, ahg_info, pbc);
 945                 if (unlikely(ret))
 946                         goto bail_build;
 947         }
 948         ret =  sdma_send_txreq(tx->sde, &priv->s_iowait, &tx->txreq,
 949                                ps->pkts_sent);
 950         if (unlikely(ret < 0)) {
 951                 if (ret == -ECOMM)
 952                         goto bail_ecomm;
 953                 return ret;
 954         }
 955
 956         update_tx_opstats(qp, ps, plen);
 957         trace_sdma_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
 958                                 &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5));
 959         return ret;
 960
 961 bail_ecomm:
 962         /* The current one got "sent" */
 963         return 0;
 964 bail_build:
 965         ret = wait_kmem(dev, qp, ps);
 966         if (!ret) {
 967                 /* free txreq - bad state */
 968                 hfi1_put_txreq(ps->s_txreq);
 969                 ps->s_txreq = NULL;
 970         }
 971         return ret;
 972 }
 973
 974 /*
 975  * If we are now in the error state, return zero to flush the
 976  * send work request.
 977  */
 978 static int pio_wait(struct rvt_qp *qp,
 979                     struct send_context *sc,
 980                     struct hfi1_pkt_state *ps,
 981                     u32 flag)
 982 {
 983         struct hfi1_qp_priv *priv = qp->priv;
 984         struct hfi1_devdata *dd = sc->dd;
 985         struct hfi1_ibdev *dev = &dd->verbs_dev;
 986         unsigned long flags;
 987         int ret = 0;
 988
 989         /*
 990          * Note that as soon as want_buffer() is called and
 991          * possibly before it returns, sc_piobufavail()
 992          * could be called. Therefore, put QP on the I/O wait list before
 993          * enabling the PIO avail interrupt.
 994          */
 995         spin_lock_irqsave(&qp->s_lock, flags);
 996         if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
 997                 write_seqlock(&dev->iowait_lock);
 998                 list_add_tail(&ps->s_txreq->txreq.list,
 999                               &priv->s_iowait.tx_head);
1000                 if (list_empty(&priv->s_iowait.list)) {
1001                         struct hfi1_ibdev *dev = &dd->verbs_dev;
1002                         int was_empty;
1003
1004                         dev->n_piowait += !!(flag & RVT_S_WAIT_PIO);
1005                         dev->n_piodrain += !!(flag & RVT_S_WAIT_PIO_DRAIN);
1006                         qp->s_flags |= flag;
1007                         was_empty = list_empty(&sc->piowait);
1008                         iowait_queue(ps->pkts_sent, &priv->s_iowait,
1009                                      &sc->piowait);
1010                         priv->s_iowait.lock = &dev->iowait_lock;
1011                         trace_hfi1_qpsleep(qp, RVT_S_WAIT_PIO);
1012                         rvt_get_qp(qp);
1013                         /* counting: only call wantpiobuf_intr if first user */
1014                         if (was_empty)
1015                                 hfi1_sc_wantpiobuf_intr(sc, 1);
1016                 }
1017                 write_sequnlock(&dev->iowait_lock);
1018                 qp->s_flags &= ~RVT_S_BUSY;
1019                 ret = -EBUSY;
1020         }
1021         spin_unlock_irqrestore(&qp->s_lock, flags);
1022         return ret;
1023 }
1024
1025 static void verbs_pio_complete(void *arg, int code)
1026 {
1027         struct rvt_qp *qp = (struct rvt_qp *)arg;
1028         struct hfi1_qp_priv *priv = qp->priv;
1029
1030         if (iowait_pio_dec(&priv->s_iowait))
1031                 iowait_drain_wakeup(&priv->s_iowait);
1032 }
1033
1034 int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
1035                         u64 pbc)
1036 {
1037         struct hfi1_qp_priv *priv = qp->priv;
1038         u32 hdrwords = ps->s_txreq->hdr_dwords;
1039         struct rvt_sge_state *ss = ps->s_txreq->ss;
1040         u32 len = ps->s_txreq->s_cur_size;
1041         u32 dwords;
1042         u32 plen;
1043         struct hfi1_pportdata *ppd = ps->ppd;
1044         u32 *hdr;
1045         u8 sc5;
1046         unsigned long flags = 0;
1047         struct send_context *sc;
1048         struct pio_buf *pbuf;
1049         int wc_status = IB_WC_SUCCESS;
1050         int ret = 0;
1051         pio_release_cb cb = NULL;
1052         u8 extra_bytes = 0;
1053
1054         if (ps->s_txreq->phdr.hdr.hdr_type) {
1055                 u8 pad_size = hfi1_get_16b_padding((hdrwords << 2), len);
1056
1057                 extra_bytes = pad_size + (SIZE_OF_CRC << 2) + SIZE_OF_LT;
1058                 dwords = (len + extra_bytes) >> 2;
1059                 hdr = (u32 *)&ps->s_txreq->phdr.hdr.opah;
1060         } else {
1061                 dwords = (len + 3) >> 2;
1062                 hdr = (u32 *)&ps->s_txreq->phdr.hdr.ibh;
1063         }
1064         plen = hdrwords + dwords + sizeof(pbc) / 4;
1065
1066         /* only RC/UC use complete */
1067         switch (qp->ibqp.qp_type) {
1068         case IB_QPT_RC:
1069         case IB_QPT_UC:
1070                 cb = verbs_pio_complete;
1071                 break;
1072         default:
1073                 break;
1074         }
1075
1076         /* vl15 special case taken care of in ud.c */
1077         sc5 = priv->s_sc;
1078         sc = ps->s_txreq->psc;
1079
1080         if (likely(pbc == 0)) {
1081                 u8 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1082
1083                 /* set PBC_DC_INFO bit (aka SC[4]) in pbc */
1084                 if (ps->s_txreq->phdr.hdr.hdr_type)
1085                         pbc |= PBC_PACKET_BYPASS | PBC_INSERT_BYPASS_ICRC;
1086                 else
1087                         pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT);
1088
1089                 if (unlikely(hfi1_dbg_should_fault_tx(qp, ps->opcode)))
1090                         pbc = hfi1_fault_tx(qp, ps->opcode, pbc);
1091                 pbc = create_pbc(ppd, pbc, qp->srate_mbps, vl, plen);
1092         }
1093         if (cb)
1094                 iowait_pio_inc(&priv->s_iowait);
1095         pbuf = sc_buffer_alloc(sc, plen, cb, qp);
1096         if (unlikely(!pbuf)) {
1097                 if (cb)
1098                         verbs_pio_complete(qp, 0);
1099                 if (ppd->host_link_state != HLS_UP_ACTIVE) {
1100                         /*
1101                          * If we have filled the PIO buffers to capacity and are
1102                          * not in an active state this request is not going to
1103                          * go out to so just complete it with an error or else a
1104                          * ULP or the core may be stuck waiting.
1105                          */
1106                         hfi1_cdbg(
1107                                 PIO,
1108                                 "alloc failed. state not active, completing");
1109                         wc_status = IB_WC_GENERAL_ERR;
1110                         goto pio_bail;
1111                 } else {
1112                         /*
1113                          * This is a normal occurrence. The PIO buffs are full
1114                          * up but we are still happily sending, well we could be
1115                          * so lets continue to queue the request.
1116                          */
1117                         hfi1_cdbg(PIO, "alloc failed. state active, queuing");
1118                         ret = pio_wait(qp, sc, ps, RVT_S_WAIT_PIO);
1119                         if (!ret)
1120                                 /* txreq not queued - free */
1121                                 goto bail;
1122                         /* tx consumed in wait */
1123                         return ret;
1124                 }
1125         }
1126
1127         if (dwords == 0) {
1128                 pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords);
1129         } else {
1130                 seg_pio_copy_start(pbuf, pbc,
1131                                    hdr, hdrwords * 4);
1132                 if (ss) {
1133                         while (len) {
1134                                 void *addr = ss->sge.vaddr;
1135                                 u32 slen = ss->sge.length;
1136
1137                                 if (slen > len)
1138                                         slen = len;
1139                                 rvt_update_sge(ss, slen, false);
1140                                 seg_pio_copy_mid(pbuf, addr, slen);
1141                                 len -= slen;
1142                         }
1143                 }
1144                 /* add icrc, lt byte, and padding to flit */
1145                 if (extra_bytes)
1146                         seg_pio_copy_mid(pbuf, trail_buf, extra_bytes);
1147
1148                 seg_pio_copy_end(pbuf);
1149         }
1150
1151         update_tx_opstats(qp, ps, plen);
1152         trace_pio_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
1153                                &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5));
1154
1155 pio_bail:
1156         if (qp->s_wqe) {
1157                 spin_lock_irqsave(&qp->s_lock, flags);
1158                 hfi1_send_complete(qp, qp->s_wqe, wc_status);
1159                 spin_unlock_irqrestore(&qp->s_lock, flags);
1160         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1161                 spin_lock_irqsave(&qp->s_lock, flags);
1162                 hfi1_rc_send_complete(qp, &ps->s_txreq->phdr.hdr);
1163                 spin_unlock_irqrestore(&qp->s_lock, flags);
1164         }
1165
1166         ret = 0;
1167
1168 bail:
1169         hfi1_put_txreq(ps->s_txreq);
1170         return ret;
1171 }
1172
1173 /*
1174  * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1175  * being an entry from the partition key table), return 0
1176  * otherwise. Use the matching criteria for egress partition keys
1177  * specified in the OPAv1 spec., section 9.1l.7.
1178  */
1179 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent)
1180 {
1181         u16 mkey = pkey & PKEY_LOW_15_MASK;
1182         u16 mentry = ent & PKEY_LOW_15_MASK;
1183
1184         if (mkey == mentry) {
1185                 /*
1186                  * If pkey[15] is set (full partition member),
1187                  * is bit 15 in the corresponding table element
1188                  * clear (limited member)?
1189                  */
1190                 if (pkey & PKEY_MEMBER_MASK)
1191                         return !!(ent & PKEY_MEMBER_MASK);
1192                 return 1;
1193         }
1194         return 0;
1195 }
1196
1197 /**
1198  * egress_pkey_check - check P_KEY of a packet
1199  * @ppd:  Physical IB port data
1200  * @slid: SLID for packet
1201  * @bkey: PKEY for header
1202  * @sc5:  SC for packet
1203  * @s_pkey_index: It will be used for look up optimization for kernel contexts
1204  * only. If it is negative value, then it means user contexts is calling this
1205  * function.
1206  *
1207  * It checks if hdr's pkey is valid.
1208  *
1209  * Return: 0 on success, otherwise, 1
1210  */
1211 int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1212                       u8 sc5, int8_t s_pkey_index)
1213 {
1214         struct hfi1_devdata *dd;
1215         int i;
1216         int is_user_ctxt_mechanism = (s_pkey_index < 0);
1217
1218         if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT))
1219                 return 0;
1220
1221         /* If SC15, pkey[0:14] must be 0x7fff */
1222         if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1223                 goto bad;
1224
1225         /* Is the pkey = 0x0, or 0x8000? */
1226         if ((pkey & PKEY_LOW_15_MASK) == 0)
1227                 goto bad;
1228
1229         /*
1230          * For the kernel contexts only, if a qp is passed into the function,
1231          * the most likely matching pkey has index qp->s_pkey_index
1232          */
1233         if (!is_user_ctxt_mechanism &&
1234             egress_pkey_matches_entry(pkey, ppd->pkeys[s_pkey_index])) {
1235                 return 0;
1236         }
1237
1238         for (i = 0; i < MAX_PKEY_VALUES; i++) {
1239                 if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1240                         return 0;
1241         }
1242 bad:
1243         /*
1244          * For the user-context mechanism, the P_KEY check would only happen
1245          * once per SDMA request, not once per packet.  Therefore, there's no
1246          * need to increment the counter for the user-context mechanism.
1247          */
1248         if (!is_user_ctxt_mechanism) {
1249                 incr_cntr64(&ppd->port_xmit_constraint_errors);
1250                 dd = ppd->dd;
1251                 if (!(dd->err_info_xmit_constraint.status &
1252                       OPA_EI_STATUS_SMASK)) {
1253                         dd->err_info_xmit_constraint.status |=
1254                                 OPA_EI_STATUS_SMASK;
1255                         dd->err_info_xmit_constraint.slid = slid;
1256                         dd->err_info_xmit_constraint.pkey = pkey;
1257                 }
1258         }
1259         return 1;
1260 }
1261
1262 /**
1263  * get_send_routine - choose an egress routine
1264  *
1265  * Choose an egress routine based on QP type
1266  * and size
1267  */
1268 static inline send_routine get_send_routine(struct rvt_qp *qp,
1269                                             struct hfi1_pkt_state *ps)
1270 {
1271         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1272         struct hfi1_qp_priv *priv = qp->priv;
1273         struct verbs_txreq *tx = ps->s_txreq;
1274
1275         if (unlikely(!(dd->flags & HFI1_HAS_SEND_DMA)))
1276                 return dd->process_pio_send;
1277         switch (qp->ibqp.qp_type) {
1278         case IB_QPT_SMI:
1279                 return dd->process_pio_send;
1280         case IB_QPT_GSI:
1281         case IB_QPT_UD:
1282                 break;
1283         case IB_QPT_UC:
1284         case IB_QPT_RC: {
1285                 if (piothreshold &&
1286                     tx->s_cur_size <= min(piothreshold, qp->pmtu) &&
1287                     (BIT(ps->opcode & OPMASK) & pio_opmask[ps->opcode >> 5]) &&
1288                     iowait_sdma_pending(&priv->s_iowait) == 0 &&
1289                     !sdma_txreq_built(&tx->txreq))
1290                         return dd->process_pio_send;
1291                 break;
1292         }
1293         default:
1294                 break;
1295         }
1296         return dd->process_dma_send;
1297 }
1298
1299 /**
1300  * hfi1_verbs_send - send a packet
1301  * @qp: the QP to send on
1302  * @ps: the state of the packet to send
1303  *
1304  * Return zero if packet is sent or queued OK.
1305  * Return non-zero and clear qp->s_flags RVT_S_BUSY otherwise.
1306  */
1307 int hfi1_verbs_send(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
1308 {
1309         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1310         struct hfi1_qp_priv *priv = qp->priv;
1311         struct ib_other_headers *ohdr;
1312         send_routine sr;
1313         int ret;
1314         u16 pkey;
1315         u32 slid;
1316
1317         /* locate the pkey within the headers */
1318         if (ps->s_txreq->phdr.hdr.hdr_type) {
1319                 struct hfi1_16b_header *hdr = &ps->s_txreq->phdr.hdr.opah;
1320                 u8 l4 = hfi1_16B_get_l4(hdr);
1321
1322                 if (l4 == OPA_16B_L4_IB_GLOBAL)
1323                         ohdr = &hdr->u.l.oth;
1324                 else
1325                         ohdr = &hdr->u.oth;
1326                 slid = hfi1_16B_get_slid(hdr);
1327                 pkey = hfi1_16B_get_pkey(hdr);
1328         } else {
1329                 struct ib_header *hdr = &ps->s_txreq->phdr.hdr.ibh;
1330                 u8 lnh = ib_get_lnh(hdr);
1331
1332                 if (lnh == HFI1_LRH_GRH)
1333                         ohdr = &hdr->u.l.oth;
1334                 else
1335                         ohdr = &hdr->u.oth;
1336                 slid = ib_get_slid(hdr);
1337                 pkey = ib_bth_get_pkey(ohdr);
1338         }
1339
1340         ps->opcode = ib_bth_get_opcode(ohdr);
1341         sr = get_send_routine(qp, ps);
1342         ret = egress_pkey_check(dd->pport, slid, pkey,
1343                                 priv->s_sc, qp->s_pkey_index);
1344         if (unlikely(ret)) {
1345                 /*
1346                  * The value we are returning here does not get propagated to
1347                  * the verbs caller. Thus we need to complete the request with
1348                  * error otherwise the caller could be sitting waiting on the
1349                  * completion event. Only do this for PIO. SDMA has its own
1350                  * mechanism for handling the errors. So for SDMA we can just
1351                  * return.
1352                  */
1353                 if (sr == dd->process_pio_send) {
1354                         unsigned long flags;
1355
1356                         hfi1_cdbg(PIO, "%s() Failed. Completing with err",
1357                                   __func__);
1358                         spin_lock_irqsave(&qp->s_lock, flags);
1359                         hfi1_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
1360                         spin_unlock_irqrestore(&qp->s_lock, flags);
1361                 }
1362                 return -EINVAL;
1363         }
1364         if (sr == dd->process_dma_send && iowait_pio_pending(&priv->s_iowait))
1365                 return pio_wait(qp,
1366                                 ps->s_txreq->psc,
1367                                 ps,
1368                                 RVT_S_WAIT_PIO_DRAIN);
1369         return sr(qp, ps, 0);
1370 }
1371
1372 /**
1373  * hfi1_fill_device_attr - Fill in rvt dev info device attributes.
1374  * @dd: the device data structure
1375  */
1376 static void hfi1_fill_device_attr(struct hfi1_devdata *dd)
1377 {
1378         struct rvt_dev_info *rdi = &dd->verbs_dev.rdi;
1379         u32 ver = dd->dc8051_ver;
1380
1381         memset(&rdi->dparms.props, 0, sizeof(rdi->dparms.props));
1382
1383         rdi->dparms.props.fw_ver = ((u64)(dc8051_ver_maj(ver)) << 32) |
1384                 ((u64)(dc8051_ver_min(ver)) << 16) |
1385                 (u64)dc8051_ver_patch(ver);
1386
1387         rdi->dparms.props.device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1388                         IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1389                         IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1390                         IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE |
1391                         IB_DEVICE_MEM_MGT_EXTENSIONS |
1392                         IB_DEVICE_RDMA_NETDEV_OPA_VNIC;
1393         rdi->dparms.props.page_size_cap = PAGE_SIZE;
1394         rdi->dparms.props.vendor_id = dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3;
1395         rdi->dparms.props.vendor_part_id = dd->pcidev->device;
1396         rdi->dparms.props.hw_ver = dd->minrev;
1397         rdi->dparms.props.sys_image_guid = ib_hfi1_sys_image_guid;
1398         rdi->dparms.props.max_mr_size = U64_MAX;
1399         rdi->dparms.props.max_fast_reg_page_list_len = UINT_MAX;
1400         rdi->dparms.props.max_qp = hfi1_max_qps;
1401         rdi->dparms.props.max_qp_wr = hfi1_max_qp_wrs;
1402         rdi->dparms.props.max_sge = hfi1_max_sges;
1403         rdi->dparms.props.max_sge_rd = hfi1_max_sges;
1404         rdi->dparms.props.max_cq = hfi1_max_cqs;
1405         rdi->dparms.props.max_ah = hfi1_max_ahs;
1406         rdi->dparms.props.max_cqe = hfi1_max_cqes;
1407         rdi->dparms.props.max_mr = rdi->lkey_table.max;
1408         rdi->dparms.props.max_fmr = rdi->lkey_table.max;
1409         rdi->dparms.props.max_map_per_fmr = 32767;
1410         rdi->dparms.props.max_pd = hfi1_max_pds;
1411         rdi->dparms.props.max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC;
1412         rdi->dparms.props.max_qp_init_rd_atom = 255;
1413         rdi->dparms.props.max_srq = hfi1_max_srqs;
1414         rdi->dparms.props.max_srq_wr = hfi1_max_srq_wrs;
1415         rdi->dparms.props.max_srq_sge = hfi1_max_srq_sges;
1416         rdi->dparms.props.atomic_cap = IB_ATOMIC_GLOB;
1417         rdi->dparms.props.max_pkeys = hfi1_get_npkeys(dd);
1418         rdi->dparms.props.max_mcast_grp = hfi1_max_mcast_grps;
1419         rdi->dparms.props.max_mcast_qp_attach = hfi1_max_mcast_qp_attached;
1420         rdi->dparms.props.max_total_mcast_qp_attach =
1421                                         rdi->dparms.props.max_mcast_qp_attach *
1422                                         rdi->dparms.props.max_mcast_grp;
1423 }
1424
1425 static inline u16 opa_speed_to_ib(u16 in)
1426 {
1427         u16 out = 0;
1428
1429         if (in & OPA_LINK_SPEED_25G)
1430                 out |= IB_SPEED_EDR;
1431         if (in & OPA_LINK_SPEED_12_5G)
1432                 out |= IB_SPEED_FDR;
1433
1434         return out;
1435 }
1436
1437 /*
1438  * Convert a single OPA link width (no multiple flags) to an IB value.
1439  * A zero OPA link width means link down, which means the IB width value
1440  * is a don't care.
1441  */
1442 static inline u16 opa_width_to_ib(u16 in)
1443 {
1444         switch (in) {
1445         case OPA_LINK_WIDTH_1X:
1446         /* map 2x and 3x to 1x as they don't exist in IB */
1447         case OPA_LINK_WIDTH_2X:
1448         case OPA_LINK_WIDTH_3X:
1449                 return IB_WIDTH_1X;
1450         default: /* link down or unknown, return our largest width */
1451         case OPA_LINK_WIDTH_4X:
1452                 return IB_WIDTH_4X;
1453         }
1454 }
1455
1456 static int query_port(struct rvt_dev_info *rdi, u8 port_num,
1457                       struct ib_port_attr *props)
1458 {
1459         struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1460         struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1461         struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1462         u32 lid = ppd->lid;
1463
1464         /* props being zeroed by the caller, avoid zeroing it here */
1465         props->lid = lid ? lid : 0;
1466         props->lmc = ppd->lmc;
1467         /* OPA logical states match IB logical states */
1468         props->state = driver_lstate(ppd);
1469         props->phys_state = driver_pstate(ppd);
1470         props->gid_tbl_len = HFI1_GUIDS_PER_PORT;
1471         props->active_width = (u8)opa_width_to_ib(ppd->link_width_active);
1472         /* see rate_show() in ib core/sysfs.c */
1473         props->active_speed = (u8)opa_speed_to_ib(ppd->link_speed_active);
1474         props->max_vl_num = ppd->vls_supported;
1475
1476         /* Once we are a "first class" citizen and have added the OPA MTUs to
1477          * the core we can advertise the larger MTU enum to the ULPs, for now
1478          * advertise only 4K.
1479          *
1480          * Those applications which are either OPA aware or pass the MTU enum
1481          * from the Path Records to us will get the new 8k MTU.  Those that
1482          * attempt to process the MTU enum may fail in various ways.
1483          */
1484         props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ?
1485                                       4096 : hfi1_max_mtu), IB_MTU_4096);
1486         props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
1487                 mtu_to_enum(ppd->ibmtu, IB_MTU_4096);
1488
1489         /*
1490          * sm_lid of 0xFFFF needs special handling so that it can
1491          * be differentiated from a permissve LID of 0xFFFF.
1492          * We set the grh_required flag here so the SA can program
1493          * the DGID in the address handle appropriately
1494          */
1495         if (props->sm_lid == be16_to_cpu(IB_LID_PERMISSIVE))
1496                 props->grh_required = true;
1497
1498         return 0;
1499 }
1500
1501 static int modify_device(struct ib_device *device,
1502                          int device_modify_mask,
1503                          struct ib_device_modify *device_modify)
1504 {
1505         struct hfi1_devdata *dd = dd_from_ibdev(device);
1506         unsigned i;
1507         int ret;
1508
1509         if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1510                                    IB_DEVICE_MODIFY_NODE_DESC)) {
1511                 ret = -EOPNOTSUPP;
1512                 goto bail;
1513         }
1514
1515         if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1516                 memcpy(device->node_desc, device_modify->node_desc,
1517                        IB_DEVICE_NODE_DESC_MAX);
1518                 for (i = 0; i < dd->num_pports; i++) {
1519                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1520
1521                         hfi1_node_desc_chg(ibp);
1522                 }
1523         }
1524
1525         if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1526                 ib_hfi1_sys_image_guid =
1527                         cpu_to_be64(device_modify->sys_image_guid);
1528                 for (i = 0; i < dd->num_pports; i++) {
1529                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1530
1531                         hfi1_sys_guid_chg(ibp);
1532                 }
1533         }
1534
1535         ret = 0;
1536
1537 bail:
1538         return ret;
1539 }
1540
1541 static int shut_down_port(struct rvt_dev_info *rdi, u8 port_num)
1542 {
1543         struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1544         struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1545         struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1546         int ret;
1547
1548         set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0,
1549                              OPA_LINKDOWN_REASON_UNKNOWN);
1550         ret = set_link_state(ppd, HLS_DN_DOWNDEF);
1551         return ret;
1552 }
1553
1554 static int hfi1_get_guid_be(struct rvt_dev_info *rdi, struct rvt_ibport *rvp,
1555                             int guid_index, __be64 *guid)
1556 {
1557         struct hfi1_ibport *ibp = container_of(rvp, struct hfi1_ibport, rvp);
1558
1559         if (guid_index >= HFI1_GUIDS_PER_PORT)
1560                 return -EINVAL;
1561
1562         *guid = get_sguid(ibp, guid_index);
1563         return 0;
1564 }
1565
1566 /*
1567  * convert ah port,sl to sc
1568  */
1569 u8 ah_to_sc(struct ib_device *ibdev, struct rdma_ah_attr *ah)
1570 {
1571         struct hfi1_ibport *ibp = to_iport(ibdev, rdma_ah_get_port_num(ah));
1572
1573         return ibp->sl_to_sc[rdma_ah_get_sl(ah)];
1574 }
1575
1576 static int hfi1_check_ah(struct ib_device *ibdev, struct rdma_ah_attr *ah_attr)
1577 {
1578         struct hfi1_ibport *ibp;
1579         struct hfi1_pportdata *ppd;
1580         struct hfi1_devdata *dd;
1581         u8 sc5;
1582
1583         if (hfi1_check_mcast(rdma_ah_get_dlid(ah_attr)) &&
1584             !(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH))
1585                 return -EINVAL;
1586
1587         /* test the mapping for validity */
1588         ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr));
1589         ppd = ppd_from_ibp(ibp);
1590         sc5 = ibp->sl_to_sc[rdma_ah_get_sl(ah_attr)];
1591         dd = dd_from_ppd(ppd);
1592         if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf)
1593                 return -EINVAL;
1594         return 0;
1595 }
1596
1597 static void hfi1_notify_new_ah(struct ib_device *ibdev,
1598                                struct rdma_ah_attr *ah_attr,
1599                                struct rvt_ah *ah)
1600 {
1601         struct hfi1_ibport *ibp;
1602         struct hfi1_pportdata *ppd;
1603         struct hfi1_devdata *dd;
1604         u8 sc5;
1605         struct rdma_ah_attr *attr = &ah->attr;
1606
1607         /*
1608          * Do not trust reading anything from rvt_ah at this point as it is not
1609          * done being setup. We can however modify things which we need to set.
1610          */
1611
1612         ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr));
1613         ppd = ppd_from_ibp(ibp);
1614         sc5 = ibp->sl_to_sc[rdma_ah_get_sl(&ah->attr)];
1615         hfi1_update_ah_attr(ibdev, attr);
1616         hfi1_make_opa_lid(attr);
1617         dd = dd_from_ppd(ppd);
1618         ah->vl = sc_to_vlt(dd, sc5);
1619         if (ah->vl < num_vls || ah->vl == 15)
1620                 ah->log_pmtu = ilog2(dd->vld[ah->vl].mtu);
1621 }
1622
1623 /**
1624  * hfi1_get_npkeys - return the size of the PKEY table for context 0
1625  * @dd: the hfi1_ib device
1626  */
1627 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd)
1628 {
1629         return ARRAY_SIZE(dd->pport[0].pkeys);
1630 }
1631
1632 static void init_ibport(struct hfi1_pportdata *ppd)
1633 {
1634         struct hfi1_ibport *ibp = &ppd->ibport_data;
1635         size_t sz = ARRAY_SIZE(ibp->sl_to_sc);
1636         int i;
1637
1638         for (i = 0; i < sz; i++) {
1639                 ibp->sl_to_sc[i] = i;
1640                 ibp->sc_to_sl[i] = i;
1641         }
1642
1643         for (i = 0; i < RVT_MAX_TRAP_LISTS ; i++)
1644                 INIT_LIST_HEAD(&ibp->rvp.trap_lists[i].list);
1645         timer_setup(&ibp->rvp.trap_timer, hfi1_handle_trap_timer, 0);
1646
1647         spin_lock_init(&ibp->rvp.lock);
1648         /* Set the prefix to the default value (see ch. 4.1.1) */
1649         ibp->rvp.gid_prefix = IB_DEFAULT_GID_PREFIX;
1650         ibp->rvp.sm_lid = 0;
1651         /*
1652          * Below should only set bits defined in OPA PortInfo.CapabilityMask
1653          * and PortInfo.CapabilityMask3
1654          */
1655         ibp->rvp.port_cap_flags = IB_PORT_AUTO_MIGR_SUP |
1656                 IB_PORT_CAP_MASK_NOTICE_SUP;
1657         ibp->rvp.port_cap3_flags = OPA_CAP_MASK3_IsSharedSpaceSupported;
1658         ibp->rvp.pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1659         ibp->rvp.pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1660         ibp->rvp.pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1661         ibp->rvp.pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1662         ibp->rvp.pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1663
1664         RCU_INIT_POINTER(ibp->rvp.qp[0], NULL);
1665         RCU_INIT_POINTER(ibp->rvp.qp[1], NULL);
1666 }
1667
1668 static void hfi1_get_dev_fw_str(struct ib_device *ibdev, char *str)
1669 {
1670         struct rvt_dev_info *rdi = ib_to_rvt(ibdev);
1671         struct hfi1_ibdev *dev = dev_from_rdi(rdi);
1672         u32 ver = dd_from_dev(dev)->dc8051_ver;
1673
1674         snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%u", dc8051_ver_maj(ver),
1675                  dc8051_ver_min(ver), dc8051_ver_patch(ver));
1676 }
1677
1678 static const char * const driver_cntr_names[] = {
1679         /* must be element 0*/
1680         "DRIVER_KernIntr",
1681         "DRIVER_ErrorIntr",
1682         "DRIVER_Tx_Errs",
1683         "DRIVER_Rcv_Errs",
1684         "DRIVER_HW_Errs",
1685         "DRIVER_NoPIOBufs",
1686         "DRIVER_CtxtsOpen",
1687         "DRIVER_RcvLen_Errs",
1688         "DRIVER_EgrBufFull",
1689         "DRIVER_EgrHdrFull"
1690 };
1691
1692 static DEFINE_MUTEX(cntr_names_lock); /* protects the *_cntr_names bufers */
1693 static const char **dev_cntr_names;
1694 static const char **port_cntr_names;
1695 static int num_driver_cntrs = ARRAY_SIZE(driver_cntr_names);
1696 static int num_dev_cntrs;
1697 static int num_port_cntrs;
1698 static int cntr_names_initialized;
1699
1700 /*
1701  * Convert a list of names separated by '\n' into an array of NULL terminated
1702  * strings. Optionally some entries can be reserved in the array to hold extra
1703  * external strings.
1704  */
1705 static int init_cntr_names(const char *names_in,
1706                            const size_t names_len,
1707                            int num_extra_names,
1708                            int *num_cntrs,
1709                            const char ***cntr_names)
1710 {
1711         char *names_out, *p, **q;
1712         int i, n;
1713
1714         n = 0;
1715         for (i = 0; i < names_len; i++)
1716                 if (names_in[i] == '\n')
1717                         n++;
1718
1719         names_out = kmalloc((n + num_extra_names) * sizeof(char *) + names_len,
1720                             GFP_KERNEL);
1721         if (!names_out) {
1722                 *num_cntrs = 0;
1723                 *cntr_names = NULL;
1724                 return -ENOMEM;
1725         }
1726
1727         p = names_out + (n + num_extra_names) * sizeof(char *);
1728         memcpy(p, names_in, names_len);
1729
1730         q = (char **)names_out;
1731         for (i = 0; i < n; i++) {
1732                 q[i] = p;
1733                 p = strchr(p, '\n');
1734                 *p++ = '\0';
1735         }
1736
1737         *num_cntrs = n;
1738         *cntr_names = (const char **)names_out;
1739         return 0;
1740 }
1741
1742 static struct rdma_hw_stats *alloc_hw_stats(struct ib_device *ibdev,
1743                                             u8 port_num)
1744 {
1745         int i, err;
1746
1747         mutex_lock(&cntr_names_lock);
1748         if (!cntr_names_initialized) {
1749                 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1750
1751                 err = init_cntr_names(dd->cntrnames,
1752                                       dd->cntrnameslen,
1753                                       num_driver_cntrs,
1754                                       &num_dev_cntrs,
1755                                       &dev_cntr_names);
1756                 if (err) {
1757                         mutex_unlock(&cntr_names_lock);
1758                         return NULL;
1759                 }
1760
1761                 for (i = 0; i < num_driver_cntrs; i++)
1762                         dev_cntr_names[num_dev_cntrs + i] =
1763                                 driver_cntr_names[i];
1764
1765                 err = init_cntr_names(dd->portcntrnames,
1766                                       dd->portcntrnameslen,
1767                                       0,
1768                                       &num_port_cntrs,
1769                                       &port_cntr_names);
1770                 if (err) {
1771                         kfree(dev_cntr_names);
1772                         dev_cntr_names = NULL;
1773                         mutex_unlock(&cntr_names_lock);
1774                         return NULL;
1775                 }
1776                 cntr_names_initialized = 1;
1777         }
1778         mutex_unlock(&cntr_names_lock);
1779
1780         if (!port_num)
1781                 return rdma_alloc_hw_stats_struct(
1782                                 dev_cntr_names,
1783                                 num_dev_cntrs + num_driver_cntrs,
1784                                 RDMA_HW_STATS_DEFAULT_LIFESPAN);
1785         else
1786                 return rdma_alloc_hw_stats_struct(
1787                                 port_cntr_names,
1788                                 num_port_cntrs,
1789                                 RDMA_HW_STATS_DEFAULT_LIFESPAN);
1790 }
1791
1792 static u64 hfi1_sps_ints(void)
1793 {
1794         unsigned long flags;
1795         struct hfi1_devdata *dd;
1796         u64 sps_ints = 0;
1797
1798         spin_lock_irqsave(&hfi1_devs_lock, flags);
1799         list_for_each_entry(dd, &hfi1_dev_list, list) {
1800                 sps_ints += get_all_cpu_total(dd->int_counter);
1801         }
1802         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
1803         return sps_ints;
1804 }
1805
1806 static int get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats,
1807                         u8 port, int index)
1808 {
1809         u64 *values;
1810         int count;
1811
1812         if (!port) {
1813                 u64 *stats = (u64 *)&hfi1_stats;
1814                 int i;
1815
1816                 hfi1_read_cntrs(dd_from_ibdev(ibdev), NULL, &values);
1817                 values[num_dev_cntrs] = hfi1_sps_ints();
1818                 for (i = 1; i < num_driver_cntrs; i++)
1819                         values[num_dev_cntrs + i] = stats[i];
1820                 count = num_dev_cntrs + num_driver_cntrs;
1821         } else {
1822                 struct hfi1_ibport *ibp = to_iport(ibdev, port);
1823
1824                 hfi1_read_portcntrs(ppd_from_ibp(ibp), NULL, &values);
1825                 count = num_port_cntrs;
1826         }
1827
1828         memcpy(stats->value, values, count * sizeof(u64));
1829         return count;
1830 }
1831
1832 /**
1833  * hfi1_register_ib_device - register our device with the infiniband core
1834  * @dd: the device data structure
1835  * Return 0 if successful, errno if unsuccessful.
1836  */
1837 int hfi1_register_ib_device(struct hfi1_devdata *dd)
1838 {
1839         struct hfi1_ibdev *dev = &dd->verbs_dev;
1840         struct ib_device *ibdev = &dev->rdi.ibdev;
1841         struct hfi1_pportdata *ppd = dd->pport;
1842         struct hfi1_ibport *ibp = &ppd->ibport_data;
1843         unsigned i;
1844         int ret;
1845
1846         for (i = 0; i < dd->num_pports; i++)
1847                 init_ibport(ppd + i);
1848
1849         /* Only need to initialize non-zero fields. */
1850
1851         timer_setup(&dev->mem_timer, mem_timer, 0);
1852
1853         seqlock_init(&dev->iowait_lock);
1854         seqlock_init(&dev->txwait_lock);
1855         INIT_LIST_HEAD(&dev->txwait);
1856         INIT_LIST_HEAD(&dev->memwait);
1857
1858         ret = verbs_txreq_init(dev);
1859         if (ret)
1860                 goto err_verbs_txreq;
1861
1862         /* Use first-port GUID as node guid */
1863         ibdev->node_guid = get_sguid(ibp, HFI1_PORT_GUID_INDEX);
1864
1865         /*
1866          * The system image GUID is supposed to be the same for all
1867          * HFIs in a single system but since there can be other
1868          * device types in the system, we can't be sure this is unique.
1869          */
1870         if (!ib_hfi1_sys_image_guid)
1871                 ib_hfi1_sys_image_guid = ibdev->node_guid;
1872         ibdev->owner = THIS_MODULE;
1873         ibdev->phys_port_cnt = dd->num_pports;
1874         ibdev->dev.parent = &dd->pcidev->dev;
1875         ibdev->modify_device = modify_device;
1876         ibdev->alloc_hw_stats = alloc_hw_stats;
1877         ibdev->get_hw_stats = get_hw_stats;
1878         ibdev->alloc_rdma_netdev = hfi1_vnic_alloc_rn;
1879
1880         /* keep process mad in the driver */
1881         ibdev->process_mad = hfi1_process_mad;
1882         ibdev->get_dev_fw_str = hfi1_get_dev_fw_str;
1883
1884         strncpy(ibdev->node_desc, init_utsname()->nodename,
1885                 sizeof(ibdev->node_desc));
1886
1887         /*
1888          * Fill in rvt info object.
1889          */
1890         dd->verbs_dev.rdi.driver_f.port_callback = hfi1_create_port_files;
1891         dd->verbs_dev.rdi.driver_f.get_pci_dev = get_pci_dev;
1892         dd->verbs_dev.rdi.driver_f.check_ah = hfi1_check_ah;
1893         dd->verbs_dev.rdi.driver_f.notify_new_ah = hfi1_notify_new_ah;
1894         dd->verbs_dev.rdi.driver_f.get_guid_be = hfi1_get_guid_be;
1895         dd->verbs_dev.rdi.driver_f.query_port_state = query_port;
1896         dd->verbs_dev.rdi.driver_f.shut_down_port = shut_down_port;
1897         dd->verbs_dev.rdi.driver_f.cap_mask_chg = hfi1_cap_mask_chg;
1898         /*
1899          * Fill in rvt info device attributes.
1900          */
1901         hfi1_fill_device_attr(dd);
1902
1903         /* queue pair */
1904         dd->verbs_dev.rdi.dparms.qp_table_size = hfi1_qp_table_size;
1905         dd->verbs_dev.rdi.dparms.qpn_start = 0;
1906         dd->verbs_dev.rdi.dparms.qpn_inc = 1;
1907         dd->verbs_dev.rdi.dparms.qos_shift = dd->qos_shift;
1908         dd->verbs_dev.rdi.dparms.qpn_res_start = kdeth_qp << 16;
1909         dd->verbs_dev.rdi.dparms.qpn_res_end =
1910         dd->verbs_dev.rdi.dparms.qpn_res_start + 65535;
1911         dd->verbs_dev.rdi.dparms.max_rdma_atomic = HFI1_MAX_RDMA_ATOMIC;
1912         dd->verbs_dev.rdi.dparms.psn_mask = PSN_MASK;
1913         dd->verbs_dev.rdi.dparms.psn_shift = PSN_SHIFT;
1914         dd->verbs_dev.rdi.dparms.psn_modify_mask = PSN_MODIFY_MASK;
1915         dd->verbs_dev.rdi.dparms.core_cap_flags = RDMA_CORE_PORT_INTEL_OPA |
1916                                                 RDMA_CORE_CAP_OPA_AH;
1917         dd->verbs_dev.rdi.dparms.max_mad_size = OPA_MGMT_MAD_SIZE;
1918
1919         dd->verbs_dev.rdi.driver_f.qp_priv_alloc = qp_priv_alloc;
1920         dd->verbs_dev.rdi.driver_f.qp_priv_free = qp_priv_free;
1921         dd->verbs_dev.rdi.driver_f.free_all_qps = free_all_qps;
1922         dd->verbs_dev.rdi.driver_f.notify_qp_reset = notify_qp_reset;
1923         dd->verbs_dev.rdi.driver_f.do_send = hfi1_do_send_from_rvt;
1924         dd->verbs_dev.rdi.driver_f.schedule_send = hfi1_schedule_send;
1925         dd->verbs_dev.rdi.driver_f.schedule_send_no_lock = _hfi1_schedule_send;
1926         dd->verbs_dev.rdi.driver_f.get_pmtu_from_attr = get_pmtu_from_attr;
1927         dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1928         dd->verbs_dev.rdi.driver_f.flush_qp_waiters = flush_qp_waiters;
1929         dd->verbs_dev.rdi.driver_f.stop_send_queue = stop_send_queue;
1930         dd->verbs_dev.rdi.driver_f.quiesce_qp = quiesce_qp;
1931         dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1932         dd->verbs_dev.rdi.driver_f.mtu_from_qp = mtu_from_qp;
1933         dd->verbs_dev.rdi.driver_f.mtu_to_path_mtu = mtu_to_path_mtu;
1934         dd->verbs_dev.rdi.driver_f.check_modify_qp = hfi1_check_modify_qp;
1935         dd->verbs_dev.rdi.driver_f.modify_qp = hfi1_modify_qp;
1936         dd->verbs_dev.rdi.driver_f.notify_restart_rc = hfi1_restart_rc;
1937         dd->verbs_dev.rdi.driver_f.check_send_wqe = hfi1_check_send_wqe;
1938         dd->verbs_dev.rdi.driver_f.comp_vect_cpu_lookup =
1939                                                 hfi1_comp_vect_mappings_lookup;
1940
1941         /* completeion queue */
1942         dd->verbs_dev.rdi.ibdev.num_comp_vectors = dd->comp_vect_possible_cpus;
1943         dd->verbs_dev.rdi.dparms.node = dd->node;
1944
1945         /* misc settings */
1946         dd->verbs_dev.rdi.flags = 0; /* Let rdmavt handle it all */
1947         dd->verbs_dev.rdi.dparms.lkey_table_size = hfi1_lkey_table_size;
1948         dd->verbs_dev.rdi.dparms.nports = dd->num_pports;
1949         dd->verbs_dev.rdi.dparms.npkeys = hfi1_get_npkeys(dd);
1950
1951         /* post send table */
1952         dd->verbs_dev.rdi.post_parms = hfi1_post_parms;
1953
1954         ppd = dd->pport;
1955         for (i = 0; i < dd->num_pports; i++, ppd++)
1956                 rvt_init_port(&dd->verbs_dev.rdi,
1957                               &ppd->ibport_data.rvp,
1958                               i,
1959                               ppd->pkeys);
1960
1961         ret = rvt_register_device(&dd->verbs_dev.rdi, RDMA_DRIVER_HFI1);
1962         if (ret)
1963                 goto err_verbs_txreq;
1964
1965         ret = hfi1_verbs_register_sysfs(dd);
1966         if (ret)
1967                 goto err_class;
1968
1969         return ret;
1970
1971 err_class:
1972         rvt_unregister_device(&dd->verbs_dev.rdi);
1973 err_verbs_txreq:
1974         verbs_txreq_exit(dev);
1975         dd_dev_err(dd, "cannot register verbs: %d!\n", -ret);
1976         return ret;
1977 }
1978
1979 void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
1980 {
1981         struct hfi1_ibdev *dev = &dd->verbs_dev;
1982
1983         hfi1_verbs_unregister_sysfs(dd);
1984
1985         rvt_unregister_device(&dd->verbs_dev.rdi);
1986
1987         if (!list_empty(&dev->txwait))
1988                 dd_dev_err(dd, "txwait list not empty!\n");
1989         if (!list_empty(&dev->memwait))
1990                 dd_dev_err(dd, "memwait list not empty!\n");
1991
1992         del_timer_sync(&dev->mem_timer);
1993         verbs_txreq_exit(dev);
1994
1995         mutex_lock(&cntr_names_lock);
1996         kfree(dev_cntr_names);
1997         kfree(port_cntr_names);
1998         dev_cntr_names = NULL;
1999         port_cntr_names = NULL;
2000         cntr_names_initialized = 0;
2001         mutex_unlock(&cntr_names_lock);
2002 }
2003
2004 void hfi1_cnp_rcv(struct hfi1_packet *packet)
2005 {
2006         struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd);
2007         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2008         struct ib_header *hdr = packet->hdr;
2009         struct rvt_qp *qp = packet->qp;
2010         u32 lqpn, rqpn = 0;
2011         u16 rlid = 0;
2012         u8 sl, sc5, svc_type;
2013
2014         switch (packet->qp->ibqp.qp_type) {
2015         case IB_QPT_UC:
2016                 rlid = rdma_ah_get_dlid(&qp->remote_ah_attr);
2017                 rqpn = qp->remote_qpn;
2018                 svc_type = IB_CC_SVCTYPE_UC;
2019                 break;
2020         case IB_QPT_RC:
2021                 rlid = rdma_ah_get_dlid(&qp->remote_ah_attr);
2022                 rqpn = qp->remote_qpn;
2023                 svc_type = IB_CC_SVCTYPE_RC;
2024                 break;
2025         case IB_QPT_SMI:
2026         case IB_QPT_GSI:
2027         case IB_QPT_UD:
2028                 svc_type = IB_CC_SVCTYPE_UD;
2029                 break;
2030         default:
2031                 ibp->rvp.n_pkt_drops++;
2032                 return;
2033         }
2034
2035         sc5 = hfi1_9B_get_sc5(hdr, packet->rhf);
2036         sl = ibp->sc_to_sl[sc5];
2037         lqpn = qp->ibqp.qp_num;
2038
2039         process_becn(ppd, sl, rlid, lqpn, rqpn, svc_type);
2040 }