drivers/infiniband/hw/hfi1/verbs.c

   1 /*
   2  * Copyright(c) 2015 - 2018 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 #include <rdma/ib_mad.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <linux/io.h>
  51 #include <linux/module.h>
  52 #include <linux/utsname.h>
  53 #include <linux/rculist.h>
  54 #include <linux/mm.h>
  55 #include <linux/vmalloc.h>
  56 #include <rdma/opa_addr.h>
  57
  58 #include "hfi.h"
  59 #include "common.h"
  60 #include "device.h"
  61 #include "trace.h"
  62 #include "qp.h"
  63 #include "verbs_txreq.h"
  64 #include "debugfs.h"
  65 #include "vnic.h"
  66 #include "fault.h"
  67 #include "affinity.h"
  68
  69 static unsigned int hfi1_lkey_table_size = 16;
  70 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint,
  71                    S_IRUGO);
  72 MODULE_PARM_DESC(lkey_table_size,
  73                  "LKEY table size in bits (2^n, 1 <= n <= 23)");
  74
  75 static unsigned int hfi1_max_pds = 0xFFFF;
  76 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO);
  77 MODULE_PARM_DESC(max_pds,
  78                  "Maximum number of protection domains to support");
  79
  80 static unsigned int hfi1_max_ahs = 0xFFFF;
  81 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO);
  82 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
  83
  84 unsigned int hfi1_max_cqes = 0x2FFFFF;
  85 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO);
  86 MODULE_PARM_DESC(max_cqes,
  87                  "Maximum number of completion queue entries to support");
  88
  89 unsigned int hfi1_max_cqs = 0x1FFFF;
  90 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO);
  91 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
  92
  93 unsigned int hfi1_max_qp_wrs = 0x3FFF;
  94 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO);
  95 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
  96
  97 unsigned int hfi1_max_qps = 32768;
  98 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO);
  99 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
 100
 101 unsigned int hfi1_max_sges = 0x60;
 102 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO);
 103 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
 104
 105 unsigned int hfi1_max_mcast_grps = 16384;
 106 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO);
 107 MODULE_PARM_DESC(max_mcast_grps,
 108                  "Maximum number of multicast groups to support");
 109
 110 unsigned int hfi1_max_mcast_qp_attached = 16;
 111 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached,
 112                    uint, S_IRUGO);
 113 MODULE_PARM_DESC(max_mcast_qp_attached,
 114                  "Maximum number of attached QPs to support");
 115
 116 unsigned int hfi1_max_srqs = 1024;
 117 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO);
 118 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
 119
 120 unsigned int hfi1_max_srq_sges = 128;
 121 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO);
 122 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
 123
 124 unsigned int hfi1_max_srq_wrs = 0x1FFFF;
 125 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO);
 126 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
 127
 128 unsigned short piothreshold = 256;
 129 module_param(piothreshold, ushort, S_IRUGO);
 130 MODULE_PARM_DESC(piothreshold, "size used to determine sdma vs. pio");
 131
 132 #define COPY_CACHELESS 1
 133 #define COPY_ADAPTIVE  2
 134 static unsigned int sge_copy_mode;
 135 module_param(sge_copy_mode, uint, S_IRUGO);
 136 MODULE_PARM_DESC(sge_copy_mode,
 137                  "Verbs copy mode: 0 use memcpy, 1 use cacheless copy, 2 adapt based on WSS");
 138
 139 static void verbs_sdma_complete(
 140         struct sdma_txreq *cookie,
 141         int status);
 142
 143 static int pio_wait(struct rvt_qp *qp,
 144                     struct send_context *sc,
 145                     struct hfi1_pkt_state *ps,
 146                     u32 flag);
 147
 148 /* Length of buffer to create verbs txreq cache name */
 149 #define TXREQ_NAME_LEN 24
 150
 151 /* 16B trailing buffer */
 152 static const u8 trail_buf[MAX_16B_PADDING];
 153
 154 static uint wss_threshold;
 155 module_param(wss_threshold, uint, S_IRUGO);
 156 MODULE_PARM_DESC(wss_threshold, "Percentage (1-100) of LLC to use as a threshold for a cacheless copy");
 157 static uint wss_clean_period = 256;
 158 module_param(wss_clean_period, uint, S_IRUGO);
 159 MODULE_PARM_DESC(wss_clean_period, "Count of verbs copies before an entry in the page copy table is cleaned");
 160
 161 /* memory working set size */
 162 struct hfi1_wss {
 163         unsigned long *entries;
 164         atomic_t total_count;
 165         atomic_t clean_counter;
 166         atomic_t clean_entry;
 167
 168         int threshold;
 169         int num_entries;
 170         long pages_mask;
 171 };
 172
 173 static struct hfi1_wss wss;
 174
 175 int hfi1_wss_init(void)
 176 {
 177         long llc_size;
 178         long llc_bits;
 179         long table_size;
 180         long table_bits;
 181
 182         /* check for a valid percent range - default to 80 if none or invalid */
 183         if (wss_threshold < 1 || wss_threshold > 100)
 184                 wss_threshold = 80;
 185         /* reject a wildly large period */
 186         if (wss_clean_period > 1000000)
 187                 wss_clean_period = 256;
 188         /* reject a zero period */
 189         if (wss_clean_period == 0)
 190                 wss_clean_period = 1;
 191
 192         /*
 193          * Calculate the table size - the next power of 2 larger than the
 194          * LLC size.  LLC size is in KiB.
 195          */
 196         llc_size = wss_llc_size() * 1024;
 197         table_size = roundup_pow_of_two(llc_size);
 198
 199         /* one bit per page in rounded up table */
 200         llc_bits = llc_size / PAGE_SIZE;
 201         table_bits = table_size / PAGE_SIZE;
 202         wss.pages_mask = table_bits - 1;
 203         wss.num_entries = table_bits / BITS_PER_LONG;
 204
 205         wss.threshold = (llc_bits * wss_threshold) / 100;
 206         if (wss.threshold == 0)
 207                 wss.threshold = 1;
 208
 209         atomic_set(&wss.clean_counter, wss_clean_period);
 210
 211         wss.entries = kcalloc(wss.num_entries, sizeof(*wss.entries),
 212                               GFP_KERNEL);
 213         if (!wss.entries) {
 214                 hfi1_wss_exit();
 215                 return -ENOMEM;
 216         }
 217
 218         return 0;
 219 }
 220
 221 void hfi1_wss_exit(void)
 222 {
 223         /* coded to handle partially initialized and repeat callers */
 224         kfree(wss.entries);
 225         wss.entries = NULL;
 226 }
 227
 228 /*
 229  * Advance the clean counter.  When the clean period has expired,
 230  * clean an entry.
 231  *
 232  * This is implemented in atomics to avoid locking.  Because multiple
 233  * variables are involved, it can be racy which can lead to slightly
 234  * inaccurate information.  Since this is only a heuristic, this is
 235  * OK.  Any innaccuracies will clean themselves out as the counter
 236  * advances.  That said, it is unlikely the entry clean operation will
 237  * race - the next possible racer will not start until the next clean
 238  * period.
 239  *
 240  * The clean counter is implemented as a decrement to zero.  When zero
 241  * is reached an entry is cleaned.
 242  */
 243 static void wss_advance_clean_counter(void)
 244 {
 245         int entry;
 246         int weight;
 247         unsigned long bits;
 248
 249         /* become the cleaner if we decrement the counter to zero */
 250         if (atomic_dec_and_test(&wss.clean_counter)) {
 251                 /*
 252                  * Set, not add, the clean period.  This avoids an issue
 253                  * where the counter could decrement below the clean period.
 254                  * Doing a set can result in lost decrements, slowing the
 255                  * clean advance.  Since this a heuristic, this possible
 256                  * slowdown is OK.
 257                  *
 258                  * An alternative is to loop, advancing the counter by a
 259                  * clean period until the result is > 0. However, this could
 260                  * lead to several threads keeping another in the clean loop.
 261                  * This could be mitigated by limiting the number of times
 262                  * we stay in the loop.
 263                  */
 264                 atomic_set(&wss.clean_counter, wss_clean_period);
 265
 266                 /*
 267                  * Uniquely grab the entry to clean and move to next.
 268                  * The current entry is always the lower bits of
 269                  * wss.clean_entry.  The table size, wss.num_entries,
 270                  * is always a power-of-2.
 271                  */
 272                 entry = (atomic_inc_return(&wss.clean_entry) - 1)
 273                         & (wss.num_entries - 1);
 274
 275                 /* clear the entry and count the bits */
 276                 bits = xchg(&wss.entries[entry], 0);
 277                 weight = hweight64((u64)bits);
 278                 /* only adjust the contended total count if needed */
 279                 if (weight)
 280                         atomic_sub(weight, &wss.total_count);
 281         }
 282 }
 283
 284 /*
 285  * Insert the given address into the working set array.
 286  */
 287 static void wss_insert(void *address)
 288 {
 289         u32 page = ((unsigned long)address >> PAGE_SHIFT) & wss.pages_mask;
 290         u32 entry = page / BITS_PER_LONG; /* assumes this ends up a shift */
 291         u32 nr = page & (BITS_PER_LONG - 1);
 292
 293         if (!test_and_set_bit(nr, &wss.entries[entry]))
 294                 atomic_inc(&wss.total_count);
 295
 296         wss_advance_clean_counter();
 297 }
 298
 299 /*
 300  * Is the working set larger than the threshold?
 301  */
 302 static inline bool wss_exceeds_threshold(void)
 303 {
 304         return atomic_read(&wss.total_count) >= wss.threshold;
 305 }
 306
 307 /*
 308  * Translate ib_wr_opcode into ib_wc_opcode.
 309  */
 310 const enum ib_wc_opcode ib_hfi1_wc_opcode[] = {
 311         [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
 312         [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
 313         [IB_WR_SEND] = IB_WC_SEND,
 314         [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
 315         [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
 316         [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
 317         [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD,
 318         [IB_WR_SEND_WITH_INV] = IB_WC_SEND,
 319         [IB_WR_LOCAL_INV] = IB_WC_LOCAL_INV,
 320         [IB_WR_REG_MR] = IB_WC_REG_MR
 321 };
 322
 323 /*
 324  * Length of header by opcode, 0 --> not supported
 325  */
 326 const u8 hdr_len_by_opcode[256] = {
 327         /* RC */
 328         [IB_OPCODE_RC_SEND_FIRST]                     = 12 + 8,
 329         [IB_OPCODE_RC_SEND_MIDDLE]                    = 12 + 8,
 330         [IB_OPCODE_RC_SEND_LAST]                      = 12 + 8,
 331         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 332         [IB_OPCODE_RC_SEND_ONLY]                      = 12 + 8,
 333         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 334         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 335         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 336         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = 12 + 8,
 337         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 338         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 339         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 340         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = 12 + 8 + 16,
 341         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = 12 + 8 + 4,
 342         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = 12 + 8,
 343         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = 12 + 8 + 4,
 344         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = 12 + 8 + 4,
 345         [IB_OPCODE_RC_ACKNOWLEDGE]                    = 12 + 8 + 4,
 346         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = 12 + 8 + 4 + 8,
 347         [IB_OPCODE_RC_COMPARE_SWAP]                   = 12 + 8 + 28,
 348         [IB_OPCODE_RC_FETCH_ADD]                      = 12 + 8 + 28,
 349         [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE]      = 12 + 8 + 4,
 350         [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE]      = 12 + 8 + 4,
 351         /* UC */
 352         [IB_OPCODE_UC_SEND_FIRST]                     = 12 + 8,
 353         [IB_OPCODE_UC_SEND_MIDDLE]                    = 12 + 8,
 354         [IB_OPCODE_UC_SEND_LAST]                      = 12 + 8,
 355         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 356         [IB_OPCODE_UC_SEND_ONLY]                      = 12 + 8,
 357         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 358         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 359         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 360         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = 12 + 8,
 361         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 362         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 363         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 364         /* UD */
 365         [IB_OPCODE_UD_SEND_ONLY]                      = 12 + 8 + 8,
 366         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 12
 367 };
 368
 369 static const opcode_handler opcode_handler_tbl[256] = {
 370         /* RC */
 371         [IB_OPCODE_RC_SEND_FIRST]                     = &hfi1_rc_rcv,
 372         [IB_OPCODE_RC_SEND_MIDDLE]                    = &hfi1_rc_rcv,
 373         [IB_OPCODE_RC_SEND_LAST]                      = &hfi1_rc_rcv,
 374         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 375         [IB_OPCODE_RC_SEND_ONLY]                      = &hfi1_rc_rcv,
 376         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 377         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = &hfi1_rc_rcv,
 378         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = &hfi1_rc_rcv,
 379         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = &hfi1_rc_rcv,
 380         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 381         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = &hfi1_rc_rcv,
 382         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 383         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = &hfi1_rc_rcv,
 384         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = &hfi1_rc_rcv,
 385         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = &hfi1_rc_rcv,
 386         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = &hfi1_rc_rcv,
 387         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = &hfi1_rc_rcv,
 388         [IB_OPCODE_RC_ACKNOWLEDGE]                    = &hfi1_rc_rcv,
 389         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = &hfi1_rc_rcv,
 390         [IB_OPCODE_RC_COMPARE_SWAP]                   = &hfi1_rc_rcv,
 391         [IB_OPCODE_RC_FETCH_ADD]                      = &hfi1_rc_rcv,
 392         [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE]      = &hfi1_rc_rcv,
 393         [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE]      = &hfi1_rc_rcv,
 394         /* UC */
 395         [IB_OPCODE_UC_SEND_FIRST]                     = &hfi1_uc_rcv,
 396         [IB_OPCODE_UC_SEND_MIDDLE]                    = &hfi1_uc_rcv,
 397         [IB_OPCODE_UC_SEND_LAST]                      = &hfi1_uc_rcv,
 398         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 399         [IB_OPCODE_UC_SEND_ONLY]                      = &hfi1_uc_rcv,
 400         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 401         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = &hfi1_uc_rcv,
 402         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = &hfi1_uc_rcv,
 403         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = &hfi1_uc_rcv,
 404         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 405         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = &hfi1_uc_rcv,
 406         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 407         /* UD */
 408         [IB_OPCODE_UD_SEND_ONLY]                      = &hfi1_ud_rcv,
 409         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_ud_rcv,
 410         /* CNP */
 411         [IB_OPCODE_CNP]                               = &hfi1_cnp_rcv
 412 };
 413
 414 #define OPMASK 0x1f
 415
 416 static const u32 pio_opmask[BIT(3)] = {
 417         /* RC */
 418         [IB_OPCODE_RC >> 5] =
 419                 BIT(RC_OP(SEND_ONLY) & OPMASK) |
 420                 BIT(RC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
 421                 BIT(RC_OP(RDMA_WRITE_ONLY) & OPMASK) |
 422                 BIT(RC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK) |
 423                 BIT(RC_OP(RDMA_READ_REQUEST) & OPMASK) |
 424                 BIT(RC_OP(ACKNOWLEDGE) & OPMASK) |
 425                 BIT(RC_OP(ATOMIC_ACKNOWLEDGE) & OPMASK) |
 426                 BIT(RC_OP(COMPARE_SWAP) & OPMASK) |
 427                 BIT(RC_OP(FETCH_ADD) & OPMASK),
 428         /* UC */
 429         [IB_OPCODE_UC >> 5] =
 430                 BIT(UC_OP(SEND_ONLY) & OPMASK) |
 431                 BIT(UC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
 432                 BIT(UC_OP(RDMA_WRITE_ONLY) & OPMASK) |
 433                 BIT(UC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK),
 434 };
 435
 436 /*
 437  * System image GUID.
 438  */
 439 __be64 ib_hfi1_sys_image_guid;
 440
 441 /**
 442  * hfi1_copy_sge - copy data to SGE memory
 443  * @ss: the SGE state
 444  * @data: the data to copy
 445  * @length: the length of the data
 446  * @release: boolean to release MR
 447  * @copy_last: do a separate copy of the last 8 bytes
 448  */
 449 void hfi1_copy_sge(
 450         struct rvt_sge_state *ss,
 451         void *data, u32 length,
 452         bool release,
 453         bool copy_last)
 454 {
 455         struct rvt_sge *sge = &ss->sge;
 456         int i;
 457         bool in_last = false;
 458         bool cacheless_copy = false;
 459
 460         if (sge_copy_mode == COPY_CACHELESS) {
 461                 cacheless_copy = length >= PAGE_SIZE;
 462         } else if (sge_copy_mode == COPY_ADAPTIVE) {
 463                 if (length >= PAGE_SIZE) {
 464                         /*
 465                          * NOTE: this *assumes*:
 466                          * o The first vaddr is the dest.
 467                          * o If multiple pages, then vaddr is sequential.
 468                          */
 469                         wss_insert(sge->vaddr);
 470                         if (length >= (2 * PAGE_SIZE))
 471                                 wss_insert(sge->vaddr + PAGE_SIZE);
 472
 473                         cacheless_copy = wss_exceeds_threshold();
 474                 } else {
 475                         wss_advance_clean_counter();
 476                 }
 477         }
 478         if (copy_last) {
 479                 if (length > 8) {
 480                         length -= 8;
 481                 } else {
 482                         copy_last = false;
 483                         in_last = true;
 484                 }
 485         }
 486
 487 again:
 488         while (length) {
 489                 u32 len = rvt_get_sge_length(sge, length);
 490
 491                 WARN_ON_ONCE(len == 0);
 492                 if (unlikely(in_last)) {
 493                         /* enforce byte transfer ordering */
 494                         for (i = 0; i < len; i++)
 495                                 ((u8 *)sge->vaddr)[i] = ((u8 *)data)[i];
 496                 } else if (cacheless_copy) {
 497                         cacheless_memcpy(sge->vaddr, data, len);
 498                 } else {
 499                         memcpy(sge->vaddr, data, len);
 500                 }
 501                 rvt_update_sge(ss, len, release);
 502                 data += len;
 503                 length -= len;
 504         }
 505
 506         if (copy_last) {
 507                 copy_last = false;
 508                 in_last = true;
 509                 length = 8;
 510                 goto again;
 511         }
 512 }
 513
 514 /*
 515  * Make sure the QP is ready and able to accept the given opcode.
 516  */
 517 static inline opcode_handler qp_ok(struct hfi1_packet *packet)
 518 {
 519         if (!(ib_rvt_state_ops[packet->qp->state] & RVT_PROCESS_RECV_OK))
 520                 return NULL;
 521         if (((packet->opcode & RVT_OPCODE_QP_MASK) ==
 522              packet->qp->allowed_ops) ||
 523             (packet->opcode == IB_OPCODE_CNP))
 524                 return opcode_handler_tbl[packet->opcode];
 525
 526         return NULL;
 527 }
 528
 529 static u64 hfi1_fault_tx(struct rvt_qp *qp, u8 opcode, u64 pbc)
 530 {
 531 #ifdef CONFIG_FAULT_INJECTION
 532         if ((opcode & IB_OPCODE_MSP) == IB_OPCODE_MSP)
 533                 /*
 534                  * In order to drop non-IB traffic we
 535                  * set PbcInsertHrc to NONE (0x2).
 536                  * The packet will still be delivered
 537                  * to the receiving node but a
 538                  * KHdrHCRCErr (KDETH packet with a bad
 539                  * HCRC) will be triggered and the
 540                  * packet will not be delivered to the
 541                  * correct context.
 542                  */
 543                 pbc |= (u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT;
 544         else
 545                 /*
 546                  * In order to drop regular verbs
 547                  * traffic we set the PbcTestEbp
 548                  * flag. The packet will still be
 549                  * delivered to the receiving node but
 550                  * a 'late ebp error' will be
 551                  * triggered and will be dropped.
 552                  */
 553                 pbc |= PBC_TEST_EBP;
 554 #endif
 555         return pbc;
 556 }
 557
 558 static int hfi1_do_pkey_check(struct hfi1_packet *packet)
 559 {
 560         struct hfi1_ctxtdata *rcd = packet->rcd;
 561         struct hfi1_pportdata *ppd = rcd->ppd;
 562         struct hfi1_16b_header *hdr = packet->hdr;
 563         u16 pkey;
 564
 565         /* Pkey check needed only for bypass packets */
 566         if (packet->etype != RHF_RCV_TYPE_BYPASS)
 567                 return 0;
 568
 569         /* Perform pkey check */
 570         pkey = hfi1_16B_get_pkey(hdr);
 571         return ingress_pkey_check(ppd, pkey, packet->sc,
 572                                   packet->qp->s_pkey_index,
 573                                   packet->slid, true);
 574 }
 575
 576 static inline void hfi1_handle_packet(struct hfi1_packet *packet,
 577                                       bool is_mcast)
 578 {
 579         u32 qp_num;
 580         struct hfi1_ctxtdata *rcd = packet->rcd;
 581         struct hfi1_pportdata *ppd = rcd->ppd;
 582         struct hfi1_ibport *ibp = rcd_to_iport(rcd);
 583         struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi;
 584         opcode_handler packet_handler;
 585         unsigned long flags;
 586
 587         inc_opstats(packet->tlen, &rcd->opstats->stats[packet->opcode]);
 588
 589         if (unlikely(is_mcast)) {
 590                 struct rvt_mcast *mcast;
 591                 struct rvt_mcast_qp *p;
 592
 593                 if (!packet->grh)
 594                         goto drop;
 595                 mcast = rvt_mcast_find(&ibp->rvp,
 596                                        &packet->grh->dgid,
 597                                        opa_get_lid(packet->dlid, 9B));
 598                 if (!mcast)
 599                         goto drop;
 600                 list_for_each_entry_rcu(p, &mcast->qp_list, list) {
 601                         packet->qp = p->qp;
 602                         if (hfi1_do_pkey_check(packet))
 603                                 goto drop;
 604                         spin_lock_irqsave(&packet->qp->r_lock, flags);
 605                         packet_handler = qp_ok(packet);
 606                         if (likely(packet_handler))
 607                                 packet_handler(packet);
 608                         else
 609                                 ibp->rvp.n_pkt_drops++;
 610                         spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 611                 }
 612                 /*
 613                  * Notify rvt_multicast_detach() if it is waiting for us
 614                  * to finish.
 615                  */
 616                 if (atomic_dec_return(&mcast->refcount) <= 1)
 617                         wake_up(&mcast->wait);
 618         } else {
 619                 /* Get the destination QP number. */
 620                 if (packet->etype == RHF_RCV_TYPE_BYPASS &&
 621                     hfi1_16B_get_l4(packet->hdr) == OPA_16B_L4_FM)
 622                         qp_num = hfi1_16B_get_dest_qpn(packet->mgmt);
 623                 else
 624                         qp_num = ib_bth_get_qpn(packet->ohdr);
 625
 626                 rcu_read_lock();
 627                 packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
 628                 if (!packet->qp)
 629                         goto unlock_drop;
 630
 631                 if (hfi1_do_pkey_check(packet))
 632                         goto unlock_drop;
 633
 634                 spin_lock_irqsave(&packet->qp->r_lock, flags);
 635                 packet_handler = qp_ok(packet);
 636                 if (likely(packet_handler))
 637                         packet_handler(packet);
 638                 else
 639                         ibp->rvp.n_pkt_drops++;
 640                 spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 641                 rcu_read_unlock();
 642         }
 643         return;
 644 unlock_drop:
 645         rcu_read_unlock();
 646 drop:
 647         ibp->rvp.n_pkt_drops++;
 648 }
 649
 650 /**
 651  * hfi1_ib_rcv - process an incoming packet
 652  * @packet: data packet information
 653  *
 654  * This is called to process an incoming packet at interrupt level.
 655  */
 656 void hfi1_ib_rcv(struct hfi1_packet *packet)
 657 {
 658         struct hfi1_ctxtdata *rcd = packet->rcd;
 659
 660         trace_input_ibhdr(rcd->dd, packet, !!(rhf_dc_info(packet->rhf)));
 661         hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid));
 662 }
 663
 664 void hfi1_16B_rcv(struct hfi1_packet *packet)
 665 {
 666         struct hfi1_ctxtdata *rcd = packet->rcd;
 667
 668         trace_input_ibhdr(rcd->dd, packet, false);
 669         hfi1_handle_packet(packet, hfi1_check_mcast(packet->dlid));
 670 }
 671
 672 /*
 673  * This is called from a timer to check for QPs
 674  * which need kernel memory in order to send a packet.
 675  */
 676 static void mem_timer(struct timer_list *t)
 677 {
 678         struct hfi1_ibdev *dev = from_timer(dev, t, mem_timer);
 679         struct list_head *list = &dev->memwait;
 680         struct rvt_qp *qp = NULL;
 681         struct iowait *wait;
 682         unsigned long flags;
 683         struct hfi1_qp_priv *priv;
 684
 685         write_seqlock_irqsave(&dev->iowait_lock, flags);
 686         if (!list_empty(list)) {
 687                 wait = list_first_entry(list, struct iowait, list);
 688                 qp = iowait_to_qp(wait);
 689                 priv = qp->priv;
 690                 list_del_init(&priv->s_iowait.list);
 691                 priv->s_iowait.lock = NULL;
 692                 /* refcount held until actual wake up */
 693                 if (!list_empty(list))
 694                         mod_timer(&dev->mem_timer, jiffies + 1);
 695         }
 696         write_sequnlock_irqrestore(&dev->iowait_lock, flags);
 697
 698         if (qp)
 699                 hfi1_qp_wakeup(qp, RVT_S_WAIT_KMEM);
 700 }
 701
 702 /*
 703  * This is called with progress side lock held.
 704  */
 705 /* New API */
 706 static void verbs_sdma_complete(
 707         struct sdma_txreq *cookie,
 708         int status)
 709 {
 710         struct verbs_txreq *tx =
 711                 container_of(cookie, struct verbs_txreq, txreq);
 712         struct rvt_qp *qp = tx->qp;
 713
 714         spin_lock(&qp->s_lock);
 715         if (tx->wqe) {
 716                 hfi1_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
 717         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
 718                 struct hfi1_opa_header *hdr;
 719
 720                 hdr = &tx->phdr.hdr;
 721                 hfi1_rc_send_complete(qp, hdr);
 722         }
 723         spin_unlock(&qp->s_lock);
 724
 725         hfi1_put_txreq(tx);
 726 }
 727
 728 static int wait_kmem(struct hfi1_ibdev *dev,
 729                      struct rvt_qp *qp,
 730                      struct hfi1_pkt_state *ps)
 731 {
 732         struct hfi1_qp_priv *priv = qp->priv;
 733         unsigned long flags;
 734         int ret = 0;
 735
 736         spin_lock_irqsave(&qp->s_lock, flags);
 737         if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
 738                 write_seqlock(&dev->iowait_lock);
 739                 list_add_tail(&ps->s_txreq->txreq.list,
 740                               &priv->s_iowait.tx_head);
 741                 if (list_empty(&priv->s_iowait.list)) {
 742                         if (list_empty(&dev->memwait))
 743                                 mod_timer(&dev->mem_timer, jiffies + 1);
 744                         qp->s_flags |= RVT_S_WAIT_KMEM;
 745                         list_add_tail(&priv->s_iowait.list, &dev->memwait);
 746                         priv->s_iowait.lock = &dev->iowait_lock;
 747                         trace_hfi1_qpsleep(qp, RVT_S_WAIT_KMEM);
 748                         rvt_get_qp(qp);
 749                 }
 750                 write_sequnlock(&dev->iowait_lock);
 751                 qp->s_flags &= ~RVT_S_BUSY;
 752                 ret = -EBUSY;
 753         }
 754         spin_unlock_irqrestore(&qp->s_lock, flags);
 755
 756         return ret;
 757 }
 758
 759 /*
 760  * This routine calls txadds for each sg entry.
 761  *
 762  * Add failures will revert the sge cursor
 763  */
 764 static noinline int build_verbs_ulp_payload(
 765         struct sdma_engine *sde,
 766         u32 length,
 767         struct verbs_txreq *tx)
 768 {
 769         struct rvt_sge_state *ss = tx->ss;
 770         struct rvt_sge *sg_list = ss->sg_list;
 771         struct rvt_sge sge = ss->sge;
 772         u8 num_sge = ss->num_sge;
 773         u32 len;
 774         int ret = 0;
 775
 776         while (length) {
 777                 len = ss->sge.length;
 778                 if (len > length)
 779                         len = length;
 780                 if (len > ss->sge.sge_length)
 781                         len = ss->sge.sge_length;
 782                 WARN_ON_ONCE(len == 0);
 783                 ret = sdma_txadd_kvaddr(
 784                         sde->dd,
 785                         &tx->txreq,
 786                         ss->sge.vaddr,
 787                         len);
 788                 if (ret)
 789                         goto bail_txadd;
 790                 rvt_update_sge(ss, len, false);
 791                 length -= len;
 792         }
 793         return ret;
 794 bail_txadd:
 795         /* unwind cursor */
 796         ss->sge = sge;
 797         ss->num_sge = num_sge;
 798         ss->sg_list = sg_list;
 799         return ret;
 800 }
 801
 802 /**
 803  * update_tx_opstats - record stats by opcode
 804  * @qp; the qp
 805  * @ps: transmit packet state
 806  * @plen: the plen in dwords
 807  *
 808  * This is a routine to record the tx opstats after a
 809  * packet has been presented to the egress mechanism.
 810  */
 811 static void update_tx_opstats(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
 812                               u32 plen)
 813 {
 814 #ifdef CONFIG_DEBUG_FS
 815         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
 816         struct hfi1_opcode_stats_perctx *s = get_cpu_ptr(dd->tx_opstats);
 817
 818         inc_opstats(plen * 4, &s->stats[ps->opcode]);
 819         put_cpu_ptr(s);
 820 #endif
 821 }
 822
 823 /*
 824  * Build the number of DMA descriptors needed to send length bytes of data.
 825  *
 826  * NOTE: DMA mapping is held in the tx until completed in the ring or
 827  *       the tx desc is freed without having been submitted to the ring
 828  *
 829  * This routine ensures all the helper routine calls succeed.
 830  */
 831 /* New API */
 832 static int build_verbs_tx_desc(
 833         struct sdma_engine *sde,
 834         u32 length,
 835         struct verbs_txreq *tx,
 836         struct hfi1_ahg_info *ahg_info,
 837         u64 pbc)
 838 {
 839         int ret = 0;
 840         struct hfi1_sdma_header *phdr = &tx->phdr;
 841         u16 hdrbytes = (tx->hdr_dwords + sizeof(pbc) / 4) << 2;
 842         u8 extra_bytes = 0;
 843
 844         if (tx->phdr.hdr.hdr_type) {
 845                 /*
 846                  * hdrbytes accounts for PBC. Need to subtract 8 bytes
 847                  * before calculating padding.
 848                  */
 849                 extra_bytes = hfi1_get_16b_padding(hdrbytes - 8, length) +
 850                               (SIZE_OF_CRC << 2) + SIZE_OF_LT;
 851         }
 852         if (!ahg_info->ahgcount) {
 853                 ret = sdma_txinit_ahg(
 854                         &tx->txreq,
 855                         ahg_info->tx_flags,
 856                         hdrbytes + length +
 857                         extra_bytes,
 858                         ahg_info->ahgidx,
 859                         0,
 860                         NULL,
 861                         0,
 862                         verbs_sdma_complete);
 863                 if (ret)
 864                         goto bail_txadd;
 865                 phdr->pbc = cpu_to_le64(pbc);
 866                 ret = sdma_txadd_kvaddr(
 867                         sde->dd,
 868                         &tx->txreq,
 869                         phdr,
 870                         hdrbytes);
 871                 if (ret)
 872                         goto bail_txadd;
 873         } else {
 874                 ret = sdma_txinit_ahg(
 875                         &tx->txreq,
 876                         ahg_info->tx_flags,
 877                         length,
 878                         ahg_info->ahgidx,
 879                         ahg_info->ahgcount,
 880                         ahg_info->ahgdesc,
 881                         hdrbytes,
 882                         verbs_sdma_complete);
 883                 if (ret)
 884                         goto bail_txadd;
 885         }
 886         /* add the ulp payload - if any. tx->ss can be NULL for acks */
 887         if (tx->ss) {
 888                 ret = build_verbs_ulp_payload(sde, length, tx);
 889                 if (ret)
 890                         goto bail_txadd;
 891         }
 892
 893         /* add icrc, lt byte, and padding to flit */
 894         if (extra_bytes)
 895                 ret = sdma_txadd_kvaddr(sde->dd, &tx->txreq,
 896                                         (void *)trail_buf, extra_bytes);
 897
 898 bail_txadd:
 899         return ret;
 900 }
 901
 902 int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
 903                         u64 pbc)
 904 {
 905         struct hfi1_qp_priv *priv = qp->priv;
 906         struct hfi1_ahg_info *ahg_info = priv->s_ahg;
 907         u32 hdrwords = ps->s_txreq->hdr_dwords;
 908         u32 len = ps->s_txreq->s_cur_size;
 909         u32 plen;
 910         struct hfi1_ibdev *dev = ps->dev;
 911         struct hfi1_pportdata *ppd = ps->ppd;
 912         struct verbs_txreq *tx;
 913         u8 sc5 = priv->s_sc;
 914         int ret;
 915         u32 dwords;
 916
 917         if (ps->s_txreq->phdr.hdr.hdr_type) {
 918                 u8 extra_bytes = hfi1_get_16b_padding((hdrwords << 2), len);
 919
 920                 dwords = (len + extra_bytes + (SIZE_OF_CRC << 2) +
 921                           SIZE_OF_LT) >> 2;
 922         } else {
 923                 dwords = (len + 3) >> 2;
 924         }
 925         plen = hdrwords + dwords + sizeof(pbc) / 4;
 926
 927         tx = ps->s_txreq;
 928         if (!sdma_txreq_built(&tx->txreq)) {
 929                 if (likely(pbc == 0)) {
 930                         u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
 931
 932                         /* No vl15 here */
 933                         /* set PBC_DC_INFO bit (aka SC[4]) in pbc */
 934                         if (ps->s_txreq->phdr.hdr.hdr_type)
 935                                 pbc |= PBC_PACKET_BYPASS |
 936                                        PBC_INSERT_BYPASS_ICRC;
 937                         else
 938                                 pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT);
 939
 940                         if (unlikely(hfi1_dbg_should_fault_tx(qp, ps->opcode)))
 941                                 pbc = hfi1_fault_tx(qp, ps->opcode, pbc);
 942                         pbc = create_pbc(ppd,
 943                                          pbc,
 944                                          qp->srate_mbps,
 945                                          vl,
 946                                          plen);
 947                 }
 948                 tx->wqe = qp->s_wqe;
 949                 ret = build_verbs_tx_desc(tx->sde, len, tx, ahg_info, pbc);
 950                 if (unlikely(ret))
 951                         goto bail_build;
 952         }
 953         ret =  sdma_send_txreq(tx->sde, &priv->s_iowait, &tx->txreq,
 954                                ps->pkts_sent);
 955         if (unlikely(ret < 0)) {
 956                 if (ret == -ECOMM)
 957                         goto bail_ecomm;
 958                 return ret;
 959         }
 960
 961         update_tx_opstats(qp, ps, plen);
 962         trace_sdma_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
 963                                 &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5));
 964         return ret;
 965
 966 bail_ecomm:
 967         /* The current one got "sent" */
 968         return 0;
 969 bail_build:
 970         ret = wait_kmem(dev, qp, ps);
 971         if (!ret) {
 972                 /* free txreq - bad state */
 973                 hfi1_put_txreq(ps->s_txreq);
 974                 ps->s_txreq = NULL;
 975         }
 976         return ret;
 977 }
 978
 979 /*
 980  * If we are now in the error state, return zero to flush the
 981  * send work request.
 982  */
 983 static int pio_wait(struct rvt_qp *qp,
 984                     struct send_context *sc,
 985                     struct hfi1_pkt_state *ps,
 986                     u32 flag)
 987 {
 988         struct hfi1_qp_priv *priv = qp->priv;
 989         struct hfi1_devdata *dd = sc->dd;
 990         struct hfi1_ibdev *dev = &dd->verbs_dev;
 991         unsigned long flags;
 992         int ret = 0;
 993
 994         /*
 995          * Note that as soon as want_buffer() is called and
 996          * possibly before it returns, sc_piobufavail()
 997          * could be called. Therefore, put QP on the I/O wait list before
 998          * enabling the PIO avail interrupt.
 999          */
1000         spin_lock_irqsave(&qp->s_lock, flags);
1001         if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
1002                 write_seqlock(&dev->iowait_lock);
1003                 list_add_tail(&ps->s_txreq->txreq.list,
1004                               &priv->s_iowait.tx_head);
1005                 if (list_empty(&priv->s_iowait.list)) {
1006                         struct hfi1_ibdev *dev = &dd->verbs_dev;
1007                         int was_empty;
1008
1009                         dev->n_piowait += !!(flag & RVT_S_WAIT_PIO);
1010                         dev->n_piodrain += !!(flag & HFI1_S_WAIT_PIO_DRAIN);
1011                         qp->s_flags |= flag;
1012                         was_empty = list_empty(&sc->piowait);
1013                         iowait_queue(ps->pkts_sent, &priv->s_iowait,
1014                                      &sc->piowait);
1015                         priv->s_iowait.lock = &dev->iowait_lock;
1016                         trace_hfi1_qpsleep(qp, RVT_S_WAIT_PIO);
1017                         rvt_get_qp(qp);
1018                         /* counting: only call wantpiobuf_intr if first user */
1019                         if (was_empty)
1020                                 hfi1_sc_wantpiobuf_intr(sc, 1);
1021                 }
1022                 write_sequnlock(&dev->iowait_lock);
1023                 qp->s_flags &= ~RVT_S_BUSY;
1024                 ret = -EBUSY;
1025         }
1026         spin_unlock_irqrestore(&qp->s_lock, flags);
1027         return ret;
1028 }
1029
1030 static void verbs_pio_complete(void *arg, int code)
1031 {
1032         struct rvt_qp *qp = (struct rvt_qp *)arg;
1033         struct hfi1_qp_priv *priv = qp->priv;
1034
1035         if (iowait_pio_dec(&priv->s_iowait))
1036                 iowait_drain_wakeup(&priv->s_iowait);
1037 }
1038
1039 int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
1040                         u64 pbc)
1041 {
1042         struct hfi1_qp_priv *priv = qp->priv;
1043         u32 hdrwords = ps->s_txreq->hdr_dwords;
1044         struct rvt_sge_state *ss = ps->s_txreq->ss;
1045         u32 len = ps->s_txreq->s_cur_size;
1046         u32 dwords;
1047         u32 plen;
1048         struct hfi1_pportdata *ppd = ps->ppd;
1049         u32 *hdr;
1050         u8 sc5;
1051         unsigned long flags = 0;
1052         struct send_context *sc;
1053         struct pio_buf *pbuf;
1054         int wc_status = IB_WC_SUCCESS;
1055         int ret = 0;
1056         pio_release_cb cb = NULL;
1057         u8 extra_bytes = 0;
1058
1059         if (ps->s_txreq->phdr.hdr.hdr_type) {
1060                 u8 pad_size = hfi1_get_16b_padding((hdrwords << 2), len);
1061
1062                 extra_bytes = pad_size + (SIZE_OF_CRC << 2) + SIZE_OF_LT;
1063                 dwords = (len + extra_bytes) >> 2;
1064                 hdr = (u32 *)&ps->s_txreq->phdr.hdr.opah;
1065         } else {
1066                 dwords = (len + 3) >> 2;
1067                 hdr = (u32 *)&ps->s_txreq->phdr.hdr.ibh;
1068         }
1069         plen = hdrwords + dwords + sizeof(pbc) / 4;
1070
1071         /* only RC/UC use complete */
1072         switch (qp->ibqp.qp_type) {
1073         case IB_QPT_RC:
1074         case IB_QPT_UC:
1075                 cb = verbs_pio_complete;
1076                 break;
1077         default:
1078                 break;
1079         }
1080
1081         /* vl15 special case taken care of in ud.c */
1082         sc5 = priv->s_sc;
1083         sc = ps->s_txreq->psc;
1084
1085         if (likely(pbc == 0)) {
1086                 u8 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1087
1088                 /* set PBC_DC_INFO bit (aka SC[4]) in pbc */
1089                 if (ps->s_txreq->phdr.hdr.hdr_type)
1090                         pbc |= PBC_PACKET_BYPASS | PBC_INSERT_BYPASS_ICRC;
1091                 else
1092                         pbc |= (ib_is_sc5(sc5) << PBC_DC_INFO_SHIFT);
1093
1094                 if (unlikely(hfi1_dbg_should_fault_tx(qp, ps->opcode)))
1095                         pbc = hfi1_fault_tx(qp, ps->opcode, pbc);
1096                 pbc = create_pbc(ppd, pbc, qp->srate_mbps, vl, plen);
1097         }
1098         if (cb)
1099                 iowait_pio_inc(&priv->s_iowait);
1100         pbuf = sc_buffer_alloc(sc, plen, cb, qp);
1101         if (unlikely(!pbuf)) {
1102                 if (cb)
1103                         verbs_pio_complete(qp, 0);
1104                 if (ppd->host_link_state != HLS_UP_ACTIVE) {
1105                         /*
1106                          * If we have filled the PIO buffers to capacity and are
1107                          * not in an active state this request is not going to
1108                          * go out to so just complete it with an error or else a
1109                          * ULP or the core may be stuck waiting.
1110                          */
1111                         hfi1_cdbg(
1112                                 PIO,
1113                                 "alloc failed. state not active, completing");
1114                         wc_status = IB_WC_GENERAL_ERR;
1115                         goto pio_bail;
1116                 } else {
1117                         /*
1118                          * This is a normal occurrence. The PIO buffs are full
1119                          * up but we are still happily sending, well we could be
1120                          * so lets continue to queue the request.
1121                          */
1122                         hfi1_cdbg(PIO, "alloc failed. state active, queuing");
1123                         ret = pio_wait(qp, sc, ps, RVT_S_WAIT_PIO);
1124                         if (!ret)
1125                                 /* txreq not queued - free */
1126                                 goto bail;
1127                         /* tx consumed in wait */
1128                         return ret;
1129                 }
1130         }
1131
1132         if (dwords == 0) {
1133                 pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords);
1134         } else {
1135                 seg_pio_copy_start(pbuf, pbc,
1136                                    hdr, hdrwords * 4);
1137                 if (ss) {
1138                         while (len) {
1139                                 void *addr = ss->sge.vaddr;
1140                                 u32 slen = ss->sge.length;
1141
1142                                 if (slen > len)
1143                                         slen = len;
1144                                 rvt_update_sge(ss, slen, false);
1145                                 seg_pio_copy_mid(pbuf, addr, slen);
1146                                 len -= slen;
1147                         }
1148                 }
1149                 /* add icrc, lt byte, and padding to flit */
1150                 if (extra_bytes)
1151                         seg_pio_copy_mid(pbuf, trail_buf, extra_bytes);
1152
1153                 seg_pio_copy_end(pbuf);
1154         }
1155
1156         update_tx_opstats(qp, ps, plen);
1157         trace_pio_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
1158                                &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5));
1159
1160 pio_bail:
1161         if (qp->s_wqe) {
1162                 spin_lock_irqsave(&qp->s_lock, flags);
1163                 hfi1_send_complete(qp, qp->s_wqe, wc_status);
1164                 spin_unlock_irqrestore(&qp->s_lock, flags);
1165         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1166                 spin_lock_irqsave(&qp->s_lock, flags);
1167                 hfi1_rc_send_complete(qp, &ps->s_txreq->phdr.hdr);
1168                 spin_unlock_irqrestore(&qp->s_lock, flags);
1169         }
1170
1171         ret = 0;
1172
1173 bail:
1174         hfi1_put_txreq(ps->s_txreq);
1175         return ret;
1176 }
1177
1178 /*
1179  * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1180  * being an entry from the partition key table), return 0
1181  * otherwise. Use the matching criteria for egress partition keys
1182  * specified in the OPAv1 spec., section 9.1l.7.
1183  */
1184 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent)
1185 {
1186         u16 mkey = pkey & PKEY_LOW_15_MASK;
1187         u16 mentry = ent & PKEY_LOW_15_MASK;
1188
1189         if (mkey == mentry) {
1190                 /*
1191                  * If pkey[15] is set (full partition member),
1192                  * is bit 15 in the corresponding table element
1193                  * clear (limited member)?
1194                  */
1195                 if (pkey & PKEY_MEMBER_MASK)
1196                         return !!(ent & PKEY_MEMBER_MASK);
1197                 return 1;
1198         }
1199         return 0;
1200 }
1201
1202 /**
1203  * egress_pkey_check - check P_KEY of a packet
1204  * @ppd:  Physical IB port data
1205  * @slid: SLID for packet
1206  * @bkey: PKEY for header
1207  * @sc5:  SC for packet
1208  * @s_pkey_index: It will be used for look up optimization for kernel contexts
1209  * only. If it is negative value, then it means user contexts is calling this
1210  * function.
1211  *
1212  * It checks if hdr's pkey is valid.
1213  *
1214  * Return: 0 on success, otherwise, 1
1215  */
1216 int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1217                       u8 sc5, int8_t s_pkey_index)
1218 {
1219         struct hfi1_devdata *dd;
1220         int i;
1221         int is_user_ctxt_mechanism = (s_pkey_index < 0);
1222
1223         if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT))
1224                 return 0;
1225
1226         /* If SC15, pkey[0:14] must be 0x7fff */
1227         if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1228                 goto bad;
1229
1230         /* Is the pkey = 0x0, or 0x8000? */
1231         if ((pkey & PKEY_LOW_15_MASK) == 0)
1232                 goto bad;
1233
1234         /*
1235          * For the kernel contexts only, if a qp is passed into the function,
1236          * the most likely matching pkey has index qp->s_pkey_index
1237          */
1238         if (!is_user_ctxt_mechanism &&
1239             egress_pkey_matches_entry(pkey, ppd->pkeys[s_pkey_index])) {
1240                 return 0;
1241         }
1242
1243         for (i = 0; i < MAX_PKEY_VALUES; i++) {
1244                 if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1245                         return 0;
1246         }
1247 bad:
1248         /*
1249          * For the user-context mechanism, the P_KEY check would only happen
1250          * once per SDMA request, not once per packet.  Therefore, there's no
1251          * need to increment the counter for the user-context mechanism.
1252          */
1253         if (!is_user_ctxt_mechanism) {
1254                 incr_cntr64(&ppd->port_xmit_constraint_errors);
1255                 dd = ppd->dd;
1256                 if (!(dd->err_info_xmit_constraint.status &
1257                       OPA_EI_STATUS_SMASK)) {
1258                         dd->err_info_xmit_constraint.status |=
1259                                 OPA_EI_STATUS_SMASK;
1260                         dd->err_info_xmit_constraint.slid = slid;
1261                         dd->err_info_xmit_constraint.pkey = pkey;
1262                 }
1263         }
1264         return 1;
1265 }
1266
1267 /**
1268  * get_send_routine - choose an egress routine
1269  *
1270  * Choose an egress routine based on QP type
1271  * and size
1272  */
1273 static inline send_routine get_send_routine(struct rvt_qp *qp,
1274                                             struct hfi1_pkt_state *ps)
1275 {
1276         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1277         struct hfi1_qp_priv *priv = qp->priv;
1278         struct verbs_txreq *tx = ps->s_txreq;
1279
1280         if (unlikely(!(dd->flags & HFI1_HAS_SEND_DMA)))
1281                 return dd->process_pio_send;
1282         switch (qp->ibqp.qp_type) {
1283         case IB_QPT_SMI:
1284                 return dd->process_pio_send;
1285         case IB_QPT_GSI:
1286         case IB_QPT_UD:
1287                 break;
1288         case IB_QPT_UC:
1289         case IB_QPT_RC: {
1290                 if (piothreshold &&
1291                     tx->s_cur_size <= min(piothreshold, qp->pmtu) &&
1292                     (BIT(ps->opcode & OPMASK) & pio_opmask[ps->opcode >> 5]) &&
1293                     iowait_sdma_pending(&priv->s_iowait) == 0 &&
1294                     !sdma_txreq_built(&tx->txreq))
1295                         return dd->process_pio_send;
1296                 break;
1297         }
1298         default:
1299                 break;
1300         }
1301         return dd->process_dma_send;
1302 }
1303
1304 /**
1305  * hfi1_verbs_send - send a packet
1306  * @qp: the QP to send on
1307  * @ps: the state of the packet to send
1308  *
1309  * Return zero if packet is sent or queued OK.
1310  * Return non-zero and clear qp->s_flags RVT_S_BUSY otherwise.
1311  */
1312 int hfi1_verbs_send(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
1313 {
1314         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1315         struct hfi1_qp_priv *priv = qp->priv;
1316         struct ib_other_headers *ohdr = NULL;
1317         send_routine sr;
1318         int ret;
1319         u16 pkey;
1320         u32 slid;
1321         u8 l4 = 0;
1322
1323         /* locate the pkey within the headers */
1324         if (ps->s_txreq->phdr.hdr.hdr_type) {
1325                 struct hfi1_16b_header *hdr = &ps->s_txreq->phdr.hdr.opah;
1326
1327                 l4 = hfi1_16B_get_l4(hdr);
1328                 if (l4 == OPA_16B_L4_IB_LOCAL)
1329                         ohdr = &hdr->u.oth;
1330                 else if (l4 == OPA_16B_L4_IB_GLOBAL)
1331                         ohdr = &hdr->u.l.oth;
1332
1333                 slid = hfi1_16B_get_slid(hdr);
1334                 pkey = hfi1_16B_get_pkey(hdr);
1335         } else {
1336                 struct ib_header *hdr = &ps->s_txreq->phdr.hdr.ibh;
1337                 u8 lnh = ib_get_lnh(hdr);
1338
1339                 if (lnh == HFI1_LRH_GRH)
1340                         ohdr = &hdr->u.l.oth;
1341                 else
1342                         ohdr = &hdr->u.oth;
1343                 slid = ib_get_slid(hdr);
1344                 pkey = ib_bth_get_pkey(ohdr);
1345         }
1346
1347         if (likely(l4 != OPA_16B_L4_FM))
1348                 ps->opcode = ib_bth_get_opcode(ohdr);
1349         else
1350                 ps->opcode = IB_OPCODE_UD_SEND_ONLY;
1351
1352         sr = get_send_routine(qp, ps);
1353         ret = egress_pkey_check(dd->pport, slid, pkey,
1354                                 priv->s_sc, qp->s_pkey_index);
1355         if (unlikely(ret)) {
1356                 /*
1357                  * The value we are returning here does not get propagated to
1358                  * the verbs caller. Thus we need to complete the request with
1359                  * error otherwise the caller could be sitting waiting on the
1360                  * completion event. Only do this for PIO. SDMA has its own
1361                  * mechanism for handling the errors. So for SDMA we can just
1362                  * return.
1363                  */
1364                 if (sr == dd->process_pio_send) {
1365                         unsigned long flags;
1366
1367                         hfi1_cdbg(PIO, "%s() Failed. Completing with err",
1368                                   __func__);
1369                         spin_lock_irqsave(&qp->s_lock, flags);
1370                         hfi1_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
1371                         spin_unlock_irqrestore(&qp->s_lock, flags);
1372                 }
1373                 return -EINVAL;
1374         }
1375         if (sr == dd->process_dma_send && iowait_pio_pending(&priv->s_iowait))
1376                 return pio_wait(qp,
1377                                 ps->s_txreq->psc,
1378                                 ps,
1379                                 HFI1_S_WAIT_PIO_DRAIN);
1380         return sr(qp, ps, 0);
1381 }
1382
1383 /**
1384  * hfi1_fill_device_attr - Fill in rvt dev info device attributes.
1385  * @dd: the device data structure
1386  */
1387 static void hfi1_fill_device_attr(struct hfi1_devdata *dd)
1388 {
1389         struct rvt_dev_info *rdi = &dd->verbs_dev.rdi;
1390         u32 ver = dd->dc8051_ver;
1391
1392         memset(&rdi->dparms.props, 0, sizeof(rdi->dparms.props));
1393
1394         rdi->dparms.props.fw_ver = ((u64)(dc8051_ver_maj(ver)) << 32) |
1395                 ((u64)(dc8051_ver_min(ver)) << 16) |
1396                 (u64)dc8051_ver_patch(ver);
1397
1398         rdi->dparms.props.device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1399                         IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1400                         IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1401                         IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE |
1402                         IB_DEVICE_MEM_MGT_EXTENSIONS |
1403                         IB_DEVICE_RDMA_NETDEV_OPA_VNIC;
1404         rdi->dparms.props.page_size_cap = PAGE_SIZE;
1405         rdi->dparms.props.vendor_id = dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3;
1406         rdi->dparms.props.vendor_part_id = dd->pcidev->device;
1407         rdi->dparms.props.hw_ver = dd->minrev;
1408         rdi->dparms.props.sys_image_guid = ib_hfi1_sys_image_guid;
1409         rdi->dparms.props.max_mr_size = U64_MAX;
1410         rdi->dparms.props.max_fast_reg_page_list_len = UINT_MAX;
1411         rdi->dparms.props.max_qp = hfi1_max_qps;
1412         rdi->dparms.props.max_qp_wr = hfi1_max_qp_wrs;
1413         rdi->dparms.props.max_send_sge = hfi1_max_sges;
1414         rdi->dparms.props.max_recv_sge = hfi1_max_sges;
1415         rdi->dparms.props.max_sge_rd = hfi1_max_sges;
1416         rdi->dparms.props.max_cq = hfi1_max_cqs;
1417         rdi->dparms.props.max_ah = hfi1_max_ahs;
1418         rdi->dparms.props.max_cqe = hfi1_max_cqes;
1419         rdi->dparms.props.max_mr = rdi->lkey_table.max;
1420         rdi->dparms.props.max_fmr = rdi->lkey_table.max;
1421         rdi->dparms.props.max_map_per_fmr = 32767;
1422         rdi->dparms.props.max_pd = hfi1_max_pds;
1423         rdi->dparms.props.max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC;
1424         rdi->dparms.props.max_qp_init_rd_atom = 255;
1425         rdi->dparms.props.max_srq = hfi1_max_srqs;
1426         rdi->dparms.props.max_srq_wr = hfi1_max_srq_wrs;
1427         rdi->dparms.props.max_srq_sge = hfi1_max_srq_sges;
1428         rdi->dparms.props.atomic_cap = IB_ATOMIC_GLOB;
1429         rdi->dparms.props.max_pkeys = hfi1_get_npkeys(dd);
1430         rdi->dparms.props.max_mcast_grp = hfi1_max_mcast_grps;
1431         rdi->dparms.props.max_mcast_qp_attach = hfi1_max_mcast_qp_attached;
1432         rdi->dparms.props.max_total_mcast_qp_attach =
1433                                         rdi->dparms.props.max_mcast_qp_attach *
1434                                         rdi->dparms.props.max_mcast_grp;
1435 }
1436
1437 static inline u16 opa_speed_to_ib(u16 in)
1438 {
1439         u16 out = 0;
1440
1441         if (in & OPA_LINK_SPEED_25G)
1442                 out |= IB_SPEED_EDR;
1443         if (in & OPA_LINK_SPEED_12_5G)
1444                 out |= IB_SPEED_FDR;
1445
1446         return out;
1447 }
1448
1449 /*
1450  * Convert a single OPA link width (no multiple flags) to an IB value.
1451  * A zero OPA link width means link down, which means the IB width value
1452  * is a don't care.
1453  */
1454 static inline u16 opa_width_to_ib(u16 in)
1455 {
1456         switch (in) {
1457         case OPA_LINK_WIDTH_1X:
1458         /* map 2x and 3x to 1x as they don't exist in IB */
1459         case OPA_LINK_WIDTH_2X:
1460         case OPA_LINK_WIDTH_3X:
1461                 return IB_WIDTH_1X;
1462         default: /* link down or unknown, return our largest width */
1463         case OPA_LINK_WIDTH_4X:
1464                 return IB_WIDTH_4X;
1465         }
1466 }
1467
1468 static int query_port(struct rvt_dev_info *rdi, u8 port_num,
1469                       struct ib_port_attr *props)
1470 {
1471         struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1472         struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1473         struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1474         u32 lid = ppd->lid;
1475
1476         /* props being zeroed by the caller, avoid zeroing it here */
1477         props->lid = lid ? lid : 0;
1478         props->lmc = ppd->lmc;
1479         /* OPA logical states match IB logical states */
1480         props->state = driver_lstate(ppd);
1481         props->phys_state = driver_pstate(ppd);
1482         props->gid_tbl_len = HFI1_GUIDS_PER_PORT;
1483         props->active_width = (u8)opa_width_to_ib(ppd->link_width_active);
1484         /* see rate_show() in ib core/sysfs.c */
1485         props->active_speed = (u8)opa_speed_to_ib(ppd->link_speed_active);
1486         props->max_vl_num = ppd->vls_supported;
1487
1488         /* Once we are a "first class" citizen and have added the OPA MTUs to
1489          * the core we can advertise the larger MTU enum to the ULPs, for now
1490          * advertise only 4K.
1491          *
1492          * Those applications which are either OPA aware or pass the MTU enum
1493          * from the Path Records to us will get the new 8k MTU.  Those that
1494          * attempt to process the MTU enum may fail in various ways.
1495          */
1496         props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ?
1497                                       4096 : hfi1_max_mtu), IB_MTU_4096);
1498         props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
1499                 mtu_to_enum(ppd->ibmtu, IB_MTU_4096);
1500
1501         return 0;
1502 }
1503
1504 static int modify_device(struct ib_device *device,
1505                          int device_modify_mask,
1506                          struct ib_device_modify *device_modify)
1507 {
1508         struct hfi1_devdata *dd = dd_from_ibdev(device);
1509         unsigned i;
1510         int ret;
1511
1512         if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1513                                    IB_DEVICE_MODIFY_NODE_DESC)) {
1514                 ret = -EOPNOTSUPP;
1515                 goto bail;
1516         }
1517
1518         if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1519                 memcpy(device->node_desc, device_modify->node_desc,
1520                        IB_DEVICE_NODE_DESC_MAX);
1521                 for (i = 0; i < dd->num_pports; i++) {
1522                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1523
1524                         hfi1_node_desc_chg(ibp);
1525                 }
1526         }
1527
1528         if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1529                 ib_hfi1_sys_image_guid =
1530                         cpu_to_be64(device_modify->sys_image_guid);
1531                 for (i = 0; i < dd->num_pports; i++) {
1532                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1533
1534                         hfi1_sys_guid_chg(ibp);
1535                 }
1536         }
1537
1538         ret = 0;
1539
1540 bail:
1541         return ret;
1542 }
1543
1544 static int shut_down_port(struct rvt_dev_info *rdi, u8 port_num)
1545 {
1546         struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1547         struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1548         struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1549         int ret;
1550
1551         set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0,
1552                              OPA_LINKDOWN_REASON_UNKNOWN);
1553         ret = set_link_state(ppd, HLS_DN_DOWNDEF);
1554         return ret;
1555 }
1556
1557 static int hfi1_get_guid_be(struct rvt_dev_info *rdi, struct rvt_ibport *rvp,
1558                             int guid_index, __be64 *guid)
1559 {
1560         struct hfi1_ibport *ibp = container_of(rvp, struct hfi1_ibport, rvp);
1561
1562         if (guid_index >= HFI1_GUIDS_PER_PORT)
1563                 return -EINVAL;
1564
1565         *guid = get_sguid(ibp, guid_index);
1566         return 0;
1567 }
1568
1569 /*
1570  * convert ah port,sl to sc
1571  */
1572 u8 ah_to_sc(struct ib_device *ibdev, struct rdma_ah_attr *ah)
1573 {
1574         struct hfi1_ibport *ibp = to_iport(ibdev, rdma_ah_get_port_num(ah));
1575
1576         return ibp->sl_to_sc[rdma_ah_get_sl(ah)];
1577 }
1578
1579 static int hfi1_check_ah(struct ib_device *ibdev, struct rdma_ah_attr *ah_attr)
1580 {
1581         struct hfi1_ibport *ibp;
1582         struct hfi1_pportdata *ppd;
1583         struct hfi1_devdata *dd;
1584         u8 sc5;
1585
1586         if (hfi1_check_mcast(rdma_ah_get_dlid(ah_attr)) &&
1587             !(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH))
1588                 return -EINVAL;
1589
1590         /* test the mapping for validity */
1591         ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr));
1592         ppd = ppd_from_ibp(ibp);
1593         sc5 = ibp->sl_to_sc[rdma_ah_get_sl(ah_attr)];
1594         dd = dd_from_ppd(ppd);
1595         if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf)
1596                 return -EINVAL;
1597         return 0;
1598 }
1599
1600 static void hfi1_notify_new_ah(struct ib_device *ibdev,
1601                                struct rdma_ah_attr *ah_attr,
1602                                struct rvt_ah *ah)
1603 {
1604         struct hfi1_ibport *ibp;
1605         struct hfi1_pportdata *ppd;
1606         struct hfi1_devdata *dd;
1607         u8 sc5;
1608         struct rdma_ah_attr *attr = &ah->attr;
1609
1610         /*
1611          * Do not trust reading anything from rvt_ah at this point as it is not
1612          * done being setup. We can however modify things which we need to set.
1613          */
1614
1615         ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr));
1616         ppd = ppd_from_ibp(ibp);
1617         sc5 = ibp->sl_to_sc[rdma_ah_get_sl(&ah->attr)];
1618         hfi1_update_ah_attr(ibdev, attr);
1619         hfi1_make_opa_lid(attr);
1620         dd = dd_from_ppd(ppd);
1621         ah->vl = sc_to_vlt(dd, sc5);
1622         if (ah->vl < num_vls || ah->vl == 15)
1623                 ah->log_pmtu = ilog2(dd->vld[ah->vl].mtu);
1624 }
1625
1626 /**
1627  * hfi1_get_npkeys - return the size of the PKEY table for context 0
1628  * @dd: the hfi1_ib device
1629  */
1630 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd)
1631 {
1632         return ARRAY_SIZE(dd->pport[0].pkeys);
1633 }
1634
1635 static void init_ibport(struct hfi1_pportdata *ppd)
1636 {
1637         struct hfi1_ibport *ibp = &ppd->ibport_data;
1638         size_t sz = ARRAY_SIZE(ibp->sl_to_sc);
1639         int i;
1640
1641         for (i = 0; i < sz; i++) {
1642                 ibp->sl_to_sc[i] = i;
1643                 ibp->sc_to_sl[i] = i;
1644         }
1645
1646         for (i = 0; i < RVT_MAX_TRAP_LISTS ; i++)
1647                 INIT_LIST_HEAD(&ibp->rvp.trap_lists[i].list);
1648         timer_setup(&ibp->rvp.trap_timer, hfi1_handle_trap_timer, 0);
1649
1650         spin_lock_init(&ibp->rvp.lock);
1651         /* Set the prefix to the default value (see ch. 4.1.1) */
1652         ibp->rvp.gid_prefix = IB_DEFAULT_GID_PREFIX;
1653         ibp->rvp.sm_lid = 0;
1654         /*
1655          * Below should only set bits defined in OPA PortInfo.CapabilityMask
1656          * and PortInfo.CapabilityMask3
1657          */
1658         ibp->rvp.port_cap_flags = IB_PORT_AUTO_MIGR_SUP |
1659                 IB_PORT_CAP_MASK_NOTICE_SUP;
1660         ibp->rvp.port_cap3_flags = OPA_CAP_MASK3_IsSharedSpaceSupported;
1661         ibp->rvp.pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1662         ibp->rvp.pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1663         ibp->rvp.pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1664         ibp->rvp.pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1665         ibp->rvp.pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1666
1667         RCU_INIT_POINTER(ibp->rvp.qp[0], NULL);
1668         RCU_INIT_POINTER(ibp->rvp.qp[1], NULL);
1669 }
1670
1671 static void hfi1_get_dev_fw_str(struct ib_device *ibdev, char *str)
1672 {
1673         struct rvt_dev_info *rdi = ib_to_rvt(ibdev);
1674         struct hfi1_ibdev *dev = dev_from_rdi(rdi);
1675         u32 ver = dd_from_dev(dev)->dc8051_ver;
1676
1677         snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%u", dc8051_ver_maj(ver),
1678                  dc8051_ver_min(ver), dc8051_ver_patch(ver));
1679 }
1680
1681 static const char * const driver_cntr_names[] = {
1682         /* must be element 0*/
1683         "DRIVER_KernIntr",
1684         "DRIVER_ErrorIntr",
1685         "DRIVER_Tx_Errs",
1686         "DRIVER_Rcv_Errs",
1687         "DRIVER_HW_Errs",
1688         "DRIVER_NoPIOBufs",
1689         "DRIVER_CtxtsOpen",
1690         "DRIVER_RcvLen_Errs",
1691         "DRIVER_EgrBufFull",
1692         "DRIVER_EgrHdrFull"
1693 };
1694
1695 static DEFINE_MUTEX(cntr_names_lock); /* protects the *_cntr_names bufers */
1696 static const char **dev_cntr_names;
1697 static const char **port_cntr_names;
1698 static int num_driver_cntrs = ARRAY_SIZE(driver_cntr_names);
1699 static int num_dev_cntrs;
1700 static int num_port_cntrs;
1701 static int cntr_names_initialized;
1702
1703 /*
1704  * Convert a list of names separated by '\n' into an array of NULL terminated
1705  * strings. Optionally some entries can be reserved in the array to hold extra
1706  * external strings.
1707  */
1708 static int init_cntr_names(const char *names_in,
1709                            const size_t names_len,
1710                            int num_extra_names,
1711                            int *num_cntrs,
1712                            const char ***cntr_names)
1713 {
1714         char *names_out, *p, **q;
1715         int i, n;
1716
1717         n = 0;
1718         for (i = 0; i < names_len; i++)
1719                 if (names_in[i] == '\n')
1720                         n++;
1721
1722         names_out = kmalloc((n + num_extra_names) * sizeof(char *) + names_len,
1723                             GFP_KERNEL);
1724         if (!names_out) {
1725                 *num_cntrs = 0;
1726                 *cntr_names = NULL;
1727                 return -ENOMEM;
1728         }
1729
1730         p = names_out + (n + num_extra_names) * sizeof(char *);
1731         memcpy(p, names_in, names_len);
1732
1733         q = (char **)names_out;
1734         for (i = 0; i < n; i++) {
1735                 q[i] = p;
1736                 p = strchr(p, '\n');
1737                 *p++ = '\0';
1738         }
1739
1740         *num_cntrs = n;
1741         *cntr_names = (const char **)names_out;
1742         return 0;
1743 }
1744
1745 static struct rdma_hw_stats *alloc_hw_stats(struct ib_device *ibdev,
1746                                             u8 port_num)
1747 {
1748         int i, err;
1749
1750         mutex_lock(&cntr_names_lock);
1751         if (!cntr_names_initialized) {
1752                 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1753
1754                 err = init_cntr_names(dd->cntrnames,
1755                                       dd->cntrnameslen,
1756                                       num_driver_cntrs,
1757                                       &num_dev_cntrs,
1758                                       &dev_cntr_names);
1759                 if (err) {
1760                         mutex_unlock(&cntr_names_lock);
1761                         return NULL;
1762                 }
1763
1764                 for (i = 0; i < num_driver_cntrs; i++)
1765                         dev_cntr_names[num_dev_cntrs + i] =
1766                                 driver_cntr_names[i];
1767
1768                 err = init_cntr_names(dd->portcntrnames,
1769                                       dd->portcntrnameslen,
1770                                       0,
1771                                       &num_port_cntrs,
1772                                       &port_cntr_names);
1773                 if (err) {
1774                         kfree(dev_cntr_names);
1775                         dev_cntr_names = NULL;
1776                         mutex_unlock(&cntr_names_lock);
1777                         return NULL;
1778                 }
1779                 cntr_names_initialized = 1;
1780         }
1781         mutex_unlock(&cntr_names_lock);
1782
1783         if (!port_num)
1784                 return rdma_alloc_hw_stats_struct(
1785                                 dev_cntr_names,
1786                                 num_dev_cntrs + num_driver_cntrs,
1787                                 RDMA_HW_STATS_DEFAULT_LIFESPAN);
1788         else
1789                 return rdma_alloc_hw_stats_struct(
1790                                 port_cntr_names,
1791                                 num_port_cntrs,
1792                                 RDMA_HW_STATS_DEFAULT_LIFESPAN);
1793 }
1794
1795 static u64 hfi1_sps_ints(void)
1796 {
1797         unsigned long flags;
1798         struct hfi1_devdata *dd;
1799         u64 sps_ints = 0;
1800
1801         spin_lock_irqsave(&hfi1_devs_lock, flags);
1802         list_for_each_entry(dd, &hfi1_dev_list, list) {
1803                 sps_ints += get_all_cpu_total(dd->int_counter);
1804         }
1805         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
1806         return sps_ints;
1807 }
1808
1809 static int get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats,
1810                         u8 port, int index)
1811 {
1812         u64 *values;
1813         int count;
1814
1815         if (!port) {
1816                 u64 *stats = (u64 *)&hfi1_stats;
1817                 int i;
1818
1819                 hfi1_read_cntrs(dd_from_ibdev(ibdev), NULL, &values);
1820                 values[num_dev_cntrs] = hfi1_sps_ints();
1821                 for (i = 1; i < num_driver_cntrs; i++)
1822                         values[num_dev_cntrs + i] = stats[i];
1823                 count = num_dev_cntrs + num_driver_cntrs;
1824         } else {
1825                 struct hfi1_ibport *ibp = to_iport(ibdev, port);
1826
1827                 hfi1_read_portcntrs(ppd_from_ibp(ibp), NULL, &values);
1828                 count = num_port_cntrs;
1829         }
1830
1831         memcpy(stats->value, values, count * sizeof(u64));
1832         return count;
1833 }
1834
1835 /**
1836  * hfi1_register_ib_device - register our device with the infiniband core
1837  * @dd: the device data structure
1838  * Return 0 if successful, errno if unsuccessful.
1839  */
1840 int hfi1_register_ib_device(struct hfi1_devdata *dd)
1841 {
1842         struct hfi1_ibdev *dev = &dd->verbs_dev;
1843         struct ib_device *ibdev = &dev->rdi.ibdev;
1844         struct hfi1_pportdata *ppd = dd->pport;
1845         struct hfi1_ibport *ibp = &ppd->ibport_data;
1846         unsigned i;
1847         int ret;
1848
1849         for (i = 0; i < dd->num_pports; i++)
1850                 init_ibport(ppd + i);
1851
1852         /* Only need to initialize non-zero fields. */
1853
1854         timer_setup(&dev->mem_timer, mem_timer, 0);
1855
1856         seqlock_init(&dev->iowait_lock);
1857         seqlock_init(&dev->txwait_lock);
1858         INIT_LIST_HEAD(&dev->txwait);
1859         INIT_LIST_HEAD(&dev->memwait);
1860
1861         ret = verbs_txreq_init(dev);
1862         if (ret)
1863                 goto err_verbs_txreq;
1864
1865         /* Use first-port GUID as node guid */
1866         ibdev->node_guid = get_sguid(ibp, HFI1_PORT_GUID_INDEX);
1867
1868         /*
1869          * The system image GUID is supposed to be the same for all
1870          * HFIs in a single system but since there can be other
1871          * device types in the system, we can't be sure this is unique.
1872          */
1873         if (!ib_hfi1_sys_image_guid)
1874                 ib_hfi1_sys_image_guid = ibdev->node_guid;
1875         ibdev->owner = THIS_MODULE;
1876         ibdev->phys_port_cnt = dd->num_pports;
1877         ibdev->dev.parent = &dd->pcidev->dev;
1878         ibdev->modify_device = modify_device;
1879         ibdev->alloc_hw_stats = alloc_hw_stats;
1880         ibdev->get_hw_stats = get_hw_stats;
1881         ibdev->alloc_rdma_netdev = hfi1_vnic_alloc_rn;
1882
1883         /* keep process mad in the driver */
1884         ibdev->process_mad = hfi1_process_mad;
1885         ibdev->get_dev_fw_str = hfi1_get_dev_fw_str;
1886
1887         strlcpy(ibdev->node_desc, init_utsname()->nodename,
1888                 sizeof(ibdev->node_desc));
1889
1890         /*
1891          * Fill in rvt info object.
1892          */
1893         dd->verbs_dev.rdi.driver_f.port_callback = hfi1_create_port_files;
1894         dd->verbs_dev.rdi.driver_f.get_pci_dev = get_pci_dev;
1895         dd->verbs_dev.rdi.driver_f.check_ah = hfi1_check_ah;
1896         dd->verbs_dev.rdi.driver_f.notify_new_ah = hfi1_notify_new_ah;
1897         dd->verbs_dev.rdi.driver_f.get_guid_be = hfi1_get_guid_be;
1898         dd->verbs_dev.rdi.driver_f.query_port_state = query_port;
1899         dd->verbs_dev.rdi.driver_f.shut_down_port = shut_down_port;
1900         dd->verbs_dev.rdi.driver_f.cap_mask_chg = hfi1_cap_mask_chg;
1901         /*
1902          * Fill in rvt info device attributes.
1903          */
1904         hfi1_fill_device_attr(dd);
1905
1906         /* queue pair */
1907         dd->verbs_dev.rdi.dparms.qp_table_size = hfi1_qp_table_size;
1908         dd->verbs_dev.rdi.dparms.qpn_start = 0;
1909         dd->verbs_dev.rdi.dparms.qpn_inc = 1;
1910         dd->verbs_dev.rdi.dparms.qos_shift = dd->qos_shift;
1911         dd->verbs_dev.rdi.dparms.qpn_res_start = kdeth_qp << 16;
1912         dd->verbs_dev.rdi.dparms.qpn_res_end =
1913         dd->verbs_dev.rdi.dparms.qpn_res_start + 65535;
1914         dd->verbs_dev.rdi.dparms.max_rdma_atomic = HFI1_MAX_RDMA_ATOMIC;
1915         dd->verbs_dev.rdi.dparms.psn_mask = PSN_MASK;
1916         dd->verbs_dev.rdi.dparms.psn_shift = PSN_SHIFT;
1917         dd->verbs_dev.rdi.dparms.psn_modify_mask = PSN_MODIFY_MASK;
1918         dd->verbs_dev.rdi.dparms.core_cap_flags = RDMA_CORE_PORT_INTEL_OPA |
1919                                                 RDMA_CORE_CAP_OPA_AH;
1920         dd->verbs_dev.rdi.dparms.max_mad_size = OPA_MGMT_MAD_SIZE;
1921
1922         dd->verbs_dev.rdi.driver_f.qp_priv_alloc = qp_priv_alloc;
1923         dd->verbs_dev.rdi.driver_f.qp_priv_free = qp_priv_free;
1924         dd->verbs_dev.rdi.driver_f.free_all_qps = free_all_qps;
1925         dd->verbs_dev.rdi.driver_f.notify_qp_reset = notify_qp_reset;
1926         dd->verbs_dev.rdi.driver_f.do_send = hfi1_do_send_from_rvt;
1927         dd->verbs_dev.rdi.driver_f.schedule_send = hfi1_schedule_send;
1928         dd->verbs_dev.rdi.driver_f.schedule_send_no_lock = _hfi1_schedule_send;
1929         dd->verbs_dev.rdi.driver_f.get_pmtu_from_attr = get_pmtu_from_attr;
1930         dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1931         dd->verbs_dev.rdi.driver_f.flush_qp_waiters = flush_qp_waiters;
1932         dd->verbs_dev.rdi.driver_f.stop_send_queue = stop_send_queue;
1933         dd->verbs_dev.rdi.driver_f.quiesce_qp = quiesce_qp;
1934         dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1935         dd->verbs_dev.rdi.driver_f.mtu_from_qp = mtu_from_qp;
1936         dd->verbs_dev.rdi.driver_f.mtu_to_path_mtu = mtu_to_path_mtu;
1937         dd->verbs_dev.rdi.driver_f.check_modify_qp = hfi1_check_modify_qp;
1938         dd->verbs_dev.rdi.driver_f.modify_qp = hfi1_modify_qp;
1939         dd->verbs_dev.rdi.driver_f.notify_restart_rc = hfi1_restart_rc;
1940         dd->verbs_dev.rdi.driver_f.check_send_wqe = hfi1_check_send_wqe;
1941         dd->verbs_dev.rdi.driver_f.comp_vect_cpu_lookup =
1942                                                 hfi1_comp_vect_mappings_lookup;
1943
1944         /* completeion queue */
1945         dd->verbs_dev.rdi.ibdev.num_comp_vectors = dd->comp_vect_possible_cpus;
1946         dd->verbs_dev.rdi.dparms.node = dd->node;
1947
1948         /* misc settings */
1949         dd->verbs_dev.rdi.flags = 0; /* Let rdmavt handle it all */
1950         dd->verbs_dev.rdi.dparms.lkey_table_size = hfi1_lkey_table_size;
1951         dd->verbs_dev.rdi.dparms.nports = dd->num_pports;
1952         dd->verbs_dev.rdi.dparms.npkeys = hfi1_get_npkeys(dd);
1953
1954         /* post send table */
1955         dd->verbs_dev.rdi.post_parms = hfi1_post_parms;
1956
1957         ppd = dd->pport;
1958         for (i = 0; i < dd->num_pports; i++, ppd++)
1959                 rvt_init_port(&dd->verbs_dev.rdi,
1960                               &ppd->ibport_data.rvp,
1961                               i,
1962                               ppd->pkeys);
1963
1964         ret = rvt_register_device(&dd->verbs_dev.rdi, RDMA_DRIVER_HFI1);
1965         if (ret)
1966                 goto err_verbs_txreq;
1967
1968         ret = hfi1_verbs_register_sysfs(dd);
1969         if (ret)
1970                 goto err_class;
1971
1972         return ret;
1973
1974 err_class:
1975         rvt_unregister_device(&dd->verbs_dev.rdi);
1976 err_verbs_txreq:
1977         verbs_txreq_exit(dev);
1978         dd_dev_err(dd, "cannot register verbs: %d!\n", -ret);
1979         return ret;
1980 }
1981
1982 void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
1983 {
1984         struct hfi1_ibdev *dev = &dd->verbs_dev;
1985
1986         hfi1_verbs_unregister_sysfs(dd);
1987
1988         rvt_unregister_device(&dd->verbs_dev.rdi);
1989
1990         if (!list_empty(&dev->txwait))
1991                 dd_dev_err(dd, "txwait list not empty!\n");
1992         if (!list_empty(&dev->memwait))
1993                 dd_dev_err(dd, "memwait list not empty!\n");
1994
1995         del_timer_sync(&dev->mem_timer);
1996         verbs_txreq_exit(dev);
1997
1998         mutex_lock(&cntr_names_lock);
1999         kfree(dev_cntr_names);
2000         kfree(port_cntr_names);
2001         dev_cntr_names = NULL;
2002         port_cntr_names = NULL;
2003         cntr_names_initialized = 0;
2004         mutex_unlock(&cntr_names_lock);
2005 }
2006
2007 void hfi1_cnp_rcv(struct hfi1_packet *packet)
2008 {
2009         struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd);
2010         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2011         struct ib_header *hdr = packet->hdr;
2012         struct rvt_qp *qp = packet->qp;
2013         u32 lqpn, rqpn = 0;
2014         u16 rlid = 0;
2015         u8 sl, sc5, svc_type;
2016
2017         switch (packet->qp->ibqp.qp_type) {
2018         case IB_QPT_UC:
2019                 rlid = rdma_ah_get_dlid(&qp->remote_ah_attr);
2020                 rqpn = qp->remote_qpn;
2021                 svc_type = IB_CC_SVCTYPE_UC;
2022                 break;
2023         case IB_QPT_RC:
2024                 rlid = rdma_ah_get_dlid(&qp->remote_ah_attr);
2025                 rqpn = qp->remote_qpn;
2026                 svc_type = IB_CC_SVCTYPE_RC;
2027                 break;
2028         case IB_QPT_SMI:
2029         case IB_QPT_GSI:
2030         case IB_QPT_UD:
2031                 svc_type = IB_CC_SVCTYPE_UD;
2032                 break;
2033         default:
2034                 ibp->rvp.n_pkt_drops++;
2035                 return;
2036         }
2037
2038         sc5 = hfi1_9B_get_sc5(hdr, packet->rhf);
2039         sl = ibp->sc_to_sl[sc5];
2040         lqpn = qp->ibqp.qp_num;
2041
2042         process_becn(ppd, sl, rlid, lqpn, rqpn, svc_type);
2043 }