drivers/infiniband/hw/hfi1/chip.c

   1 /*
   2  * Copyright(c) 2015 - 2017 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 /*
  49  * This file contains all of the code that is specific to the HFI chip
  50  */
  51
  52 #include <linux/pci.h>
  53 #include <linux/delay.h>
  54 #include <linux/interrupt.h>
  55 #include <linux/module.h>
  56
  57 #include "hfi.h"
  58 #include "trace.h"
  59 #include "mad.h"
  60 #include "pio.h"
  61 #include "sdma.h"
  62 #include "eprom.h"
  63 #include "efivar.h"
  64 #include "platform.h"
  65 #include "aspm.h"
  66 #include "affinity.h"
  67 #include "debugfs.h"
  68
  69 #define NUM_IB_PORTS 1
  70
  71 uint kdeth_qp;
  72 module_param_named(kdeth_qp, kdeth_qp, uint, S_IRUGO);
  73 MODULE_PARM_DESC(kdeth_qp, "Set the KDETH queue pair prefix");
  74
  75 uint num_vls = HFI1_MAX_VLS_SUPPORTED;
  76 module_param(num_vls, uint, S_IRUGO);
  77 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
  78
  79 /*
  80  * Default time to aggregate two 10K packets from the idle state
  81  * (timer not running). The timer starts at the end of the first packet,
  82  * so only the time for one 10K packet and header plus a bit extra is needed.
  83  * 10 * 1024 + 64 header byte = 10304 byte
  84  * 10304 byte / 12.5 GB/s = 824.32ns
  85  */
  86 uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */
  87 module_param(rcv_intr_timeout, uint, S_IRUGO);
  88 MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns");
  89
  90 uint rcv_intr_count = 16; /* same as qib */
  91 module_param(rcv_intr_count, uint, S_IRUGO);
  92 MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count");
  93
  94 ushort link_crc_mask = SUPPORTED_CRCS;
  95 module_param(link_crc_mask, ushort, S_IRUGO);
  96 MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link");
  97
  98 uint loopback;
  99 module_param_named(loopback, loopback, uint, S_IRUGO);
 100 MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable");
 101
 102 /* Other driver tunables */
 103 uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/
 104 static ushort crc_14b_sideband = 1;
 105 static uint use_flr = 1;
 106 uint quick_linkup; /* skip LNI */
 107
 108 struct flag_table {
 109         u64 flag;       /* the flag */
 110         char *str;      /* description string */
 111         u16 extra;      /* extra information */
 112         u16 unused0;
 113         u32 unused1;
 114 };
 115
 116 /* str must be a string constant */
 117 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
 118 #define FLAG_ENTRY0(str, flag) {flag, str, 0}
 119
 120 /* Send Error Consequences */
 121 #define SEC_WRITE_DROPPED       0x1
 122 #define SEC_PACKET_DROPPED      0x2
 123 #define SEC_SC_HALTED           0x4     /* per-context only */
 124 #define SEC_SPC_FREEZE          0x8     /* per-HFI only */
 125
 126 #define DEFAULT_KRCVQS            2
 127 #define MIN_KERNEL_KCTXTS         2
 128 #define FIRST_KERNEL_KCTXT        1
 129
 130 /*
 131  * RSM instance allocation
 132  *   0 - Verbs
 133  *   1 - User Fecn Handling
 134  *   2 - Vnic
 135  */
 136 #define RSM_INS_VERBS             0
 137 #define RSM_INS_FECN              1
 138 #define RSM_INS_VNIC              2
 139
 140 /* Bit offset into the GUID which carries HFI id information */
 141 #define GUID_HFI_INDEX_SHIFT     39
 142
 143 /* extract the emulation revision */
 144 #define emulator_rev(dd) ((dd)->irev >> 8)
 145 /* parallel and serial emulation versions are 3 and 4 respectively */
 146 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
 147 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
 148
 149 /* RSM fields for Verbs */
 150 /* packet type */
 151 #define IB_PACKET_TYPE         2ull
 152 #define QW_SHIFT               6ull
 153 /* QPN[7..1] */
 154 #define QPN_WIDTH              7ull
 155
 156 /* LRH.BTH: QW 0, OFFSET 48 - for match */
 157 #define LRH_BTH_QW             0ull
 158 #define LRH_BTH_BIT_OFFSET     48ull
 159 #define LRH_BTH_OFFSET(off)    ((LRH_BTH_QW << QW_SHIFT) | (off))
 160 #define LRH_BTH_MATCH_OFFSET   LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
 161 #define LRH_BTH_SELECT
 162 #define LRH_BTH_MASK           3ull
 163 #define LRH_BTH_VALUE          2ull
 164
 165 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
 166 #define LRH_SC_QW              0ull
 167 #define LRH_SC_BIT_OFFSET      56ull
 168 #define LRH_SC_OFFSET(off)     ((LRH_SC_QW << QW_SHIFT) | (off))
 169 #define LRH_SC_MATCH_OFFSET    LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
 170 #define LRH_SC_MASK            128ull
 171 #define LRH_SC_VALUE           0ull
 172
 173 /* SC[n..0] QW 0, OFFSET 60 - for select */
 174 #define LRH_SC_SELECT_OFFSET  ((LRH_SC_QW << QW_SHIFT) | (60ull))
 175
 176 /* QPN[m+n:1] QW 1, OFFSET 1 */
 177 #define QPN_SELECT_OFFSET      ((1ull << QW_SHIFT) | (1ull))
 178
 179 /* RSM fields for Vnic */
 180 /* L2_TYPE: QW 0, OFFSET 61 - for match */
 181 #define L2_TYPE_QW             0ull
 182 #define L2_TYPE_BIT_OFFSET     61ull
 183 #define L2_TYPE_OFFSET(off)    ((L2_TYPE_QW << QW_SHIFT) | (off))
 184 #define L2_TYPE_MATCH_OFFSET   L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET)
 185 #define L2_TYPE_MASK           3ull
 186 #define L2_16B_VALUE           2ull
 187
 188 /* L4_TYPE QW 1, OFFSET 0 - for match */
 189 #define L4_TYPE_QW              1ull
 190 #define L4_TYPE_BIT_OFFSET      0ull
 191 #define L4_TYPE_OFFSET(off)     ((L4_TYPE_QW << QW_SHIFT) | (off))
 192 #define L4_TYPE_MATCH_OFFSET    L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET)
 193 #define L4_16B_TYPE_MASK        0xFFull
 194 #define L4_16B_ETH_VALUE        0x78ull
 195
 196 /* 16B VESWID - for select */
 197 #define L4_16B_HDR_VESWID_OFFSET  ((2 << QW_SHIFT) | (16ull))
 198 /* 16B ENTROPY - for select */
 199 #define L2_16B_ENTROPY_OFFSET     ((1 << QW_SHIFT) | (32ull))
 200
 201 /* defines to build power on SC2VL table */
 202 #define SC2VL_VAL( \
 203         num, \
 204         sc0, sc0val, \
 205         sc1, sc1val, \
 206         sc2, sc2val, \
 207         sc3, sc3val, \
 208         sc4, sc4val, \
 209         sc5, sc5val, \
 210         sc6, sc6val, \
 211         sc7, sc7val) \
 212 ( \
 213         ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
 214         ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
 215         ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
 216         ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
 217         ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
 218         ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
 219         ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
 220         ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT)   \
 221 )
 222
 223 #define DC_SC_VL_VAL( \
 224         range, \
 225         e0, e0val, \
 226         e1, e1val, \
 227         e2, e2val, \
 228         e3, e3val, \
 229         e4, e4val, \
 230         e5, e5val, \
 231         e6, e6val, \
 232         e7, e7val, \
 233         e8, e8val, \
 234         e9, e9val, \
 235         e10, e10val, \
 236         e11, e11val, \
 237         e12, e12val, \
 238         e13, e13val, \
 239         e14, e14val, \
 240         e15, e15val) \
 241 ( \
 242         ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
 243         ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
 244         ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
 245         ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
 246         ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
 247         ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
 248         ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
 249         ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
 250         ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
 251         ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
 252         ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
 253         ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
 254         ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
 255         ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
 256         ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
 257         ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
 258 )
 259
 260 /* all CceStatus sub-block freeze bits */
 261 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
 262                         | CCE_STATUS_RXE_FROZE_SMASK \
 263                         | CCE_STATUS_TXE_FROZE_SMASK \
 264                         | CCE_STATUS_TXE_PIO_FROZE_SMASK)
 265 /* all CceStatus sub-block TXE pause bits */
 266 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
 267                         | CCE_STATUS_TXE_PAUSED_SMASK \
 268                         | CCE_STATUS_SDMA_PAUSED_SMASK)
 269 /* all CceStatus sub-block RXE pause bits */
 270 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
 271
 272 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
 273 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF
 274
 275 /*
 276  * CCE Error flags.
 277  */
 278 static struct flag_table cce_err_status_flags[] = {
 279 /* 0*/  FLAG_ENTRY0("CceCsrParityErr",
 280                 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
 281 /* 1*/  FLAG_ENTRY0("CceCsrReadBadAddrErr",
 282                 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
 283 /* 2*/  FLAG_ENTRY0("CceCsrWriteBadAddrErr",
 284                 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
 285 /* 3*/  FLAG_ENTRY0("CceTrgtAsyncFifoParityErr",
 286                 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
 287 /* 4*/  FLAG_ENTRY0("CceTrgtAccessErr",
 288                 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
 289 /* 5*/  FLAG_ENTRY0("CceRspdDataParityErr",
 290                 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
 291 /* 6*/  FLAG_ENTRY0("CceCli0AsyncFifoParityErr",
 292                 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
 293 /* 7*/  FLAG_ENTRY0("CceCsrCfgBusParityErr",
 294                 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
 295 /* 8*/  FLAG_ENTRY0("CceCli2AsyncFifoParityErr",
 296                 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
 297 /* 9*/  FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
 298             CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
 299 /*10*/  FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
 300             CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
 301 /*11*/  FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError",
 302             CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
 303 /*12*/  FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError",
 304                 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
 305 /*13*/  FLAG_ENTRY0("PcicRetryMemCorErr",
 306                 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
 307 /*14*/  FLAG_ENTRY0("PcicRetryMemCorErr",
 308                 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
 309 /*15*/  FLAG_ENTRY0("PcicPostHdQCorErr",
 310                 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
 311 /*16*/  FLAG_ENTRY0("PcicPostHdQCorErr",
 312                 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
 313 /*17*/  FLAG_ENTRY0("PcicPostHdQCorErr",
 314                 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
 315 /*18*/  FLAG_ENTRY0("PcicCplDatQCorErr",
 316                 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
 317 /*19*/  FLAG_ENTRY0("PcicNPostHQParityErr",
 318                 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
 319 /*20*/  FLAG_ENTRY0("PcicNPostDatQParityErr",
 320                 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
 321 /*21*/  FLAG_ENTRY0("PcicRetryMemUncErr",
 322                 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
 323 /*22*/  FLAG_ENTRY0("PcicRetrySotMemUncErr",
 324                 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
 325 /*23*/  FLAG_ENTRY0("PcicPostHdQUncErr",
 326                 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
 327 /*24*/  FLAG_ENTRY0("PcicPostDatQUncErr",
 328                 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
 329 /*25*/  FLAG_ENTRY0("PcicCplHdQUncErr",
 330                 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
 331 /*26*/  FLAG_ENTRY0("PcicCplDatQUncErr",
 332                 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
 333 /*27*/  FLAG_ENTRY0("PcicTransmitFrontParityErr",
 334                 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
 335 /*28*/  FLAG_ENTRY0("PcicTransmitBackParityErr",
 336                 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
 337 /*29*/  FLAG_ENTRY0("PcicReceiveParityErr",
 338                 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
 339 /*30*/  FLAG_ENTRY0("CceTrgtCplTimeoutErr",
 340                 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
 341 /*31*/  FLAG_ENTRY0("LATriggered",
 342                 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
 343 /*32*/  FLAG_ENTRY0("CceSegReadBadAddrErr",
 344                 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
 345 /*33*/  FLAG_ENTRY0("CceSegWriteBadAddrErr",
 346                 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
 347 /*34*/  FLAG_ENTRY0("CceRcplAsyncFifoParityErr",
 348                 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
 349 /*35*/  FLAG_ENTRY0("CceRxdmaConvFifoParityErr",
 350                 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
 351 /*36*/  FLAG_ENTRY0("CceMsixTableCorErr",
 352                 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
 353 /*37*/  FLAG_ENTRY0("CceMsixTableUncErr",
 354                 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
 355 /*38*/  FLAG_ENTRY0("CceIntMapCorErr",
 356                 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
 357 /*39*/  FLAG_ENTRY0("CceIntMapUncErr",
 358                 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
 359 /*40*/  FLAG_ENTRY0("CceMsixCsrParityErr",
 360                 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
 361 /*41-63 reserved*/
 362 };
 363
 364 /*
 365  * Misc Error flags
 366  */
 367 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
 368 static struct flag_table misc_err_status_flags[] = {
 369 /* 0*/  FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)),
 370 /* 1*/  FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)),
 371 /* 2*/  FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)),
 372 /* 3*/  FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)),
 373 /* 4*/  FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)),
 374 /* 5*/  FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)),
 375 /* 6*/  FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)),
 376 /* 7*/  FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)),
 377 /* 8*/  FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)),
 378 /* 9*/  FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)),
 379 /*10*/  FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)),
 380 /*11*/  FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)),
 381 /*12*/  FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL))
 382 };
 383
 384 /*
 385  * TXE PIO Error flags and consequences
 386  */
 387 static struct flag_table pio_err_status_flags[] = {
 388 /* 0*/  FLAG_ENTRY("PioWriteBadCtxt",
 389         SEC_WRITE_DROPPED,
 390         SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
 391 /* 1*/  FLAG_ENTRY("PioWriteAddrParity",
 392         SEC_SPC_FREEZE,
 393         SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
 394 /* 2*/  FLAG_ENTRY("PioCsrParity",
 395         SEC_SPC_FREEZE,
 396         SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
 397 /* 3*/  FLAG_ENTRY("PioSbMemFifo0",
 398         SEC_SPC_FREEZE,
 399         SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
 400 /* 4*/  FLAG_ENTRY("PioSbMemFifo1",
 401         SEC_SPC_FREEZE,
 402         SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
 403 /* 5*/  FLAG_ENTRY("PioPccFifoParity",
 404         SEC_SPC_FREEZE,
 405         SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
 406 /* 6*/  FLAG_ENTRY("PioPecFifoParity",
 407         SEC_SPC_FREEZE,
 408         SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
 409 /* 7*/  FLAG_ENTRY("PioSbrdctlCrrelParity",
 410         SEC_SPC_FREEZE,
 411         SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
 412 /* 8*/  FLAG_ENTRY("PioSbrdctrlCrrelFifoParity",
 413         SEC_SPC_FREEZE,
 414         SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
 415 /* 9*/  FLAG_ENTRY("PioPktEvictFifoParityErr",
 416         SEC_SPC_FREEZE,
 417         SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
 418 /*10*/  FLAG_ENTRY("PioSmPktResetParity",
 419         SEC_SPC_FREEZE,
 420         SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
 421 /*11*/  FLAG_ENTRY("PioVlLenMemBank0Unc",
 422         SEC_SPC_FREEZE,
 423         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
 424 /*12*/  FLAG_ENTRY("PioVlLenMemBank1Unc",
 425         SEC_SPC_FREEZE,
 426         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
 427 /*13*/  FLAG_ENTRY("PioVlLenMemBank0Cor",
 428         0,
 429         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
 430 /*14*/  FLAG_ENTRY("PioVlLenMemBank1Cor",
 431         0,
 432         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
 433 /*15*/  FLAG_ENTRY("PioCreditRetFifoParity",
 434         SEC_SPC_FREEZE,
 435         SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
 436 /*16*/  FLAG_ENTRY("PioPpmcPblFifo",
 437         SEC_SPC_FREEZE,
 438         SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
 439 /*17*/  FLAG_ENTRY("PioInitSmIn",
 440         0,
 441         SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
 442 /*18*/  FLAG_ENTRY("PioPktEvictSmOrArbSm",
 443         SEC_SPC_FREEZE,
 444         SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
 445 /*19*/  FLAG_ENTRY("PioHostAddrMemUnc",
 446         SEC_SPC_FREEZE,
 447         SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
 448 /*20*/  FLAG_ENTRY("PioHostAddrMemCor",
 449         0,
 450         SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
 451 /*21*/  FLAG_ENTRY("PioWriteDataParity",
 452         SEC_SPC_FREEZE,
 453         SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
 454 /*22*/  FLAG_ENTRY("PioStateMachine",
 455         SEC_SPC_FREEZE,
 456         SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
 457 /*23*/  FLAG_ENTRY("PioWriteQwValidParity",
 458         SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
 459         SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
 460 /*24*/  FLAG_ENTRY("PioBlockQwCountParity",
 461         SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
 462         SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
 463 /*25*/  FLAG_ENTRY("PioVlfVlLenParity",
 464         SEC_SPC_FREEZE,
 465         SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
 466 /*26*/  FLAG_ENTRY("PioVlfSopParity",
 467         SEC_SPC_FREEZE,
 468         SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
 469 /*27*/  FLAG_ENTRY("PioVlFifoParity",
 470         SEC_SPC_FREEZE,
 471         SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
 472 /*28*/  FLAG_ENTRY("PioPpmcBqcMemParity",
 473         SEC_SPC_FREEZE,
 474         SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
 475 /*29*/  FLAG_ENTRY("PioPpmcSopLen",
 476         SEC_SPC_FREEZE,
 477         SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
 478 /*30-31 reserved*/
 479 /*32*/  FLAG_ENTRY("PioCurrentFreeCntParity",
 480         SEC_SPC_FREEZE,
 481         SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
 482 /*33*/  FLAG_ENTRY("PioLastReturnedCntParity",
 483         SEC_SPC_FREEZE,
 484         SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
 485 /*34*/  FLAG_ENTRY("PioPccSopHeadParity",
 486         SEC_SPC_FREEZE,
 487         SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
 488 /*35*/  FLAG_ENTRY("PioPecSopHeadParityErr",
 489         SEC_SPC_FREEZE,
 490         SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
 491 /*36-63 reserved*/
 492 };
 493
 494 /* TXE PIO errors that cause an SPC freeze */
 495 #define ALL_PIO_FREEZE_ERR \
 496         (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
 497         | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
 498         | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
 499         | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
 500         | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
 501         | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
 502         | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
 503         | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
 504         | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
 505         | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
 506         | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
 507         | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
 508         | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
 509         | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
 510         | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
 511         | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
 512         | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
 513         | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
 514         | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
 515         | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
 516         | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
 517         | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
 518         | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
 519         | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
 520         | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
 521         | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
 522         | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
 523         | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
 524         | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
 525
 526 /*
 527  * TXE SDMA Error flags
 528  */
 529 static struct flag_table sdma_err_status_flags[] = {
 530 /* 0*/  FLAG_ENTRY0("SDmaRpyTagErr",
 531                 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
 532 /* 1*/  FLAG_ENTRY0("SDmaCsrParityErr",
 533                 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
 534 /* 2*/  FLAG_ENTRY0("SDmaPcieReqTrackingUncErr",
 535                 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
 536 /* 3*/  FLAG_ENTRY0("SDmaPcieReqTrackingCorErr",
 537                 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
 538 /*04-63 reserved*/
 539 };
 540
 541 /* TXE SDMA errors that cause an SPC freeze */
 542 #define ALL_SDMA_FREEZE_ERR  \
 543                 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
 544                 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
 545                 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
 546
 547 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
 548 #define PORT_DISCARD_EGRESS_ERRS \
 549         (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
 550         | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
 551         | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
 552
 553 /*
 554  * TXE Egress Error flags
 555  */
 556 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
 557 static struct flag_table egress_err_status_flags[] = {
 558 /* 0*/  FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)),
 559 /* 1*/  FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)),
 560 /* 2 reserved */
 561 /* 3*/  FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr",
 562                 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)),
 563 /* 4*/  FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)),
 564 /* 5*/  FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)),
 565 /* 6 reserved */
 566 /* 7*/  FLAG_ENTRY0("TxPioLaunchIntfParityErr",
 567                 SEES(TX_PIO_LAUNCH_INTF_PARITY)),
 568 /* 8*/  FLAG_ENTRY0("TxSdmaLaunchIntfParityErr",
 569                 SEES(TX_SDMA_LAUNCH_INTF_PARITY)),
 570 /* 9-10 reserved */
 571 /*11*/  FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr",
 572                 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)),
 573 /*12*/  FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)),
 574 /*13*/  FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)),
 575 /*14*/  FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)),
 576 /*15*/  FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)),
 577 /*16*/  FLAG_ENTRY0("TxSdma0DisallowedPacketErr",
 578                 SEES(TX_SDMA0_DISALLOWED_PACKET)),
 579 /*17*/  FLAG_ENTRY0("TxSdma1DisallowedPacketErr",
 580                 SEES(TX_SDMA1_DISALLOWED_PACKET)),
 581 /*18*/  FLAG_ENTRY0("TxSdma2DisallowedPacketErr",
 582                 SEES(TX_SDMA2_DISALLOWED_PACKET)),
 583 /*19*/  FLAG_ENTRY0("TxSdma3DisallowedPacketErr",
 584                 SEES(TX_SDMA3_DISALLOWED_PACKET)),
 585 /*20*/  FLAG_ENTRY0("TxSdma4DisallowedPacketErr",
 586                 SEES(TX_SDMA4_DISALLOWED_PACKET)),
 587 /*21*/  FLAG_ENTRY0("TxSdma5DisallowedPacketErr",
 588                 SEES(TX_SDMA5_DISALLOWED_PACKET)),
 589 /*22*/  FLAG_ENTRY0("TxSdma6DisallowedPacketErr",
 590                 SEES(TX_SDMA6_DISALLOWED_PACKET)),
 591 /*23*/  FLAG_ENTRY0("TxSdma7DisallowedPacketErr",
 592                 SEES(TX_SDMA7_DISALLOWED_PACKET)),
 593 /*24*/  FLAG_ENTRY0("TxSdma8DisallowedPacketErr",
 594                 SEES(TX_SDMA8_DISALLOWED_PACKET)),
 595 /*25*/  FLAG_ENTRY0("TxSdma9DisallowedPacketErr",
 596                 SEES(TX_SDMA9_DISALLOWED_PACKET)),
 597 /*26*/  FLAG_ENTRY0("TxSdma10DisallowedPacketErr",
 598                 SEES(TX_SDMA10_DISALLOWED_PACKET)),
 599 /*27*/  FLAG_ENTRY0("TxSdma11DisallowedPacketErr",
 600                 SEES(TX_SDMA11_DISALLOWED_PACKET)),
 601 /*28*/  FLAG_ENTRY0("TxSdma12DisallowedPacketErr",
 602                 SEES(TX_SDMA12_DISALLOWED_PACKET)),
 603 /*29*/  FLAG_ENTRY0("TxSdma13DisallowedPacketErr",
 604                 SEES(TX_SDMA13_DISALLOWED_PACKET)),
 605 /*30*/  FLAG_ENTRY0("TxSdma14DisallowedPacketErr",
 606                 SEES(TX_SDMA14_DISALLOWED_PACKET)),
 607 /*31*/  FLAG_ENTRY0("TxSdma15DisallowedPacketErr",
 608                 SEES(TX_SDMA15_DISALLOWED_PACKET)),
 609 /*32*/  FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr",
 610                 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)),
 611 /*33*/  FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr",
 612                 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)),
 613 /*34*/  FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr",
 614                 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)),
 615 /*35*/  FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr",
 616                 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)),
 617 /*36*/  FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr",
 618                 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)),
 619 /*37*/  FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr",
 620                 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)),
 621 /*38*/  FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr",
 622                 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)),
 623 /*39*/  FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr",
 624                 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)),
 625 /*40*/  FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr",
 626                 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)),
 627 /*41*/  FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)),
 628 /*42*/  FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)),
 629 /*43*/  FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)),
 630 /*44*/  FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)),
 631 /*45*/  FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)),
 632 /*46*/  FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)),
 633 /*47*/  FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)),
 634 /*48*/  FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)),
 635 /*49*/  FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)),
 636 /*50*/  FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)),
 637 /*51*/  FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)),
 638 /*52*/  FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)),
 639 /*53*/  FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)),
 640 /*54*/  FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)),
 641 /*55*/  FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)),
 642 /*56*/  FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)),
 643 /*57*/  FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)),
 644 /*58*/  FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)),
 645 /*59*/  FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)),
 646 /*60*/  FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)),
 647 /*61*/  FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)),
 648 /*62*/  FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr",
 649                 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)),
 650 /*63*/  FLAG_ENTRY0("TxReadPioMemoryCsrUncErr",
 651                 SEES(TX_READ_PIO_MEMORY_CSR_UNC)),
 652 };
 653
 654 /*
 655  * TXE Egress Error Info flags
 656  */
 657 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
 658 static struct flag_table egress_err_info_flags[] = {
 659 /* 0*/  FLAG_ENTRY0("Reserved", 0ull),
 660 /* 1*/  FLAG_ENTRY0("VLErr", SEEI(VL)),
 661 /* 2*/  FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
 662 /* 3*/  FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
 663 /* 4*/  FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)),
 664 /* 5*/  FLAG_ENTRY0("SLIDErr", SEEI(SLID)),
 665 /* 6*/  FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)),
 666 /* 7*/  FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)),
 667 /* 8*/  FLAG_ENTRY0("RawErr", SEEI(RAW)),
 668 /* 9*/  FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)),
 669 /*10*/  FLAG_ENTRY0("GRHErr", SEEI(GRH)),
 670 /*11*/  FLAG_ENTRY0("BypassErr", SEEI(BYPASS)),
 671 /*12*/  FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)),
 672 /*13*/  FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)),
 673 /*14*/  FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)),
 674 /*15*/  FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)),
 675 /*16*/  FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)),
 676 /*17*/  FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)),
 677 /*18*/  FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)),
 678 /*19*/  FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)),
 679 /*20*/  FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)),
 680 /*21*/  FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)),
 681 };
 682
 683 /* TXE Egress errors that cause an SPC freeze */
 684 #define ALL_TXE_EGRESS_FREEZE_ERR \
 685         (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
 686         | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
 687         | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
 688         | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
 689         | SEES(TX_LAUNCH_CSR_PARITY) \
 690         | SEES(TX_SBRD_CTL_CSR_PARITY) \
 691         | SEES(TX_CONFIG_PARITY) \
 692         | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
 693         | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
 694         | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
 695         | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
 696         | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
 697         | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
 698         | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
 699         | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
 700         | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
 701         | SEES(TX_CREDIT_RETURN_PARITY))
 702
 703 /*
 704  * TXE Send error flags
 705  */
 706 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
 707 static struct flag_table send_err_status_flags[] = {
 708 /* 0*/  FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)),
 709 /* 1*/  FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)),
 710 /* 2*/  FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR))
 711 };
 712
 713 /*
 714  * TXE Send Context Error flags and consequences
 715  */
 716 static struct flag_table sc_err_status_flags[] = {
 717 /* 0*/  FLAG_ENTRY("InconsistentSop",
 718                 SEC_PACKET_DROPPED | SEC_SC_HALTED,
 719                 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
 720 /* 1*/  FLAG_ENTRY("DisallowedPacket",
 721                 SEC_PACKET_DROPPED | SEC_SC_HALTED,
 722                 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
 723 /* 2*/  FLAG_ENTRY("WriteCrossesBoundary",
 724                 SEC_WRITE_DROPPED | SEC_SC_HALTED,
 725                 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
 726 /* 3*/  FLAG_ENTRY("WriteOverflow",
 727                 SEC_WRITE_DROPPED | SEC_SC_HALTED,
 728                 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
 729 /* 4*/  FLAG_ENTRY("WriteOutOfBounds",
 730                 SEC_WRITE_DROPPED | SEC_SC_HALTED,
 731                 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
 732 /* 5-63 reserved*/
 733 };
 734
 735 /*
 736  * RXE Receive Error flags
 737  */
 738 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
 739 static struct flag_table rxe_err_status_flags[] = {
 740 /* 0*/  FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)),
 741 /* 1*/  FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)),
 742 /* 2*/  FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)),
 743 /* 3*/  FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)),
 744 /* 4*/  FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)),
 745 /* 5*/  FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)),
 746 /* 6*/  FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)),
 747 /* 7*/  FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)),
 748 /* 8*/  FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)),
 749 /* 9*/  FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)),
 750 /*10*/  FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)),
 751 /*11*/  FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)),
 752 /*12*/  FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)),
 753 /*13*/  FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)),
 754 /*14*/  FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)),
 755 /*15*/  FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)),
 756 /*16*/  FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr",
 757                 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)),
 758 /*17*/  FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)),
 759 /*18*/  FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)),
 760 /*19*/  FLAG_ENTRY0("RxRbufBlockListReadUncErr",
 761                 RXES(RBUF_BLOCK_LIST_READ_UNC)),
 762 /*20*/  FLAG_ENTRY0("RxRbufBlockListReadCorErr",
 763                 RXES(RBUF_BLOCK_LIST_READ_COR)),
 764 /*21*/  FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr",
 765                 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)),
 766 /*22*/  FLAG_ENTRY0("RxRbufCsrQEntCntParityErr",
 767                 RXES(RBUF_CSR_QENT_CNT_PARITY)),
 768 /*23*/  FLAG_ENTRY0("RxRbufCsrQNextBufParityErr",
 769                 RXES(RBUF_CSR_QNEXT_BUF_PARITY)),
 770 /*24*/  FLAG_ENTRY0("RxRbufCsrQVldBitParityErr",
 771                 RXES(RBUF_CSR_QVLD_BIT_PARITY)),
 772 /*25*/  FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)),
 773 /*26*/  FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)),
 774 /*27*/  FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr",
 775                 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)),
 776 /*28*/  FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)),
 777 /*29*/  FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)),
 778 /*30*/  FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)),
 779 /*31*/  FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)),
 780 /*32*/  FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)),
 781 /*33*/  FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)),
 782 /*34*/  FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)),
 783 /*35*/  FLAG_ENTRY0("RxRbufFlInitdoneParityErr",
 784                 RXES(RBUF_FL_INITDONE_PARITY)),
 785 /*36*/  FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr",
 786                 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)),
 787 /*37*/  FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)),
 788 /*38*/  FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)),
 789 /*39*/  FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)),
 790 /*40*/  FLAG_ENTRY0("RxLookupDesPart1UncCorErr",
 791                 RXES(LOOKUP_DES_PART1_UNC_COR)),
 792 /*41*/  FLAG_ENTRY0("RxLookupDesPart2ParityErr",
 793                 RXES(LOOKUP_DES_PART2_PARITY)),
 794 /*42*/  FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)),
 795 /*43*/  FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)),
 796 /*44*/  FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)),
 797 /*45*/  FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)),
 798 /*46*/  FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)),
 799 /*47*/  FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)),
 800 /*48*/  FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)),
 801 /*49*/  FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)),
 802 /*50*/  FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)),
 803 /*51*/  FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)),
 804 /*52*/  FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)),
 805 /*53*/  FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)),
 806 /*54*/  FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)),
 807 /*55*/  FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)),
 808 /*56*/  FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)),
 809 /*57*/  FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)),
 810 /*58*/  FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)),
 811 /*59*/  FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)),
 812 /*60*/  FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)),
 813 /*61*/  FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)),
 814 /*62*/  FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)),
 815 /*63*/  FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY))
 816 };
 817
 818 /* RXE errors that will trigger an SPC freeze */
 819 #define ALL_RXE_FREEZE_ERR  \
 820         (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
 821         | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
 822         | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
 823         | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
 824         | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
 825         | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
 826         | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
 827         | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
 828         | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
 829         | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
 830         | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
 831         | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
 832         | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
 833         | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
 834         | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
 835         | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
 836         | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
 837         | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
 838         | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
 839         | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
 840         | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
 841         | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
 842         | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
 843         | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
 844         | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
 845         | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
 846         | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
 847         | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
 848         | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
 849         | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
 850         | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
 851         | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
 852         | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
 853         | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
 854         | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
 855         | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
 856         | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
 857         | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
 858         | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
 859         | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
 860         | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
 861         | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
 862         | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
 863         | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
 864
 865 #define RXE_FREEZE_ABORT_MASK \
 866         (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
 867         RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
 868         RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
 869
 870 /*
 871  * DCC Error Flags
 872  */
 873 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK
 874 static struct flag_table dcc_err_flags[] = {
 875         FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)),
 876         FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)),
 877         FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)),
 878         FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)),
 879         FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)),
 880         FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)),
 881         FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)),
 882         FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)),
 883         FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)),
 884         FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)),
 885         FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)),
 886         FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)),
 887         FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)),
 888         FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)),
 889         FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)),
 890         FLAG_ENTRY0("link_err", DCCE(LINK_ERR)),
 891         FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)),
 892         FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)),
 893         FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)),
 894         FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)),
 895         FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)),
 896         FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)),
 897         FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)),
 898         FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)),
 899         FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)),
 900         FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)),
 901         FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)),
 902         FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)),
 903         FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)),
 904         FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)),
 905         FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)),
 906         FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)),
 907         FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)),
 908         FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)),
 909         FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)),
 910         FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)),
 911         FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)),
 912         FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)),
 913         FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)),
 914         FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)),
 915         FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)),
 916         FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)),
 917         FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)),
 918         FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)),
 919         FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)),
 920         FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)),
 921 };
 922
 923 /*
 924  * LCB error flags
 925  */
 926 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
 927 static struct flag_table lcb_err_flags[] = {
 928 /* 0*/  FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)),
 929 /* 1*/  FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)),
 930 /* 2*/  FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)),
 931 /* 3*/  FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST",
 932                 LCBE(ALL_LNS_FAILED_REINIT_TEST)),
 933 /* 4*/  FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)),
 934 /* 5*/  FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)),
 935 /* 6*/  FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)),
 936 /* 7*/  FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)),
 937 /* 8*/  FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)),
 938 /* 9*/  FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)),
 939 /*10*/  FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)),
 940 /*11*/  FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)),
 941 /*12*/  FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)),
 942 /*13*/  FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER",
 943                 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)),
 944 /*14*/  FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)),
 945 /*15*/  FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)),
 946 /*16*/  FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)),
 947 /*17*/  FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)),
 948 /*18*/  FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)),
 949 /*19*/  FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE",
 950                 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)),
 951 /*20*/  FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)),
 952 /*21*/  FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)),
 953 /*22*/  FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)),
 954 /*23*/  FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)),
 955 /*24*/  FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)),
 956 /*25*/  FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)),
 957 /*26*/  FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP",
 958                 LCBE(RST_FOR_INCOMPLT_RND_TRIP)),
 959 /*27*/  FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)),
 960 /*28*/  FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE",
 961                 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)),
 962 /*29*/  FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR",
 963                 LCBE(REDUNDANT_FLIT_PARITY_ERR))
 964 };
 965
 966 /*
 967  * DC8051 Error Flags
 968  */
 969 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
 970 static struct flag_table dc8051_err_flags[] = {
 971         FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)),
 972         FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)),
 973         FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)),
 974         FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)),
 975         FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)),
 976         FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)),
 977         FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)),
 978         FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)),
 979         FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES",
 980                     D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)),
 981         FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)),
 982 };
 983
 984 /*
 985  * DC8051 Information Error flags
 986  *
 987  * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
 988  */
 989 static struct flag_table dc8051_info_err_flags[] = {
 990         FLAG_ENTRY0("Spico ROM check failed",  SPICO_ROM_FAILED),
 991         FLAG_ENTRY0("Unknown frame received",  UNKNOWN_FRAME),
 992         FLAG_ENTRY0("Target BER not met",      TARGET_BER_NOT_MET),
 993         FLAG_ENTRY0("Serdes internal loopback failure",
 994                     FAILED_SERDES_INTERNAL_LOOPBACK),
 995         FLAG_ENTRY0("Failed SerDes init",      FAILED_SERDES_INIT),
 996         FLAG_ENTRY0("Failed LNI(Polling)",     FAILED_LNI_POLLING),
 997         FLAG_ENTRY0("Failed LNI(Debounce)",    FAILED_LNI_DEBOUNCE),
 998         FLAG_ENTRY0("Failed LNI(EstbComm)",    FAILED_LNI_ESTBCOMM),
 999         FLAG_ENTRY0("Failed LNI(OptEq)",       FAILED_LNI_OPTEQ),
1000         FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1),
1001         FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2),
1002         FLAG_ENTRY0("Failed LNI(ConfigLT)",    FAILED_LNI_CONFIGLT),
1003         FLAG_ENTRY0("Host Handshake Timeout",  HOST_HANDSHAKE_TIMEOUT),
1004         FLAG_ENTRY0("External Device Request Timeout",
1005                     EXTERNAL_DEVICE_REQ_TIMEOUT),
1006 };
1007
1008 /*
1009  * DC8051 Information Host Information flags
1010  *
1011  * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
1012  */
1013 static struct flag_table dc8051_info_host_msg_flags[] = {
1014         FLAG_ENTRY0("Host request done", 0x0001),
1015         FLAG_ENTRY0("BC PWR_MGM message", 0x0002),
1016         FLAG_ENTRY0("BC SMA message", 0x0004),
1017         FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008),
1018         FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010),
1019         FLAG_ENTRY0("External device config request", 0x0020),
1020         FLAG_ENTRY0("VerifyCap all frames received", 0x0040),
1021         FLAG_ENTRY0("LinkUp achieved", 0x0080),
1022         FLAG_ENTRY0("Link going down", 0x0100),
1023         FLAG_ENTRY0("Link width downgraded", 0x0200),
1024 };
1025
1026 static u32 encoded_size(u32 size);
1027 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate);
1028 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state);
1029 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
1030                                u8 *continuous);
1031 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
1032                                   u8 *vcu, u16 *vl15buf, u8 *crc_sizes);
1033 static void read_vc_remote_link_width(struct hfi1_devdata *dd,
1034                                       u8 *remote_tx_rate, u16 *link_widths);
1035 static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
1036                                      u8 *flag_bits, u16 *link_widths);
1037 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
1038                                   u8 *device_rev);
1039 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx);
1040 static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx,
1041                             u8 *tx_polarity_inversion,
1042                             u8 *rx_polarity_inversion, u8 *max_rate);
1043 static void handle_sdma_eng_err(struct hfi1_devdata *dd,
1044                                 unsigned int context, u64 err_status);
1045 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg);
1046 static void handle_dcc_err(struct hfi1_devdata *dd,
1047                            unsigned int context, u64 err_status);
1048 static void handle_lcb_err(struct hfi1_devdata *dd,
1049                            unsigned int context, u64 err_status);
1050 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg);
1051 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1052 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1053 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1054 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1055 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1056 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1057 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1058 static void set_partition_keys(struct hfi1_pportdata *ppd);
1059 static const char *link_state_name(u32 state);
1060 static const char *link_state_reason_name(struct hfi1_pportdata *ppd,
1061                                           u32 state);
1062 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
1063                            u64 *out_data);
1064 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data);
1065 static int thermal_init(struct hfi1_devdata *dd);
1066
1067 static void update_statusp(struct hfi1_pportdata *ppd, u32 state);
1068 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd,
1069                                             int msecs);
1070 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
1071                                   int msecs);
1072 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state);
1073 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state);
1074 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state,
1075                                    int msecs);
1076 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc);
1077 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr);
1078 static void handle_temp_err(struct hfi1_devdata *dd);
1079 static void dc_shutdown(struct hfi1_devdata *dd);
1080 static void dc_start(struct hfi1_devdata *dd);
1081 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
1082                            unsigned int *np);
1083 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd);
1084 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms);
1085 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index);
1086 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width);
1087
1088 /*
1089  * Error interrupt table entry.  This is used as input to the interrupt
1090  * "clear down" routine used for all second tier error interrupt register.
1091  * Second tier interrupt registers have a single bit representing them
1092  * in the top-level CceIntStatus.
1093  */
1094 struct err_reg_info {
1095         u32 status;             /* status CSR offset */
1096         u32 clear;              /* clear CSR offset */
1097         u32 mask;               /* mask CSR offset */
1098         void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg);
1099         const char *desc;
1100 };
1101
1102 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END - IS_GENERAL_ERR_START)
1103 #define NUM_DC_ERRS (IS_DC_END - IS_DC_START)
1104 #define NUM_VARIOUS (IS_VARIOUS_END - IS_VARIOUS_START)
1105
1106 /*
1107  * Helpers for building HFI and DC error interrupt table entries.  Different
1108  * helpers are needed because of inconsistent register names.
1109  */
1110 #define EE(reg, handler, desc) \
1111         { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1112                 handler, desc }
1113 #define DC_EE1(reg, handler, desc) \
1114         { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1115 #define DC_EE2(reg, handler, desc) \
1116         { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1117
1118 /*
1119  * Table of the "misc" grouping of error interrupts.  Each entry refers to
1120  * another register containing more information.
1121  */
1122 static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = {
1123 /* 0*/  EE(CCE_ERR,             handle_cce_err,    "CceErr"),
1124 /* 1*/  EE(RCV_ERR,             handle_rxe_err,    "RxeErr"),
1125 /* 2*/  EE(MISC_ERR,    handle_misc_err,   "MiscErr"),
1126 /* 3*/  { 0, 0, 0, NULL }, /* reserved */
1127 /* 4*/  EE(SEND_PIO_ERR,    handle_pio_err,    "PioErr"),
1128 /* 5*/  EE(SEND_DMA_ERR,    handle_sdma_err,   "SDmaErr"),
1129 /* 6*/  EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"),
1130 /* 7*/  EE(SEND_ERR,    handle_txe_err,    "TxeErr")
1131         /* the rest are reserved */
1132 };
1133
1134 /*
1135  * Index into the Various section of the interrupt sources
1136  * corresponding to the Critical Temperature interrupt.
1137  */
1138 #define TCRIT_INT_SOURCE 4
1139
1140 /*
1141  * SDMA error interrupt entry - refers to another register containing more
1142  * information.
1143  */
1144 static const struct err_reg_info sdma_eng_err =
1145         EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr");
1146
1147 static const struct err_reg_info various_err[NUM_VARIOUS] = {
1148 /* 0*/  { 0, 0, 0, NULL }, /* PbcInt */
1149 /* 1*/  { 0, 0, 0, NULL }, /* GpioAssertInt */
1150 /* 2*/  EE(ASIC_QSFP1,  handle_qsfp_int,        "QSFP1"),
1151 /* 3*/  EE(ASIC_QSFP2,  handle_qsfp_int,        "QSFP2"),
1152 /* 4*/  { 0, 0, 0, NULL }, /* TCritInt */
1153         /* rest are reserved */
1154 };
1155
1156 /*
1157  * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1158  * register can not be derived from the MTU value because 10K is not
1159  * a power of 2. Therefore, we need a constant. Everything else can
1160  * be calculated.
1161  */
1162 #define DCC_CFG_PORT_MTU_CAP_10240 7
1163
1164 /*
1165  * Table of the DC grouping of error interrupts.  Each entry refers to
1166  * another register containing more information.
1167  */
1168 static const struct err_reg_info dc_errs[NUM_DC_ERRS] = {
1169 /* 0*/  DC_EE1(DCC_ERR,         handle_dcc_err,        "DCC Err"),
1170 /* 1*/  DC_EE2(DC_LCB_ERR,      handle_lcb_err,        "LCB Err"),
1171 /* 2*/  DC_EE2(DC_DC8051_ERR,   handle_8051_interrupt, "DC8051 Interrupt"),
1172 /* 3*/  /* dc_lbm_int - special, see is_dc_int() */
1173         /* the rest are reserved */
1174 };
1175
1176 struct cntr_entry {
1177         /*
1178          * counter name
1179          */
1180         char *name;
1181
1182         /*
1183          * csr to read for name (if applicable)
1184          */
1185         u64 csr;
1186
1187         /*
1188          * offset into dd or ppd to store the counter's value
1189          */
1190         int offset;
1191
1192         /*
1193          * flags
1194          */
1195         u8 flags;
1196
1197         /*
1198          * accessor for stat element, context either dd or ppd
1199          */
1200         u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl,
1201                        int mode, u64 data);
1202 };
1203
1204 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1205 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1206
1207 #define CNTR_ELEM(name, csr, offset, flags, accessor) \
1208 { \
1209         name, \
1210         csr, \
1211         offset, \
1212         flags, \
1213         accessor \
1214 }
1215
1216 /* 32bit RXE */
1217 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1218 CNTR_ELEM(#name, \
1219           (counter * 8 + RCV_COUNTER_ARRAY32), \
1220           0, flags | CNTR_32BIT, \
1221           port_access_u32_csr)
1222
1223 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1224 CNTR_ELEM(#name, \
1225           (counter * 8 + RCV_COUNTER_ARRAY32), \
1226           0, flags | CNTR_32BIT, \
1227           dev_access_u32_csr)
1228
1229 /* 64bit RXE */
1230 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1231 CNTR_ELEM(#name, \
1232           (counter * 8 + RCV_COUNTER_ARRAY64), \
1233           0, flags, \
1234           port_access_u64_csr)
1235
1236 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1237 CNTR_ELEM(#name, \
1238           (counter * 8 + RCV_COUNTER_ARRAY64), \
1239           0, flags, \
1240           dev_access_u64_csr)
1241
1242 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1243 #define OVR_ELM(ctx) \
1244 CNTR_ELEM("RcvHdrOvr" #ctx, \
1245           (RCV_HDR_OVFL_CNT + ctx * 0x100), \
1246           0, CNTR_NORMAL, port_access_u64_csr)
1247
1248 /* 32bit TXE */
1249 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1250 CNTR_ELEM(#name, \
1251           (counter * 8 + SEND_COUNTER_ARRAY32), \
1252           0, flags | CNTR_32BIT, \
1253           port_access_u32_csr)
1254
1255 /* 64bit TXE */
1256 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1257 CNTR_ELEM(#name, \
1258           (counter * 8 + SEND_COUNTER_ARRAY64), \
1259           0, flags, \
1260           port_access_u64_csr)
1261
1262 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1263 CNTR_ELEM(#name,\
1264           counter * 8 + SEND_COUNTER_ARRAY64, \
1265           0, \
1266           flags, \
1267           dev_access_u64_csr)
1268
1269 /* CCE */
1270 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1271 CNTR_ELEM(#name, \
1272           (counter * 8 + CCE_COUNTER_ARRAY32), \
1273           0, flags | CNTR_32BIT, \
1274           dev_access_u32_csr)
1275
1276 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1277 CNTR_ELEM(#name, \
1278           (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1279           0, flags | CNTR_32BIT, \
1280           dev_access_u32_csr)
1281
1282 /* DC */
1283 #define DC_PERF_CNTR(name, counter, flags) \
1284 CNTR_ELEM(#name, \
1285           counter, \
1286           0, \
1287           flags, \
1288           dev_access_u64_csr)
1289
1290 #define DC_PERF_CNTR_LCB(name, counter, flags) \
1291 CNTR_ELEM(#name, \
1292           counter, \
1293           0, \
1294           flags, \
1295           dc_access_lcb_cntr)
1296
1297 /* ibp counters */
1298 #define SW_IBP_CNTR(name, cntr) \
1299 CNTR_ELEM(#name, \
1300           0, \
1301           0, \
1302           CNTR_SYNTH, \
1303           access_ibp_##cntr)
1304
1305 /**
1306  * hfi_addr_from_offset - return addr for readq/writeq
1307  * @dd - the dd device
1308  * @offset - the offset of the CSR within bar0
1309  *
1310  * This routine selects the appropriate base address
1311  * based on the indicated offset.
1312  */
1313 static inline void __iomem *hfi1_addr_from_offset(
1314         const struct hfi1_devdata *dd,
1315         u32 offset)
1316 {
1317         if (offset >= dd->base2_start)
1318                 return dd->kregbase2 + (offset - dd->base2_start);
1319         return dd->kregbase1 + offset;
1320 }
1321
1322 /**
1323  * read_csr - read CSR at the indicated offset
1324  * @dd - the dd device
1325  * @offset - the offset of the CSR within bar0
1326  *
1327  * Return: the value read or all FF's if there
1328  * is no mapping
1329  */
1330 u64 read_csr(const struct hfi1_devdata *dd, u32 offset)
1331 {
1332         if (dd->flags & HFI1_PRESENT)
1333                 return readq(hfi1_addr_from_offset(dd, offset));
1334         return -1;
1335 }
1336
1337 /**
1338  * write_csr - write CSR at the indicated offset
1339  * @dd - the dd device
1340  * @offset - the offset of the CSR within bar0
1341  * @value - value to write
1342  */
1343 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value)
1344 {
1345         if (dd->flags & HFI1_PRESENT) {
1346                 void __iomem *base = hfi1_addr_from_offset(dd, offset);
1347
1348                 /* avoid write to RcvArray */
1349                 if (WARN_ON(offset >= RCV_ARRAY && offset < dd->base2_start))
1350                         return;
1351                 writeq(value, base);
1352         }
1353 }
1354
1355 /**
1356  * get_csr_addr - return te iomem address for offset
1357  * @dd - the dd device
1358  * @offset - the offset of the CSR within bar0
1359  *
1360  * Return: The iomem address to use in subsequent
1361  * writeq/readq operations.
1362  */
1363 void __iomem *get_csr_addr(
1364         const struct hfi1_devdata *dd,
1365         u32 offset)
1366 {
1367         if (dd->flags & HFI1_PRESENT)
1368                 return hfi1_addr_from_offset(dd, offset);
1369         return NULL;
1370 }
1371
1372 static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr,
1373                                  int mode, u64 value)
1374 {
1375         u64 ret;
1376
1377         if (mode == CNTR_MODE_R) {
1378                 ret = read_csr(dd, csr);
1379         } else if (mode == CNTR_MODE_W) {
1380                 write_csr(dd, csr, value);
1381                 ret = value;
1382         } else {
1383                 dd_dev_err(dd, "Invalid cntr register access mode");
1384                 return 0;
1385         }
1386
1387         hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);
1388         return ret;
1389 }
1390
1391 /* Dev Access */
1392 static u64 dev_access_u32_csr(const struct cntr_entry *entry,
1393                               void *context, int vl, int mode, u64 data)
1394 {
1395         struct hfi1_devdata *dd = context;
1396         u64 csr = entry->csr;
1397
1398         if (entry->flags & CNTR_SDMA) {
1399                 if (vl == CNTR_INVALID_VL)
1400                         return 0;
1401                 csr += 0x100 * vl;
1402         } else {
1403                 if (vl != CNTR_INVALID_VL)
1404                         return 0;
1405         }
1406         return read_write_csr(dd, csr, mode, data);
1407 }
1408
1409 static u64 access_sde_err_cnt(const struct cntr_entry *entry,
1410                               void *context, int idx, int mode, u64 data)
1411 {
1412         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1413
1414         if (dd->per_sdma && idx < dd->num_sdma)
1415                 return dd->per_sdma[idx].err_cnt;
1416         return 0;
1417 }
1418
1419 static u64 access_sde_int_cnt(const struct cntr_entry *entry,
1420                               void *context, int idx, int mode, u64 data)
1421 {
1422         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1423
1424         if (dd->per_sdma && idx < dd->num_sdma)
1425                 return dd->per_sdma[idx].sdma_int_cnt;
1426         return 0;
1427 }
1428
1429 static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry,
1430                                    void *context, int idx, int mode, u64 data)
1431 {
1432         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1433
1434         if (dd->per_sdma && idx < dd->num_sdma)
1435                 return dd->per_sdma[idx].idle_int_cnt;
1436         return 0;
1437 }
1438
1439 static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry,
1440                                        void *context, int idx, int mode,
1441                                        u64 data)
1442 {
1443         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1444
1445         if (dd->per_sdma && idx < dd->num_sdma)
1446                 return dd->per_sdma[idx].progress_int_cnt;
1447         return 0;
1448 }
1449
1450 static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context,
1451                               int vl, int mode, u64 data)
1452 {
1453         struct hfi1_devdata *dd = context;
1454
1455         u64 val = 0;
1456         u64 csr = entry->csr;
1457
1458         if (entry->flags & CNTR_VL) {
1459                 if (vl == CNTR_INVALID_VL)
1460                         return 0;
1461                 csr += 8 * vl;
1462         } else {
1463                 if (vl != CNTR_INVALID_VL)
1464                         return 0;
1465         }
1466
1467         val = read_write_csr(dd, csr, mode, data);
1468         return val;
1469 }
1470
1471 static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context,
1472                               int vl, int mode, u64 data)
1473 {
1474         struct hfi1_devdata *dd = context;
1475         u32 csr = entry->csr;
1476         int ret = 0;
1477
1478         if (vl != CNTR_INVALID_VL)
1479                 return 0;
1480         if (mode == CNTR_MODE_R)
1481                 ret = read_lcb_csr(dd, csr, &data);
1482         else if (mode == CNTR_MODE_W)
1483                 ret = write_lcb_csr(dd, csr, data);
1484
1485         if (ret) {
1486                 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr);
1487                 return 0;
1488         }
1489
1490         hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);
1491         return data;
1492 }
1493
1494 /* Port Access */
1495 static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context,
1496                                int vl, int mode, u64 data)
1497 {
1498         struct hfi1_pportdata *ppd = context;
1499
1500         if (vl != CNTR_INVALID_VL)
1501                 return 0;
1502         return read_write_csr(ppd->dd, entry->csr, mode, data);
1503 }
1504
1505 static u64 port_access_u64_csr(const struct cntr_entry *entry,
1506                                void *context, int vl, int mode, u64 data)
1507 {
1508         struct hfi1_pportdata *ppd = context;
1509         u64 val;
1510         u64 csr = entry->csr;
1511
1512         if (entry->flags & CNTR_VL) {
1513                 if (vl == CNTR_INVALID_VL)
1514                         return 0;
1515                 csr += 8 * vl;
1516         } else {
1517                 if (vl != CNTR_INVALID_VL)
1518                         return 0;
1519         }
1520         val = read_write_csr(ppd->dd, csr, mode, data);
1521         return val;
1522 }
1523
1524 /* Software defined */
1525 static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode,
1526                                 u64 data)
1527 {
1528         u64 ret;
1529
1530         if (mode == CNTR_MODE_R) {
1531                 ret = *cntr;
1532         } else if (mode == CNTR_MODE_W) {
1533                 *cntr = data;
1534                 ret = data;
1535         } else {
1536                 dd_dev_err(dd, "Invalid cntr sw access mode");
1537                 return 0;
1538         }
1539
1540         hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);
1541
1542         return ret;
1543 }
1544
1545 static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context,
1546                                  int vl, int mode, u64 data)
1547 {
1548         struct hfi1_pportdata *ppd = context;
1549
1550         if (vl != CNTR_INVALID_VL)
1551                 return 0;
1552         return read_write_sw(ppd->dd, &ppd->link_downed, mode, data);
1553 }
1554
1555 static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context,
1556                                  int vl, int mode, u64 data)
1557 {
1558         struct hfi1_pportdata *ppd = context;
1559
1560         if (vl != CNTR_INVALID_VL)
1561                 return 0;
1562         return read_write_sw(ppd->dd, &ppd->link_up, mode, data);
1563 }
1564
1565 static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry,
1566                                        void *context, int vl, int mode,
1567                                        u64 data)
1568 {
1569         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1570
1571         if (vl != CNTR_INVALID_VL)
1572                 return 0;
1573         return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data);
1574 }
1575
1576 static u64 access_sw_xmit_discards(const struct cntr_entry *entry,
1577                                    void *context, int vl, int mode, u64 data)
1578 {
1579         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1580         u64 zero = 0;
1581         u64 *counter;
1582
1583         if (vl == CNTR_INVALID_VL)
1584                 counter = &ppd->port_xmit_discards;
1585         else if (vl >= 0 && vl < C_VL_COUNT)
1586                 counter = &ppd->port_xmit_discards_vl[vl];
1587         else
1588                 counter = &zero;
1589
1590         return read_write_sw(ppd->dd, counter, mode, data);
1591 }
1592
1593 static u64 access_xmit_constraint_errs(const struct cntr_entry *entry,
1594                                        void *context, int vl, int mode,
1595                                        u64 data)
1596 {
1597         struct hfi1_pportdata *ppd = context;
1598
1599         if (vl != CNTR_INVALID_VL)
1600                 return 0;
1601
1602         return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors,
1603                              mode, data);
1604 }
1605
1606 static u64 access_rcv_constraint_errs(const struct cntr_entry *entry,
1607                                       void *context, int vl, int mode, u64 data)
1608 {
1609         struct hfi1_pportdata *ppd = context;
1610
1611         if (vl != CNTR_INVALID_VL)
1612                 return 0;
1613
1614         return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors,
1615                              mode, data);
1616 }
1617
1618 u64 get_all_cpu_total(u64 __percpu *cntr)
1619 {
1620         int cpu;
1621         u64 counter = 0;
1622
1623         for_each_possible_cpu(cpu)
1624                 counter += *per_cpu_ptr(cntr, cpu);
1625         return counter;
1626 }
1627
1628 static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val,
1629                           u64 __percpu *cntr,
1630                           int vl, int mode, u64 data)
1631 {
1632         u64 ret = 0;
1633
1634         if (vl != CNTR_INVALID_VL)
1635                 return 0;
1636
1637         if (mode == CNTR_MODE_R) {
1638                 ret = get_all_cpu_total(cntr) - *z_val;
1639         } else if (mode == CNTR_MODE_W) {
1640                 /* A write can only zero the counter */
1641                 if (data == 0)
1642                         *z_val = get_all_cpu_total(cntr);
1643                 else
1644                         dd_dev_err(dd, "Per CPU cntrs can only be zeroed");
1645         } else {
1646                 dd_dev_err(dd, "Invalid cntr sw cpu access mode");
1647                 return 0;
1648         }
1649
1650         return ret;
1651 }
1652
1653 static u64 access_sw_cpu_intr(const struct cntr_entry *entry,
1654                               void *context, int vl, int mode, u64 data)
1655 {
1656         struct hfi1_devdata *dd = context;
1657
1658         return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl,
1659                               mode, data);
1660 }
1661
1662 static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry,
1663                                    void *context, int vl, int mode, u64 data)
1664 {
1665         struct hfi1_devdata *dd = context;
1666
1667         return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl,
1668                               mode, data);
1669 }
1670
1671 static u64 access_sw_pio_wait(const struct cntr_entry *entry,
1672                               void *context, int vl, int mode, u64 data)
1673 {
1674         struct hfi1_devdata *dd = context;
1675
1676         return dd->verbs_dev.n_piowait;
1677 }
1678
1679 static u64 access_sw_pio_drain(const struct cntr_entry *entry,
1680                                void *context, int vl, int mode, u64 data)
1681 {
1682         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1683
1684         return dd->verbs_dev.n_piodrain;
1685 }
1686
1687 static u64 access_sw_vtx_wait(const struct cntr_entry *entry,
1688                               void *context, int vl, int mode, u64 data)
1689 {
1690         struct hfi1_devdata *dd = context;
1691
1692         return dd->verbs_dev.n_txwait;
1693 }
1694
1695 static u64 access_sw_kmem_wait(const struct cntr_entry *entry,
1696                                void *context, int vl, int mode, u64 data)
1697 {
1698         struct hfi1_devdata *dd = context;
1699
1700         return dd->verbs_dev.n_kmem_wait;
1701 }
1702
1703 static u64 access_sw_send_schedule(const struct cntr_entry *entry,
1704                                    void *context, int vl, int mode, u64 data)
1705 {
1706         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1707
1708         return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl,
1709                               mode, data);
1710 }
1711
1712 /* Software counters for the error status bits within MISC_ERR_STATUS */
1713 static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry,
1714                                              void *context, int vl, int mode,
1715                                              u64 data)
1716 {
1717         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1718
1719         return dd->misc_err_status_cnt[12];
1720 }
1721
1722 static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry,
1723                                           void *context, int vl, int mode,
1724                                           u64 data)
1725 {
1726         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1727
1728         return dd->misc_err_status_cnt[11];
1729 }
1730
1731 static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry,
1732                                                void *context, int vl, int mode,
1733                                                u64 data)
1734 {
1735         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1736
1737         return dd->misc_err_status_cnt[10];
1738 }
1739
1740 static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry,
1741                                                  void *context, int vl,
1742                                                  int mode, u64 data)
1743 {
1744         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1745
1746         return dd->misc_err_status_cnt[9];
1747 }
1748
1749 static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry,
1750                                            void *context, int vl, int mode,
1751                                            u64 data)
1752 {
1753         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1754
1755         return dd->misc_err_status_cnt[8];
1756 }
1757
1758 static u64 access_misc_efuse_read_bad_addr_err_cnt(
1759                                 const struct cntr_entry *entry,
1760                                 void *context, int vl, int mode, u64 data)
1761 {
1762         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1763
1764         return dd->misc_err_status_cnt[7];
1765 }
1766
1767 static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry,
1768                                                 void *context, int vl,
1769                                                 int mode, u64 data)
1770 {
1771         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1772
1773         return dd->misc_err_status_cnt[6];
1774 }
1775
1776 static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry,
1777                                               void *context, int vl, int mode,
1778                                               u64 data)
1779 {
1780         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1781
1782         return dd->misc_err_status_cnt[5];
1783 }
1784
1785 static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry,
1786                                             void *context, int vl, int mode,
1787                                             u64 data)
1788 {
1789         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1790
1791         return dd->misc_err_status_cnt[4];
1792 }
1793
1794 static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry,
1795                                                  void *context, int vl,
1796                                                  int mode, u64 data)
1797 {
1798         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1799
1800         return dd->misc_err_status_cnt[3];
1801 }
1802
1803 static u64 access_misc_csr_write_bad_addr_err_cnt(
1804                                 const struct cntr_entry *entry,
1805                                 void *context, int vl, int mode, u64 data)
1806 {
1807         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1808
1809         return dd->misc_err_status_cnt[2];
1810 }
1811
1812 static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1813                                                  void *context, int vl,
1814                                                  int mode, u64 data)
1815 {
1816         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1817
1818         return dd->misc_err_status_cnt[1];
1819 }
1820
1821 static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry,
1822                                           void *context, int vl, int mode,
1823                                           u64 data)
1824 {
1825         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1826
1827         return dd->misc_err_status_cnt[0];
1828 }
1829
1830 /*
1831  * Software counter for the aggregate of
1832  * individual CceErrStatus counters
1833  */
1834 static u64 access_sw_cce_err_status_aggregated_cnt(
1835                                 const struct cntr_entry *entry,
1836                                 void *context, int vl, int mode, u64 data)
1837 {
1838         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1839
1840         return dd->sw_cce_err_status_aggregate;
1841 }
1842
1843 /*
1844  * Software counters corresponding to each of the
1845  * error status bits within CceErrStatus
1846  */
1847 static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry,
1848                                               void *context, int vl, int mode,
1849                                               u64 data)
1850 {
1851         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1852
1853         return dd->cce_err_status_cnt[40];
1854 }
1855
1856 static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry,
1857                                           void *context, int vl, int mode,
1858                                           u64 data)
1859 {
1860         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1861
1862         return dd->cce_err_status_cnt[39];
1863 }
1864
1865 static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry,
1866                                           void *context, int vl, int mode,
1867                                           u64 data)
1868 {
1869         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1870
1871         return dd->cce_err_status_cnt[38];
1872 }
1873
1874 static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry,
1875                                              void *context, int vl, int mode,
1876                                              u64 data)
1877 {
1878         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1879
1880         return dd->cce_err_status_cnt[37];
1881 }
1882
1883 static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry,
1884                                              void *context, int vl, int mode,
1885                                              u64 data)
1886 {
1887         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1888
1889         return dd->cce_err_status_cnt[36];
1890 }
1891
1892 static u64 access_cce_rxdma_conv_fifo_parity_err_cnt(
1893                                 const struct cntr_entry *entry,
1894                                 void *context, int vl, int mode, u64 data)
1895 {
1896         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1897
1898         return dd->cce_err_status_cnt[35];
1899 }
1900
1901 static u64 access_cce_rcpl_async_fifo_parity_err_cnt(
1902                                 const struct cntr_entry *entry,
1903                                 void *context, int vl, int mode, u64 data)
1904 {
1905         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1906
1907         return dd->cce_err_status_cnt[34];
1908 }
1909
1910 static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry,
1911                                                  void *context, int vl,
1912                                                  int mode, u64 data)
1913 {
1914         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1915
1916         return dd->cce_err_status_cnt[33];
1917 }
1918
1919 static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1920                                                 void *context, int vl, int mode,
1921                                                 u64 data)
1922 {
1923         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1924
1925         return dd->cce_err_status_cnt[32];
1926 }
1927
1928 static u64 access_la_triggered_cnt(const struct cntr_entry *entry,
1929                                    void *context, int vl, int mode, u64 data)
1930 {
1931         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1932
1933         return dd->cce_err_status_cnt[31];
1934 }
1935
1936 static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry,
1937                                                void *context, int vl, int mode,
1938                                                u64 data)
1939 {
1940         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1941
1942         return dd->cce_err_status_cnt[30];
1943 }
1944
1945 static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry,
1946                                               void *context, int vl, int mode,
1947                                               u64 data)
1948 {
1949         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1950
1951         return dd->cce_err_status_cnt[29];
1952 }
1953
1954 static u64 access_pcic_transmit_back_parity_err_cnt(
1955                                 const struct cntr_entry *entry,
1956                                 void *context, int vl, int mode, u64 data)
1957 {
1958         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1959
1960         return dd->cce_err_status_cnt[28];
1961 }
1962
1963 static u64 access_pcic_transmit_front_parity_err_cnt(
1964                                 const struct cntr_entry *entry,
1965                                 void *context, int vl, int mode, u64 data)
1966 {
1967         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1968
1969         return dd->cce_err_status_cnt[27];
1970 }
1971
1972 static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1973                                              void *context, int vl, int mode,
1974                                              u64 data)
1975 {
1976         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1977
1978         return dd->cce_err_status_cnt[26];
1979 }
1980
1981 static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1982                                             void *context, int vl, int mode,
1983                                             u64 data)
1984 {
1985         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1986
1987         return dd->cce_err_status_cnt[25];
1988 }
1989
1990 static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1991                                               void *context, int vl, int mode,
1992                                               u64 data)
1993 {
1994         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1995
1996         return dd->cce_err_status_cnt[24];
1997 }
1998
1999 static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry,
2000                                              void *context, int vl, int mode,
2001                                              u64 data)
2002 {
2003         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2004
2005         return dd->cce_err_status_cnt[23];
2006 }
2007
2008 static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry,
2009                                                  void *context, int vl,
2010                                                  int mode, u64 data)
2011 {
2012         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2013
2014         return dd->cce_err_status_cnt[22];
2015 }
2016
2017 static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry,
2018                                          void *context, int vl, int mode,
2019                                          u64 data)
2020 {
2021         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2022
2023         return dd->cce_err_status_cnt[21];
2024 }
2025
2026 static u64 access_pcic_n_post_dat_q_parity_err_cnt(
2027                                 const struct cntr_entry *entry,
2028                                 void *context, int vl, int mode, u64 data)
2029 {
2030         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2031
2032         return dd->cce_err_status_cnt[20];
2033 }
2034
2035 static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry,
2036                                                  void *context, int vl,
2037                                                  int mode, u64 data)
2038 {
2039         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2040
2041         return dd->cce_err_status_cnt[19];
2042 }
2043
2044 static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry,
2045                                              void *context, int vl, int mode,
2046                                              u64 data)
2047 {
2048         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2049
2050         return dd->cce_err_status_cnt[18];
2051 }
2052
2053 static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry,
2054                                             void *context, int vl, int mode,
2055                                             u64 data)
2056 {
2057         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2058
2059         return dd->cce_err_status_cnt[17];
2060 }
2061
2062 static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry,
2063                                               void *context, int vl, int mode,
2064                                               u64 data)
2065 {
2066         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2067
2068         return dd->cce_err_status_cnt[16];
2069 }
2070
2071 static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry,
2072                                              void *context, int vl, int mode,
2073                                              u64 data)
2074 {
2075         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2076
2077         return dd->cce_err_status_cnt[15];
2078 }
2079
2080 static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry,
2081                                                  void *context, int vl,
2082                                                  int mode, u64 data)
2083 {
2084         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2085
2086         return dd->cce_err_status_cnt[14];
2087 }
2088
2089 static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry,
2090                                              void *context, int vl, int mode,
2091                                              u64 data)
2092 {
2093         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2094
2095         return dd->cce_err_status_cnt[13];
2096 }
2097
2098 static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt(
2099                                 const struct cntr_entry *entry,
2100                                 void *context, int vl, int mode, u64 data)
2101 {
2102         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2103
2104         return dd->cce_err_status_cnt[12];
2105 }
2106
2107 static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt(
2108                                 const struct cntr_entry *entry,
2109                                 void *context, int vl, int mode, u64 data)
2110 {
2111         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2112
2113         return dd->cce_err_status_cnt[11];
2114 }
2115
2116 static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt(
2117                                 const struct cntr_entry *entry,
2118                                 void *context, int vl, int mode, u64 data)
2119 {
2120         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2121
2122         return dd->cce_err_status_cnt[10];
2123 }
2124
2125 static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt(
2126                                 const struct cntr_entry *entry,
2127                                 void *context, int vl, int mode, u64 data)
2128 {
2129         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2130
2131         return dd->cce_err_status_cnt[9];
2132 }
2133
2134 static u64 access_cce_cli2_async_fifo_parity_err_cnt(
2135                                 const struct cntr_entry *entry,
2136                                 void *context, int vl, int mode, u64 data)
2137 {
2138         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2139
2140         return dd->cce_err_status_cnt[8];
2141 }
2142
2143 static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry,
2144                                                  void *context, int vl,
2145                                                  int mode, u64 data)
2146 {
2147         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2148
2149         return dd->cce_err_status_cnt[7];
2150 }
2151
2152 static u64 access_cce_cli0_async_fifo_parity_err_cnt(
2153                                 const struct cntr_entry *entry,
2154                                 void *context, int vl, int mode, u64 data)
2155 {
2156         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2157
2158         return dd->cce_err_status_cnt[6];
2159 }
2160
2161 static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry,
2162                                                void *context, int vl, int mode,
2163                                                u64 data)
2164 {
2165         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2166
2167         return dd->cce_err_status_cnt[5];
2168 }
2169
2170 static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry,
2171                                           void *context, int vl, int mode,
2172                                           u64 data)
2173 {
2174         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2175
2176         return dd->cce_err_status_cnt[4];
2177 }
2178
2179 static u64 access_cce_trgt_async_fifo_parity_err_cnt(
2180                                 const struct cntr_entry *entry,
2181                                 void *context, int vl, int mode, u64 data)
2182 {
2183         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2184
2185         return dd->cce_err_status_cnt[3];
2186 }
2187
2188 static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2189                                                  void *context, int vl,
2190                                                  int mode, u64 data)
2191 {
2192         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2193
2194         return dd->cce_err_status_cnt[2];
2195 }
2196
2197 static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2198                                                 void *context, int vl,
2199                                                 int mode, u64 data)
2200 {
2201         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2202
2203         return dd->cce_err_status_cnt[1];
2204 }
2205
2206 static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry,
2207                                          void *context, int vl, int mode,
2208                                          u64 data)
2209 {
2210         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2211
2212         return dd->cce_err_status_cnt[0];
2213 }
2214
2215 /*
2216  * Software counters corresponding to each of the
2217  * error status bits within RcvErrStatus
2218  */
2219 static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry,
2220                                         void *context, int vl, int mode,
2221                                         u64 data)
2222 {
2223         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2224
2225         return dd->rcv_err_status_cnt[63];
2226 }
2227
2228 static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2229                                                 void *context, int vl,
2230                                                 int mode, u64 data)
2231 {
2232         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2233
2234         return dd->rcv_err_status_cnt[62];
2235 }
2236
2237 static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2238                                                void *context, int vl, int mode,
2239                                                u64 data)
2240 {
2241         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2242
2243         return dd->rcv_err_status_cnt[61];
2244 }
2245
2246 static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry,
2247                                          void *context, int vl, int mode,
2248                                          u64 data)
2249 {
2250         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2251
2252         return dd->rcv_err_status_cnt[60];
2253 }
2254
2255 static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2256                                                  void *context, int vl,
2257                                                  int mode, u64 data)
2258 {
2259         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2260
2261         return dd->rcv_err_status_cnt[59];
2262 }
2263
2264 static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2265                                                  void *context, int vl,
2266                                                  int mode, u64 data)
2267 {
2268         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2269
2270         return dd->rcv_err_status_cnt[58];
2271 }
2272
2273 static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry,
2274                                             void *context, int vl, int mode,
2275                                             u64 data)
2276 {
2277         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2278
2279         return dd->rcv_err_status_cnt[57];
2280 }
2281
2282 static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry,
2283                                            void *context, int vl, int mode,
2284                                            u64 data)
2285 {
2286         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2287
2288         return dd->rcv_err_status_cnt[56];
2289 }
2290
2291 static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry,
2292                                            void *context, int vl, int mode,
2293                                            u64 data)
2294 {
2295         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2296
2297         return dd->rcv_err_status_cnt[55];
2298 }
2299
2300 static u64 access_rx_dma_data_fifo_rd_cor_err_cnt(
2301                                 const struct cntr_entry *entry,
2302                                 void *context, int vl, int mode, u64 data)
2303 {
2304         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2305
2306         return dd->rcv_err_status_cnt[54];
2307 }
2308
2309 static u64 access_rx_dma_data_fifo_rd_unc_err_cnt(
2310                                 const struct cntr_entry *entry,
2311                                 void *context, int vl, int mode, u64 data)
2312 {
2313         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2314
2315         return dd->rcv_err_status_cnt[53];
2316 }
2317
2318 static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry,
2319                                                  void *context, int vl,
2320                                                  int mode, u64 data)
2321 {
2322         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2323
2324         return dd->rcv_err_status_cnt[52];
2325 }
2326
2327 static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry,
2328                                                  void *context, int vl,
2329                                                  int mode, u64 data)
2330 {
2331         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2332
2333         return dd->rcv_err_status_cnt[51];
2334 }
2335
2336 static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry,
2337                                                  void *context, int vl,
2338                                                  int mode, u64 data)
2339 {
2340         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2341
2342         return dd->rcv_err_status_cnt[50];
2343 }
2344
2345 static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry,
2346                                                  void *context, int vl,
2347                                                  int mode, u64 data)
2348 {
2349         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2350
2351         return dd->rcv_err_status_cnt[49];
2352 }
2353
2354 static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry,
2355                                                  void *context, int vl,
2356                                                  int mode, u64 data)
2357 {
2358         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2359
2360         return dd->rcv_err_status_cnt[48];
2361 }
2362
2363 static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry,
2364                                                  void *context, int vl,
2365                                                  int mode, u64 data)
2366 {
2367         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2368
2369         return dd->rcv_err_status_cnt[47];
2370 }
2371
2372 static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry,
2373                                          void *context, int vl, int mode,
2374                                          u64 data)
2375 {
2376         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2377
2378         return dd->rcv_err_status_cnt[46];
2379 }
2380
2381 static u64 access_rx_hq_intr_csr_parity_err_cnt(
2382                                 const struct cntr_entry *entry,
2383                                 void *context, int vl, int mode, u64 data)
2384 {
2385         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2386
2387         return dd->rcv_err_status_cnt[45];
2388 }
2389
2390 static u64 access_rx_lookup_csr_parity_err_cnt(
2391                                 const struct cntr_entry *entry,
2392                                 void *context, int vl, int mode, u64 data)
2393 {
2394         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2395
2396         return dd->rcv_err_status_cnt[44];
2397 }
2398
2399 static u64 access_rx_lookup_rcv_array_cor_err_cnt(
2400                                 const struct cntr_entry *entry,
2401                                 void *context, int vl, int mode, u64 data)
2402 {
2403         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2404
2405         return dd->rcv_err_status_cnt[43];
2406 }
2407
2408 static u64 access_rx_lookup_rcv_array_unc_err_cnt(
2409                                 const struct cntr_entry *entry,
2410                                 void *context, int vl, int mode, u64 data)
2411 {
2412         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2413
2414         return dd->rcv_err_status_cnt[42];
2415 }
2416
2417 static u64 access_rx_lookup_des_part2_parity_err_cnt(
2418                                 const struct cntr_entry *entry,
2419                                 void *context, int vl, int mode, u64 data)
2420 {
2421         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2422
2423         return dd->rcv_err_status_cnt[41];
2424 }
2425
2426 static u64 access_rx_lookup_des_part1_unc_cor_err_cnt(
2427                                 const struct cntr_entry *entry,
2428                                 void *context, int vl, int mode, u64 data)
2429 {
2430         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2431
2432         return dd->rcv_err_status_cnt[40];
2433 }
2434
2435 static u64 access_rx_lookup_des_part1_unc_err_cnt(
2436                                 const struct cntr_entry *entry,
2437                                 void *context, int vl, int mode, u64 data)
2438 {
2439         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2440
2441         return dd->rcv_err_status_cnt[39];
2442 }
2443
2444 static u64 access_rx_rbuf_next_free_buf_cor_err_cnt(
2445                                 const struct cntr_entry *entry,
2446                                 void *context, int vl, int mode, u64 data)
2447 {
2448         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2449
2450         return dd->rcv_err_status_cnt[38];
2451 }
2452
2453 static u64 access_rx_rbuf_next_free_buf_unc_err_cnt(
2454                                 const struct cntr_entry *entry,
2455                                 void *context, int vl, int mode, u64 data)
2456 {
2457         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2458
2459         return dd->rcv_err_status_cnt[37];
2460 }
2461
2462 static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt(
2463                                 const struct cntr_entry *entry,
2464                                 void *context, int vl, int mode, u64 data)
2465 {
2466         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2467
2468         return dd->rcv_err_status_cnt[36];
2469 }
2470
2471 static u64 access_rx_rbuf_fl_initdone_parity_err_cnt(
2472                                 const struct cntr_entry *entry,
2473                                 void *context, int vl, int mode, u64 data)
2474 {
2475         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2476
2477         return dd->rcv_err_status_cnt[35];
2478 }
2479
2480 static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt(
2481                                 const struct cntr_entry *entry,
2482                                 void *context, int vl, int mode, u64 data)
2483 {
2484         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2485
2486         return dd->rcv_err_status_cnt[34];
2487 }
2488
2489 static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt(
2490                                 const struct cntr_entry *entry,
2491                                 void *context, int vl, int mode, u64 data)
2492 {
2493         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2494
2495         return dd->rcv_err_status_cnt[33];
2496 }
2497
2498 static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry,
2499                                         void *context, int vl, int mode,
2500                                         u64 data)
2501 {
2502         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2503
2504         return dd->rcv_err_status_cnt[32];
2505 }
2506
2507 static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry,
2508                                        void *context, int vl, int mode,
2509                                        u64 data)
2510 {
2511         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2512
2513         return dd->rcv_err_status_cnt[31];
2514 }
2515
2516 static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry,
2517                                           void *context, int vl, int mode,
2518                                           u64 data)
2519 {
2520         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2521
2522         return dd->rcv_err_status_cnt[30];
2523 }
2524
2525 static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry,
2526                                              void *context, int vl, int mode,
2527                                              u64 data)
2528 {
2529         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2530
2531         return dd->rcv_err_status_cnt[29];
2532 }
2533
2534 static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry,
2535                                                  void *context, int vl,
2536                                                  int mode, u64 data)
2537 {
2538         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2539
2540         return dd->rcv_err_status_cnt[28];
2541 }
2542
2543 static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt(
2544                                 const struct cntr_entry *entry,
2545                                 void *context, int vl, int mode, u64 data)
2546 {
2547         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2548
2549         return dd->rcv_err_status_cnt[27];
2550 }
2551
2552 static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt(
2553                                 const struct cntr_entry *entry,
2554                                 void *context, int vl, int mode, u64 data)
2555 {
2556         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2557
2558         return dd->rcv_err_status_cnt[26];
2559 }
2560
2561 static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt(
2562                                 const struct cntr_entry *entry,
2563                                 void *context, int vl, int mode, u64 data)
2564 {
2565         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2566
2567         return dd->rcv_err_status_cnt[25];
2568 }
2569
2570 static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt(
2571                                 const struct cntr_entry *entry,
2572                                 void *context, int vl, int mode, u64 data)
2573 {
2574         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2575
2576         return dd->rcv_err_status_cnt[24];
2577 }
2578
2579 static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt(
2580                                 const struct cntr_entry *entry,
2581                                 void *context, int vl, int mode, u64 data)
2582 {
2583         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2584
2585         return dd->rcv_err_status_cnt[23];
2586 }
2587
2588 static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt(
2589                                 const struct cntr_entry *entry,
2590                                 void *context, int vl, int mode, u64 data)
2591 {
2592         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2593
2594         return dd->rcv_err_status_cnt[22];
2595 }
2596
2597 static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt(
2598                                 const struct cntr_entry *entry,
2599                                 void *context, int vl, int mode, u64 data)
2600 {
2601         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2602
2603         return dd->rcv_err_status_cnt[21];
2604 }
2605
2606 static u64 access_rx_rbuf_block_list_read_cor_err_cnt(
2607                                 const struct cntr_entry *entry,
2608                                 void *context, int vl, int mode, u64 data)
2609 {
2610         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2611
2612         return dd->rcv_err_status_cnt[20];
2613 }
2614
2615 static u64 access_rx_rbuf_block_list_read_unc_err_cnt(
2616                                 const struct cntr_entry *entry,
2617                                 void *context, int vl, int mode, u64 data)
2618 {
2619         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2620
2621         return dd->rcv_err_status_cnt[19];
2622 }
2623
2624 static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry,
2625                                                  void *context, int vl,
2626                                                  int mode, u64 data)
2627 {
2628         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2629
2630         return dd->rcv_err_status_cnt[18];
2631 }
2632
2633 static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry,
2634                                                  void *context, int vl,
2635                                                  int mode, u64 data)
2636 {
2637         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2638
2639         return dd->rcv_err_status_cnt[17];
2640 }
2641
2642 static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt(
2643                                 const struct cntr_entry *entry,
2644                                 void *context, int vl, int mode, u64 data)
2645 {
2646         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2647
2648         return dd->rcv_err_status_cnt[16];
2649 }
2650
2651 static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt(
2652                                 const struct cntr_entry *entry,
2653                                 void *context, int vl, int mode, u64 data)
2654 {
2655         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2656
2657         return dd->rcv_err_status_cnt[15];
2658 }
2659
2660 static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry,
2661                                                 void *context, int vl,
2662                                                 int mode, u64 data)
2663 {
2664         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2665
2666         return dd->rcv_err_status_cnt[14];
2667 }
2668
2669 static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry,
2670                                                 void *context, int vl,
2671                                                 int mode, u64 data)
2672 {
2673         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2674
2675         return dd->rcv_err_status_cnt[13];
2676 }
2677
2678 static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2679                                               void *context, int vl, int mode,
2680                                               u64 data)
2681 {
2682         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2683
2684         return dd->rcv_err_status_cnt[12];
2685 }
2686
2687 static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry,
2688                                           void *context, int vl, int mode,
2689                                           u64 data)
2690 {
2691         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2692
2693         return dd->rcv_err_status_cnt[11];
2694 }
2695
2696 static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry,
2697                                           void *context, int vl, int mode,
2698                                           u64 data)
2699 {
2700         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2701
2702         return dd->rcv_err_status_cnt[10];
2703 }
2704
2705 static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry,
2706                                                void *context, int vl, int mode,
2707                                                u64 data)
2708 {
2709         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2710
2711         return dd->rcv_err_status_cnt[9];
2712 }
2713
2714 static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry,
2715                                             void *context, int vl, int mode,
2716                                             u64 data)
2717 {
2718         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2719
2720         return dd->rcv_err_status_cnt[8];
2721 }
2722
2723 static u64 access_rx_rcv_qp_map_table_cor_err_cnt(
2724                                 const struct cntr_entry *entry,
2725                                 void *context, int vl, int mode, u64 data)
2726 {
2727         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2728
2729         return dd->rcv_err_status_cnt[7];
2730 }
2731
2732 static u64 access_rx_rcv_qp_map_table_unc_err_cnt(
2733                                 const struct cntr_entry *entry,
2734                                 void *context, int vl, int mode, u64 data)
2735 {
2736         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2737
2738         return dd->rcv_err_status_cnt[6];
2739 }
2740
2741 static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry,
2742                                           void *context, int vl, int mode,
2743                                           u64 data)
2744 {
2745         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2746
2747         return dd->rcv_err_status_cnt[5];
2748 }
2749
2750 static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry,
2751                                           void *context, int vl, int mode,
2752                                           u64 data)
2753 {
2754         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2755
2756         return dd->rcv_err_status_cnt[4];
2757 }
2758
2759 static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry,
2760                                          void *context, int vl, int mode,
2761                                          u64 data)
2762 {
2763         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2764
2765         return dd->rcv_err_status_cnt[3];
2766 }
2767
2768 static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry,
2769                                          void *context, int vl, int mode,
2770                                          u64 data)
2771 {
2772         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2773
2774         return dd->rcv_err_status_cnt[2];
2775 }
2776
2777 static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry,
2778                                             void *context, int vl, int mode,
2779                                             u64 data)
2780 {
2781         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2782
2783         return dd->rcv_err_status_cnt[1];
2784 }
2785
2786 static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry,
2787                                          void *context, int vl, int mode,
2788                                          u64 data)
2789 {
2790         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2791
2792         return dd->rcv_err_status_cnt[0];
2793 }
2794
2795 /*
2796  * Software counters corresponding to each of the
2797  * error status bits within SendPioErrStatus
2798  */
2799 static u64 access_pio_pec_sop_head_parity_err_cnt(
2800                                 const struct cntr_entry *entry,
2801                                 void *context, int vl, int mode, u64 data)
2802 {
2803         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2804
2805         return dd->send_pio_err_status_cnt[35];
2806 }
2807
2808 static u64 access_pio_pcc_sop_head_parity_err_cnt(
2809                                 const struct cntr_entry *entry,
2810                                 void *context, int vl, int mode, u64 data)
2811 {
2812         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2813
2814         return dd->send_pio_err_status_cnt[34];
2815 }
2816
2817 static u64 access_pio_last_returned_cnt_parity_err_cnt(
2818                                 const struct cntr_entry *entry,
2819                                 void *context, int vl, int mode, u64 data)
2820 {
2821         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2822
2823         return dd->send_pio_err_status_cnt[33];
2824 }
2825
2826 static u64 access_pio_current_free_cnt_parity_err_cnt(
2827                                 const struct cntr_entry *entry,
2828                                 void *context, int vl, int mode, u64 data)
2829 {
2830         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2831
2832         return dd->send_pio_err_status_cnt[32];
2833 }
2834
2835 static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry,
2836                                           void *context, int vl, int mode,
2837                                           u64 data)
2838 {
2839         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2840
2841         return dd->send_pio_err_status_cnt[31];
2842 }
2843
2844 static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry,
2845                                           void *context, int vl, int mode,
2846                                           u64 data)
2847 {
2848         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2849
2850         return dd->send_pio_err_status_cnt[30];
2851 }
2852
2853 static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry,
2854                                            void *context, int vl, int mode,
2855                                            u64 data)
2856 {
2857         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2858
2859         return dd->send_pio_err_status_cnt[29];
2860 }
2861
2862 static u64 access_pio_ppmc_bqc_mem_parity_err_cnt(
2863                                 const struct cntr_entry *entry,
2864                                 void *context, int vl, int mode, u64 data)
2865 {
2866         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2867
2868         return dd->send_pio_err_status_cnt[28];
2869 }
2870
2871 static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry,
2872                                              void *context, int vl, int mode,
2873                                              u64 data)
2874 {
2875         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2876
2877         return dd->send_pio_err_status_cnt[27];
2878 }
2879
2880 static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry,
2881                                              void *context, int vl, int mode,
2882                                              u64 data)
2883 {
2884         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2885
2886         return dd->send_pio_err_status_cnt[26];
2887 }
2888
2889 static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry,
2890                                                 void *context, int vl,
2891                                                 int mode, u64 data)
2892 {
2893         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2894
2895         return dd->send_pio_err_status_cnt[25];
2896 }
2897
2898 static u64 access_pio_block_qw_count_parity_err_cnt(
2899                                 const struct cntr_entry *entry,
2900                                 void *context, int vl, int mode, u64 data)
2901 {
2902         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2903
2904         return dd->send_pio_err_status_cnt[24];
2905 }
2906
2907 static u64 access_pio_write_qw_valid_parity_err_cnt(
2908                                 const struct cntr_entry *entry,
2909                                 void *context, int vl, int mode, u64 data)
2910 {
2911         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2912
2913         return dd->send_pio_err_status_cnt[23];
2914 }
2915
2916 static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry,
2917                                             void *context, int vl, int mode,
2918                                             u64 data)
2919 {
2920         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2921
2922         return dd->send_pio_err_status_cnt[22];
2923 }
2924
2925 static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry,
2926                                                 void *context, int vl,
2927                                                 int mode, u64 data)
2928 {
2929         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2930
2931         return dd->send_pio_err_status_cnt[21];
2932 }
2933
2934 static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry,
2935                                                 void *context, int vl,
2936                                                 int mode, u64 data)
2937 {
2938         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2939
2940         return dd->send_pio_err_status_cnt[20];
2941 }
2942
2943 static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry,
2944                                                 void *context, int vl,
2945                                                 int mode, u64 data)
2946 {
2947         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2948
2949         return dd->send_pio_err_status_cnt[19];
2950 }
2951
2952 static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt(
2953                                 const struct cntr_entry *entry,
2954                                 void *context, int vl, int mode, u64 data)
2955 {
2956         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2957
2958         return dd->send_pio_err_status_cnt[18];
2959 }
2960
2961 static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry,
2962                                          void *context, int vl, int mode,
2963                                          u64 data)
2964 {
2965         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2966
2967         return dd->send_pio_err_status_cnt[17];
2968 }
2969
2970 static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry,
2971                                             void *context, int vl, int mode,
2972                                             u64 data)
2973 {
2974         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2975
2976         return dd->send_pio_err_status_cnt[16];
2977 }
2978
2979 static u64 access_pio_credit_ret_fifo_parity_err_cnt(
2980                                 const struct cntr_entry *entry,
2981                                 void *context, int vl, int mode, u64 data)
2982 {
2983         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2984
2985         return dd->send_pio_err_status_cnt[15];
2986 }
2987
2988 static u64 access_pio_v1_len_mem_bank1_cor_err_cnt(
2989                                 const struct cntr_entry *entry,
2990                                 void *context, int vl, int mode, u64 data)
2991 {
2992         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2993
2994         return dd->send_pio_err_status_cnt[14];
2995 }
2996
2997 static u64 access_pio_v1_len_mem_bank0_cor_err_cnt(
2998                                 const struct cntr_entry *entry,
2999                                 void *context, int vl, int mode, u64 data)
3000 {
3001         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3002
3003         return dd->send_pio_err_status_cnt[13];
3004 }
3005
3006 static u64 access_pio_v1_len_mem_bank1_unc_err_cnt(
3007                                 const struct cntr_entry *entry,
3008                                 void *context, int vl, int mode, u64 data)
3009 {
3010         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3011
3012         return dd->send_pio_err_status_cnt[12];
3013 }
3014
3015 static u64 access_pio_v1_len_mem_bank0_unc_err_cnt(
3016                                 const struct cntr_entry *entry,
3017                                 void *context, int vl, int mode, u64 data)
3018 {
3019         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3020
3021         return dd->send_pio_err_status_cnt[11];
3022 }
3023
3024 static u64 access_pio_sm_pkt_reset_parity_err_cnt(
3025                                 const struct cntr_entry *entry,
3026                                 void *context, int vl, int mode, u64 data)
3027 {
3028         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3029
3030         return dd->send_pio_err_status_cnt[10];
3031 }
3032
3033 static u64 access_pio_pkt_evict_fifo_parity_err_cnt(
3034                                 const struct cntr_entry *entry,
3035                                 void *context, int vl, int mode, u64 data)
3036 {
3037         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3038
3039         return dd->send_pio_err_status_cnt[9];
3040 }
3041
3042 static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt(
3043                                 const struct cntr_entry *entry,
3044                                 void *context, int vl, int mode, u64 data)
3045 {
3046         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3047
3048         return dd->send_pio_err_status_cnt[8];
3049 }
3050
3051 static u64 access_pio_sbrdctl_crrel_parity_err_cnt(
3052                                 const struct cntr_entry *entry,
3053                                 void *context, int vl, int mode, u64 data)
3054 {
3055         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3056
3057         return dd->send_pio_err_status_cnt[7];
3058 }
3059
3060 static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry,
3061                                               void *context, int vl, int mode,
3062                                               u64 data)
3063 {
3064         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3065
3066         return dd->send_pio_err_status_cnt[6];
3067 }
3068
3069 static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry,
3070                                               void *context, int vl, int mode,
3071                                               u64 data)
3072 {
3073         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3074
3075         return dd->send_pio_err_status_cnt[5];
3076 }
3077
3078 static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry,
3079                                            void *context, int vl, int mode,
3080                                            u64 data)
3081 {
3082         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3083
3084         return dd->send_pio_err_status_cnt[4];
3085 }
3086
3087 static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry,
3088                                            void *context, int vl, int mode,
3089                                            u64 data)
3090 {
3091         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3092
3093         return dd->send_pio_err_status_cnt[3];
3094 }
3095
3096 static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry,
3097                                          void *context, int vl, int mode,
3098                                          u64 data)
3099 {
3100         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3101
3102         return dd->send_pio_err_status_cnt[2];
3103 }
3104
3105 static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry,
3106                                                 void *context, int vl,
3107                                                 int mode, u64 data)
3108 {
3109         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3110
3111         return dd->send_pio_err_status_cnt[1];
3112 }
3113
3114 static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry,
3115                                              void *context, int vl, int mode,
3116                                              u64 data)
3117 {
3118         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3119
3120         return dd->send_pio_err_status_cnt[0];
3121 }
3122
3123 /*
3124  * Software counters corresponding to each of the
3125  * error status bits within SendDmaErrStatus
3126  */
3127 static u64 access_sdma_pcie_req_tracking_cor_err_cnt(
3128                                 const struct cntr_entry *entry,
3129                                 void *context, int vl, int mode, u64 data)
3130 {
3131         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3132
3133         return dd->send_dma_err_status_cnt[3];
3134 }
3135
3136 static u64 access_sdma_pcie_req_tracking_unc_err_cnt(
3137                                 const struct cntr_entry *entry,
3138                                 void *context, int vl, int mode, u64 data)
3139 {
3140         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3141
3142         return dd->send_dma_err_status_cnt[2];
3143 }
3144
3145 static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry,
3146                                           void *context, int vl, int mode,
3147                                           u64 data)
3148 {
3149         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3150
3151         return dd->send_dma_err_status_cnt[1];
3152 }
3153
3154 static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry,
3155                                        void *context, int vl, int mode,
3156                                        u64 data)
3157 {
3158         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3159
3160         return dd->send_dma_err_status_cnt[0];
3161 }
3162
3163 /*
3164  * Software counters corresponding to each of the
3165  * error status bits within SendEgressErrStatus
3166  */
3167 static u64 access_tx_read_pio_memory_csr_unc_err_cnt(
3168                                 const struct cntr_entry *entry,
3169                                 void *context, int vl, int mode, u64 data)
3170 {
3171         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3172
3173         return dd->send_egress_err_status_cnt[63];
3174 }
3175
3176 static u64 access_tx_read_sdma_memory_csr_err_cnt(
3177                                 const struct cntr_entry *entry,
3178                                 void *context, int vl, int mode, u64 data)
3179 {
3180         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3181
3182         return dd->send_egress_err_status_cnt[62];
3183 }
3184
3185 static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry,
3186                                              void *context, int vl, int mode,
3187                                              u64 data)
3188 {
3189         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3190
3191         return dd->send_egress_err_status_cnt[61];
3192 }
3193
3194 static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry,
3195                                                  void *context, int vl,
3196                                                  int mode, u64 data)
3197 {
3198         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3199
3200         return dd->send_egress_err_status_cnt[60];
3201 }
3202
3203 static u64 access_tx_read_sdma_memory_cor_err_cnt(
3204                                 const struct cntr_entry *entry,
3205                                 void *context, int vl, int mode, u64 data)
3206 {
3207         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3208
3209         return dd->send_egress_err_status_cnt[59];
3210 }
3211
3212 static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry,
3213                                         void *context, int vl, int mode,
3214                                         u64 data)
3215 {
3216         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3217
3218         return dd->send_egress_err_status_cnt[58];
3219 }
3220
3221 static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry,
3222                                             void *context, int vl, int mode,
3223                                             u64 data)
3224 {
3225         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3226
3227         return dd->send_egress_err_status_cnt[57];
3228 }
3229
3230 static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry,
3231                                               void *context, int vl, int mode,
3232                                               u64 data)
3233 {
3234         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3235
3236         return dd->send_egress_err_status_cnt[56];
3237 }
3238
3239 static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry,
3240                                               void *context, int vl, int mode,
3241                                               u64 data)
3242 {
3243         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3244
3245         return dd->send_egress_err_status_cnt[55];
3246 }
3247
3248 static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry,
3249                                               void *context, int vl, int mode,
3250                                               u64 data)
3251 {
3252         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3253
3254         return dd->send_egress_err_status_cnt[54];
3255 }
3256
3257 static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry,
3258                                               void *context, int vl, int mode,
3259                                               u64 data)
3260 {
3261         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3262
3263         return dd->send_egress_err_status_cnt[53];
3264 }
3265
3266 static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry,
3267                                               void *context, int vl, int mode,
3268                                               u64 data)
3269 {
3270         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3271
3272         return dd->send_egress_err_status_cnt[52];
3273 }
3274
3275 static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry,
3276                                               void *context, int vl, int mode,
3277                                               u64 data)
3278 {
3279         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3280
3281         return dd->send_egress_err_status_cnt[51];
3282 }
3283
3284 static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry,
3285                                               void *context, int vl, int mode,
3286                                               u64 data)
3287 {
3288         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3289
3290         return dd->send_egress_err_status_cnt[50];
3291 }
3292
3293 static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry,
3294                                               void *context, int vl, int mode,
3295                                               u64 data)
3296 {
3297         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3298
3299         return dd->send_egress_err_status_cnt[49];
3300 }
3301
3302 static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry,
3303                                               void *context, int vl, int mode,
3304                                               u64 data)
3305 {
3306         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3307
3308         return dd->send_egress_err_status_cnt[48];
3309 }
3310
3311 static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry,
3312                                               void *context, int vl, int mode,
3313                                               u64 data)
3314 {
3315         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3316
3317         return dd->send_egress_err_status_cnt[47];
3318 }
3319
3320 static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry,
3321                                             void *context, int vl, int mode,
3322                                             u64 data)
3323 {
3324         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3325
3326         return dd->send_egress_err_status_cnt[46];
3327 }
3328
3329 static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry,
3330                                              void *context, int vl, int mode,
3331                                              u64 data)
3332 {
3333         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3334
3335         return dd->send_egress_err_status_cnt[45];
3336 }
3337
3338 static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry,
3339                                                  void *context, int vl,
3340                                                  int mode, u64 data)
3341 {
3342         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3343
3344         return dd->send_egress_err_status_cnt[44];
3345 }
3346
3347 static u64 access_tx_read_sdma_memory_unc_err_cnt(
3348                                 const struct cntr_entry *entry,
3349                                 void *context, int vl, int mode, u64 data)
3350 {
3351         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3352
3353         return dd->send_egress_err_status_cnt[43];
3354 }
3355
3356 static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry,
3357                                         void *context, int vl, int mode,
3358                                         u64 data)
3359 {
3360         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3361
3362         return dd->send_egress_err_status_cnt[42];
3363 }
3364
3365 static u64 access_tx_credit_return_partiy_err_cnt(
3366                                 const struct cntr_entry *entry,
3367                                 void *context, int vl, int mode, u64 data)
3368 {
3369         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3370
3371         return dd->send_egress_err_status_cnt[41];
3372 }
3373
3374 static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt(
3375                                 const struct cntr_entry *entry,
3376                                 void *context, int vl, int mode, u64 data)
3377 {
3378         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3379
3380         return dd->send_egress_err_status_cnt[40];
3381 }
3382
3383 static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt(
3384                                 const struct cntr_entry *entry,
3385                                 void *context, int vl, int mode, u64 data)
3386 {
3387         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3388
3389         return dd->send_egress_err_status_cnt[39];
3390 }
3391
3392 static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt(
3393                                 const struct cntr_entry *entry,
3394                                 void *context, int vl, int mode, u64 data)
3395 {
3396         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3397
3398         return dd->send_egress_err_status_cnt[38];
3399 }
3400
3401 static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt(
3402                                 const struct cntr_entry *entry,
3403                                 void *context, int vl, int mode, u64 data)
3404 {
3405         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3406
3407         return dd->send_egress_err_status_cnt[37];
3408 }
3409
3410 static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt(
3411                                 const struct cntr_entry *entry,
3412                                 void *context, int vl, int mode, u64 data)
3413 {
3414         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3415
3416         return dd->send_egress_err_status_cnt[36];
3417 }
3418
3419 static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt(
3420                                 const struct cntr_entry *entry,
3421                                 void *context, int vl, int mode, u64 data)
3422 {
3423         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3424
3425         return dd->send_egress_err_status_cnt[35];
3426 }
3427
3428 static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt(
3429                                 const struct cntr_entry *entry,
3430                                 void *context, int vl, int mode, u64 data)
3431 {
3432         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3433
3434         return dd->send_egress_err_status_cnt[34];
3435 }
3436
3437 static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt(
3438                                 const struct cntr_entry *entry,
3439                                 void *context, int vl, int mode, u64 data)
3440 {
3441         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3442
3443         return dd->send_egress_err_status_cnt[33];
3444 }
3445
3446 static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt(
3447                                 const struct cntr_entry *entry,
3448                                 void *context, int vl, int mode, u64 data)
3449 {
3450         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3451
3452         return dd->send_egress_err_status_cnt[32];
3453 }
3454
3455 static u64 access_tx_sdma15_disallowed_packet_err_cnt(
3456                                 const struct cntr_entry *entry,
3457                                 void *context, int vl, int mode, u64 data)
3458 {
3459         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3460
3461         return dd->send_egress_err_status_cnt[31];
3462 }
3463
3464 static u64 access_tx_sdma14_disallowed_packet_err_cnt(
3465                                 const struct cntr_entry *entry,
3466                                 void *context, int vl, int mode, u64 data)
3467 {
3468         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3469
3470         return dd->send_egress_err_status_cnt[30];
3471 }
3472
3473 static u64 access_tx_sdma13_disallowed_packet_err_cnt(
3474                                 const struct cntr_entry *entry,
3475                                 void *context, int vl, int mode, u64 data)
3476 {
3477         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3478
3479         return dd->send_egress_err_status_cnt[29];
3480 }
3481
3482 static u64 access_tx_sdma12_disallowed_packet_err_cnt(
3483                                 const struct cntr_entry *entry,
3484                                 void *context, int vl, int mode, u64 data)
3485 {
3486         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3487
3488         return dd->send_egress_err_status_cnt[28];
3489 }
3490
3491 static u64 access_tx_sdma11_disallowed_packet_err_cnt(
3492                                 const struct cntr_entry *entry,
3493                                 void *context, int vl, int mode, u64 data)
3494 {
3495         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3496
3497         return dd->send_egress_err_status_cnt[27];
3498 }
3499
3500 static u64 access_tx_sdma10_disallowed_packet_err_cnt(
3501                                 const struct cntr_entry *entry,
3502                                 void *context, int vl, int mode, u64 data)
3503 {
3504         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3505
3506         return dd->send_egress_err_status_cnt[26];
3507 }
3508
3509 static u64 access_tx_sdma9_disallowed_packet_err_cnt(
3510                                 const struct cntr_entry *entry,
3511                                 void *context, int vl, int mode, u64 data)
3512 {
3513         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3514
3515         return dd->send_egress_err_status_cnt[25];
3516 }
3517
3518 static u64 access_tx_sdma8_disallowed_packet_err_cnt(
3519                                 const struct cntr_entry *entry,
3520                                 void *context, int vl, int mode, u64 data)
3521 {
3522         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3523
3524         return dd->send_egress_err_status_cnt[24];
3525 }
3526
3527 static u64 access_tx_sdma7_disallowed_packet_err_cnt(
3528                                 const struct cntr_entry *entry,
3529                                 void *context, int vl, int mode, u64 data)
3530 {
3531         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3532
3533         return dd->send_egress_err_status_cnt[23];
3534 }
3535
3536 static u64 access_tx_sdma6_disallowed_packet_err_cnt(
3537                                 const struct cntr_entry *entry,
3538                                 void *context, int vl, int mode, u64 data)
3539 {
3540         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3541
3542         return dd->send_egress_err_status_cnt[22];
3543 }
3544
3545 static u64 access_tx_sdma5_disallowed_packet_err_cnt(
3546                                 const struct cntr_entry *entry,
3547                                 void *context, int vl, int mode, u64 data)
3548 {
3549         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3550
3551         return dd->send_egress_err_status_cnt[21];
3552 }
3553
3554 static u64 access_tx_sdma4_disallowed_packet_err_cnt(
3555                                 const struct cntr_entry *entry,
3556                                 void *context, int vl, int mode, u64 data)
3557 {
3558         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3559
3560         return dd->send_egress_err_status_cnt[20];
3561 }
3562
3563 static u64 access_tx_sdma3_disallowed_packet_err_cnt(
3564                                 const struct cntr_entry *entry,
3565                                 void *context, int vl, int mode, u64 data)
3566 {
3567         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3568
3569         return dd->send_egress_err_status_cnt[19];
3570 }
3571
3572 static u64 access_tx_sdma2_disallowed_packet_err_cnt(
3573                                 const struct cntr_entry *entry,
3574                                 void *context, int vl, int mode, u64 data)
3575 {
3576         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3577
3578         return dd->send_egress_err_status_cnt[18];
3579 }
3580
3581 static u64 access_tx_sdma1_disallowed_packet_err_cnt(
3582                                 const struct cntr_entry *entry,
3583                                 void *context, int vl, int mode, u64 data)
3584 {
3585         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3586
3587         return dd->send_egress_err_status_cnt[17];
3588 }
3589
3590 static u64 access_tx_sdma0_disallowed_packet_err_cnt(
3591                                 const struct cntr_entry *entry,
3592                                 void *context, int vl, int mode, u64 data)
3593 {
3594         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3595
3596         return dd->send_egress_err_status_cnt[16];
3597 }
3598
3599 static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry,
3600                                            void *context, int vl, int mode,
3601                                            u64 data)
3602 {
3603         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3604
3605         return dd->send_egress_err_status_cnt[15];
3606 }
3607
3608 static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry,
3609                                                  void *context, int vl,
3610                                                  int mode, u64 data)
3611 {
3612         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3613
3614         return dd->send_egress_err_status_cnt[14];
3615 }
3616
3617 static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry,
3618                                                void *context, int vl, int mode,
3619                                                u64 data)
3620 {
3621         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3622
3623         return dd->send_egress_err_status_cnt[13];
3624 }
3625
3626 static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry,
3627                                         void *context, int vl, int mode,
3628                                         u64 data)
3629 {
3630         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3631
3632         return dd->send_egress_err_status_cnt[12];
3633 }
3634
3635 static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt(
3636                                 const struct cntr_entry *entry,
3637                                 void *context, int vl, int mode, u64 data)
3638 {
3639         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3640
3641         return dd->send_egress_err_status_cnt[11];
3642 }
3643
3644 static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry,
3645                                              void *context, int vl, int mode,
3646                                              u64 data)
3647 {
3648         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3649
3650         return dd->send_egress_err_status_cnt[10];
3651 }
3652
3653 static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry,
3654                                             void *context, int vl, int mode,
3655                                             u64 data)
3656 {
3657         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3658
3659         return dd->send_egress_err_status_cnt[9];
3660 }
3661
3662 static u64 access_tx_sdma_launch_intf_parity_err_cnt(
3663                                 const struct cntr_entry *entry,
3664                                 void *context, int vl, int mode, u64 data)
3665 {
3666         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3667
3668         return dd->send_egress_err_status_cnt[8];
3669 }
3670
3671 static u64 access_tx_pio_launch_intf_parity_err_cnt(
3672                                 const struct cntr_entry *entry,
3673                                 void *context, int vl, int mode, u64 data)
3674 {
3675         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3676
3677         return dd->send_egress_err_status_cnt[7];
3678 }
3679
3680 static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry,
3681                                             void *context, int vl, int mode,
3682                                             u64 data)
3683 {
3684         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3685
3686         return dd->send_egress_err_status_cnt[6];
3687 }
3688
3689 static u64 access_tx_incorrect_link_state_err_cnt(
3690                                 const struct cntr_entry *entry,
3691                                 void *context, int vl, int mode, u64 data)
3692 {
3693         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3694
3695         return dd->send_egress_err_status_cnt[5];
3696 }
3697
3698 static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry,
3699                                       void *context, int vl, int mode,
3700                                       u64 data)
3701 {
3702         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3703
3704         return dd->send_egress_err_status_cnt[4];
3705 }
3706
3707 static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt(
3708                                 const struct cntr_entry *entry,
3709                                 void *context, int vl, int mode, u64 data)
3710 {
3711         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3712
3713         return dd->send_egress_err_status_cnt[3];
3714 }
3715
3716 static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry,
3717                                             void *context, int vl, int mode,
3718                                             u64 data)
3719 {
3720         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3721
3722         return dd->send_egress_err_status_cnt[2];
3723 }
3724
3725 static u64 access_tx_pkt_integrity_mem_unc_err_cnt(
3726                                 const struct cntr_entry *entry,
3727                                 void *context, int vl, int mode, u64 data)
3728 {
3729         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3730
3731         return dd->send_egress_err_status_cnt[1];
3732 }
3733
3734 static u64 access_tx_pkt_integrity_mem_cor_err_cnt(
3735                                 const struct cntr_entry *entry,
3736                                 void *context, int vl, int mode, u64 data)
3737 {
3738         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3739
3740         return dd->send_egress_err_status_cnt[0];
3741 }
3742
3743 /*
3744  * Software counters corresponding to each of the
3745  * error status bits within SendErrStatus
3746  */
3747 static u64 access_send_csr_write_bad_addr_err_cnt(
3748                                 const struct cntr_entry *entry,
3749                                 void *context, int vl, int mode, u64 data)
3750 {
3751         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3752
3753         return dd->send_err_status_cnt[2];
3754 }
3755
3756 static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
3757                                                  void *context, int vl,
3758                                                  int mode, u64 data)
3759 {
3760         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3761
3762         return dd->send_err_status_cnt[1];
3763 }
3764
3765 static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry,
3766                                       void *context, int vl, int mode,
3767                                       u64 data)
3768 {
3769         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3770
3771         return dd->send_err_status_cnt[0];
3772 }
3773
3774 /*
3775  * Software counters corresponding to each of the
3776  * error status bits within SendCtxtErrStatus
3777  */
3778 static u64 access_pio_write_out_of_bounds_err_cnt(
3779                                 const struct cntr_entry *entry,
3780                                 void *context, int vl, int mode, u64 data)
3781 {
3782         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3783
3784         return dd->sw_ctxt_err_status_cnt[4];
3785 }
3786
3787 static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry,
3788                                              void *context, int vl, int mode,
3789                                              u64 data)
3790 {
3791         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3792
3793         return dd->sw_ctxt_err_status_cnt[3];
3794 }
3795
3796 static u64 access_pio_write_crosses_boundary_err_cnt(
3797                                 const struct cntr_entry *entry,
3798                                 void *context, int vl, int mode, u64 data)
3799 {
3800         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3801
3802         return dd->sw_ctxt_err_status_cnt[2];
3803 }
3804
3805 static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry,
3806                                                 void *context, int vl,
3807                                                 int mode, u64 data)
3808 {
3809         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3810
3811         return dd->sw_ctxt_err_status_cnt[1];
3812 }
3813
3814 static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry,
3815                                                void *context, int vl, int mode,
3816                                                u64 data)
3817 {
3818         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3819
3820         return dd->sw_ctxt_err_status_cnt[0];
3821 }
3822
3823 /*
3824  * Software counters corresponding to each of the
3825  * error status bits within SendDmaEngErrStatus
3826  */
3827 static u64 access_sdma_header_request_fifo_cor_err_cnt(
3828                                 const struct cntr_entry *entry,
3829                                 void *context, int vl, int mode, u64 data)
3830 {
3831         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3832
3833         return dd->sw_send_dma_eng_err_status_cnt[23];
3834 }
3835
3836 static u64 access_sdma_header_storage_cor_err_cnt(
3837                                 const struct cntr_entry *entry,
3838                                 void *context, int vl, int mode, u64 data)
3839 {
3840         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3841
3842         return dd->sw_send_dma_eng_err_status_cnt[22];
3843 }
3844
3845 static u64 access_sdma_packet_tracking_cor_err_cnt(
3846                                 const struct cntr_entry *entry,
3847                                 void *context, int vl, int mode, u64 data)
3848 {
3849         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3850
3851         return dd->sw_send_dma_eng_err_status_cnt[21];
3852 }
3853
3854 static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry,
3855                                             void *context, int vl, int mode,
3856                                             u64 data)
3857 {
3858         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3859
3860         return dd->sw_send_dma_eng_err_status_cnt[20];
3861 }
3862
3863 static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry,
3864                                               void *context, int vl, int mode,
3865                                               u64 data)
3866 {
3867         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3868
3869         return dd->sw_send_dma_eng_err_status_cnt[19];
3870 }
3871
3872 static u64 access_sdma_header_request_fifo_unc_err_cnt(
3873                                 const struct cntr_entry *entry,
3874                                 void *context, int vl, int mode, u64 data)
3875 {
3876         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3877
3878         return dd->sw_send_dma_eng_err_status_cnt[18];
3879 }
3880
3881 static u64 access_sdma_header_storage_unc_err_cnt(
3882                                 const struct cntr_entry *entry,
3883                                 void *context, int vl, int mode, u64 data)
3884 {
3885         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3886
3887         return dd->sw_send_dma_eng_err_status_cnt[17];
3888 }
3889
3890 static u64 access_sdma_packet_tracking_unc_err_cnt(
3891                                 const struct cntr_entry *entry,
3892                                 void *context, int vl, int mode, u64 data)
3893 {
3894         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3895
3896         return dd->sw_send_dma_eng_err_status_cnt[16];
3897 }
3898
3899 static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry,
3900                                             void *context, int vl, int mode,
3901                                             u64 data)
3902 {
3903         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3904
3905         return dd->sw_send_dma_eng_err_status_cnt[15];
3906 }
3907
3908 static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry,
3909                                               void *context, int vl, int mode,
3910                                               u64 data)
3911 {
3912         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3913
3914         return dd->sw_send_dma_eng_err_status_cnt[14];
3915 }
3916
3917 static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry,
3918                                        void *context, int vl, int mode,
3919                                        u64 data)
3920 {
3921         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3922
3923         return dd->sw_send_dma_eng_err_status_cnt[13];
3924 }
3925
3926 static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry,
3927                                              void *context, int vl, int mode,
3928                                              u64 data)
3929 {
3930         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3931
3932         return dd->sw_send_dma_eng_err_status_cnt[12];
3933 }
3934
3935 static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry,
3936                                               void *context, int vl, int mode,
3937                                               u64 data)
3938 {
3939         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3940
3941         return dd->sw_send_dma_eng_err_status_cnt[11];
3942 }
3943
3944 static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry,
3945                                              void *context, int vl, int mode,
3946                                              u64 data)
3947 {
3948         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3949
3950         return dd->sw_send_dma_eng_err_status_cnt[10];
3951 }
3952
3953 static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry,
3954                                           void *context, int vl, int mode,
3955                                           u64 data)
3956 {
3957         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3958
3959         return dd->sw_send_dma_eng_err_status_cnt[9];
3960 }
3961
3962 static u64 access_sdma_packet_desc_overflow_err_cnt(
3963                                 const struct cntr_entry *entry,
3964                                 void *context, int vl, int mode, u64 data)
3965 {
3966         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3967
3968         return dd->sw_send_dma_eng_err_status_cnt[8];
3969 }
3970
3971 static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry,
3972                                                void *context, int vl,
3973                                                int mode, u64 data)
3974 {
3975         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3976
3977         return dd->sw_send_dma_eng_err_status_cnt[7];
3978 }
3979
3980 static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry,
3981                                     void *context, int vl, int mode, u64 data)
3982 {
3983         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3984
3985         return dd->sw_send_dma_eng_err_status_cnt[6];
3986 }
3987
3988 static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry,
3989                                         void *context, int vl, int mode,
3990                                         u64 data)
3991 {
3992         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3993
3994         return dd->sw_send_dma_eng_err_status_cnt[5];
3995 }
3996
3997 static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry,
3998                                           void *context, int vl, int mode,
3999                                           u64 data)
4000 {
4001         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4002
4003         return dd->sw_send_dma_eng_err_status_cnt[4];
4004 }
4005
4006 static u64 access_sdma_tail_out_of_bounds_err_cnt(
4007                                 const struct cntr_entry *entry,
4008                                 void *context, int vl, int mode, u64 data)
4009 {
4010         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4011
4012         return dd->sw_send_dma_eng_err_status_cnt[3];
4013 }
4014
4015 static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry,
4016                                         void *context, int vl, int mode,
4017                                         u64 data)
4018 {
4019         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4020
4021         return dd->sw_send_dma_eng_err_status_cnt[2];
4022 }
4023
4024 static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry,
4025                                             void *context, int vl, int mode,
4026                                             u64 data)
4027 {
4028         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4029
4030         return dd->sw_send_dma_eng_err_status_cnt[1];
4031 }
4032
4033 static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry,
4034                                         void *context, int vl, int mode,
4035                                         u64 data)
4036 {
4037         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4038
4039         return dd->sw_send_dma_eng_err_status_cnt[0];
4040 }
4041
4042 static u64 access_dc_rcv_err_cnt(const struct cntr_entry *entry,
4043                                  void *context, int vl, int mode,
4044                                  u64 data)
4045 {
4046         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4047
4048         u64 val = 0;
4049         u64 csr = entry->csr;
4050
4051         val = read_write_csr(dd, csr, mode, data);
4052         if (mode == CNTR_MODE_R) {
4053                 val = val > CNTR_MAX - dd->sw_rcv_bypass_packet_errors ?
4054                         CNTR_MAX : val + dd->sw_rcv_bypass_packet_errors;
4055         } else if (mode == CNTR_MODE_W) {
4056                 dd->sw_rcv_bypass_packet_errors = 0;
4057         } else {
4058                 dd_dev_err(dd, "Invalid cntr register access mode");
4059                 return 0;
4060         }
4061         return val;
4062 }
4063
4064 #define def_access_sw_cpu(cntr) \
4065 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry,               \
4066                               void *context, int vl, int mode, u64 data)      \
4067 {                                                                             \
4068         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;        \
4069         return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr,       \
4070                               ppd->ibport_data.rvp.cntr, vl,                  \
4071                               mode, data);                                    \
4072 }
4073
4074 def_access_sw_cpu(rc_acks);
4075 def_access_sw_cpu(rc_qacks);
4076 def_access_sw_cpu(rc_delayed_comp);
4077
4078 #define def_access_ibp_counter(cntr) \
4079 static u64 access_ibp_##cntr(const struct cntr_entry *entry,                  \
4080                                 void *context, int vl, int mode, u64 data)    \
4081 {                                                                             \
4082         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;        \
4083                                                                               \
4084         if (vl != CNTR_INVALID_VL)                                            \
4085                 return 0;                                                     \
4086                                                                               \
4087         return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr,        \
4088                              mode, data);                                     \
4089 }
4090
4091 def_access_ibp_counter(loop_pkts);
4092 def_access_ibp_counter(rc_resends);
4093 def_access_ibp_counter(rnr_naks);
4094 def_access_ibp_counter(other_naks);
4095 def_access_ibp_counter(rc_timeouts);
4096 def_access_ibp_counter(pkt_drops);
4097 def_access_ibp_counter(dmawait);
4098 def_access_ibp_counter(rc_seqnak);
4099 def_access_ibp_counter(rc_dupreq);
4100 def_access_ibp_counter(rdma_seq);
4101 def_access_ibp_counter(unaligned);
4102 def_access_ibp_counter(seq_naks);
4103
4104 static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = {
4105 [C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH),
4106 [C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT,
4107                         CNTR_NORMAL),
4108 [C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT,
4109                         CNTR_NORMAL),
4110 [C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs,
4111                         RCV_TID_FLOW_GEN_MISMATCH_CNT,
4112                         CNTR_NORMAL),
4113 [C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL,
4114                         CNTR_NORMAL),
4115 [C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs,
4116                         RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL),
4117 [C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt,
4118                         CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL),
4119 [C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT,
4120                         CNTR_NORMAL),
4121 [C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT,
4122                         CNTR_NORMAL),
4123 [C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT,
4124                         CNTR_NORMAL),
4125 [C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT,
4126                         CNTR_NORMAL),
4127 [C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT,
4128                         CNTR_NORMAL),
4129 [C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT,
4130                         CNTR_NORMAL),
4131 [C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt,
4132                         CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL),
4133 [C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt,
4134                         CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL),
4135 [C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT,
4136                               CNTR_SYNTH),
4137 [C_DC_RCV_ERR] = CNTR_ELEM("DcRecvErr", DCC_ERR_PORTRCV_ERR_CNT, 0, CNTR_SYNTH,
4138                             access_dc_rcv_err_cnt),
4139 [C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT,
4140                                  CNTR_SYNTH),
4141 [C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT,
4142                                   CNTR_SYNTH),
4143 [C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT,
4144                                   CNTR_SYNTH),
4145 [C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts,
4146                                    DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH),
4147 [C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts,
4148                                   DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4149                                   CNTR_SYNTH),
4150 [C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr,
4151                                 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH),
4152 [C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT,
4153                                CNTR_SYNTH),
4154 [C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT,
4155                               CNTR_SYNTH),
4156 [C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT,
4157                                CNTR_SYNTH),
4158 [C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT,
4159                                  CNTR_SYNTH),
4160 [C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT,
4161                                 CNTR_SYNTH),
4162 [C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT,
4163                                 CNTR_SYNTH),
4164 [C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT,
4165                                CNTR_SYNTH),
4166 [C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT,
4167                                  CNTR_SYNTH | CNTR_VL),
4168 [C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT,
4169                                 CNTR_SYNTH | CNTR_VL),
4170 [C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH),
4171 [C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT,
4172                                  CNTR_SYNTH | CNTR_VL),
4173 [C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH),
4174 [C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT,
4175                                  CNTR_SYNTH | CNTR_VL),
4176 [C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT,
4177                               CNTR_SYNTH),
4178 [C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT,
4179                                  CNTR_SYNTH | CNTR_VL),
4180 [C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT,
4181                                 CNTR_SYNTH),
4182 [C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT,
4183                                    CNTR_SYNTH | CNTR_VL),
4184 [C_DC_TOTAL_CRC] =
4185         DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR,
4186                          CNTR_SYNTH),
4187 [C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0,
4188                                   CNTR_SYNTH),
4189 [C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1,
4190                                   CNTR_SYNTH),
4191 [C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2,
4192                                   CNTR_SYNTH),
4193 [C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3,
4194                                   CNTR_SYNTH),
4195 [C_DC_CRC_MULT_LN] =
4196         DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN,
4197                          CNTR_SYNTH),
4198 [C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT,
4199                                     CNTR_SYNTH),
4200 [C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT,
4201                                     CNTR_SYNTH),
4202 [C_DC_SEQ_CRC_CNT] =
4203         DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT,
4204                          CNTR_SYNTH),
4205 [C_DC_ESC0_ONLY_CNT] =
4206         DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT,
4207                          CNTR_SYNTH),
4208 [C_DC_ESC0_PLUS1_CNT] =
4209         DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT,
4210                          CNTR_SYNTH),
4211 [C_DC_ESC0_PLUS2_CNT] =
4212         DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT,
4213                          CNTR_SYNTH),
4214 [C_DC_REINIT_FROM_PEER_CNT] =
4215         DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT,
4216                          CNTR_SYNTH),
4217 [C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT,
4218                                   CNTR_SYNTH),
4219 [C_DC_MISC_FLG_CNT] =
4220         DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT,
4221                          CNTR_SYNTH),
4222 [C_DC_PRF_GOOD_LTP_CNT] =
4223         DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH),
4224 [C_DC_PRF_ACCEPTED_LTP_CNT] =
4225         DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT,
4226                          CNTR_SYNTH),
4227 [C_DC_PRF_RX_FLIT_CNT] =
4228         DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH),
4229 [C_DC_PRF_TX_FLIT_CNT] =
4230         DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH),
4231 [C_DC_PRF_CLK_CNTR] =
4232         DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH),
4233 [C_DC_PG_DBG_FLIT_CRDTS_CNT] =
4234         DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH),
4235 [C_DC_PG_STS_PAUSE_COMPLETE_CNT] =
4236         DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT,
4237                          CNTR_SYNTH),
4238 [C_DC_PG_STS_TX_SBE_CNT] =
4239         DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH),
4240 [C_DC_PG_STS_TX_MBE_CNT] =
4241         DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT,
4242                          CNTR_SYNTH),
4243 [C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL,
4244                             access_sw_cpu_intr),
4245 [C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL,
4246                             access_sw_cpu_rcv_limit),
4247 [C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL,
4248                             access_sw_vtx_wait),
4249 [C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL,
4250                             access_sw_pio_wait),
4251 [C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL,
4252                             access_sw_pio_drain),
4253 [C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL,
4254                             access_sw_kmem_wait),
4255 [C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL,
4256                             access_sw_send_schedule),
4257 [C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn",
4258                                       SEND_DMA_DESC_FETCHED_CNT, 0,
4259                                       CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4260                                       dev_access_u32_csr),
4261 [C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0,
4262                              CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4263                              access_sde_int_cnt),
4264 [C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0,
4265                              CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4266                              access_sde_err_cnt),
4267 [C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0,
4268                                   CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4269                                   access_sde_idle_int_cnt),
4270 [C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0,
4271                                       CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4272                                       access_sde_progress_int_cnt),
4273 /* MISC_ERR_STATUS */
4274 [C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0,
4275                                 CNTR_NORMAL,
4276                                 access_misc_pll_lock_fail_err_cnt),
4277 [C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0,
4278                                 CNTR_NORMAL,
4279                                 access_misc_mbist_fail_err_cnt),
4280 [C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0,
4281                                 CNTR_NORMAL,
4282                                 access_misc_invalid_eep_cmd_err_cnt),
4283 [C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0,
4284                                 CNTR_NORMAL,
4285                                 access_misc_efuse_done_parity_err_cnt),
4286 [C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0,
4287                                 CNTR_NORMAL,
4288                                 access_misc_efuse_write_err_cnt),
4289 [C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0,
4290                                 0, CNTR_NORMAL,
4291                                 access_misc_efuse_read_bad_addr_err_cnt),
4292 [C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0,
4293                                 CNTR_NORMAL,
4294                                 access_misc_efuse_csr_parity_err_cnt),
4295 [C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0,
4296                                 CNTR_NORMAL,
4297                                 access_misc_fw_auth_failed_err_cnt),
4298 [C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0,
4299                                 CNTR_NORMAL,
4300                                 access_misc_key_mismatch_err_cnt),
4301 [C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0,
4302                                 CNTR_NORMAL,
4303                                 access_misc_sbus_write_failed_err_cnt),
4304 [C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0,
4305                                 CNTR_NORMAL,
4306                                 access_misc_csr_write_bad_addr_err_cnt),
4307 [C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0,
4308                                 CNTR_NORMAL,
4309                                 access_misc_csr_read_bad_addr_err_cnt),
4310 [C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0,
4311                                 CNTR_NORMAL,
4312                                 access_misc_csr_parity_err_cnt),
4313 /* CceErrStatus */
4314 [C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0,
4315                                 CNTR_NORMAL,
4316                                 access_sw_cce_err_status_aggregated_cnt),
4317 [C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0,
4318                                 CNTR_NORMAL,
4319                                 access_cce_msix_csr_parity_err_cnt),
4320 [C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0,
4321                                 CNTR_NORMAL,
4322                                 access_cce_int_map_unc_err_cnt),
4323 [C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0,
4324                                 CNTR_NORMAL,
4325                                 access_cce_int_map_cor_err_cnt),
4326 [C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0,
4327                                 CNTR_NORMAL,
4328                                 access_cce_msix_table_unc_err_cnt),
4329 [C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0,
4330                                 CNTR_NORMAL,
4331                                 access_cce_msix_table_cor_err_cnt),
4332 [C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0,
4333                                 0, CNTR_NORMAL,
4334                                 access_cce_rxdma_conv_fifo_parity_err_cnt),
4335 [C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0,
4336                                 0, CNTR_NORMAL,
4337                                 access_cce_rcpl_async_fifo_parity_err_cnt),
4338 [C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0,
4339                                 CNTR_NORMAL,
4340                                 access_cce_seg_write_bad_addr_err_cnt),
4341 [C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0,
4342                                 CNTR_NORMAL,
4343                                 access_cce_seg_read_bad_addr_err_cnt),
4344 [C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0,
4345                                 CNTR_NORMAL,
4346                                 access_la_triggered_cnt),
4347 [C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0,
4348                                 CNTR_NORMAL,
4349                                 access_cce_trgt_cpl_timeout_err_cnt),
4350 [C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0,
4351                                 CNTR_NORMAL,
4352                                 access_pcic_receive_parity_err_cnt),
4353 [C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0,
4354                                 CNTR_NORMAL,
4355                                 access_pcic_transmit_back_parity_err_cnt),
4356 [C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0,
4357                                 0, CNTR_NORMAL,
4358                                 access_pcic_transmit_front_parity_err_cnt),
4359 [C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0,
4360                                 CNTR_NORMAL,
4361                                 access_pcic_cpl_dat_q_unc_err_cnt),
4362 [C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0,
4363                                 CNTR_NORMAL,
4364                                 access_pcic_cpl_hd_q_unc_err_cnt),
4365 [C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0,
4366                                 CNTR_NORMAL,
4367                                 access_pcic_post_dat_q_unc_err_cnt),
4368 [C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0,
4369                                 CNTR_NORMAL,
4370                                 access_pcic_post_hd_q_unc_err_cnt),
4371 [C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0,
4372                                 CNTR_NORMAL,
4373                                 access_pcic_retry_sot_mem_unc_err_cnt),
4374 [C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0,
4375                                 CNTR_NORMAL,
4376                                 access_pcic_retry_mem_unc_err),
4377 [C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0,
4378                                 CNTR_NORMAL,
4379                                 access_pcic_n_post_dat_q_parity_err_cnt),
4380 [C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0,
4381                                 CNTR_NORMAL,
4382                                 access_pcic_n_post_h_q_parity_err_cnt),
4383 [C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0,
4384                                 CNTR_NORMAL,
4385                                 access_pcic_cpl_dat_q_cor_err_cnt),
4386 [C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0,
4387                                 CNTR_NORMAL,
4388                                 access_pcic_cpl_hd_q_cor_err_cnt),
4389 [C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0,
4390                                 CNTR_NORMAL,
4391                                 access_pcic_post_dat_q_cor_err_cnt),
4392 [C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0,
4393                                 CNTR_NORMAL,
4394                                 access_pcic_post_hd_q_cor_err_cnt),
4395 [C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0,
4396                                 CNTR_NORMAL,
4397                                 access_pcic_retry_sot_mem_cor_err_cnt),
4398 [C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0,
4399                                 CNTR_NORMAL,
4400                                 access_pcic_retry_mem_cor_err_cnt),
4401 [C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM(
4402                                 "CceCli1AsyncFifoDbgParityError", 0, 0,
4403                                 CNTR_NORMAL,
4404                                 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4405 [C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM(
4406                                 "CceCli1AsyncFifoRxdmaParityError", 0, 0,
4407                                 CNTR_NORMAL,
4408                                 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4409                                 ),
4410 [C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM(
4411                         "CceCli1AsyncFifoSdmaHdParityErr", 0, 0,
4412                         CNTR_NORMAL,
4413                         access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4414 [C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM(
4415                         "CceCli1AsyncFifoPioCrdtParityErr", 0, 0,
4416                         CNTR_NORMAL,
4417                         access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4418 [C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0,
4419                         0, CNTR_NORMAL,
4420                         access_cce_cli2_async_fifo_parity_err_cnt),
4421 [C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0,
4422                         CNTR_NORMAL,
4423                         access_cce_csr_cfg_bus_parity_err_cnt),
4424 [C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0,
4425                         0, CNTR_NORMAL,
4426                         access_cce_cli0_async_fifo_parity_err_cnt),
4427 [C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0,
4428                         CNTR_NORMAL,
4429                         access_cce_rspd_data_parity_err_cnt),
4430 [C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0,
4431                         CNTR_NORMAL,
4432                         access_cce_trgt_access_err_cnt),
4433 [C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0,
4434                         0, CNTR_NORMAL,
4435                         access_cce_trgt_async_fifo_parity_err_cnt),
4436 [C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0,
4437                         CNTR_NORMAL,
4438                         access_cce_csr_write_bad_addr_err_cnt),
4439 [C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0,
4440                         CNTR_NORMAL,
4441                         access_cce_csr_read_bad_addr_err_cnt),
4442 [C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0,
4443                         CNTR_NORMAL,
4444                         access_ccs_csr_parity_err_cnt),
4445
4446 /* RcvErrStatus */
4447 [C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0,
4448                         CNTR_NORMAL,
4449                         access_rx_csr_parity_err_cnt),
4450 [C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0,
4451                         CNTR_NORMAL,
4452                         access_rx_csr_write_bad_addr_err_cnt),
4453 [C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0,
4454                         CNTR_NORMAL,
4455                         access_rx_csr_read_bad_addr_err_cnt),
4456 [C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0,
4457                         CNTR_NORMAL,
4458                         access_rx_dma_csr_unc_err_cnt),
4459 [C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0,
4460                         CNTR_NORMAL,
4461                         access_rx_dma_dq_fsm_encoding_err_cnt),
4462 [C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0,
4463                         CNTR_NORMAL,
4464                         access_rx_dma_eq_fsm_encoding_err_cnt),
4465 [C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0,
4466                         CNTR_NORMAL,
4467                         access_rx_dma_csr_parity_err_cnt),
4468 [C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0,
4469                         CNTR_NORMAL,
4470                         access_rx_rbuf_data_cor_err_cnt),
4471 [C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0,
4472                         CNTR_NORMAL,
4473                         access_rx_rbuf_data_unc_err_cnt),
4474 [C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0,
4475                         CNTR_NORMAL,
4476                         access_rx_dma_data_fifo_rd_cor_err_cnt),
4477 [C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0,
4478                         CNTR_NORMAL,
4479                         access_rx_dma_data_fifo_rd_unc_err_cnt),
4480 [C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0,
4481                         CNTR_NORMAL,
4482                         access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4483 [C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0,
4484                         CNTR_NORMAL,
4485                         access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4486 [C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0,
4487                         CNTR_NORMAL,
4488                         access_rx_rbuf_desc_part2_cor_err_cnt),
4489 [C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0,
4490                         CNTR_NORMAL,
4491                         access_rx_rbuf_desc_part2_unc_err_cnt),
4492 [C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0,
4493                         CNTR_NORMAL,
4494                         access_rx_rbuf_desc_part1_cor_err_cnt),
4495 [C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0,
4496                         CNTR_NORMAL,
4497                         access_rx_rbuf_desc_part1_unc_err_cnt),
4498 [C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0,
4499                         CNTR_NORMAL,
4500                         access_rx_hq_intr_fsm_err_cnt),
4501 [C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0,
4502                         CNTR_NORMAL,
4503                         access_rx_hq_intr_csr_parity_err_cnt),
4504 [C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0,
4505                         CNTR_NORMAL,
4506                         access_rx_lookup_csr_parity_err_cnt),
4507 [C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0,
4508                         CNTR_NORMAL,
4509                         access_rx_lookup_rcv_array_cor_err_cnt),
4510 [C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0,
4511                         CNTR_NORMAL,
4512                         access_rx_lookup_rcv_array_unc_err_cnt),
4513 [C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0,
4514                         0, CNTR_NORMAL,
4515                         access_rx_lookup_des_part2_parity_err_cnt),
4516 [C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0,
4517                         0, CNTR_NORMAL,
4518                         access_rx_lookup_des_part1_unc_cor_err_cnt),
4519 [C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0,
4520                         CNTR_NORMAL,
4521                         access_rx_lookup_des_part1_unc_err_cnt),
4522 [C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0,
4523                         CNTR_NORMAL,
4524                         access_rx_rbuf_next_free_buf_cor_err_cnt),
4525 [C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0,
4526                         CNTR_NORMAL,
4527                         access_rx_rbuf_next_free_buf_unc_err_cnt),
4528 [C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM(
4529                         "RxRbufFlInitWrAddrParityErr", 0, 0,
4530                         CNTR_NORMAL,
4531                         access_rbuf_fl_init_wr_addr_parity_err_cnt),
4532 [C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0,
4533                         0, CNTR_NORMAL,
4534                         access_rx_rbuf_fl_initdone_parity_err_cnt),
4535 [C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0,
4536                         0, CNTR_NORMAL,
4537                         access_rx_rbuf_fl_write_addr_parity_err_cnt),
4538 [C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0,
4539                         CNTR_NORMAL,
4540                         access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4541 [C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0,
4542                         CNTR_NORMAL,
4543                         access_rx_rbuf_empty_err_cnt),
4544 [C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0,
4545                         CNTR_NORMAL,
4546                         access_rx_rbuf_full_err_cnt),
4547 [C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0,
4548                         CNTR_NORMAL,
4549                         access_rbuf_bad_lookup_err_cnt),
4550 [C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0,
4551                         CNTR_NORMAL,
4552                         access_rbuf_ctx_id_parity_err_cnt),
4553 [C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0,
4554                         CNTR_NORMAL,
4555                         access_rbuf_csr_qeopdw_parity_err_cnt),
4556 [C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM(
4557                         "RxRbufCsrQNumOfPktParityErr", 0, 0,
4558                         CNTR_NORMAL,
4559                         access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4560 [C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM(
4561                         "RxRbufCsrQTlPtrParityErr", 0, 0,
4562                         CNTR_NORMAL,
4563                         access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4564 [C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0,
4565                         0, CNTR_NORMAL,
4566                         access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4567 [C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0,
4568                         0, CNTR_NORMAL,
4569                         access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4570 [C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr",
4571                         0, 0, CNTR_NORMAL,
4572                         access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4573 [C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0,
4574                         0, CNTR_NORMAL,
4575                         access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4576 [C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM(
4577                         "RxRbufCsrQHeadBufNumParityErr", 0, 0,
4578                         CNTR_NORMAL,
4579                         access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4580 [C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0,
4581                         0, CNTR_NORMAL,
4582                         access_rx_rbuf_block_list_read_cor_err_cnt),
4583 [C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0,
4584                         0, CNTR_NORMAL,
4585                         access_rx_rbuf_block_list_read_unc_err_cnt),
4586 [C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0,
4587                         CNTR_NORMAL,
4588                         access_rx_rbuf_lookup_des_cor_err_cnt),
4589 [C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0,
4590                         CNTR_NORMAL,
4591                         access_rx_rbuf_lookup_des_unc_err_cnt),
4592 [C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM(
4593                         "RxRbufLookupDesRegUncCorErr", 0, 0,
4594                         CNTR_NORMAL,
4595                         access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4596 [C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0,
4597                         CNTR_NORMAL,
4598                         access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4599 [C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0,
4600                         CNTR_NORMAL,
4601                         access_rx_rbuf_free_list_cor_err_cnt),
4602 [C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0,
4603                         CNTR_NORMAL,
4604                         access_rx_rbuf_free_list_unc_err_cnt),
4605 [C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0,
4606                         CNTR_NORMAL,
4607                         access_rx_rcv_fsm_encoding_err_cnt),
4608 [C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0,
4609                         CNTR_NORMAL,
4610                         access_rx_dma_flag_cor_err_cnt),
4611 [C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0,
4612                         CNTR_NORMAL,
4613                         access_rx_dma_flag_unc_err_cnt),
4614 [C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0,
4615                         CNTR_NORMAL,
4616                         access_rx_dc_sop_eop_parity_err_cnt),
4617 [C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0,
4618                         CNTR_NORMAL,
4619                         access_rx_rcv_csr_parity_err_cnt),
4620 [C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0,
4621                         CNTR_NORMAL,
4622                         access_rx_rcv_qp_map_table_cor_err_cnt),
4623 [C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0,
4624                         CNTR_NORMAL,
4625                         access_rx_rcv_qp_map_table_unc_err_cnt),
4626 [C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0,
4627                         CNTR_NORMAL,
4628                         access_rx_rcv_data_cor_err_cnt),
4629 [C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0,
4630                         CNTR_NORMAL,
4631                         access_rx_rcv_data_unc_err_cnt),
4632 [C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0,
4633                         CNTR_NORMAL,
4634                         access_rx_rcv_hdr_cor_err_cnt),
4635 [C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0,
4636                         CNTR_NORMAL,
4637                         access_rx_rcv_hdr_unc_err_cnt),
4638 [C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0,
4639                         CNTR_NORMAL,
4640                         access_rx_dc_intf_parity_err_cnt),
4641 [C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0,
4642                         CNTR_NORMAL,
4643                         access_rx_dma_csr_cor_err_cnt),
4644 /* SendPioErrStatus */
4645 [C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0,
4646                         CNTR_NORMAL,
4647                         access_pio_pec_sop_head_parity_err_cnt),
4648 [C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0,
4649                         CNTR_NORMAL,
4650                         access_pio_pcc_sop_head_parity_err_cnt),
4651 [C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr",
4652                         0, 0, CNTR_NORMAL,
4653                         access_pio_last_returned_cnt_parity_err_cnt),
4654 [C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0,
4655                         0, CNTR_NORMAL,
4656                         access_pio_current_free_cnt_parity_err_cnt),
4657 [C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0,
4658                         CNTR_NORMAL,
4659                         access_pio_reserved_31_err_cnt),
4660 [C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0,
4661                         CNTR_NORMAL,
4662                         access_pio_reserved_30_err_cnt),
4663 [C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0,
4664                         CNTR_NORMAL,
4665                         access_pio_ppmc_sop_len_err_cnt),
4666 [C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0,
4667                         CNTR_NORMAL,
4668                         access_pio_ppmc_bqc_mem_parity_err_cnt),
4669 [C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0,
4670                         CNTR_NORMAL,
4671                         access_pio_vl_fifo_parity_err_cnt),
4672 [C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0,
4673                         CNTR_NORMAL,
4674                         access_pio_vlf_sop_parity_err_cnt),
4675 [C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0,
4676                         CNTR_NORMAL,
4677                         access_pio_vlf_v1_len_parity_err_cnt),
4678 [C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0,
4679                         CNTR_NORMAL,
4680                         access_pio_block_qw_count_parity_err_cnt),
4681 [C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0,
4682                         CNTR_NORMAL,
4683                         access_pio_write_qw_valid_parity_err_cnt),
4684 [C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0,
4685                         CNTR_NORMAL,
4686                         access_pio_state_machine_err_cnt),
4687 [C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0,
4688                         CNTR_NORMAL,
4689                         access_pio_write_data_parity_err_cnt),
4690 [C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0,
4691                         CNTR_NORMAL,
4692                         access_pio_host_addr_mem_cor_err_cnt),
4693 [C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0,
4694                         CNTR_NORMAL,
4695                         access_pio_host_addr_mem_unc_err_cnt),
4696 [C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0,
4697                         CNTR_NORMAL,
4698                         access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4699 [C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0,
4700                         CNTR_NORMAL,
4701                         access_pio_init_sm_in_err_cnt),
4702 [C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0,
4703                         CNTR_NORMAL,
4704                         access_pio_ppmc_pbl_fifo_err_cnt),
4705 [C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0,
4706                         0, CNTR_NORMAL,
4707                         access_pio_credit_ret_fifo_parity_err_cnt),
4708 [C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0,
4709                         CNTR_NORMAL,
4710                         access_pio_v1_len_mem_bank1_cor_err_cnt),
4711 [C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0,
4712                         CNTR_NORMAL,
4713                         access_pio_v1_len_mem_bank0_cor_err_cnt),
4714 [C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0,
4715                         CNTR_NORMAL,
4716                         access_pio_v1_len_mem_bank1_unc_err_cnt),
4717 [C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0,
4718                         CNTR_NORMAL,
4719                         access_pio_v1_len_mem_bank0_unc_err_cnt),
4720 [C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0,
4721                         CNTR_NORMAL,
4722                         access_pio_sm_pkt_reset_parity_err_cnt),
4723 [C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0,
4724                         CNTR_NORMAL,
4725                         access_pio_pkt_evict_fifo_parity_err_cnt),
4726 [C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM(
4727                         "PioSbrdctrlCrrelFifoParityErr", 0, 0,
4728                         CNTR_NORMAL,
4729                         access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4730 [C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0,
4731                         CNTR_NORMAL,
4732                         access_pio_sbrdctl_crrel_parity_err_cnt),
4733 [C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0,
4734                         CNTR_NORMAL,
4735                         access_pio_pec_fifo_parity_err_cnt),
4736 [C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0,
4737                         CNTR_NORMAL,
4738                         access_pio_pcc_fifo_parity_err_cnt),
4739 [C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0,
4740                         CNTR_NORMAL,
4741                         access_pio_sb_mem_fifo1_err_cnt),
4742 [C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0,
4743                         CNTR_NORMAL,
4744                         access_pio_sb_mem_fifo0_err_cnt),
4745 [C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0,
4746                         CNTR_NORMAL,
4747                         access_pio_csr_parity_err_cnt),
4748 [C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0,
4749                         CNTR_NORMAL,
4750                         access_pio_write_addr_parity_err_cnt),
4751 [C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0,
4752                         CNTR_NORMAL,
4753                         access_pio_write_bad_ctxt_err_cnt),
4754 /* SendDmaErrStatus */
4755 [C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0,
4756                         0, CNTR_NORMAL,
4757                         access_sdma_pcie_req_tracking_cor_err_cnt),
4758 [C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0,
4759                         0, CNTR_NORMAL,
4760                         access_sdma_pcie_req_tracking_unc_err_cnt),
4761 [C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0,
4762                         CNTR_NORMAL,
4763                         access_sdma_csr_parity_err_cnt),
4764 [C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0,
4765                         CNTR_NORMAL,
4766                         access_sdma_rpy_tag_err_cnt),
4767 /* SendEgressErrStatus */
4768 [C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0,
4769                         CNTR_NORMAL,
4770                         access_tx_read_pio_memory_csr_unc_err_cnt),
4771 [C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0,
4772                         0, CNTR_NORMAL,
4773                         access_tx_read_sdma_memory_csr_err_cnt),
4774 [C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0,
4775                         CNTR_NORMAL,
4776                         access_tx_egress_fifo_cor_err_cnt),
4777 [C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0,
4778                         CNTR_NORMAL,
4779                         access_tx_read_pio_memory_cor_err_cnt),
4780 [C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0,
4781                         CNTR_NORMAL,
4782                         access_tx_read_sdma_memory_cor_err_cnt),
4783 [C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0,
4784                         CNTR_NORMAL,
4785                         access_tx_sb_hdr_cor_err_cnt),
4786 [C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0,
4787                         CNTR_NORMAL,
4788                         access_tx_credit_overrun_err_cnt),
4789 [C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0,
4790                         CNTR_NORMAL,
4791                         access_tx_launch_fifo8_cor_err_cnt),
4792 [C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0,
4793                         CNTR_NORMAL,
4794                         access_tx_launch_fifo7_cor_err_cnt),
4795 [C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0,
4796                         CNTR_NORMAL,
4797                         access_tx_launch_fifo6_cor_err_cnt),
4798 [C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0,
4799                         CNTR_NORMAL,
4800                         access_tx_launch_fifo5_cor_err_cnt),
4801 [C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0,
4802                         CNTR_NORMAL,
4803                         access_tx_launch_fifo4_cor_err_cnt),
4804 [C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0,
4805                         CNTR_NORMAL,
4806                         access_tx_launch_fifo3_cor_err_cnt),
4807 [C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0,
4808                         CNTR_NORMAL,
4809                         access_tx_launch_fifo2_cor_err_cnt),
4810 [C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0,
4811                         CNTR_NORMAL,
4812                         access_tx_launch_fifo1_cor_err_cnt),
4813 [C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0,
4814                         CNTR_NORMAL,
4815                         access_tx_launch_fifo0_cor_err_cnt),
4816 [C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0,
4817                         CNTR_NORMAL,
4818                         access_tx_credit_return_vl_err_cnt),
4819 [C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0,
4820                         CNTR_NORMAL,
4821                         access_tx_hcrc_insertion_err_cnt),
4822 [C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0,
4823                         CNTR_NORMAL,
4824                         access_tx_egress_fifo_unc_err_cnt),
4825 [C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0,
4826                         CNTR_NORMAL,
4827                         access_tx_read_pio_memory_unc_err_cnt),
4828 [C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0,
4829                         CNTR_NORMAL,
4830                         access_tx_read_sdma_memory_unc_err_cnt),
4831 [C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0,
4832                         CNTR_NORMAL,
4833                         access_tx_sb_hdr_unc_err_cnt),
4834 [C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0,
4835                         CNTR_NORMAL,
4836                         access_tx_credit_return_partiy_err_cnt),
4837 [C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr",
4838                         0, 0, CNTR_NORMAL,
4839                         access_tx_launch_fifo8_unc_or_parity_err_cnt),
4840 [C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr",
4841                         0, 0, CNTR_NORMAL,
4842                         access_tx_launch_fifo7_unc_or_parity_err_cnt),
4843 [C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr",
4844                         0, 0, CNTR_NORMAL,
4845                         access_tx_launch_fifo6_unc_or_parity_err_cnt),
4846 [C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr",
4847                         0, 0, CNTR_NORMAL,
4848                         access_tx_launch_fifo5_unc_or_parity_err_cnt),
4849 [C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr",
4850                         0, 0, CNTR_NORMAL,
4851                         access_tx_launch_fifo4_unc_or_parity_err_cnt),
4852 [C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr",
4853                         0, 0, CNTR_NORMAL,
4854                         access_tx_launch_fifo3_unc_or_parity_err_cnt),
4855 [C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr",
4856                         0, 0, CNTR_NORMAL,
4857                         access_tx_launch_fifo2_unc_or_parity_err_cnt),
4858 [C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr",
4859                         0, 0, CNTR_NORMAL,
4860                         access_tx_launch_fifo1_unc_or_parity_err_cnt),
4861 [C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr",
4862                         0, 0, CNTR_NORMAL,
4863                         access_tx_launch_fifo0_unc_or_parity_err_cnt),
4864 [C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr",
4865                         0, 0, CNTR_NORMAL,
4866                         access_tx_sdma15_disallowed_packet_err_cnt),
4867 [C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr",
4868                         0, 0, CNTR_NORMAL,
4869                         access_tx_sdma14_disallowed_packet_err_cnt),
4870 [C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr",
4871                         0, 0, CNTR_NORMAL,
4872                         access_tx_sdma13_disallowed_packet_err_cnt),
4873 [C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr",
4874                         0, 0, CNTR_NORMAL,
4875                         access_tx_sdma12_disallowed_packet_err_cnt),
4876 [C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr",
4877                         0, 0, CNTR_NORMAL,
4878                         access_tx_sdma11_disallowed_packet_err_cnt),
4879 [C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr",
4880                         0, 0, CNTR_NORMAL,
4881                         access_tx_sdma10_disallowed_packet_err_cnt),
4882 [C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr",
4883                         0, 0, CNTR_NORMAL,
4884                         access_tx_sdma9_disallowed_packet_err_cnt),
4885 [C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr",
4886                         0, 0, CNTR_NORMAL,
4887                         access_tx_sdma8_disallowed_packet_err_cnt),
4888 [C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr",
4889                         0, 0, CNTR_NORMAL,
4890                         access_tx_sdma7_disallowed_packet_err_cnt),
4891 [C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr",
4892                         0, 0, CNTR_NORMAL,
4893                         access_tx_sdma6_disallowed_packet_err_cnt),
4894 [C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr",
4895                         0, 0, CNTR_NORMAL,
4896                         access_tx_sdma5_disallowed_packet_err_cnt),
4897 [C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr",
4898                         0, 0, CNTR_NORMAL,
4899                         access_tx_sdma4_disallowed_packet_err_cnt),
4900 [C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr",
4901                         0, 0, CNTR_NORMAL,
4902                         access_tx_sdma3_disallowed_packet_err_cnt),
4903 [C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr",
4904                         0, 0, CNTR_NORMAL,
4905                         access_tx_sdma2_disallowed_packet_err_cnt),
4906 [C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr",
4907                         0, 0, CNTR_NORMAL,
4908                         access_tx_sdma1_disallowed_packet_err_cnt),
4909 [C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr",
4910                         0, 0, CNTR_NORMAL,
4911                         access_tx_sdma0_disallowed_packet_err_cnt),
4912 [C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0,
4913                         CNTR_NORMAL,
4914                         access_tx_config_parity_err_cnt),
4915 [C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0,
4916                         CNTR_NORMAL,
4917                         access_tx_sbrd_ctl_csr_parity_err_cnt),
4918 [C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0,
4919                         CNTR_NORMAL,
4920                         access_tx_launch_csr_parity_err_cnt),
4921 [C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0,
4922                         CNTR_NORMAL,
4923                         access_tx_illegal_vl_err_cnt),
4924 [C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM(
4925                         "TxSbrdCtlStateMachineParityErr", 0, 0,
4926                         CNTR_NORMAL,
4927                         access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4928 [C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0,
4929                         CNTR_NORMAL,
4930                         access_egress_reserved_10_err_cnt),
4931 [C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0,
4932                         CNTR_NORMAL,
4933                         access_egress_reserved_9_err_cnt),
4934 [C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr",
4935                         0, 0, CNTR_NORMAL,
4936                         access_tx_sdma_launch_intf_parity_err_cnt),
4937 [C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0,
4938                         CNTR_NORMAL,
4939                         access_tx_pio_launch_intf_parity_err_cnt),
4940 [C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0,
4941                         CNTR_NORMAL,
4942                         access_egress_reserved_6_err_cnt),
4943 [C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0,
4944                         CNTR_NORMAL,
4945                         access_tx_incorrect_link_state_err_cnt),
4946 [C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0,
4947                         CNTR_NORMAL,
4948                         access_tx_linkdown_err_cnt),
4949 [C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM(
4950                         "EgressFifoUnderrunOrParityErr", 0, 0,
4951                         CNTR_NORMAL,
4952                         access_tx_egress_fifi_underrun_or_parity_err_cnt),
4953 [C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0,
4954                         CNTR_NORMAL,
4955                         access_egress_reserved_2_err_cnt),
4956 [C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0,
4957                         CNTR_NORMAL,
4958                         access_tx_pkt_integrity_mem_unc_err_cnt),
4959 [C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0,
4960                         CNTR_NORMAL,
4961                         access_tx_pkt_integrity_mem_cor_err_cnt),
4962 /* SendErrStatus */
4963 [C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0,
4964                         CNTR_NORMAL,
4965                         access_send_csr_write_bad_addr_err_cnt),
4966 [C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0,
4967                         CNTR_NORMAL,
4968                         access_send_csr_read_bad_addr_err_cnt),
4969 [C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0,
4970                         CNTR_NORMAL,
4971                         access_send_csr_parity_cnt),
4972 /* SendCtxtErrStatus */
4973 [C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0,
4974                         CNTR_NORMAL,
4975                         access_pio_write_out_of_bounds_err_cnt),
4976 [C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0,
4977                         CNTR_NORMAL,
4978                         access_pio_write_overflow_err_cnt),
4979 [C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr",
4980                         0, 0, CNTR_NORMAL,
4981                         access_pio_write_crosses_boundary_err_cnt),
4982 [C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0,
4983                         CNTR_NORMAL,
4984                         access_pio_disallowed_packet_err_cnt),
4985 [C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0,
4986                         CNTR_NORMAL,
4987                         access_pio_inconsistent_sop_err_cnt),
4988 /* SendDmaEngErrStatus */
4989 [C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr",
4990                         0, 0, CNTR_NORMAL,
4991                         access_sdma_header_request_fifo_cor_err_cnt),
4992 [C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0,
4993                         CNTR_NORMAL,
4994                         access_sdma_header_storage_cor_err_cnt),
4995 [C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0,
4996                         CNTR_NORMAL,
4997                         access_sdma_packet_tracking_cor_err_cnt),
4998 [C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0,
4999                         CNTR_NORMAL,
5000                         access_sdma_assembly_cor_err_cnt),
5001 [C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0,
5002                         CNTR_NORMAL,
5003                         access_sdma_desc_table_cor_err_cnt),
5004 [C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr",
5005                         0, 0, CNTR_NORMAL,
5006                         access_sdma_header_request_fifo_unc_err_cnt),
5007 [C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0,
5008                         CNTR_NORMAL,
5009                         access_sdma_header_storage_unc_err_cnt),
5010 [C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0,
5011                         CNTR_NORMAL,
5012                         access_sdma_packet_tracking_unc_err_cnt),
5013 [C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0,
5014                         CNTR_NORMAL,
5015                         access_sdma_assembly_unc_err_cnt),
5016 [C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0,
5017                         CNTR_NORMAL,
5018                         access_sdma_desc_table_unc_err_cnt),
5019 [C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0,
5020                         CNTR_NORMAL,
5021                         access_sdma_timeout_err_cnt),
5022 [C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0,
5023                         CNTR_NORMAL,
5024                         access_sdma_header_length_err_cnt),
5025 [C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0,
5026                         CNTR_NORMAL,
5027                         access_sdma_header_address_err_cnt),
5028 [C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0,
5029                         CNTR_NORMAL,
5030                         access_sdma_header_select_err_cnt),
5031 [C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0,
5032                         CNTR_NORMAL,
5033                         access_sdma_reserved_9_err_cnt),
5034 [C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0,
5035                         CNTR_NORMAL,
5036                         access_sdma_packet_desc_overflow_err_cnt),
5037 [C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0,
5038                         CNTR_NORMAL,
5039                         access_sdma_length_mismatch_err_cnt),
5040 [C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0,
5041                         CNTR_NORMAL,
5042                         access_sdma_halt_err_cnt),
5043 [C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0,
5044                         CNTR_NORMAL,
5045                         access_sdma_mem_read_err_cnt),
5046 [C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0,
5047                         CNTR_NORMAL,
5048                         access_sdma_first_desc_err_cnt),
5049 [C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0,
5050                         CNTR_NORMAL,
5051                         access_sdma_tail_out_of_bounds_err_cnt),
5052 [C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0,
5053                         CNTR_NORMAL,
5054                         access_sdma_too_long_err_cnt),
5055 [C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0,
5056                         CNTR_NORMAL,
5057                         access_sdma_gen_mismatch_err_cnt),
5058 [C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0,
5059                         CNTR_NORMAL,
5060                         access_sdma_wrong_dw_err_cnt),
5061 };
5062
5063 static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = {
5064 [C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT,
5065                         CNTR_NORMAL),
5066 [C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT,
5067                         CNTR_NORMAL),
5068 [C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT,
5069                         CNTR_NORMAL),
5070 [C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT,
5071                         CNTR_NORMAL),
5072 [C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT,
5073                         CNTR_NORMAL),
5074 [C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT,
5075                         CNTR_NORMAL),
5076 [C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT,
5077                         CNTR_NORMAL),
5078 [C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL),
5079 [C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL),
5080 [C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH),
5081 [C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT,
5082                                       CNTR_SYNTH | CNTR_VL),
5083 [C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT,
5084                                      CNTR_SYNTH | CNTR_VL),
5085 [C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT,
5086                                       CNTR_SYNTH | CNTR_VL),
5087 [C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL),
5088 [C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL),
5089 [C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT,
5090                              access_sw_link_dn_cnt),
5091 [C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT,
5092                            access_sw_link_up_cnt),
5093 [C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL,
5094                                  access_sw_unknown_frame_cnt),
5095 [C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT,
5096                              access_sw_xmit_discards),
5097 [C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0,
5098                                 CNTR_SYNTH | CNTR_32BIT | CNTR_VL,
5099                                 access_sw_xmit_discards),
5100 [C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH,
5101                                  access_xmit_constraint_errs),
5102 [C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH,
5103                                 access_rcv_constraint_errs),
5104 [C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts),
5105 [C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends),
5106 [C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks),
5107 [C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks),
5108 [C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts),
5109 [C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops),
5110 [C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait),
5111 [C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak),
5112 [C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq),
5113 [C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq),
5114 [C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned),
5115 [C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks),
5116 [C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL,
5117                                access_sw_cpu_rc_acks),
5118 [C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL,
5119                                 access_sw_cpu_rc_qacks),
5120 [C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL,
5121                                        access_sw_cpu_rc_delayed_comp),
5122 [OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1),
5123 [OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3),
5124 [OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5),
5125 [OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7),
5126 [OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9),
5127 [OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11),
5128 [OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13),
5129 [OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15),
5130 [OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17),
5131 [OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19),
5132 [OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21),
5133 [OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23),
5134 [OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25),
5135 [OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27),
5136 [OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29),
5137 [OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31),
5138 [OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33),
5139 [OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35),
5140 [OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37),
5141 [OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39),
5142 [OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41),
5143 [OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43),
5144 [OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45),
5145 [OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47),
5146 [OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49),
5147 [OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51),
5148 [OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53),
5149 [OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55),
5150 [OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57),
5151 [OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59),
5152 [OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61),
5153 [OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63),
5154 [OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65),
5155 [OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67),
5156 [OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69),
5157 [OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71),
5158 [OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73),
5159 [OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75),
5160 [OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77),
5161 [OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79),
5162 [OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81),
5163 [OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83),
5164 [OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85),
5165 [OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87),
5166 [OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89),
5167 [OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91),
5168 [OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93),
5169 [OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95),
5170 [OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97),
5171 [OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99),
5172 [OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101),
5173 [OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103),
5174 [OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105),
5175 [OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107),
5176 [OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109),
5177 [OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111),
5178 [OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113),
5179 [OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115),
5180 [OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117),
5181 [OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119),
5182 [OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121),
5183 [OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123),
5184 [OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125),
5185 [OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127),
5186 [OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129),
5187 [OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131),
5188 [OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133),
5189 [OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135),
5190 [OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137),
5191 [OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139),
5192 [OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141),
5193 [OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143),
5194 [OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145),
5195 [OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147),
5196 [OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149),
5197 [OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151),
5198 [OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153),
5199 [OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155),
5200 [OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157),
5201 [OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159),
5202 };
5203
5204 /* ======================================================================== */
5205
5206 /* return true if this is chip revision revision a */
5207 int is_ax(struct hfi1_devdata *dd)
5208 {
5209         u8 chip_rev_minor =
5210                 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5211                         & CCE_REVISION_CHIP_REV_MINOR_MASK;
5212         return (chip_rev_minor & 0xf0) == 0;
5213 }
5214
5215 /* return true if this is chip revision revision b */
5216 int is_bx(struct hfi1_devdata *dd)
5217 {
5218         u8 chip_rev_minor =
5219                 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5220                         & CCE_REVISION_CHIP_REV_MINOR_MASK;
5221         return (chip_rev_minor & 0xF0) == 0x10;
5222 }
5223
5224 /*
5225  * Append string s to buffer buf.  Arguments curp and len are the current
5226  * position and remaining length, respectively.
5227  *
5228  * return 0 on success, 1 on out of room
5229  */
5230 static int append_str(char *buf, char **curp, int *lenp, const char *s)
5231 {
5232         char *p = *curp;
5233         int len = *lenp;
5234         int result = 0; /* success */
5235         char c;
5236
5237         /* add a comma, if first in the buffer */
5238         if (p != buf) {
5239                 if (len == 0) {
5240                         result = 1; /* out of room */
5241                         goto done;
5242                 }
5243                 *p++ = ',';
5244                 len--;
5245         }
5246
5247         /* copy the string */
5248         while ((c = *s++) != 0) {
5249                 if (len == 0) {
5250                         result = 1; /* out of room */
5251                         goto done;
5252                 }
5253                 *p++ = c;
5254                 len--;
5255         }
5256
5257 done:
5258         /* write return values */
5259         *curp = p;
5260         *lenp = len;
5261
5262         return result;
5263 }
5264
5265 /*
5266  * Using the given flag table, print a comma separated string into
5267  * the buffer.  End in '*' if the buffer is too short.
5268  */
5269 static char *flag_string(char *buf, int buf_len, u64 flags,
5270                          struct flag_table *table, int table_size)
5271 {
5272         char extra[32];
5273         char *p = buf;
5274         int len = buf_len;
5275         int no_room = 0;
5276         int i;
5277
5278         /* make sure there is at least 2 so we can form "*" */
5279         if (len < 2)
5280                 return "";
5281
5282         len--;  /* leave room for a nul */
5283         for (i = 0; i < table_size; i++) {
5284                 if (flags & table[i].flag) {
5285                         no_room = append_str(buf, &p, &len, table[i].str);
5286                         if (no_room)
5287                                 break;
5288                         flags &= ~table[i].flag;
5289                 }
5290         }
5291
5292         /* any undocumented bits left? */
5293         if (!no_room && flags) {
5294                 snprintf(extra, sizeof(extra), "bits 0x%llx", flags);
5295                 no_room = append_str(buf, &p, &len, extra);
5296         }
5297
5298         /* add * if ran out of room */
5299         if (no_room) {
5300                 /* may need to back up to add space for a '*' */
5301                 if (len == 0)
5302                         --p;
5303                 *p++ = '*';
5304         }
5305
5306         /* add final nul - space already allocated above */
5307         *p = 0;
5308         return buf;
5309 }
5310
5311 /* first 8 CCE error interrupt source names */
5312 static const char * const cce_misc_names[] = {
5313         "CceErrInt",            /* 0 */
5314         "RxeErrInt",            /* 1 */
5315         "MiscErrInt",           /* 2 */
5316         "Reserved3",            /* 3 */
5317         "PioErrInt",            /* 4 */
5318         "SDmaErrInt",           /* 5 */
5319         "EgressErrInt",         /* 6 */
5320         "TxeErrInt"             /* 7 */
5321 };
5322
5323 /*
5324  * Return the miscellaneous error interrupt name.
5325  */
5326 static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source)
5327 {
5328         if (source < ARRAY_SIZE(cce_misc_names))
5329                 strncpy(buf, cce_misc_names[source], bsize);
5330         else
5331                 snprintf(buf, bsize, "Reserved%u",
5332                          source + IS_GENERAL_ERR_START);
5333
5334         return buf;
5335 }
5336
5337 /*
5338  * Return the SDMA engine error interrupt name.
5339  */
5340 static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source)
5341 {
5342         snprintf(buf, bsize, "SDmaEngErrInt%u", source);
5343         return buf;
5344 }
5345
5346 /*
5347  * Return the send context error interrupt name.
5348  */
5349 static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source)
5350 {
5351         snprintf(buf, bsize, "SendCtxtErrInt%u", source);
5352         return buf;
5353 }
5354
5355 static const char * const various_names[] = {
5356         "PbcInt",
5357         "GpioAssertInt",
5358         "Qsfp1Int",
5359         "Qsfp2Int",
5360         "TCritInt"
5361 };
5362
5363 /*
5364  * Return the various interrupt name.
5365  */
5366 static char *is_various_name(char *buf, size_t bsize, unsigned int source)
5367 {
5368         if (source < ARRAY_SIZE(various_names))
5369                 strncpy(buf, various_names[source], bsize);
5370         else
5371                 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START);
5372         return buf;
5373 }
5374
5375 /*
5376  * Return the DC interrupt name.
5377  */
5378 static char *is_dc_name(char *buf, size_t bsize, unsigned int source)
5379 {
5380         static const char * const dc_int_names[] = {
5381                 "common",
5382                 "lcb",
5383                 "8051",
5384                 "lbm"   /* local block merge */
5385         };
5386
5387         if (source < ARRAY_SIZE(dc_int_names))
5388                 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]);
5389         else
5390                 snprintf(buf, bsize, "DCInt%u", source);
5391         return buf;
5392 }
5393
5394 static const char * const sdma_int_names[] = {
5395         "SDmaInt",
5396         "SdmaIdleInt",
5397         "SdmaProgressInt",
5398 };
5399
5400 /*
5401  * Return the SDMA engine interrupt name.
5402  */
5403 static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source)
5404 {
5405         /* what interrupt */
5406         unsigned int what  = source / TXE_NUM_SDMA_ENGINES;
5407         /* which engine */
5408         unsigned int which = source % TXE_NUM_SDMA_ENGINES;
5409
5410         if (likely(what < 3))
5411                 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which);
5412         else
5413                 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source);
5414         return buf;
5415 }
5416
5417 /*
5418  * Return the receive available interrupt name.
5419  */
5420 static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source)
5421 {
5422         snprintf(buf, bsize, "RcvAvailInt%u", source);
5423         return buf;
5424 }
5425
5426 /*
5427  * Return the receive urgent interrupt name.
5428  */
5429 static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source)
5430 {
5431         snprintf(buf, bsize, "RcvUrgentInt%u", source);
5432         return buf;
5433 }
5434
5435 /*
5436  * Return the send credit interrupt name.
5437  */
5438 static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source)
5439 {
5440         snprintf(buf, bsize, "SendCreditInt%u", source);
5441         return buf;
5442 }
5443
5444 /*
5445  * Return the reserved interrupt name.
5446  */
5447 static char *is_reserved_name(char *buf, size_t bsize, unsigned int source)
5448 {
5449         snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START);
5450         return buf;
5451 }
5452
5453 static char *cce_err_status_string(char *buf, int buf_len, u64 flags)
5454 {
5455         return flag_string(buf, buf_len, flags,
5456                            cce_err_status_flags,
5457                            ARRAY_SIZE(cce_err_status_flags));
5458 }
5459
5460 static char *rxe_err_status_string(char *buf, int buf_len, u64 flags)
5461 {
5462         return flag_string(buf, buf_len, flags,
5463                            rxe_err_status_flags,
5464                            ARRAY_SIZE(rxe_err_status_flags));
5465 }
5466
5467 static char *misc_err_status_string(char *buf, int buf_len, u64 flags)
5468 {
5469         return flag_string(buf, buf_len, flags, misc_err_status_flags,
5470                            ARRAY_SIZE(misc_err_status_flags));
5471 }
5472
5473 static char *pio_err_status_string(char *buf, int buf_len, u64 flags)
5474 {
5475         return flag_string(buf, buf_len, flags,
5476                            pio_err_status_flags,
5477                            ARRAY_SIZE(pio_err_status_flags));
5478 }
5479
5480 static char *sdma_err_status_string(char *buf, int buf_len, u64 flags)
5481 {
5482         return flag_string(buf, buf_len, flags,
5483                            sdma_err_status_flags,
5484                            ARRAY_SIZE(sdma_err_status_flags));
5485 }
5486
5487 static char *egress_err_status_string(char *buf, int buf_len, u64 flags)
5488 {
5489         return flag_string(buf, buf_len, flags,
5490                            egress_err_status_flags,
5491                            ARRAY_SIZE(egress_err_status_flags));
5492 }
5493
5494 static char *egress_err_info_string(char *buf, int buf_len, u64 flags)
5495 {
5496         return flag_string(buf, buf_len, flags,
5497                            egress_err_info_flags,
5498                            ARRAY_SIZE(egress_err_info_flags));
5499 }
5500
5501 static char *send_err_status_string(char *buf, int buf_len, u64 flags)
5502 {
5503         return flag_string(buf, buf_len, flags,
5504                            send_err_status_flags,
5505                            ARRAY_SIZE(send_err_status_flags));
5506 }
5507
5508 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5509 {
5510         char buf[96];
5511         int i = 0;
5512
5513         /*
5514          * For most these errors, there is nothing that can be done except
5515          * report or record it.
5516          */
5517         dd_dev_info(dd, "CCE Error: %s\n",
5518                     cce_err_status_string(buf, sizeof(buf), reg));
5519
5520         if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) &&
5521             is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) {
5522                 /* this error requires a manual drop into SPC freeze mode */
5523                 /* then a fix up */
5524                 start_freeze_handling(dd->pport, FREEZE_SELF);
5525         }
5526
5527         for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) {
5528                 if (reg & (1ull << i)) {
5529                         incr_cntr64(&dd->cce_err_status_cnt[i]);
5530                         /* maintain a counter over all cce_err_status errors */
5531                         incr_cntr64(&dd->sw_cce_err_status_aggregate);
5532                 }
5533         }
5534 }
5535
5536 /*
5537  * Check counters for receive errors that do not have an interrupt
5538  * associated with them.
5539  */
5540 #define RCVERR_CHECK_TIME 10
5541 static void update_rcverr_timer(struct timer_list *t)
5542 {
5543         struct hfi1_devdata *dd = from_timer(dd, t, rcverr_timer);
5544         struct hfi1_pportdata *ppd = dd->pport;
5545         u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);
5546
5547         if (dd->rcv_ovfl_cnt < cur_ovfl_cnt &&
5548             ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) {
5549                 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
5550                 set_link_down_reason(
5551                 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0,
5552                 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
5553                 queue_work(ppd->link_wq, &ppd->link_bounce_work);
5554         }
5555         dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt;
5556
5557         mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5558 }
5559
5560 static int init_rcverr(struct hfi1_devdata *dd)
5561 {
5562         timer_setup(&dd->rcverr_timer, update_rcverr_timer, 0);
5563         /* Assume the hardware counter has been reset */
5564         dd->rcv_ovfl_cnt = 0;
5565         return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5566 }
5567
5568 static void free_rcverr(struct hfi1_devdata *dd)
5569 {
5570         if (dd->rcverr_timer.function)
5571                 del_timer_sync(&dd->rcverr_timer);
5572 }
5573
5574 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5575 {
5576         char buf[96];
5577         int i = 0;
5578
5579         dd_dev_info(dd, "Receive Error: %s\n",
5580                     rxe_err_status_string(buf, sizeof(buf), reg));
5581
5582         if (reg & ALL_RXE_FREEZE_ERR) {
5583                 int flags = 0;
5584
5585                 /*
5586                  * Freeze mode recovery is disabled for the errors
5587                  * in RXE_FREEZE_ABORT_MASK
5588                  */
5589                 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK))
5590                         flags = FREEZE_ABORT;
5591
5592                 start_freeze_handling(dd->pport, flags);
5593         }
5594
5595         for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) {
5596                 if (reg & (1ull << i))
5597                         incr_cntr64(&dd->rcv_err_status_cnt[i]);
5598         }
5599 }
5600
5601 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5602 {
5603         char buf[96];
5604         int i = 0;
5605
5606         dd_dev_info(dd, "Misc Error: %s",
5607                     misc_err_status_string(buf, sizeof(buf), reg));
5608         for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) {
5609                 if (reg & (1ull << i))
5610                         incr_cntr64(&dd->misc_err_status_cnt[i]);
5611         }
5612 }
5613
5614 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5615 {
5616         char buf[96];
5617         int i = 0;
5618
5619         dd_dev_info(dd, "PIO Error: %s\n",
5620                     pio_err_status_string(buf, sizeof(buf), reg));
5621
5622         if (reg & ALL_PIO_FREEZE_ERR)
5623                 start_freeze_handling(dd->pport, 0);
5624
5625         for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) {
5626                 if (reg & (1ull << i))
5627                         incr_cntr64(&dd->send_pio_err_status_cnt[i]);
5628         }
5629 }
5630
5631 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5632 {
5633         char buf[96];
5634         int i = 0;
5635
5636         dd_dev_info(dd, "SDMA Error: %s\n",
5637                     sdma_err_status_string(buf, sizeof(buf), reg));
5638
5639         if (reg & ALL_SDMA_FREEZE_ERR)
5640                 start_freeze_handling(dd->pport, 0);
5641
5642         for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) {
5643                 if (reg & (1ull << i))
5644                         incr_cntr64(&dd->send_dma_err_status_cnt[i]);
5645         }
5646 }
5647
5648 static inline void __count_port_discards(struct hfi1_pportdata *ppd)
5649 {
5650         incr_cntr64(&ppd->port_xmit_discards);
5651 }
5652
5653 static void count_port_inactive(struct hfi1_devdata *dd)
5654 {
5655         __count_port_discards(dd->pport);
5656 }
5657
5658 /*
5659  * We have had a "disallowed packet" error during egress. Determine the
5660  * integrity check which failed, and update relevant error counter, etc.
5661  *
5662  * Note that the SEND_EGRESS_ERR_INFO register has only a single
5663  * bit of state per integrity check, and so we can miss the reason for an
5664  * egress error if more than one packet fails the same integrity check
5665  * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5666  */
5667 static void handle_send_egress_err_info(struct hfi1_devdata *dd,
5668                                         int vl)
5669 {
5670         struct hfi1_pportdata *ppd = dd->pport;
5671         u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */
5672         u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);
5673         char buf[96];
5674
5675         /* clear down all observed info as quickly as possible after read */
5676         write_csr(dd, SEND_EGRESS_ERR_INFO, info);
5677
5678         dd_dev_info(dd,
5679                     "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n",
5680                     info, egress_err_info_string(buf, sizeof(buf), info), src);
5681
5682         /* Eventually add other counters for each bit */
5683         if (info & PORT_DISCARD_EGRESS_ERRS) {
5684                 int weight, i;
5685
5686                 /*
5687                  * Count all applicable bits as individual errors and
5688                  * attribute them to the packet that triggered this handler.
5689                  * This may not be completely accurate due to limitations
5690                  * on the available hardware error information.  There is
5691                  * a single information register and any number of error
5692                  * packets may have occurred and contributed to it before
5693                  * this routine is called.  This means that:
5694                  * a) If multiple packets with the same error occur before
5695                  *    this routine is called, earlier packets are missed.
5696                  *    There is only a single bit for each error type.
5697                  * b) Errors may not be attributed to the correct VL.
5698                  *    The driver is attributing all bits in the info register
5699                  *    to the packet that triggered this call, but bits
5700                  *    could be an accumulation of different packets with
5701                  *    different VLs.
5702                  * c) A single error packet may have multiple counts attached
5703                  *    to it.  There is no way for the driver to know if
5704                  *    multiple bits set in the info register are due to a
5705                  *    single packet or multiple packets.  The driver assumes
5706                  *    multiple packets.
5707                  */
5708                 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS);
5709                 for (i = 0; i < weight; i++) {
5710                         __count_port_discards(ppd);
5711                         if (vl >= 0 && vl < TXE_NUM_DATA_VL)
5712                                 incr_cntr64(&ppd->port_xmit_discards_vl[vl]);
5713                         else if (vl == 15)
5714                                 incr_cntr64(&ppd->port_xmit_discards_vl
5715                                             [C_VL_15]);
5716                 }
5717         }
5718 }
5719
5720 /*
5721  * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5722  * register. Does it represent a 'port inactive' error?
5723  */
5724 static inline int port_inactive_err(u64 posn)
5725 {
5726         return (posn >= SEES(TX_LINKDOWN) &&
5727                 posn <= SEES(TX_INCORRECT_LINK_STATE));
5728 }
5729
5730 /*
5731  * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5732  * register. Does it represent a 'disallowed packet' error?
5733  */
5734 static inline int disallowed_pkt_err(int posn)
5735 {
5736         return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) &&
5737                 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET));
5738 }
5739
5740 /*
5741  * Input value is a bit position of one of the SDMA engine disallowed
5742  * packet errors.  Return which engine.  Use of this must be guarded by
5743  * disallowed_pkt_err().
5744  */
5745 static inline int disallowed_pkt_engine(int posn)
5746 {
5747         return posn - SEES(TX_SDMA0_DISALLOWED_PACKET);
5748 }
5749
5750 /*
5751  * Translate an SDMA engine to a VL.  Return -1 if the tranlation cannot
5752  * be done.
5753  */
5754 static int engine_to_vl(struct hfi1_devdata *dd, int engine)
5755 {
5756         struct sdma_vl_map *m;
5757         int vl;
5758
5759         /* range check */
5760         if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES)
5761                 return -1;
5762
5763         rcu_read_lock();
5764         m = rcu_dereference(dd->sdma_map);
5765         vl = m->engine_to_vl[engine];
5766         rcu_read_unlock();
5767
5768         return vl;
5769 }
5770
5771 /*
5772  * Translate the send context (sofware index) into a VL.  Return -1 if the
5773  * translation cannot be done.
5774  */
5775 static int sc_to_vl(struct hfi1_devdata *dd, int sw_index)
5776 {
5777         struct send_context_info *sci;
5778         struct send_context *sc;
5779         int i;
5780
5781         sci = &dd->send_contexts[sw_index];
5782
5783         /* there is no information for user (PSM) and ack contexts */
5784         if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15))
5785                 return -1;
5786
5787         sc = sci->sc;
5788         if (!sc)
5789                 return -1;
5790         if (dd->vld[15].sc == sc)
5791                 return 15;
5792         for (i = 0; i < num_vls; i++)
5793                 if (dd->vld[i].sc == sc)
5794                         return i;
5795
5796         return -1;
5797 }
5798
5799 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5800 {
5801         u64 reg_copy = reg, handled = 0;
5802         char buf[96];
5803         int i = 0;
5804
5805         if (reg & ALL_TXE_EGRESS_FREEZE_ERR)
5806                 start_freeze_handling(dd->pport, 0);
5807         else if (is_ax(dd) &&
5808                  (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) &&
5809                  (dd->icode != ICODE_FUNCTIONAL_SIMULATOR))
5810                 start_freeze_handling(dd->pport, 0);
5811
5812         while (reg_copy) {
5813                 int posn = fls64(reg_copy);
5814                 /* fls64() returns a 1-based offset, we want it zero based */
5815                 int shift = posn - 1;
5816                 u64 mask = 1ULL << shift;
5817
5818                 if (port_inactive_err(shift)) {
5819                         count_port_inactive(dd);
5820                         handled |= mask;
5821                 } else if (disallowed_pkt_err(shift)) {
5822                         int vl = engine_to_vl(dd, disallowed_pkt_engine(shift));
5823
5824                         handle_send_egress_err_info(dd, vl);
5825                         handled |= mask;
5826                 }
5827                 reg_copy &= ~mask;
5828         }
5829
5830         reg &= ~handled;
5831
5832         if (reg)
5833                 dd_dev_info(dd, "Egress Error: %s\n",
5834                             egress_err_status_string(buf, sizeof(buf), reg));
5835
5836         for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) {
5837                 if (reg & (1ull << i))
5838                         incr_cntr64(&dd->send_egress_err_status_cnt[i]);
5839         }
5840 }
5841
5842 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5843 {
5844         char buf[96];
5845         int i = 0;
5846
5847         dd_dev_info(dd, "Send Error: %s\n",
5848                     send_err_status_string(buf, sizeof(buf), reg));
5849
5850         for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) {
5851                 if (reg & (1ull << i))
5852                         incr_cntr64(&dd->send_err_status_cnt[i]);
5853         }
5854 }
5855
5856 /*
5857  * The maximum number of times the error clear down will loop before
5858  * blocking a repeating error.  This value is arbitrary.
5859  */
5860 #define MAX_CLEAR_COUNT 20
5861
5862 /*
5863  * Clear and handle an error register.  All error interrupts are funneled
5864  * through here to have a central location to correctly handle single-
5865  * or multi-shot errors.
5866  *
5867  * For non per-context registers, call this routine with a context value
5868  * of 0 so the per-context offset is zero.
5869  *
5870  * If the handler loops too many times, assume that something is wrong
5871  * and can't be fixed, so mask the error bits.
5872  */
5873 static void interrupt_clear_down(struct hfi1_devdata *dd,
5874                                  u32 context,
5875                                  const struct err_reg_info *eri)
5876 {
5877         u64 reg;
5878         u32 count;
5879
5880         /* read in a loop until no more errors are seen */
5881         count = 0;
5882         while (1) {
5883                 reg = read_kctxt_csr(dd, context, eri->status);
5884                 if (reg == 0)
5885                         break;
5886                 write_kctxt_csr(dd, context, eri->clear, reg);
5887                 if (likely(eri->handler))
5888                         eri->handler(dd, context, reg);
5889                 count++;
5890                 if (count > MAX_CLEAR_COUNT) {
5891                         u64 mask;
5892
5893                         dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n",
5894                                    eri->desc, reg);
5895                         /*
5896                          * Read-modify-write so any other masked bits
5897                          * remain masked.
5898                          */
5899                         mask = read_kctxt_csr(dd, context, eri->mask);
5900                         mask &= ~reg;
5901                         write_kctxt_csr(dd, context, eri->mask, mask);
5902                         break;
5903                 }
5904         }
5905 }
5906
5907 /*
5908  * CCE block "misc" interrupt.  Source is < 16.
5909  */
5910 static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source)
5911 {
5912         const struct err_reg_info *eri = &misc_errs[source];
5913
5914         if (eri->handler) {
5915                 interrupt_clear_down(dd, 0, eri);
5916         } else {
5917                 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n",
5918                            source);
5919         }
5920 }
5921
5922 static char *send_context_err_status_string(char *buf, int buf_len, u64 flags)
5923 {
5924         return flag_string(buf, buf_len, flags,
5925                            sc_err_status_flags,
5926                            ARRAY_SIZE(sc_err_status_flags));
5927 }
5928
5929 /*
5930  * Send context error interrupt.  Source (hw_context) is < 160.
5931  *
5932  * All send context errors cause the send context to halt.  The normal
5933  * clear-down mechanism cannot be used because we cannot clear the
5934  * error bits until several other long-running items are done first.
5935  * This is OK because with the context halted, nothing else is going
5936  * to happen on it anyway.
5937  */
5938 static void is_sendctxt_err_int(struct hfi1_devdata *dd,
5939                                 unsigned int hw_context)
5940 {
5941         struct send_context_info *sci;
5942         struct send_context *sc;
5943         char flags[96];
5944         u64 status;
5945         u32 sw_index;
5946         int i = 0;
5947
5948         sw_index = dd->hw_to_sw[hw_context];
5949         if (sw_index >= dd->num_send_contexts) {
5950                 dd_dev_err(dd,
5951                            "out of range sw index %u for send context %u\n",
5952                            sw_index, hw_context);
5953                 return;
5954         }
5955         sci = &dd->send_contexts[sw_index];
5956         sc = sci->sc;
5957         if (!sc) {
5958                 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__,
5959                            sw_index, hw_context);
5960                 return;
5961         }
5962
5963         /* tell the software that a halt has begun */
5964         sc_stop(sc, SCF_HALTED);
5965
5966         status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS);
5967
5968         dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context,
5969                     send_context_err_status_string(flags, sizeof(flags),
5970                                                    status));
5971
5972         if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK)
5973                 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index));
5974
5975         /*
5976          * Automatically restart halted kernel contexts out of interrupt
5977          * context.  User contexts must ask the driver to restart the context.
5978          */
5979         if (sc->type != SC_USER)
5980                 queue_work(dd->pport->hfi1_wq, &sc->halt_work);
5981
5982         /*
5983          * Update the counters for the corresponding status bits.
5984          * Note that these particular counters are aggregated over all
5985          * 160 contexts.
5986          */
5987         for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) {
5988                 if (status & (1ull << i))
5989                         incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]);
5990         }
5991 }
5992
5993 static void handle_sdma_eng_err(struct hfi1_devdata *dd,
5994                                 unsigned int source, u64 status)
5995 {
5996         struct sdma_engine *sde;
5997         int i = 0;
5998
5999         sde = &dd->per_sdma[source];
6000 #ifdef CONFIG_SDMA_VERBOSITY
6001         dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
6002                    slashstrip(__FILE__), __LINE__, __func__);
6003         dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n",
6004                    sde->this_idx, source, (unsigned long long)status);
6005 #endif
6006         sde->err_cnt++;
6007         sdma_engine_error(sde, status);
6008
6009         /*
6010         * Update the counters for the corresponding status bits.
6011         * Note that these particular counters are aggregated over
6012         * all 16 DMA engines.
6013         */
6014         for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) {
6015                 if (status & (1ull << i))
6016                         incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]);
6017         }
6018 }
6019
6020 /*
6021  * CCE block SDMA error interrupt.  Source is < 16.
6022  */
6023 static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source)
6024 {
6025 #ifdef CONFIG_SDMA_VERBOSITY
6026         struct sdma_engine *sde = &dd->per_sdma[source];
6027
6028         dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
6029                    slashstrip(__FILE__), __LINE__, __func__);
6030         dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx,
6031                    source);
6032         sdma_dumpstate(sde);
6033 #endif
6034         interrupt_clear_down(dd, source, &sdma_eng_err);
6035 }
6036
6037 /*
6038  * CCE block "various" interrupt.  Source is < 8.
6039  */
6040 static void is_various_int(struct hfi1_devdata *dd, unsigned int source)
6041 {
6042         const struct err_reg_info *eri = &various_err[source];
6043
6044         /*
6045          * TCritInt cannot go through interrupt_clear_down()
6046          * because it is not a second tier interrupt. The handler
6047          * should be called directly.
6048          */
6049         if (source == TCRIT_INT_SOURCE)
6050                 handle_temp_err(dd);
6051         else if (eri->handler)
6052                 interrupt_clear_down(dd, 0, eri);
6053         else
6054                 dd_dev_info(dd,
6055                             "%s: Unimplemented/reserved interrupt %d\n",
6056                             __func__, source);
6057 }
6058
6059 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg)
6060 {
6061         /* src_ctx is always zero */
6062         struct hfi1_pportdata *ppd = dd->pport;
6063         unsigned long flags;
6064         u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
6065
6066         if (reg & QSFP_HFI0_MODPRST_N) {
6067                 if (!qsfp_mod_present(ppd)) {
6068                         dd_dev_info(dd, "%s: QSFP module removed\n",
6069                                     __func__);
6070
6071                         ppd->driver_link_ready = 0;
6072                         /*
6073                          * Cable removed, reset all our information about the
6074                          * cache and cable capabilities
6075                          */
6076
6077                         spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6078                         /*
6079                          * We don't set cache_refresh_required here as we expect
6080                          * an interrupt when a cable is inserted
6081                          */
6082                         ppd->qsfp_info.cache_valid = 0;
6083                         ppd->qsfp_info.reset_needed = 0;
6084                         ppd->qsfp_info.limiting_active = 0;
6085                         spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
6086                                                flags);
6087                         /* Invert the ModPresent pin now to detect plug-in */
6088                         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6089                                   ASIC_QSFP1_INVERT, qsfp_int_mgmt);
6090
6091                         if ((ppd->offline_disabled_reason >
6092                           HFI1_ODR_MASK(
6093                           OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
6094                           (ppd->offline_disabled_reason ==
6095                           HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)))
6096                                 ppd->offline_disabled_reason =
6097                                 HFI1_ODR_MASK(
6098                                 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
6099
6100                         if (ppd->host_link_state == HLS_DN_POLL) {
6101                                 /*
6102                                  * The link is still in POLL. This means
6103                                  * that the normal link down processing
6104                                  * will not happen. We have to do it here
6105                                  * before turning the DC off.
6106                                  */
6107                                 queue_work(ppd->link_wq, &ppd->link_down_work);
6108                         }
6109                 } else {
6110                         dd_dev_info(dd, "%s: QSFP module inserted\n",
6111                                     __func__);
6112
6113                         spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6114                         ppd->qsfp_info.cache_valid = 0;
6115                         ppd->qsfp_info.cache_refresh_required = 1;
6116                         spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
6117                                                flags);
6118
6119                         /*
6120                          * Stop inversion of ModPresent pin to detect
6121                          * removal of the cable
6122                          */
6123                         qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N;
6124                         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6125                                   ASIC_QSFP1_INVERT, qsfp_int_mgmt);
6126
6127                         ppd->offline_disabled_reason =
6128                                 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
6129                 }
6130         }
6131
6132         if (reg & QSFP_HFI0_INT_N) {
6133                 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n",
6134                             __func__);
6135                 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6136                 ppd->qsfp_info.check_interrupt_flags = 1;
6137                 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags);
6138         }
6139
6140         /* Schedule the QSFP work only if there is a cable attached. */
6141         if (qsfp_mod_present(ppd))
6142                 queue_work(ppd->link_wq, &ppd->qsfp_info.qsfp_work);
6143 }
6144
6145 static int request_host_lcb_access(struct hfi1_devdata *dd)
6146 {
6147         int ret;
6148
6149         ret = do_8051_command(dd, HCMD_MISC,
6150                               (u64)HCMD_MISC_REQUEST_LCB_ACCESS <<
6151                               LOAD_DATA_FIELD_ID_SHIFT, NULL);
6152         if (ret != HCMD_SUCCESS) {
6153                 dd_dev_err(dd, "%s: command failed with error %d\n",
6154                            __func__, ret);
6155         }
6156         return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6157 }
6158
6159 static int request_8051_lcb_access(struct hfi1_devdata *dd)
6160 {
6161         int ret;
6162
6163         ret = do_8051_command(dd, HCMD_MISC,
6164                               (u64)HCMD_MISC_GRANT_LCB_ACCESS <<
6165                               LOAD_DATA_FIELD_ID_SHIFT, NULL);
6166         if (ret != HCMD_SUCCESS) {
6167                 dd_dev_err(dd, "%s: command failed with error %d\n",
6168                            __func__, ret);
6169         }
6170         return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6171 }
6172
6173 /*
6174  * Set the LCB selector - allow host access.  The DCC selector always
6175  * points to the host.
6176  */
6177 static inline void set_host_lcb_access(struct hfi1_devdata *dd)
6178 {
6179         write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6180                   DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK |
6181                   DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
6182 }
6183
6184 /*
6185  * Clear the LCB selector - allow 8051 access.  The DCC selector always
6186  * points to the host.
6187  */
6188 static inline void set_8051_lcb_access(struct hfi1_devdata *dd)
6189 {
6190         write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6191                   DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
6192 }
6193
6194 /*
6195  * Acquire LCB access from the 8051.  If the host already has access,
6196  * just increment a counter.  Otherwise, inform the 8051 that the
6197  * host is taking access.
6198  *
6199  * Returns:
6200  *      0 on success
6201  *      -EBUSY if the 8051 has control and cannot be disturbed
6202  *      -errno if unable to acquire access from the 8051
6203  */
6204 int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6205 {
6206         struct hfi1_pportdata *ppd = dd->pport;
6207         int ret = 0;
6208
6209         /*
6210          * Use the host link state lock so the operation of this routine
6211          * { link state check, selector change, count increment } can occur
6212          * as a unit against a link state change.  Otherwise there is a
6213          * race between the state change and the count increment.
6214          */
6215         if (sleep_ok) {
6216                 mutex_lock(&ppd->hls_lock);
6217         } else {
6218                 while (!mutex_trylock(&ppd->hls_lock))
6219                         udelay(1);
6220         }
6221
6222         /* this access is valid only when the link is up */
6223         if (ppd->host_link_state & HLS_DOWN) {
6224                 dd_dev_info(dd, "%s: link state %s not up\n",
6225                             __func__, link_state_name(ppd->host_link_state));
6226                 ret = -EBUSY;
6227                 goto done;
6228         }
6229
6230         if (dd->lcb_access_count == 0) {
6231                 ret = request_host_lcb_access(dd);
6232                 if (ret) {
6233                         dd_dev_err(dd,
6234                                    "%s: unable to acquire LCB access, err %d\n",
6235                                    __func__, ret);
6236                         goto done;
6237                 }
6238                 set_host_lcb_access(dd);
6239         }
6240         dd->lcb_access_count++;
6241 done:
6242         mutex_unlock(&ppd->hls_lock);
6243         return ret;
6244 }
6245
6246 /*
6247  * Release LCB access by decrementing the use count.  If the count is moving
6248  * from 1 to 0, inform 8051 that it has control back.
6249  *
6250  * Returns:
6251  *      0 on success
6252  *      -errno if unable to release access to the 8051
6253  */
6254 int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6255 {
6256         int ret = 0;
6257
6258         /*
6259          * Use the host link state lock because the acquire needed it.
6260          * Here, we only need to keep { selector change, count decrement }
6261          * as a unit.
6262          */
6263         if (sleep_ok) {
6264                 mutex_lock(&dd->pport->hls_lock);
6265         } else {
6266                 while (!mutex_trylock(&dd->pport->hls_lock))
6267                         udelay(1);
6268         }
6269
6270         if (dd->lcb_access_count == 0) {
6271                 dd_dev_err(dd, "%s: LCB access count is zero.  Skipping.\n",
6272                            __func__);
6273                 goto done;
6274         }
6275
6276         if (dd->lcb_access_count == 1) {
6277                 set_8051_lcb_access(dd);
6278                 ret = request_8051_lcb_access(dd);
6279                 if (ret) {
6280                         dd_dev_err(dd,
6281                                    "%s: unable to release LCB access, err %d\n",
6282                                    __func__, ret);
6283                         /* restore host access if the grant didn't work */
6284                         set_host_lcb_access(dd);
6285                         goto done;
6286                 }
6287         }
6288         dd->lcb_access_count--;
6289 done:
6290         mutex_unlock(&dd->pport->hls_lock);
6291         return ret;
6292 }
6293
6294 /*
6295  * Initialize LCB access variables and state.  Called during driver load,
6296  * after most of the initialization is finished.
6297  *
6298  * The DC default is LCB access on for the host.  The driver defaults to
6299  * leaving access to the 8051.  Assign access now - this constrains the call
6300  * to this routine to be after all LCB set-up is done.  In particular, after
6301  * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6302  */
6303 static void init_lcb_access(struct hfi1_devdata *dd)
6304 {
6305         dd->lcb_access_count = 0;
6306 }
6307
6308 /*
6309  * Write a response back to a 8051 request.
6310  */
6311 static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data)
6312 {
6313         write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
6314                   DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK |
6315                   (u64)return_code <<
6316                   DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT |
6317                   (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
6318 }
6319
6320 /*
6321  * Handle host requests from the 8051.
6322  */
6323 static void handle_8051_request(struct hfi1_pportdata *ppd)
6324 {
6325         struct hfi1_devdata *dd = ppd->dd;
6326         u64 reg;
6327         u16 data = 0;
6328         u8 type;
6329
6330         reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);
6331         if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0)
6332                 return; /* no request */
6333
6334         /* zero out COMPLETED so the response is seen */
6335         write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
6336
6337         /* extract request details */
6338         type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT)
6339                         & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK;
6340         data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT)
6341                         & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK;
6342
6343         switch (type) {
6344         case HREQ_LOAD_CONFIG:
6345         case HREQ_SAVE_CONFIG:
6346         case HREQ_READ_CONFIG:
6347         case HREQ_SET_TX_EQ_ABS:
6348         case HREQ_SET_TX_EQ_REL:
6349         case HREQ_ENABLE:
6350                 dd_dev_info(dd, "8051 request: request 0x%x not supported\n",
6351                             type);
6352                 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6353                 break;
6354         case HREQ_CONFIG_DONE:
6355                 hreq_response(dd, HREQ_SUCCESS, 0);
6356                 break;
6357
6358         case HREQ_INTERFACE_TEST:
6359                 hreq_response(dd, HREQ_SUCCESS, data);
6360                 break;
6361         default:
6362                 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type);
6363                 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6364                 break;
6365         }
6366 }
6367
6368 /*
6369  * Set up allocation unit vaulue.
6370  */
6371 void set_up_vau(struct hfi1_devdata *dd, u8 vau)
6372 {
6373         u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
6374
6375         /* do not modify other values in the register */
6376         reg &= ~SEND_CM_GLOBAL_CREDIT_AU_SMASK;
6377         reg |= (u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT;
6378         write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
6379 }
6380
6381 /*
6382  * Set up initial VL15 credits of the remote.  Assumes the rest of
6383  * the CM credit registers are zero from a previous global or credit reset.
6384  * Shared limit for VL15 will always be 0.
6385  */
6386 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf)
6387 {
6388         u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
6389
6390         /* set initial values for total and shared credit limit */
6391         reg &= ~(SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK |
6392                  SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK);
6393
6394         /*
6395          * Set total limit to be equal to VL15 credits.
6396          * Leave shared limit at 0.
6397          */
6398         reg |= (u64)vl15buf << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
6399         write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
6400
6401         write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
6402                   << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
6403 }
6404
6405 /*
6406  * Zero all credit details from the previous connection and
6407  * reset the CM manager's internal counters.
6408  */
6409 void reset_link_credits(struct hfi1_devdata *dd)
6410 {
6411         int i;
6412
6413         /* remove all previous VL credit limits */
6414         for (i = 0; i < TXE_NUM_DATA_VL; i++)
6415                 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
6416         write_csr(dd, SEND_CM_CREDIT_VL15, 0);
6417         write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0);
6418         /* reset the CM block */
6419         pio_send_control(dd, PSC_CM_RESET);
6420         /* reset cached value */
6421         dd->vl15buf_cached = 0;
6422 }
6423
6424 /* convert a vCU to a CU */
6425 static u32 vcu_to_cu(u8 vcu)
6426 {
6427         return 1 << vcu;
6428 }
6429
6430 /* convert a CU to a vCU */
6431 static u8 cu_to_vcu(u32 cu)
6432 {
6433         return ilog2(cu);
6434 }
6435
6436 /* convert a vAU to an AU */
6437 static u32 vau_to_au(u8 vau)
6438 {
6439         return 8 * (1 << vau);
6440 }
6441
6442 static void set_linkup_defaults(struct hfi1_pportdata *ppd)
6443 {
6444         ppd->sm_trap_qp = 0x0;
6445         ppd->sa_qp = 0x1;
6446 }
6447
6448 /*
6449  * Graceful LCB shutdown.  This leaves the LCB FIFOs in reset.
6450  */
6451 static void lcb_shutdown(struct hfi1_devdata *dd, int abort)
6452 {
6453         u64 reg;
6454
6455         /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6456         write_csr(dd, DC_LCB_CFG_RUN, 0);
6457         /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6458         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
6459                   1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT);
6460         /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6461         dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);
6462         reg = read_csr(dd, DCC_CFG_RESET);
6463         write_csr(dd, DCC_CFG_RESET, reg |
6464                   (1ull << DCC_CFG_RESET_RESET_LCB_SHIFT) |
6465                   (1ull << DCC_CFG_RESET_RESET_RX_FPE_SHIFT));
6466         (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */
6467         if (!abort) {
6468                 udelay(1);    /* must hold for the longer of 16cclks or 20ns */
6469                 write_csr(dd, DCC_CFG_RESET, reg);
6470                 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6471         }
6472 }
6473
6474 /*
6475  * This routine should be called after the link has been transitioned to
6476  * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6477  * reset).
6478  *
6479  * The expectation is that the caller of this routine would have taken
6480  * care of properly transitioning the link into the correct state.
6481  * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6482  *       before calling this function.
6483  */
6484 static void _dc_shutdown(struct hfi1_devdata *dd)
6485 {
6486         lockdep_assert_held(&dd->dc8051_lock);
6487
6488         if (dd->dc_shutdown)
6489                 return;
6490
6491         dd->dc_shutdown = 1;
6492         /* Shutdown the LCB */
6493         lcb_shutdown(dd, 1);
6494         /*
6495          * Going to OFFLINE would have causes the 8051 to put the
6496          * SerDes into reset already. Just need to shut down the 8051,
6497          * itself.
6498          */
6499         write_csr(dd, DC_DC8051_CFG_RST, 0x1);
6500 }
6501
6502 static void dc_shutdown(struct hfi1_devdata *dd)
6503 {
6504         mutex_lock(&dd->dc8051_lock);
6505         _dc_shutdown(dd);
6506         mutex_unlock(&dd->dc8051_lock);
6507 }
6508
6509 /*
6510  * Calling this after the DC has been brought out of reset should not
6511  * do any damage.
6512  * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6513  *       before calling this function.
6514  */
6515 static void _dc_start(struct hfi1_devdata *dd)
6516 {
6517         lockdep_assert_held(&dd->dc8051_lock);
6518
6519         if (!dd->dc_shutdown)
6520                 return;
6521
6522         /* Take the 8051 out of reset */
6523         write_csr(dd, DC_DC8051_CFG_RST, 0ull);
6524         /* Wait until 8051 is ready */
6525         if (wait_fm_ready(dd, TIMEOUT_8051_START))
6526                 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n",
6527                            __func__);
6528
6529         /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6530         write_csr(dd, DCC_CFG_RESET, 0x10);
6531         /* lcb_shutdown() with abort=1 does not restore these */
6532         write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6533         dd->dc_shutdown = 0;
6534 }
6535
6536 static void dc_start(struct hfi1_devdata *dd)
6537 {
6538         mutex_lock(&dd->dc8051_lock);
6539         _dc_start(dd);
6540         mutex_unlock(&dd->dc8051_lock);
6541 }
6542
6543 /*
6544  * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6545  */
6546 static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd)
6547 {
6548         u64 rx_radr, tx_radr;
6549         u32 version;
6550
6551         if (dd->icode != ICODE_FPGA_EMULATION)
6552                 return;
6553
6554         /*
6555          * These LCB defaults on emulator _s are good, nothing to do here:
6556          *      LCB_CFG_TX_FIFOS_RADR
6557          *      LCB_CFG_RX_FIFOS_RADR
6558          *      LCB_CFG_LN_DCLK
6559          *      LCB_CFG_IGNORE_LOST_RCLK
6560          */
6561         if (is_emulator_s(dd))
6562                 return;
6563         /* else this is _p */
6564
6565         version = emulator_rev(dd);
6566         if (!is_ax(dd))
6567                 version = 0x2d; /* all B0 use 0x2d or higher settings */
6568
6569         if (version <= 0x12) {
6570                 /* release 0x12 and below */
6571
6572                 /*
6573                  * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6574                  * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6575                  * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6576                  */
6577                 rx_radr =
6578                       0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6579                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6580                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6581                 /*
6582                  * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6583                  * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6584                  */
6585                 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6586         } else if (version <= 0x18) {
6587                 /* release 0x13 up to 0x18 */
6588                 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6589                 rx_radr =
6590                       0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6591                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6592                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6593                 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6594         } else if (version == 0x19) {
6595                 /* release 0x19 */
6596                 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6597                 rx_radr =
6598                       0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6599                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6600                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6601                 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6602         } else if (version == 0x1a) {
6603                 /* release 0x1a */
6604                 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6605                 rx_radr =
6606                       0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6607                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6608                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6609                 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6610                 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
6611         } else {
6612                 /* release 0x1b and higher */
6613                 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6614                 rx_radr =
6615                       0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6616                     | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6617                     | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6618                 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6619         }
6620
6621         write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
6622         /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6623         write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
6624                   DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
6625         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
6626 }
6627
6628 /*
6629  * Handle a SMA idle message
6630  *
6631  * This is a work-queue function outside of the interrupt.
6632  */
6633 void handle_sma_message(struct work_struct *work)
6634 {
6635         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6636                                                         sma_message_work);
6637         struct hfi1_devdata *dd = ppd->dd;
6638         u64 msg;
6639         int ret;
6640
6641         /*
6642          * msg is bytes 1-4 of the 40-bit idle message - the command code
6643          * is stripped off
6644          */
6645         ret = read_idle_sma(dd, &msg);
6646         if (ret)
6647                 return;
6648         dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg);
6649         /*
6650          * React to the SMA message.  Byte[1] (0 for us) is the command.
6651          */
6652         switch (msg & 0xff) {
6653         case SMA_IDLE_ARM:
6654                 /*
6655                  * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6656                  * State Transitions
6657                  *
6658                  * Only expected in INIT or ARMED, discard otherwise.
6659                  */
6660                 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED))
6661                         ppd->neighbor_normal = 1;
6662                 break;
6663         case SMA_IDLE_ACTIVE:
6664                 /*
6665                  * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6666                  * State Transitions
6667                  *
6668                  * Can activate the node.  Discard otherwise.
6669                  */
6670                 if (ppd->host_link_state == HLS_UP_ARMED &&
6671                     ppd->is_active_optimize_enabled) {
6672                         ppd->neighbor_normal = 1;
6673                         ret = set_link_state(ppd, HLS_UP_ACTIVE);
6674                         if (ret)
6675                                 dd_dev_err(
6676                                         dd,
6677                                         "%s: received Active SMA idle message, couldn't set link to Active\n",
6678                                         __func__);
6679                 }
6680                 break;
6681         default:
6682                 dd_dev_err(dd,
6683                            "%s: received unexpected SMA idle message 0x%llx\n",
6684                            __func__, msg);
6685                 break;
6686         }
6687 }
6688
6689 static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear)
6690 {
6691         u64 rcvctrl;
6692         unsigned long flags;
6693
6694         spin_lock_irqsave(&dd->rcvctrl_lock, flags);
6695         rcvctrl = read_csr(dd, RCV_CTRL);
6696         rcvctrl |= add;
6697         rcvctrl &= ~clear;
6698         write_csr(dd, RCV_CTRL, rcvctrl);
6699         spin_unlock_irqrestore(&dd->rcvctrl_lock, flags);
6700 }
6701
6702 static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add)
6703 {
6704         adjust_rcvctrl(dd, add, 0);
6705 }
6706
6707 static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear)
6708 {
6709         adjust_rcvctrl(dd, 0, clear);
6710 }
6711
6712 /*
6713  * Called from all interrupt handlers to start handling an SPC freeze.
6714  */
6715 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags)
6716 {
6717         struct hfi1_devdata *dd = ppd->dd;
6718         struct send_context *sc;
6719         int i;
6720
6721         if (flags & FREEZE_SELF)
6722                 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6723
6724         /* enter frozen mode */
6725         dd->flags |= HFI1_FROZEN;
6726
6727         /* notify all SDMA engines that they are going into a freeze */
6728         sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN));
6729
6730         /* do halt pre-handling on all enabled send contexts */
6731         for (i = 0; i < dd->num_send_contexts; i++) {
6732                 sc = dd->send_contexts[i].sc;
6733                 if (sc && (sc->flags & SCF_ENABLED))
6734                         sc_stop(sc, SCF_FROZEN | SCF_HALTED);
6735         }
6736
6737         /* Send context are frozen. Notify user space */
6738         hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT);
6739
6740         if (flags & FREEZE_ABORT) {
6741                 dd_dev_err(dd,
6742                            "Aborted freeze recovery. Please REBOOT system\n");
6743                 return;
6744         }
6745         /* queue non-interrupt handler */
6746         queue_work(ppd->hfi1_wq, &ppd->freeze_work);
6747 }
6748
6749 /*
6750  * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6751  * depending on the "freeze" parameter.
6752  *
6753  * No need to return an error if it times out, our only option
6754  * is to proceed anyway.
6755  */
6756 static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze)
6757 {
6758         unsigned long timeout;
6759         u64 reg;
6760
6761         timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT);
6762         while (1) {
6763                 reg = read_csr(dd, CCE_STATUS);
6764                 if (freeze) {
6765                         /* waiting until all indicators are set */
6766                         if ((reg & ALL_FROZE) == ALL_FROZE)
6767                                 return; /* all done */
6768                 } else {
6769                         /* waiting until all indicators are clear */
6770                         if ((reg & ALL_FROZE) == 0)
6771                                 return; /* all done */
6772                 }
6773
6774                 if (time_after(jiffies, timeout)) {
6775                         dd_dev_err(dd,
6776                                    "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing",
6777                                    freeze ? "" : "un", reg & ALL_FROZE,
6778                                    freeze ? ALL_FROZE : 0ull);
6779                         return;
6780                 }
6781                 usleep_range(80, 120);
6782         }
6783 }
6784
6785 /*
6786  * Do all freeze handling for the RXE block.
6787  */
6788 static void rxe_freeze(struct hfi1_devdata *dd)
6789 {
6790         int i;
6791         struct hfi1_ctxtdata *rcd;
6792
6793         /* disable port */
6794         clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6795
6796         /* disable all receive contexts */
6797         for (i = 0; i < dd->num_rcv_contexts; i++) {
6798                 rcd = hfi1_rcd_get_by_index(dd, i);
6799                 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, rcd);
6800                 hfi1_rcd_put(rcd);
6801         }
6802 }
6803
6804 /*
6805  * Unfreeze handling for the RXE block - kernel contexts only.
6806  * This will also enable the port.  User contexts will do unfreeze
6807  * handling on a per-context basis as they call into the driver.
6808  *
6809  */
6810 static void rxe_kernel_unfreeze(struct hfi1_devdata *dd)
6811 {
6812         u32 rcvmask;
6813         u16 i;
6814         struct hfi1_ctxtdata *rcd;
6815
6816         /* enable all kernel contexts */
6817         for (i = 0; i < dd->num_rcv_contexts; i++) {
6818                 rcd = hfi1_rcd_get_by_index(dd, i);
6819
6820                 /* Ensure all non-user contexts(including vnic) are enabled */
6821                 if (!rcd ||
6822                     (i >= dd->first_dyn_alloc_ctxt && !rcd->is_vnic)) {
6823                         hfi1_rcd_put(rcd);
6824                         continue;
6825                 }
6826                 rcvmask = HFI1_RCVCTRL_CTXT_ENB;
6827                 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6828                 rcvmask |= HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL) ?
6829                         HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
6830                 hfi1_rcvctrl(dd, rcvmask, rcd);
6831                 hfi1_rcd_put(rcd);
6832         }
6833
6834         /* enable port */
6835         add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6836 }
6837
6838 /*
6839  * Non-interrupt SPC freeze handling.
6840  *
6841  * This is a work-queue function outside of the triggering interrupt.
6842  */
6843 void handle_freeze(struct work_struct *work)
6844 {
6845         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6846                                                                 freeze_work);
6847         struct hfi1_devdata *dd = ppd->dd;
6848
6849         /* wait for freeze indicators on all affected blocks */
6850         wait_for_freeze_status(dd, 1);
6851
6852         /* SPC is now frozen */
6853
6854         /* do send PIO freeze steps */
6855         pio_freeze(dd);
6856
6857         /* do send DMA freeze steps */
6858         sdma_freeze(dd);
6859
6860         /* do send egress freeze steps - nothing to do */
6861
6862         /* do receive freeze steps */
6863         rxe_freeze(dd);
6864
6865         /*
6866          * Unfreeze the hardware - clear the freeze, wait for each
6867          * block's frozen bit to clear, then clear the frozen flag.
6868          */
6869         write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6870         wait_for_freeze_status(dd, 0);
6871
6872         if (is_ax(dd)) {
6873                 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6874                 wait_for_freeze_status(dd, 1);
6875                 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6876                 wait_for_freeze_status(dd, 0);
6877         }
6878
6879         /* do send PIO unfreeze steps for kernel contexts */
6880         pio_kernel_unfreeze(dd);
6881
6882         /* do send DMA unfreeze steps */
6883         sdma_unfreeze(dd);
6884
6885         /* do send egress unfreeze steps - nothing to do */
6886
6887         /* do receive unfreeze steps for kernel contexts */
6888         rxe_kernel_unfreeze(dd);
6889
6890         /*
6891          * The unfreeze procedure touches global device registers when
6892          * it disables and re-enables RXE. Mark the device unfrozen
6893          * after all that is done so other parts of the driver waiting
6894          * for the device to unfreeze don't do things out of order.
6895          *
6896          * The above implies that the meaning of HFI1_FROZEN flag is
6897          * "Device has gone into freeze mode and freeze mode handling
6898          * is still in progress."
6899          *
6900          * The flag will be removed when freeze mode processing has
6901          * completed.
6902          */
6903         dd->flags &= ~HFI1_FROZEN;
6904         wake_up(&dd->event_queue);
6905
6906         /* no longer frozen */
6907 }
6908
6909 /**
6910  * update_xmit_counters - update PortXmitWait/PortVlXmitWait
6911  * counters.
6912  * @ppd: info of physical Hfi port
6913  * @link_width: new link width after link up or downgrade
6914  *
6915  * Update the PortXmitWait and PortVlXmitWait counters after
6916  * a link up or downgrade event to reflect a link width change.
6917  */
6918 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width)
6919 {
6920         int i;
6921         u16 tx_width;
6922         u16 link_speed;
6923
6924         tx_width = tx_link_width(link_width);
6925         link_speed = get_link_speed(ppd->link_speed_active);
6926
6927         /*
6928          * There are C_VL_COUNT number of PortVLXmitWait counters.
6929          * Adding 1 to C_VL_COUNT to include the PortXmitWait counter.
6930          */
6931         for (i = 0; i < C_VL_COUNT + 1; i++)
6932                 get_xmit_wait_counters(ppd, tx_width, link_speed, i);
6933 }
6934
6935 /*
6936  * Handle a link up interrupt from the 8051.
6937  *
6938  * This is a work-queue function outside of the interrupt.
6939  */
6940 void handle_link_up(struct work_struct *work)
6941 {
6942         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6943                                                   link_up_work);
6944         struct hfi1_devdata *dd = ppd->dd;
6945
6946         set_link_state(ppd, HLS_UP_INIT);
6947
6948         /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
6949         read_ltp_rtt(dd);
6950         /*
6951          * OPA specifies that certain counters are cleared on a transition
6952          * to link up, so do that.
6953          */
6954         clear_linkup_counters(dd);
6955         /*
6956          * And (re)set link up default values.
6957          */
6958         set_linkup_defaults(ppd);
6959
6960         /*
6961          * Set VL15 credits. Use cached value from verify cap interrupt.
6962          * In case of quick linkup or simulator, vl15 value will be set by
6963          * handle_linkup_change. VerifyCap interrupt handler will not be
6964          * called in those scenarios.
6965          */
6966         if (!(quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR))
6967                 set_up_vl15(dd, dd->vl15buf_cached);
6968
6969         /* enforce link speed enabled */
6970         if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) {
6971                 /* oops - current speed is not enabled, bounce */
6972                 dd_dev_err(dd,
6973                            "Link speed active 0x%x is outside enabled 0x%x, downing link\n",
6974                            ppd->link_speed_active, ppd->link_speed_enabled);
6975                 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0,
6976                                      OPA_LINKDOWN_REASON_SPEED_POLICY);
6977                 set_link_state(ppd, HLS_DN_OFFLINE);
6978                 start_link(ppd);
6979         }
6980 }
6981
6982 /*
6983  * Several pieces of LNI information were cached for SMA in ppd.
6984  * Reset these on link down
6985  */
6986 static void reset_neighbor_info(struct hfi1_pportdata *ppd)
6987 {
6988         ppd->neighbor_guid = 0;
6989         ppd->neighbor_port_number = 0;
6990         ppd->neighbor_type = 0;
6991         ppd->neighbor_fm_security = 0;
6992 }
6993
6994 static const char * const link_down_reason_strs[] = {
6995         [OPA_LINKDOWN_REASON_NONE] = "None",
6996         [OPA_LINKDOWN_REASON_RCV_ERROR_0] = "Receive error 0",
6997         [OPA_LINKDOWN_REASON_BAD_PKT_LEN] = "Bad packet length",
6998         [OPA_LINKDOWN_REASON_PKT_TOO_LONG] = "Packet too long",
6999         [OPA_LINKDOWN_REASON_PKT_TOO_SHORT] = "Packet too short",
7000         [OPA_LINKDOWN_REASON_BAD_SLID] = "Bad SLID",
7001         [OPA_LINKDOWN_REASON_BAD_DLID] = "Bad DLID",
7002         [OPA_LINKDOWN_REASON_BAD_L2] = "Bad L2",
7003         [OPA_LINKDOWN_REASON_BAD_SC] = "Bad SC",
7004         [OPA_LINKDOWN_REASON_RCV_ERROR_8] = "Receive error 8",
7005         [OPA_LINKDOWN_REASON_BAD_MID_TAIL] = "Bad mid tail",
7006         [OPA_LINKDOWN_REASON_RCV_ERROR_10] = "Receive error 10",
7007         [OPA_LINKDOWN_REASON_PREEMPT_ERROR] = "Preempt error",
7008         [OPA_LINKDOWN_REASON_PREEMPT_VL15] = "Preempt vl15",
7009         [OPA_LINKDOWN_REASON_BAD_VL_MARKER] = "Bad VL marker",
7010         [OPA_LINKDOWN_REASON_RCV_ERROR_14] = "Receive error 14",
7011         [OPA_LINKDOWN_REASON_RCV_ERROR_15] = "Receive error 15",
7012         [OPA_LINKDOWN_REASON_BAD_HEAD_DIST] = "Bad head distance",
7013         [OPA_LINKDOWN_REASON_BAD_TAIL_DIST] = "Bad tail distance",
7014         [OPA_LINKDOWN_REASON_BAD_CTRL_DIST] = "Bad control distance",
7015         [OPA_LINKDOWN_REASON_BAD_CREDIT_ACK] = "Bad credit ack",
7016         [OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER] = "Unsupported VL marker",
7017         [OPA_LINKDOWN_REASON_BAD_PREEMPT] = "Bad preempt",
7018         [OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT] = "Bad control flit",
7019         [OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT] = "Exceed multicast limit",
7020         [OPA_LINKDOWN_REASON_RCV_ERROR_24] = "Receive error 24",
7021         [OPA_LINKDOWN_REASON_RCV_ERROR_25] = "Receive error 25",
7022         [OPA_LINKDOWN_REASON_RCV_ERROR_26] = "Receive error 26",
7023         [OPA_LINKDOWN_REASON_RCV_ERROR_27] = "Receive error 27",
7024         [OPA_LINKDOWN_REASON_RCV_ERROR_28] = "Receive error 28",
7025         [OPA_LINKDOWN_REASON_RCV_ERROR_29] = "Receive error 29",
7026         [OPA_LINKDOWN_REASON_RCV_ERROR_30] = "Receive error 30",
7027         [OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN] =
7028                                         "Excessive buffer overrun",
7029         [OPA_LINKDOWN_REASON_UNKNOWN] = "Unknown",
7030         [OPA_LINKDOWN_REASON_REBOOT] = "Reboot",
7031         [OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN] = "Neighbor unknown",
7032         [OPA_LINKDOWN_REASON_FM_BOUNCE] = "FM bounce",
7033         [OPA_LINKDOWN_REASON_SPEED_POLICY] = "Speed policy",
7034         [OPA_LINKDOWN_REASON_WIDTH_POLICY] = "Width policy",
7035         [OPA_LINKDOWN_REASON_DISCONNECTED] = "Disconnected",
7036         [OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED] =
7037                                         "Local media not installed",
7038         [OPA_LINKDOWN_REASON_NOT_INSTALLED] = "Not installed",
7039         [OPA_LINKDOWN_REASON_CHASSIS_CONFIG] = "Chassis config",
7040         [OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED] =
7041                                         "End to end not installed",
7042         [OPA_LINKDOWN_REASON_POWER_POLICY] = "Power policy",
7043         [OPA_LINKDOWN_REASON_LINKSPEED_POLICY] = "Link speed policy",
7044         [OPA_LINKDOWN_REASON_LINKWIDTH_POLICY] = "Link width policy",
7045         [OPA_LINKDOWN_REASON_SWITCH_MGMT] = "Switch management",
7046         [OPA_LINKDOWN_REASON_SMA_DISABLED] = "SMA disabled",
7047         [OPA_LINKDOWN_REASON_TRANSIENT] = "Transient"
7048 };
7049
7050 /* return the neighbor link down reason string */
7051 static const char *link_down_reason_str(u8 reason)
7052 {
7053         const char *str = NULL;
7054
7055         if (reason < ARRAY_SIZE(link_down_reason_strs))
7056                 str = link_down_reason_strs[reason];
7057         if (!str)
7058                 str = "(invalid)";
7059
7060         return str;
7061 }
7062
7063 /*
7064  * Handle a link down interrupt from the 8051.
7065  *
7066  * This is a work-queue function outside of the interrupt.
7067  */
7068 void handle_link_down(struct work_struct *work)
7069 {
7070         u8 lcl_reason, neigh_reason = 0;
7071         u8 link_down_reason;
7072         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7073                                                   link_down_work);
7074         int was_up;
7075         static const char ldr_str[] = "Link down reason: ";
7076
7077         if ((ppd->host_link_state &
7078              (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) &&
7079              ppd->port_type == PORT_TYPE_FIXED)
7080                 ppd->offline_disabled_reason =
7081                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED);
7082
7083         /* Go offline first, then deal with reading/writing through 8051 */
7084         was_up = !!(ppd->host_link_state & HLS_UP);
7085         set_link_state(ppd, HLS_DN_OFFLINE);
7086         xchg(&ppd->is_link_down_queued, 0);
7087
7088         if (was_up) {
7089                 lcl_reason = 0;
7090                 /* link down reason is only valid if the link was up */
7091                 read_link_down_reason(ppd->dd, &link_down_reason);
7092                 switch (link_down_reason) {
7093                 case LDR_LINK_TRANSFER_ACTIVE_LOW:
7094                         /* the link went down, no idle message reason */
7095                         dd_dev_info(ppd->dd, "%sUnexpected link down\n",
7096                                     ldr_str);
7097                         break;
7098                 case LDR_RECEIVED_LINKDOWN_IDLE_MSG:
7099                         /*
7100                          * The neighbor reason is only valid if an idle message
7101                          * was received for it.
7102                          */
7103                         read_planned_down_reason_code(ppd->dd, &neigh_reason);
7104                         dd_dev_info(ppd->dd,
7105                                     "%sNeighbor link down message %d, %s\n",
7106                                     ldr_str, neigh_reason,
7107                                     link_down_reason_str(neigh_reason));
7108                         break;
7109                 case LDR_RECEIVED_HOST_OFFLINE_REQ:
7110                         dd_dev_info(ppd->dd,
7111                                     "%sHost requested link to go offline\n",
7112                                     ldr_str);
7113                         break;
7114                 default:
7115                         dd_dev_info(ppd->dd, "%sUnknown reason 0x%x\n",
7116                                     ldr_str, link_down_reason);
7117                         break;
7118                 }
7119
7120                 /*
7121                  * If no reason, assume peer-initiated but missed
7122                  * LinkGoingDown idle flits.
7123                  */
7124                 if (neigh_reason == 0)
7125                         lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN;
7126         } else {
7127                 /* went down while polling or going up */
7128                 lcl_reason = OPA_LINKDOWN_REASON_TRANSIENT;
7129         }
7130
7131         set_link_down_reason(ppd, lcl_reason, neigh_reason, 0);
7132
7133         /* inform the SMA when the link transitions from up to down */
7134         if (was_up && ppd->local_link_down_reason.sma == 0 &&
7135             ppd->neigh_link_down_reason.sma == 0) {
7136                 ppd->local_link_down_reason.sma =
7137                                         ppd->local_link_down_reason.latest;
7138                 ppd->neigh_link_down_reason.sma =
7139                                         ppd->neigh_link_down_reason.latest;
7140         }
7141
7142         reset_neighbor_info(ppd);
7143
7144         /* disable the port */
7145         clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
7146
7147         /*
7148          * If there is no cable attached, turn the DC off. Otherwise,
7149          * start the link bring up.
7150          */
7151         if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd))
7152                 dc_shutdown(ppd->dd);
7153         else
7154                 start_link(ppd);
7155 }
7156
7157 void handle_link_bounce(struct work_struct *work)
7158 {
7159         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7160                                                         link_bounce_work);
7161
7162         /*
7163          * Only do something if the link is currently up.
7164          */
7165         if (ppd->host_link_state & HLS_UP) {
7166                 set_link_state(ppd, HLS_DN_OFFLINE);
7167                 start_link(ppd);
7168         } else {
7169                 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n",
7170                             __func__, link_state_name(ppd->host_link_state));
7171         }
7172 }
7173
7174 /*
7175  * Mask conversion: Capability exchange to Port LTP.  The capability
7176  * exchange has an implicit 16b CRC that is mandatory.
7177  */
7178 static int cap_to_port_ltp(int cap)
7179 {
7180         int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */
7181
7182         if (cap & CAP_CRC_14B)
7183                 port_ltp |= PORT_LTP_CRC_MODE_14;
7184         if (cap & CAP_CRC_48B)
7185                 port_ltp |= PORT_LTP_CRC_MODE_48;
7186         if (cap & CAP_CRC_12B_16B_PER_LANE)
7187                 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE;
7188
7189         return port_ltp;
7190 }
7191
7192 /*
7193  * Convert an OPA Port LTP mask to capability mask
7194  */
7195 int port_ltp_to_cap(int port_ltp)
7196 {
7197         int cap_mask = 0;
7198
7199         if (port_ltp & PORT_LTP_CRC_MODE_14)
7200                 cap_mask |= CAP_CRC_14B;
7201         if (port_ltp & PORT_LTP_CRC_MODE_48)
7202                 cap_mask |= CAP_CRC_48B;
7203         if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE)
7204                 cap_mask |= CAP_CRC_12B_16B_PER_LANE;
7205
7206         return cap_mask;
7207 }
7208
7209 /*
7210  * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
7211  */
7212 static int lcb_to_port_ltp(int lcb_crc)
7213 {
7214         int port_ltp = 0;
7215
7216         if (lcb_crc == LCB_CRC_12B_16B_PER_LANE)
7217                 port_ltp = PORT_LTP_CRC_MODE_PER_LANE;
7218         else if (lcb_crc == LCB_CRC_48B)
7219                 port_ltp = PORT_LTP_CRC_MODE_48;
7220         else if (lcb_crc == LCB_CRC_14B)
7221                 port_ltp = PORT_LTP_CRC_MODE_14;
7222         else
7223                 port_ltp = PORT_LTP_CRC_MODE_16;
7224
7225         return port_ltp;
7226 }
7227
7228 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd)
7229 {
7230         if (ppd->pkeys[2] != 0) {
7231                 ppd->pkeys[2] = 0;
7232                 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
7233                 hfi1_event_pkey_change(ppd->dd, ppd->port);
7234         }
7235 }
7236
7237 /*
7238  * Convert the given link width to the OPA link width bitmask.
7239  */
7240 static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width)
7241 {
7242         switch (width) {
7243         case 0:
7244                 /*
7245                  * Simulator and quick linkup do not set the width.
7246                  * Just set it to 4x without complaint.
7247                  */
7248                 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup)
7249                         return OPA_LINK_WIDTH_4X;
7250                 return 0; /* no lanes up */
7251         case 1: return OPA_LINK_WIDTH_1X;
7252         case 2: return OPA_LINK_WIDTH_2X;
7253         case 3: return OPA_LINK_WIDTH_3X;
7254         default:
7255                 dd_dev_info(dd, "%s: invalid width %d, using 4\n",
7256                             __func__, width);
7257                 /* fall through */
7258         case 4: return OPA_LINK_WIDTH_4X;
7259         }
7260 }
7261
7262 /*
7263  * Do a population count on the bottom nibble.
7264  */
7265 static const u8 bit_counts[16] = {
7266         0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4
7267 };
7268
7269 static inline u8 nibble_to_count(u8 nibble)
7270 {
7271         return bit_counts[nibble & 0xf];
7272 }
7273
7274 /*
7275  * Read the active lane information from the 8051 registers and return
7276  * their widths.
7277  *
7278  * Active lane information is found in these 8051 registers:
7279  *      enable_lane_tx
7280  *      enable_lane_rx
7281  */
7282 static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width,
7283                             u16 *rx_width)
7284 {
7285         u16 tx, rx;
7286         u8 enable_lane_rx;
7287         u8 enable_lane_tx;
7288         u8 tx_polarity_inversion;
7289         u8 rx_polarity_inversion;
7290         u8 max_rate;
7291
7292         /* read the active lanes */
7293         read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
7294                          &rx_polarity_inversion, &max_rate);
7295         read_local_lni(dd, &enable_lane_rx);
7296
7297         /* convert to counts */
7298         tx = nibble_to_count(enable_lane_tx);
7299         rx = nibble_to_count(enable_lane_rx);
7300
7301         /*
7302          * Set link_speed_active here, overriding what was set in
7303          * handle_verify_cap().  The ASIC 8051 firmware does not correctly
7304          * set the max_rate field in handle_verify_cap until v0.19.
7305          */
7306         if ((dd->icode == ICODE_RTL_SILICON) &&
7307             (dd->dc8051_ver < dc8051_ver(0, 19, 0))) {
7308                 /* max_rate: 0 = 12.5G, 1 = 25G */
7309                 switch (max_rate) {
7310                 case 0:
7311                         dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G;
7312                         break;
7313                 default:
7314                         dd_dev_err(dd,
7315                                    "%s: unexpected max rate %d, using 25Gb\n",
7316                                    __func__, (int)max_rate);
7317                         /* fall through */
7318                 case 1:
7319                         dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G;
7320                         break;
7321                 }
7322         }
7323
7324         dd_dev_info(dd,
7325                     "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n",
7326                     enable_lane_tx, tx, enable_lane_rx, rx);
7327         *tx_width = link_width_to_bits(dd, tx);
7328         *rx_width = link_width_to_bits(dd, rx);
7329 }
7330
7331 /*
7332  * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7333  * Valid after the end of VerifyCap and during LinkUp.  Does not change
7334  * after link up.  I.e. look elsewhere for downgrade information.
7335  *
7336  * Bits are:
7337  *      + bits [7:4] contain the number of active transmitters
7338  *      + bits [3:0] contain the number of active receivers
7339  * These are numbers 1 through 4 and can be different values if the
7340  * link is asymmetric.
7341  *
7342  * verify_cap_local_fm_link_width[0] retains its original value.
7343  */
7344 static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width,
7345                               u16 *rx_width)
7346 {
7347         u16 widths, tx, rx;
7348         u8 misc_bits, local_flags;
7349         u16 active_tx, active_rx;
7350
7351         read_vc_local_link_width(dd, &misc_bits, &local_flags, &widths);
7352         tx = widths >> 12;
7353         rx = (widths >> 8) & 0xf;
7354
7355         *tx_width = link_width_to_bits(dd, tx);
7356         *rx_width = link_width_to_bits(dd, rx);
7357
7358         /* print the active widths */
7359         get_link_widths(dd, &active_tx, &active_rx);
7360 }
7361
7362 /*
7363  * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7364  * hardware information when the link first comes up.
7365  *
7366  * The link width is not available until after VerifyCap.AllFramesReceived
7367  * (the trigger for handle_verify_cap), so this is outside that routine
7368  * and should be called when the 8051 signals linkup.
7369  */
7370 void get_linkup_link_widths(struct hfi1_pportdata *ppd)
7371 {
7372         u16 tx_width, rx_width;
7373
7374         /* get end-of-LNI link widths */
7375         get_linkup_widths(ppd->dd, &tx_width, &rx_width);
7376
7377         /* use tx_width as the link is supposed to be symmetric on link up */
7378         ppd->link_width_active = tx_width;
7379         /* link width downgrade active (LWD.A) starts out matching LW.A */
7380         ppd->link_width_downgrade_tx_active = ppd->link_width_active;
7381         ppd->link_width_downgrade_rx_active = ppd->link_width_active;
7382         /* per OPA spec, on link up LWD.E resets to LWD.S */
7383         ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported;
7384         /* cache the active egress rate (units {10^6 bits/sec]) */
7385         ppd->current_egress_rate = active_egress_rate(ppd);
7386 }
7387
7388 /*
7389  * Handle a verify capabilities interrupt from the 8051.
7390  *
7391  * This is a work-queue function outside of the interrupt.
7392  */
7393 void handle_verify_cap(struct work_struct *work)
7394 {
7395         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7396                                                                 link_vc_work);
7397         struct hfi1_devdata *dd = ppd->dd;
7398         u64 reg;
7399         u8 power_management;
7400         u8 continuous;
7401         u8 vcu;
7402         u8 vau;
7403         u8 z;
7404         u16 vl15buf;
7405         u16 link_widths;
7406         u16 crc_mask;
7407         u16 crc_val;
7408         u16 device_id;
7409         u16 active_tx, active_rx;
7410         u8 partner_supported_crc;
7411         u8 remote_tx_rate;
7412         u8 device_rev;
7413
7414         set_link_state(ppd, HLS_VERIFY_CAP);
7415
7416         lcb_shutdown(dd, 0);
7417         adjust_lcb_for_fpga_serdes(dd);
7418
7419         read_vc_remote_phy(dd, &power_management, &continuous);
7420         read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf,
7421                               &partner_supported_crc);
7422         read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths);
7423         read_remote_device_id(dd, &device_id, &device_rev);
7424
7425         /* print the active widths */
7426         get_link_widths(dd, &active_tx, &active_rx);
7427         dd_dev_info(dd,
7428                     "Peer PHY: power management 0x%x, continuous updates 0x%x\n",
7429                     (int)power_management, (int)continuous);
7430         dd_dev_info(dd,
7431                     "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n",
7432                     (int)vau, (int)z, (int)vcu, (int)vl15buf,
7433                     (int)partner_supported_crc);
7434         dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n",
7435                     (u32)remote_tx_rate, (u32)link_widths);
7436         dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n",
7437                     (u32)device_id, (u32)device_rev);
7438         /*
7439          * The peer vAU value just read is the peer receiver value.  HFI does
7440          * not support a transmit vAU of 0 (AU == 8).  We advertised that
7441          * with Z=1 in the fabric capabilities sent to the peer.  The peer
7442          * will see our Z=1, and, if it advertised a vAU of 0, will move its
7443          * receive to vAU of 1 (AU == 16).  Do the same here.  We do not care
7444          * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7445          * subject to the Z value exception.
7446          */
7447         if (vau == 0)
7448                 vau = 1;
7449         set_up_vau(dd, vau);
7450
7451         /*
7452          * Set VL15 credits to 0 in global credit register. Cache remote VL15
7453          * credits value and wait for link-up interrupt ot set it.
7454          */
7455         set_up_vl15(dd, 0);
7456         dd->vl15buf_cached = vl15buf;
7457
7458         /* set up the LCB CRC mode */
7459         crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc;
7460
7461         /* order is important: use the lowest bit in common */
7462         if (crc_mask & CAP_CRC_14B)
7463                 crc_val = LCB_CRC_14B;
7464         else if (crc_mask & CAP_CRC_48B)
7465                 crc_val = LCB_CRC_48B;
7466         else if (crc_mask & CAP_CRC_12B_16B_PER_LANE)
7467                 crc_val = LCB_CRC_12B_16B_PER_LANE;
7468         else
7469                 crc_val = LCB_CRC_16B;
7470
7471         dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val);
7472         write_csr(dd, DC_LCB_CFG_CRC_MODE,
7473                   (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT);
7474
7475         /* set (14b only) or clear sideband credit */
7476         reg = read_csr(dd, SEND_CM_CTRL);
7477         if (crc_val == LCB_CRC_14B && crc_14b_sideband) {
7478                 write_csr(dd, SEND_CM_CTRL,
7479                           reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
7480         } else {
7481                 write_csr(dd, SEND_CM_CTRL,
7482                           reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
7483         }
7484
7485         ppd->link_speed_active = 0;     /* invalid value */
7486         if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) {
7487                 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7488                 switch (remote_tx_rate) {
7489                 case 0:
7490                         ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7491                         break;
7492                 case 1:
7493                         ppd->link_speed_active = OPA_LINK_SPEED_25G;
7494                         break;
7495                 }
7496         } else {
7497                 /* actual rate is highest bit of the ANDed rates */
7498                 u8 rate = remote_tx_rate & ppd->local_tx_rate;
7499
7500                 if (rate & 2)
7501                         ppd->link_speed_active = OPA_LINK_SPEED_25G;
7502                 else if (rate & 1)
7503                         ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7504         }
7505         if (ppd->link_speed_active == 0) {
7506                 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n",
7507                            __func__, (int)remote_tx_rate);
7508                 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7509         }
7510
7511         /*
7512          * Cache the values of the supported, enabled, and active
7513          * LTP CRC modes to return in 'portinfo' queries. But the bit
7514          * flags that are returned in the portinfo query differ from
7515          * what's in the link_crc_mask, crc_sizes, and crc_val
7516          * variables. Convert these here.
7517          */
7518         ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
7519                 /* supported crc modes */
7520         ppd->port_ltp_crc_mode |=
7521                 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4;
7522                 /* enabled crc modes */
7523         ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val);
7524                 /* active crc mode */
7525
7526         /* set up the remote credit return table */
7527         assign_remote_cm_au_table(dd, vcu);
7528
7529         /*
7530          * The LCB is reset on entry to handle_verify_cap(), so this must
7531          * be applied on every link up.
7532          *
7533          * Adjust LCB error kill enable to kill the link if
7534          * these RBUF errors are seen:
7535          *      REPLAY_BUF_MBE_SMASK
7536          *      FLIT_INPUT_BUF_MBE_SMASK
7537          */
7538         if (is_ax(dd)) {                        /* fixed in B0 */
7539                 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
7540                 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7541                         | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK;
7542                 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
7543         }
7544
7545         /* pull LCB fifos out of reset - all fifo clocks must be stable */
7546         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
7547
7548         /* give 8051 access to the LCB CSRs */
7549         write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
7550         set_8051_lcb_access(dd);
7551
7552         /* tell the 8051 to go to LinkUp */
7553         set_link_state(ppd, HLS_GOING_UP);
7554 }
7555
7556 /**
7557  * apply_link_downgrade_policy - Apply the link width downgrade enabled
7558  * policy against the current active link widths.
7559  * @ppd: info of physical Hfi port
7560  * @refresh_widths: True indicates link downgrade event
7561  * @return: True indicates a successful link downgrade. False indicates
7562  *          link downgrade event failed and the link will bounce back to
7563  *          default link width.
7564  *
7565  * Called when the enabled policy changes or the active link widths
7566  * change.
7567  * Refresh_widths indicates that a link downgrade occurred. The
7568  * link_downgraded variable is set by refresh_widths and
7569  * determines the success/failure of the policy application.
7570  */
7571 bool apply_link_downgrade_policy(struct hfi1_pportdata *ppd,
7572                                  bool refresh_widths)
7573 {
7574         int do_bounce = 0;
7575         int tries;
7576         u16 lwde;
7577         u16 tx, rx;
7578         bool link_downgraded = refresh_widths;
7579
7580         /* use the hls lock to avoid a race with actual link up */
7581         tries = 0;
7582 retry:
7583         mutex_lock(&ppd->hls_lock);
7584         /* only apply if the link is up */
7585         if (ppd->host_link_state & HLS_DOWN) {
7586                 /* still going up..wait and retry */
7587                 if (ppd->host_link_state & HLS_GOING_UP) {
7588                         if (++tries < 1000) {
7589                                 mutex_unlock(&ppd->hls_lock);
7590                                 usleep_range(100, 120); /* arbitrary */
7591                                 goto retry;
7592                         }
7593                         dd_dev_err(ppd->dd,
7594                                    "%s: giving up waiting for link state change\n",
7595                                    __func__);
7596                 }
7597                 goto done;
7598         }
7599
7600         lwde = ppd->link_width_downgrade_enabled;
7601
7602         if (refresh_widths) {
7603                 get_link_widths(ppd->dd, &tx, &rx);
7604                 ppd->link_width_downgrade_tx_active = tx;
7605                 ppd->link_width_downgrade_rx_active = rx;
7606         }
7607
7608         if (ppd->link_width_downgrade_tx_active == 0 ||
7609             ppd->link_width_downgrade_rx_active == 0) {
7610                 /* the 8051 reported a dead link as a downgrade */
7611                 dd_dev_err(ppd->dd, "Link downgrade is really a link down, ignoring\n");
7612                 link_downgraded = false;
7613         } else if (lwde == 0) {
7614                 /* downgrade is disabled */
7615
7616                 /* bounce if not at starting active width */
7617                 if ((ppd->link_width_active !=
7618                      ppd->link_width_downgrade_tx_active) ||
7619                     (ppd->link_width_active !=
7620                      ppd->link_width_downgrade_rx_active)) {
7621                         dd_dev_err(ppd->dd,
7622                                    "Link downgrade is disabled and link has downgraded, downing link\n");
7623                         dd_dev_err(ppd->dd,
7624                                    "  original 0x%x, tx active 0x%x, rx active 0x%x\n",
7625                                    ppd->link_width_active,
7626                                    ppd->link_width_downgrade_tx_active,
7627                                    ppd->link_width_downgrade_rx_active);
7628                         do_bounce = 1;
7629                         link_downgraded = false;
7630                 }
7631         } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 ||
7632                    (lwde & ppd->link_width_downgrade_rx_active) == 0) {
7633                 /* Tx or Rx is outside the enabled policy */
7634                 dd_dev_err(ppd->dd,
7635                            "Link is outside of downgrade allowed, downing link\n");
7636                 dd_dev_err(ppd->dd,
7637                            "  enabled 0x%x, tx active 0x%x, rx active 0x%x\n",
7638                            lwde, ppd->link_width_downgrade_tx_active,
7639                            ppd->link_width_downgrade_rx_active);
7640                 do_bounce = 1;
7641                 link_downgraded = false;
7642         }
7643
7644 done:
7645         mutex_unlock(&ppd->hls_lock);
7646
7647         if (do_bounce) {
7648                 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0,
7649                                      OPA_LINKDOWN_REASON_WIDTH_POLICY);
7650                 set_link_state(ppd, HLS_DN_OFFLINE);
7651                 start_link(ppd);
7652         }
7653
7654         return link_downgraded;
7655 }
7656
7657 /*
7658  * Handle a link downgrade interrupt from the 8051.
7659  *
7660  * This is a work-queue function outside of the interrupt.
7661  */
7662 void handle_link_downgrade(struct work_struct *work)
7663 {
7664         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7665                                                         link_downgrade_work);
7666
7667         dd_dev_info(ppd->dd, "8051: Link width downgrade\n");
7668         if (apply_link_downgrade_policy(ppd, true))
7669                 update_xmit_counters(ppd, ppd->link_width_downgrade_tx_active);
7670 }
7671
7672 static char *dcc_err_string(char *buf, int buf_len, u64 flags)
7673 {
7674         return flag_string(buf, buf_len, flags, dcc_err_flags,
7675                 ARRAY_SIZE(dcc_err_flags));
7676 }
7677
7678 static char *lcb_err_string(char *buf, int buf_len, u64 flags)
7679 {
7680         return flag_string(buf, buf_len, flags, lcb_err_flags,
7681                 ARRAY_SIZE(lcb_err_flags));
7682 }
7683
7684 static char *dc8051_err_string(char *buf, int buf_len, u64 flags)
7685 {
7686         return flag_string(buf, buf_len, flags, dc8051_err_flags,
7687                 ARRAY_SIZE(dc8051_err_flags));
7688 }
7689
7690 static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags)
7691 {
7692         return flag_string(buf, buf_len, flags, dc8051_info_err_flags,
7693                 ARRAY_SIZE(dc8051_info_err_flags));
7694 }
7695
7696 static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags)
7697 {
7698         return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags,
7699                 ARRAY_SIZE(dc8051_info_host_msg_flags));
7700 }
7701
7702 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg)
7703 {
7704         struct hfi1_pportdata *ppd = dd->pport;
7705         u64 info, err, host_msg;
7706         int queue_link_down = 0;
7707         char buf[96];
7708
7709         /* look at the flags */
7710         if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) {
7711                 /* 8051 information set by firmware */
7712                 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7713                 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);
7714                 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT)
7715                         & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK;
7716                 host_msg = (info >>
7717                         DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7718                         & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK;
7719
7720                 /*
7721                  * Handle error flags.
7722                  */
7723                 if (err & FAILED_LNI) {
7724                         /*
7725                          * LNI error indications are cleared by the 8051
7726                          * only when starting polling.  Only pay attention
7727                          * to them when in the states that occur during
7728                          * LNI.
7729                          */
7730                         if (ppd->host_link_state
7731                             & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
7732                                 queue_link_down = 1;
7733                                 dd_dev_info(dd, "Link error: %s\n",
7734                                             dc8051_info_err_string(buf,
7735                                                                    sizeof(buf),
7736                                                                    err &
7737                                                                    FAILED_LNI));
7738                         }
7739                         err &= ~(u64)FAILED_LNI;
7740                 }
7741                 /* unknown frames can happen durning LNI, just count */
7742                 if (err & UNKNOWN_FRAME) {
7743                         ppd->unknown_frame_count++;
7744                         err &= ~(u64)UNKNOWN_FRAME;
7745                 }
7746                 if (err) {
7747                         /* report remaining errors, but do not do anything */
7748                         dd_dev_err(dd, "8051 info error: %s\n",
7749                                    dc8051_info_err_string(buf, sizeof(buf),
7750                                                           err));
7751                 }
7752
7753                 /*
7754                  * Handle host message flags.
7755                  */
7756                 if (host_msg & HOST_REQ_DONE) {
7757                         /*
7758                          * Presently, the driver does a busy wait for
7759                          * host requests to complete.  This is only an
7760                          * informational message.
7761                          * NOTE: The 8051 clears the host message
7762                          * information *on the next 8051 command*.
7763                          * Therefore, when linkup is achieved,
7764                          * this flag will still be set.
7765                          */
7766                         host_msg &= ~(u64)HOST_REQ_DONE;
7767                 }
7768                 if (host_msg & BC_SMA_MSG) {
7769                         queue_work(ppd->link_wq, &ppd->sma_message_work);
7770                         host_msg &= ~(u64)BC_SMA_MSG;
7771                 }
7772                 if (host_msg & LINKUP_ACHIEVED) {
7773                         dd_dev_info(dd, "8051: Link up\n");
7774                         queue_work(ppd->link_wq, &ppd->link_up_work);
7775                         host_msg &= ~(u64)LINKUP_ACHIEVED;
7776                 }
7777                 if (host_msg & EXT_DEVICE_CFG_REQ) {
7778                         handle_8051_request(ppd);
7779                         host_msg &= ~(u64)EXT_DEVICE_CFG_REQ;
7780                 }
7781                 if (host_msg & VERIFY_CAP_FRAME) {
7782                         queue_work(ppd->link_wq, &ppd->link_vc_work);
7783                         host_msg &= ~(u64)VERIFY_CAP_FRAME;
7784                 }
7785                 if (host_msg & LINK_GOING_DOWN) {
7786                         const char *extra = "";
7787                         /* no downgrade action needed if going down */
7788                         if (host_msg & LINK_WIDTH_DOWNGRADED) {
7789                                 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7790                                 extra = " (ignoring downgrade)";
7791                         }
7792                         dd_dev_info(dd, "8051: Link down%s\n", extra);
7793                         queue_link_down = 1;
7794                         host_msg &= ~(u64)LINK_GOING_DOWN;
7795                 }
7796                 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7797                         queue_work(ppd->link_wq, &ppd->link_downgrade_work);
7798                         host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7799                 }
7800                 if (host_msg) {
7801                         /* report remaining messages, but do not do anything */
7802                         dd_dev_info(dd, "8051 info host message: %s\n",
7803                                     dc8051_info_host_msg_string(buf,
7804                                                                 sizeof(buf),
7805                                                                 host_msg));
7806                 }
7807
7808                 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK;
7809         }
7810         if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) {
7811                 /*
7812                  * Lost the 8051 heartbeat.  If this happens, we
7813                  * receive constant interrupts about it.  Disable
7814                  * the interrupt after the first.
7815                  */
7816                 dd_dev_err(dd, "Lost 8051 heartbeat\n");
7817                 write_csr(dd, DC_DC8051_ERR_EN,
7818                           read_csr(dd, DC_DC8051_ERR_EN) &
7819                           ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK);
7820
7821                 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK;
7822         }
7823         if (reg) {
7824                 /* report the error, but do not do anything */
7825                 dd_dev_err(dd, "8051 error: %s\n",
7826                            dc8051_err_string(buf, sizeof(buf), reg));
7827         }
7828
7829         if (queue_link_down) {
7830                 /*
7831                  * if the link is already going down or disabled, do not
7832                  * queue another. If there's a link down entry already
7833                  * queued, don't queue another one.
7834                  */
7835                 if ((ppd->host_link_state &
7836                     (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) ||
7837                     ppd->link_enabled == 0) {
7838                         dd_dev_info(dd, "%s: not queuing link down. host_link_state %x, link_enabled %x\n",
7839                                     __func__, ppd->host_link_state,
7840                                     ppd->link_enabled);
7841                 } else {
7842                         if (xchg(&ppd->is_link_down_queued, 1) == 1)
7843                                 dd_dev_info(dd,
7844                                             "%s: link down request already queued\n",
7845                                             __func__);
7846                         else
7847                                 queue_work(ppd->link_wq, &ppd->link_down_work);
7848                 }
7849         }
7850 }
7851
7852 static const char * const fm_config_txt[] = {
7853 [0] =
7854         "BadHeadDist: Distance violation between two head flits",
7855 [1] =
7856         "BadTailDist: Distance violation between two tail flits",
7857 [2] =
7858         "BadCtrlDist: Distance violation between two credit control flits",
7859 [3] =
7860         "BadCrdAck: Credits return for unsupported VL",
7861 [4] =
7862         "UnsupportedVLMarker: Received VL Marker",
7863 [5] =
7864         "BadPreempt: Exceeded the preemption nesting level",
7865 [6] =
7866         "BadControlFlit: Received unsupported control flit",
7867 /* no 7 */
7868 [8] =
7869         "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL",
7870 };
7871
7872 static const char * const port_rcv_txt[] = {
7873 [1] =
7874         "BadPktLen: Illegal PktLen",
7875 [2] =
7876         "PktLenTooLong: Packet longer than PktLen",
7877 [3] =
7878         "PktLenTooShort: Packet shorter than PktLen",
7879 [4] =
7880         "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7881 [5] =
7882         "BadDLID: Illegal DLID (0, doesn't match HFI)",
7883 [6] =
7884         "BadL2: Illegal L2 opcode",
7885 [7] =
7886         "BadSC: Unsupported SC",
7887 [9] =
7888         "BadRC: Illegal RC",
7889 [11] =
7890         "PreemptError: Preempting with same VL",
7891 [12] =
7892         "PreemptVL15: Preempting a VL15 packet",
7893 };
7894
7895 #define OPA_LDR_FMCONFIG_OFFSET 16
7896 #define OPA_LDR_PORTRCV_OFFSET 0
7897 static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7898 {
7899         u64 info, hdr0, hdr1;
7900         const char *extra;
7901         char buf[96];
7902         struct hfi1_pportdata *ppd = dd->pport;
7903         u8 lcl_reason = 0;
7904         int do_bounce = 0;
7905
7906         if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) {
7907                 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) {
7908                         info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);
7909                         dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK;
7910                         /* set status bit */
7911                         dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK;
7912                 }
7913                 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK;
7914         }
7915
7916         if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) {
7917                 struct hfi1_pportdata *ppd = dd->pport;
7918                 /* this counter saturates at (2^32) - 1 */
7919                 if (ppd->link_downed < (u32)UINT_MAX)
7920                         ppd->link_downed++;
7921                 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK;
7922         }
7923
7924         if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) {
7925                 u8 reason_valid = 1;
7926
7927                 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);
7928                 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) {
7929                         dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK;
7930                         /* set status bit */
7931                         dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK;
7932                 }
7933                 switch (info) {
7934                 case 0:
7935                 case 1:
7936                 case 2:
7937                 case 3:
7938                 case 4:
7939                 case 5:
7940                 case 6:
7941                         extra = fm_config_txt[info];
7942                         break;
7943                 case 8:
7944                         extra = fm_config_txt[info];
7945                         if (ppd->port_error_action &
7946                             OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
7947                                 do_bounce = 1;
7948                                 /*
7949                                  * lcl_reason cannot be derived from info
7950                                  * for this error
7951                                  */
7952                                 lcl_reason =
7953                                   OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
7954                         }
7955                         break;
7956                 default:
7957                         reason_valid = 0;
7958                         snprintf(buf, sizeof(buf), "reserved%lld", info);
7959                         extra = buf;
7960                         break;
7961                 }
7962
7963                 if (reason_valid && !do_bounce) {
7964                         do_bounce = ppd->port_error_action &
7965                                         (1 << (OPA_LDR_FMCONFIG_OFFSET + info));
7966                         lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST;
7967                 }
7968
7969                 /* just report this */
7970                 dd_dev_info_ratelimited(dd, "DCC Error: fmconfig error: %s\n",
7971                                         extra);
7972                 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK;
7973         }
7974
7975         if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) {
7976                 u8 reason_valid = 1;
7977
7978                 info = read_csr(dd, DCC_ERR_INFO_PORTRCV);
7979                 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);
7980                 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);
7981                 if (!(dd->err_info_rcvport.status_and_code &
7982                       OPA_EI_STATUS_SMASK)) {
7983                         dd->err_info_rcvport.status_and_code =
7984                                 info & OPA_EI_CODE_SMASK;
7985                         /* set status bit */
7986                         dd->err_info_rcvport.status_and_code |=
7987                                 OPA_EI_STATUS_SMASK;
7988                         /*
7989                          * save first 2 flits in the packet that caused
7990                          * the error
7991                          */
7992                         dd->err_info_rcvport.packet_flit1 = hdr0;
7993                         dd->err_info_rcvport.packet_flit2 = hdr1;
7994                 }
7995                 switch (info) {
7996                 case 1:
7997                 case 2:
7998                 case 3:
7999                 case 4:
8000                 case 5:
8001                 case 6:
8002                 case 7:
8003                 case 9:
8004                 case 11:
8005                 case 12:
8006                         extra = port_rcv_txt[info];
8007                         break;
8008                 default:
8009                         reason_valid = 0;
8010                         snprintf(buf, sizeof(buf), "reserved%lld", info);
8011                         extra = buf;
8012                         break;
8013                 }
8014
8015                 if (reason_valid && !do_bounce) {
8016                         do_bounce = ppd->port_error_action &
8017                                         (1 << (OPA_LDR_PORTRCV_OFFSET + info));
8018                         lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0;
8019                 }
8020
8021                 /* just report this */
8022                 dd_dev_info_ratelimited(dd, "DCC Error: PortRcv error: %s\n"
8023                                         "               hdr0 0x%llx, hdr1 0x%llx\n",
8024                                         extra, hdr0, hdr1);
8025
8026                 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK;
8027         }
8028
8029         if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) {
8030                 /* informative only */
8031                 dd_dev_info_ratelimited(dd, "8051 access to LCB blocked\n");
8032                 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK;
8033         }
8034         if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) {
8035                 /* informative only */
8036                 dd_dev_info_ratelimited(dd, "host access to LCB blocked\n");
8037                 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK;
8038         }
8039
8040         if (unlikely(hfi1_dbg_fault_suppress_err(&dd->verbs_dev)))
8041                 reg &= ~DCC_ERR_FLG_LATE_EBP_ERR_SMASK;
8042
8043         /* report any remaining errors */
8044         if (reg)
8045                 dd_dev_info_ratelimited(dd, "DCC Error: %s\n",
8046                                         dcc_err_string(buf, sizeof(buf), reg));
8047
8048         if (lcl_reason == 0)
8049                 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN;
8050
8051         if (do_bounce) {
8052                 dd_dev_info_ratelimited(dd, "%s: PortErrorAction bounce\n",
8053                                         __func__);
8054                 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason);
8055                 queue_work(ppd->link_wq, &ppd->link_bounce_work);
8056         }
8057 }
8058
8059 static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
8060 {
8061         char buf[96];
8062
8063         dd_dev_info(dd, "LCB Error: %s\n",
8064                     lcb_err_string(buf, sizeof(buf), reg));
8065 }
8066
8067 /*
8068  * CCE block DC interrupt.  Source is < 8.
8069  */
8070 static void is_dc_int(struct hfi1_devdata *dd, unsigned int source)
8071 {
8072         const struct err_reg_info *eri = &dc_errs[source];
8073
8074         if (eri->handler) {
8075                 interrupt_clear_down(dd, 0, eri);
8076         } else if (source == 3 /* dc_lbm_int */) {
8077                 /*
8078                  * This indicates that a parity error has occurred on the
8079                  * address/control lines presented to the LBM.  The error
8080                  * is a single pulse, there is no associated error flag,
8081                  * and it is non-maskable.  This is because if a parity
8082                  * error occurs on the request the request is dropped.
8083                  * This should never occur, but it is nice to know if it
8084                  * ever does.
8085                  */
8086                 dd_dev_err(dd, "Parity error in DC LBM block\n");
8087         } else {
8088                 dd_dev_err(dd, "Invalid DC interrupt %u\n", source);
8089         }
8090 }
8091
8092 /*
8093  * TX block send credit interrupt.  Source is < 160.
8094  */
8095 static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source)
8096 {
8097         sc_group_release_update(dd, source);
8098 }
8099
8100 /*
8101  * TX block SDMA interrupt.  Source is < 48.
8102  *
8103  * SDMA interrupts are grouped by type:
8104  *
8105  *       0 -  N-1 = SDma
8106  *       N - 2N-1 = SDmaProgress
8107  *      2N - 3N-1 = SDmaIdle
8108  */
8109 static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source)
8110 {
8111         /* what interrupt */
8112         unsigned int what  = source / TXE_NUM_SDMA_ENGINES;
8113         /* which engine */
8114         unsigned int which = source % TXE_NUM_SDMA_ENGINES;
8115
8116 #ifdef CONFIG_SDMA_VERBOSITY
8117         dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which,
8118                    slashstrip(__FILE__), __LINE__, __func__);
8119         sdma_dumpstate(&dd->per_sdma[which]);
8120 #endif
8121
8122         if (likely(what < 3 && which < dd->num_sdma)) {
8123                 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source);
8124         } else {
8125                 /* should not happen */
8126                 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source);
8127         }
8128 }
8129
8130 /*
8131  * RX block receive available interrupt.  Source is < 160.
8132  */
8133 static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source)
8134 {
8135         struct hfi1_ctxtdata *rcd;
8136         char *err_detail;
8137
8138         if (likely(source < dd->num_rcv_contexts)) {
8139                 rcd = hfi1_rcd_get_by_index(dd, source);
8140                 if (rcd) {
8141                         /* Check for non-user contexts, including vnic */
8142                         if (source < dd->first_dyn_alloc_ctxt || rcd->is_vnic)
8143                                 rcd->do_interrupt(rcd, 0);
8144                         else
8145                                 handle_user_interrupt(rcd);
8146
8147                         hfi1_rcd_put(rcd);
8148                         return; /* OK */
8149                 }
8150                 /* received an interrupt, but no rcd */
8151                 err_detail = "dataless";
8152         } else {
8153                 /* received an interrupt, but are not using that context */
8154                 err_detail = "out of range";
8155         }
8156         dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n",
8157                    err_detail, source);
8158 }
8159
8160 /*
8161  * RX block receive urgent interrupt.  Source is < 160.
8162  */
8163 static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source)
8164 {
8165         struct hfi1_ctxtdata *rcd;
8166         char *err_detail;
8167
8168         if (likely(source < dd->num_rcv_contexts)) {
8169                 rcd = hfi1_rcd_get_by_index(dd, source);
8170                 if (rcd) {
8171                         /* only pay attention to user urgent interrupts */
8172                         if (source >= dd->first_dyn_alloc_ctxt &&
8173                             !rcd->is_vnic)
8174                                 handle_user_interrupt(rcd);
8175
8176                         hfi1_rcd_put(rcd);
8177                         return; /* OK */
8178                 }
8179                 /* received an interrupt, but no rcd */
8180                 err_detail = "dataless";
8181         } else {
8182                 /* received an interrupt, but are not using that context */
8183                 err_detail = "out of range";
8184         }
8185         dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n",
8186                    err_detail, source);
8187 }
8188
8189 /*
8190  * Reserved range interrupt.  Should not be called in normal operation.
8191  */
8192 static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source)
8193 {
8194         char name[64];
8195
8196         dd_dev_err(dd, "unexpected %s interrupt\n",
8197                    is_reserved_name(name, sizeof(name), source));
8198 }
8199
8200 static const struct is_table is_table[] = {
8201 /*
8202  * start                 end
8203  *                              name func               interrupt func
8204  */
8205 { IS_GENERAL_ERR_START,  IS_GENERAL_ERR_END,
8206                                 is_misc_err_name,       is_misc_err_int },
8207 { IS_SDMAENG_ERR_START,  IS_SDMAENG_ERR_END,
8208                                 is_sdma_eng_err_name,   is_sdma_eng_err_int },
8209 { IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END,
8210                                 is_sendctxt_err_name,   is_sendctxt_err_int },
8211 { IS_SDMA_START,             IS_SDMA_END,
8212                                 is_sdma_eng_name,       is_sdma_eng_int },
8213 { IS_VARIOUS_START,          IS_VARIOUS_END,
8214                                 is_various_name,        is_various_int },
8215 { IS_DC_START,       IS_DC_END,
8216                                 is_dc_name,             is_dc_int },
8217 { IS_RCVAVAIL_START,     IS_RCVAVAIL_END,
8218                                 is_rcv_avail_name,      is_rcv_avail_int },
8219 { IS_RCVURGENT_START,    IS_RCVURGENT_END,
8220                                 is_rcv_urgent_name,     is_rcv_urgent_int },
8221 { IS_SENDCREDIT_START,   IS_SENDCREDIT_END,
8222                                 is_send_credit_name,    is_send_credit_int},
8223 { IS_RESERVED_START,     IS_RESERVED_END,
8224                                 is_reserved_name,       is_reserved_int},
8225 };
8226
8227 /*
8228  * Interrupt source interrupt - called when the given source has an interrupt.
8229  * Source is a bit index into an array of 64-bit integers.
8230  */
8231 static void is_interrupt(struct hfi1_devdata *dd, unsigned int source)
8232 {
8233         const struct is_table *entry;
8234
8235         /* avoids a double compare by walking the table in-order */
8236         for (entry = &is_table[0]; entry->is_name; entry++) {
8237                 if (source < entry->end) {
8238                         trace_hfi1_interrupt(dd, entry, source);
8239                         entry->is_int(dd, source - entry->start);
8240                         return;
8241                 }
8242         }
8243         /* fell off the end */
8244         dd_dev_err(dd, "invalid interrupt source %u\n", source);
8245 }
8246
8247 /*
8248  * General interrupt handler.  This is able to correctly handle
8249  * all interrupts in case INTx is used.
8250  */
8251 static irqreturn_t general_interrupt(int irq, void *data)
8252 {
8253         struct hfi1_devdata *dd = data;
8254         u64 regs[CCE_NUM_INT_CSRS];
8255         u32 bit;
8256         int i;
8257         irqreturn_t handled = IRQ_NONE;
8258
8259         this_cpu_inc(*dd->int_counter);
8260
8261         /* phase 1: scan and clear all handled interrupts */
8262         for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
8263                 if (dd->gi_mask[i] == 0) {
8264                         regs[i] = 0;    /* used later */
8265                         continue;
8266                 }
8267                 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &
8268                                 dd->gi_mask[i];
8269                 /* only clear if anything is set */
8270                 if (regs[i])
8271                         write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
8272         }
8273
8274         /* phase 2: call the appropriate handler */
8275         for_each_set_bit(bit, (unsigned long *)&regs[0],
8276                          CCE_NUM_INT_CSRS * 64) {
8277                 is_interrupt(dd, bit);
8278                 handled = IRQ_HANDLED;
8279         }
8280
8281         return handled;
8282 }
8283
8284 static irqreturn_t sdma_interrupt(int irq, void *data)
8285 {
8286         struct sdma_engine *sde = data;
8287         struct hfi1_devdata *dd = sde->dd;
8288         u64 status;
8289
8290 #ifdef CONFIG_SDMA_VERBOSITY
8291         dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
8292                    slashstrip(__FILE__), __LINE__, __func__);
8293         sdma_dumpstate(sde);
8294 #endif
8295
8296         this_cpu_inc(*dd->int_counter);
8297
8298         /* This read_csr is really bad in the hot path */
8299         status = read_csr(dd,
8300                           CCE_INT_STATUS + (8 * (IS_SDMA_START / 64)))
8301                           & sde->imask;
8302         if (likely(status)) {
8303                 /* clear the interrupt(s) */
8304                 write_csr(dd,
8305                           CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)),
8306                           status);
8307
8308                 /* handle the interrupt(s) */
8309                 sdma_engine_interrupt(sde, status);
8310         } else {
8311                 dd_dev_info_ratelimited(dd, "SDMA engine %u interrupt, but no status bits set\n",
8312                                         sde->this_idx);
8313         }
8314         return IRQ_HANDLED;
8315 }
8316
8317 /*
8318  * Clear the receive interrupt.  Use a read of the interrupt clear CSR
8319  * to insure that the write completed.  This does NOT guarantee that
8320  * queued DMA writes to memory from the chip are pushed.
8321  */
8322 static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd)
8323 {
8324         struct hfi1_devdata *dd = rcd->dd;
8325         u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg);
8326
8327         mmiowb();       /* make sure everything before is written */
8328         write_csr(dd, addr, rcd->imask);
8329         /* force the above write on the chip and get a value back */
8330         (void)read_csr(dd, addr);
8331 }
8332
8333 /* force the receive interrupt */
8334 void force_recv_intr(struct hfi1_ctxtdata *rcd)
8335 {
8336         write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8337 }
8338
8339 /*
8340  * Return non-zero if a packet is present.
8341  *
8342  * This routine is called when rechecking for packets after the RcvAvail
8343  * interrupt has been cleared down.  First, do a quick check of memory for
8344  * a packet present.  If not found, use an expensive CSR read of the context
8345  * tail to determine the actual tail.  The CSR read is necessary because there
8346  * is no method to push pending DMAs to memory other than an interrupt and we
8347  * are trying to determine if we need to force an interrupt.
8348  */
8349 static inline int check_packet_present(struct hfi1_ctxtdata *rcd)
8350 {
8351         u32 tail;
8352         int present;
8353
8354         if (!HFI1_CAP_IS_KSET(DMA_RTAIL))
8355                 present = (rcd->seq_cnt ==
8356                                 rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd))));
8357         else /* is RDMA rtail */
8358                 present = (rcd->head != get_rcvhdrtail(rcd));
8359
8360         if (present)
8361                 return 1;
8362
8363         /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8364         tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8365         return rcd->head != tail;
8366 }
8367
8368 /*
8369  * Receive packet IRQ handler.  This routine expects to be on its own IRQ.
8370  * This routine will try to handle packets immediately (latency), but if
8371  * it finds too many, it will invoke the thread handler (bandwitdh).  The
8372  * chip receive interrupt is *not* cleared down until this or the thread (if
8373  * invoked) is finished.  The intent is to avoid extra interrupts while we
8374  * are processing packets anyway.
8375  */
8376 static irqreturn_t receive_context_interrupt(int irq, void *data)
8377 {
8378         struct hfi1_ctxtdata *rcd = data;
8379         struct hfi1_devdata *dd = rcd->dd;
8380         int disposition;
8381         int present;
8382
8383         trace_hfi1_receive_interrupt(dd, rcd);
8384         this_cpu_inc(*dd->int_counter);
8385         aspm_ctx_disable(rcd);
8386
8387         /* receive interrupt remains blocked while processing packets */
8388         disposition = rcd->do_interrupt(rcd, 0);
8389
8390         /*
8391          * Too many packets were seen while processing packets in this
8392          * IRQ handler.  Invoke the handler thread.  The receive interrupt
8393          * remains blocked.
8394          */
8395         if (disposition == RCV_PKT_LIMIT)
8396                 return IRQ_WAKE_THREAD;
8397
8398         /*
8399          * The packet processor detected no more packets.  Clear the receive
8400          * interrupt and recheck for a packet packet that may have arrived
8401          * after the previous check and interrupt clear.  If a packet arrived,
8402          * force another interrupt.
8403          */
8404         clear_recv_intr(rcd);
8405         present = check_packet_present(rcd);
8406         if (present)
8407                 force_recv_intr(rcd);
8408
8409         return IRQ_HANDLED;
8410 }
8411
8412 /*
8413  * Receive packet thread handler.  This expects to be invoked with the
8414  * receive interrupt still blocked.
8415  */
8416 static irqreturn_t receive_context_thread(int irq, void *data)
8417 {
8418         struct hfi1_ctxtdata *rcd = data;
8419         int present;
8420
8421         /* receive interrupt is still blocked from the IRQ handler */
8422         (void)rcd->do_interrupt(rcd, 1);
8423
8424         /*
8425          * The packet processor will only return if it detected no more
8426          * packets.  Hold IRQs here so we can safely clear the interrupt and
8427          * recheck for a packet that may have arrived after the previous
8428          * check and the interrupt clear.  If a packet arrived, force another
8429          * interrupt.
8430          */
8431         local_irq_disable();
8432         clear_recv_intr(rcd);
8433         present = check_packet_present(rcd);
8434         if (present)
8435                 force_recv_intr(rcd);
8436         local_irq_enable();
8437
8438         return IRQ_HANDLED;
8439 }
8440
8441 /* ========================================================================= */
8442
8443 u32 read_physical_state(struct hfi1_devdata *dd)
8444 {
8445         u64 reg;
8446
8447         reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
8448         return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT)
8449                                 & DC_DC8051_STS_CUR_STATE_PORT_MASK;
8450 }
8451
8452 u32 read_logical_state(struct hfi1_devdata *dd)
8453 {
8454         u64 reg;
8455
8456         reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8457         return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT)
8458                                 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK;
8459 }
8460
8461 static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate)
8462 {
8463         u64 reg;
8464
8465         reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8466         /* clear current state, set new state */
8467         reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK;
8468         reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT;
8469         write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
8470 }
8471
8472 /*
8473  * Use the 8051 to read a LCB CSR.
8474  */
8475 static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data)
8476 {
8477         u32 regno;
8478         int ret;
8479
8480         if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8481                 if (acquire_lcb_access(dd, 0) == 0) {
8482                         *data = read_csr(dd, addr);
8483                         release_lcb_access(dd, 0);
8484                         return 0;
8485                 }
8486                 return -EBUSY;
8487         }
8488
8489         /* register is an index of LCB registers: (offset - base) / 8 */
8490         regno = (addr - DC_LCB_CFG_RUN) >> 3;
8491         ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data);
8492         if (ret != HCMD_SUCCESS)
8493                 return -EBUSY;
8494         return 0;
8495 }
8496
8497 /*
8498  * Provide a cache for some of the LCB registers in case the LCB is
8499  * unavailable.
8500  * (The LCB is unavailable in certain link states, for example.)
8501  */
8502 struct lcb_datum {
8503         u32 off;
8504         u64 val;
8505 };
8506
8507 static struct lcb_datum lcb_cache[] = {
8508         { DC_LCB_ERR_INFO_RX_REPLAY_CNT, 0},
8509         { DC_LCB_ERR_INFO_SEQ_CRC_CNT, 0 },
8510         { DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 0 },
8511 };
8512
8513 static void update_lcb_cache(struct hfi1_devdata *dd)
8514 {
8515         int i;
8516         int ret;
8517         u64 val;
8518
8519         for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) {
8520                 ret = read_lcb_csr(dd, lcb_cache[i].off, &val);
8521
8522                 /* Update if we get good data */
8523                 if (likely(ret != -EBUSY))
8524                         lcb_cache[i].val = val;
8525         }
8526 }
8527
8528 static int read_lcb_cache(u32 off, u64 *val)
8529 {
8530         int i;
8531
8532         for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) {
8533                 if (lcb_cache[i].off == off) {
8534                         *val = lcb_cache[i].val;
8535                         return 0;
8536                 }
8537         }
8538
8539         pr_warn("%s bad offset 0x%x\n", __func__, off);
8540         return -1;
8541 }
8542
8543 /*
8544  * Read an LCB CSR.  Access may not be in host control, so check.
8545  * Return 0 on success, -EBUSY on failure.
8546  */
8547 int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data)
8548 {
8549         struct hfi1_pportdata *ppd = dd->pport;
8550
8551         /* if up, go through the 8051 for the value */
8552         if (ppd->host_link_state & HLS_UP)
8553                 return read_lcb_via_8051(dd, addr, data);
8554         /* if going up or down, check the cache, otherwise, no access */
8555         if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) {
8556                 if (read_lcb_cache(addr, data))
8557                         return -EBUSY;
8558                 return 0;
8559         }
8560
8561         /* otherwise, host has access */
8562         *data = read_csr(dd, addr);
8563         return 0;
8564 }
8565
8566 /*
8567  * Use the 8051 to write a LCB CSR.
8568  */
8569 static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data)
8570 {
8571         u32 regno;
8572         int ret;
8573
8574         if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR ||
8575             (dd->dc8051_ver < dc8051_ver(0, 20, 0))) {
8576                 if (acquire_lcb_access(dd, 0) == 0) {
8577                         write_csr(dd, addr, data);
8578                         release_lcb_access(dd, 0);
8579                         return 0;
8580                 }
8581                 return -EBUSY;
8582         }
8583
8584         /* register is an index of LCB registers: (offset - base) / 8 */
8585         regno = (addr - DC_LCB_CFG_RUN) >> 3;
8586         ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data);
8587         if (ret != HCMD_SUCCESS)
8588                 return -EBUSY;
8589         return 0;
8590 }
8591
8592 /*
8593  * Write an LCB CSR.  Access may not be in host control, so check.
8594  * Return 0 on success, -EBUSY on failure.
8595  */
8596 int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data)
8597 {
8598         struct hfi1_pportdata *ppd = dd->pport;
8599
8600         /* if up, go through the 8051 for the value */
8601         if (ppd->host_link_state & HLS_UP)
8602                 return write_lcb_via_8051(dd, addr, data);
8603         /* if going up or down, no access */
8604         if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8605                 return -EBUSY;
8606         /* otherwise, host has access */
8607         write_csr(dd, addr, data);
8608         return 0;
8609 }
8610
8611 /*
8612  * Returns:
8613  *      < 0 = Linux error, not able to get access
8614  *      > 0 = 8051 command RETURN_CODE
8615  */
8616 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
8617                            u64 *out_data)
8618 {
8619         u64 reg, completed;
8620         int return_code;
8621         unsigned long timeout;
8622
8623         hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data);
8624
8625         mutex_lock(&dd->dc8051_lock);
8626
8627         /* We can't send any commands to the 8051 if it's in reset */
8628         if (dd->dc_shutdown) {
8629                 return_code = -ENODEV;
8630                 goto fail;
8631         }
8632
8633         /*
8634          * If an 8051 host command timed out previously, then the 8051 is
8635          * stuck.
8636          *
8637          * On first timeout, attempt to reset and restart the entire DC
8638          * block (including 8051). (Is this too big of a hammer?)
8639          *
8640          * If the 8051 times out a second time, the reset did not bring it
8641          * back to healthy life. In that case, fail any subsequent commands.
8642          */
8643         if (dd->dc8051_timed_out) {
8644                 if (dd->dc8051_timed_out > 1) {
8645                         dd_dev_err(dd,
8646                                    "Previous 8051 host command timed out, skipping command %u\n",
8647                                    type);
8648                         return_code = -ENXIO;
8649                         goto fail;
8650                 }
8651                 _dc_shutdown(dd);
8652                 _dc_start(dd);
8653         }
8654
8655         /*
8656          * If there is no timeout, then the 8051 command interface is
8657          * waiting for a command.
8658          */
8659
8660         /*
8661          * When writing a LCB CSR, out_data contains the full value to
8662          * to be written, while in_data contains the relative LCB
8663          * address in 7:0.  Do the work here, rather than the caller,
8664          * of distrubting the write data to where it needs to go:
8665          *
8666          * Write data
8667          *   39:00 -> in_data[47:8]
8668          *   47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8669          *   63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8670          */
8671         if (type == HCMD_WRITE_LCB_CSR) {
8672                 in_data |= ((*out_data) & 0xffffffffffull) << 8;
8673                 /* must preserve COMPLETED - it is tied to hardware */
8674                 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0);
8675                 reg &= DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK;
8676                 reg |= ((((*out_data) >> 40) & 0xff) <<
8677                                 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8678                       | ((((*out_data) >> 48) & 0xffff) <<
8679                                 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8680                 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
8681         }
8682
8683         /*
8684          * Do two writes: the first to stabilize the type and req_data, the
8685          * second to activate.
8686          */
8687         reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK)
8688                         << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8689                 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK)
8690                         << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT;
8691         write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8692         reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK;
8693         write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8694
8695         /* wait for completion, alternate: interrupt */
8696         timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT);
8697         while (1) {
8698                 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);
8699                 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK;
8700                 if (completed)
8701                         break;
8702                 if (time_after(jiffies, timeout)) {
8703                         dd->dc8051_timed_out++;
8704                         dd_dev_err(dd, "8051 host command %u timeout\n", type);
8705                         if (out_data)
8706                                 *out_data = 0;
8707                         return_code = -ETIMEDOUT;
8708                         goto fail;
8709                 }
8710                 udelay(2);
8711         }
8712
8713         if (out_data) {
8714                 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT)
8715                                 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK;
8716                 if (type == HCMD_READ_LCB_CSR) {
8717                         /* top 16 bits are in a different register */
8718                         *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)
8719                                 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK)
8720                                 << (48
8721                                     - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT);
8722                 }
8723         }
8724         return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT)
8725                                 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK;
8726         dd->dc8051_timed_out = 0;
8727         /*
8728          * Clear command for next user.
8729          */
8730         write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
8731
8732 fail:
8733         mutex_unlock(&dd->dc8051_lock);
8734         return return_code;
8735 }
8736
8737 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state)
8738 {
8739         return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL);
8740 }
8741
8742 int load_8051_config(struct hfi1_devdata *dd, u8 field_id,
8743                      u8 lane_id, u32 config_data)
8744 {
8745         u64 data;
8746         int ret;
8747
8748         data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT
8749                 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT
8750                 | (u64)config_data << LOAD_DATA_DATA_SHIFT;
8751         ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL);
8752         if (ret != HCMD_SUCCESS) {
8753                 dd_dev_err(dd,
8754                            "load 8051 config: field id %d, lane %d, err %d\n",
8755                            (int)field_id, (int)lane_id, ret);
8756         }
8757         return ret;
8758 }
8759
8760 /*
8761  * Read the 8051 firmware "registers".  Use the RAM directly.  Always
8762  * set the result, even on error.
8763  * Return 0 on success, -errno on failure
8764  */
8765 int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id,
8766                      u32 *result)
8767 {
8768         u64 big_data;
8769         u32 addr;
8770         int ret;
8771
8772         /* address start depends on the lane_id */
8773         if (lane_id < 4)
8774                 addr = (4 * NUM_GENERAL_FIELDS)
8775                         + (lane_id * 4 * NUM_LANE_FIELDS);
8776         else
8777                 addr = 0;
8778         addr += field_id * 4;
8779
8780         /* read is in 8-byte chunks, hardware will truncate the address down */
8781         ret = read_8051_data(dd, addr, 8, &big_data);
8782
8783         if (ret == 0) {
8784                 /* extract the 4 bytes we want */
8785                 if (addr & 0x4)
8786                         *result = (u32)(big_data >> 32);
8787                 else
8788                         *result = (u32)big_data;
8789         } else {
8790                 *result = 0;
8791                 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n",
8792                            __func__, lane_id, field_id);
8793         }
8794
8795         return ret;
8796 }
8797
8798 static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management,
8799                               u8 continuous)
8800 {
8801         u32 frame;
8802
8803         frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT
8804                 | power_management << POWER_MANAGEMENT_SHIFT;
8805         return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY,
8806                                 GENERAL_CONFIG, frame);
8807 }
8808
8809 static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu,
8810                                  u16 vl15buf, u8 crc_sizes)
8811 {
8812         u32 frame;
8813
8814         frame = (u32)vau << VAU_SHIFT
8815                 | (u32)z << Z_SHIFT
8816                 | (u32)vcu << VCU_SHIFT
8817                 | (u32)vl15buf << VL15BUF_SHIFT
8818                 | (u32)crc_sizes << CRC_SIZES_SHIFT;
8819         return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC,
8820                                 GENERAL_CONFIG, frame);
8821 }
8822
8823 static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
8824                                      u8 *flag_bits, u16 *link_widths)
8825 {
8826         u32 frame;
8827
8828         read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8829                          &frame);
8830         *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK;
8831         *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK;
8832         *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8833 }
8834
8835 static int write_vc_local_link_width(struct hfi1_devdata *dd,
8836                                      u8 misc_bits,
8837                                      u8 flag_bits,
8838                                      u16 link_widths)
8839 {
8840         u32 frame;
8841
8842         frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT
8843                 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT
8844                 | (u32)link_widths << LINK_WIDTH_SHIFT;
8845         return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8846                      frame);
8847 }
8848
8849 static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id,
8850                                  u8 device_rev)
8851 {
8852         u32 frame;
8853
8854         frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT)
8855                 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT);
8856         return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame);
8857 }
8858
8859 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
8860                                   u8 *device_rev)
8861 {
8862         u32 frame;
8863
8864         read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame);
8865         *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK;
8866         *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT)
8867                         & REMOTE_DEVICE_REV_MASK;
8868 }
8869
8870 int write_host_interface_version(struct hfi1_devdata *dd, u8 version)
8871 {
8872         u32 frame;
8873         u32 mask;
8874
8875         mask = (HOST_INTERFACE_VERSION_MASK << HOST_INTERFACE_VERSION_SHIFT);
8876         read_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, &frame);
8877         /* Clear, then set field */
8878         frame &= ~mask;
8879         frame |= ((u32)version << HOST_INTERFACE_VERSION_SHIFT);
8880         return load_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG,
8881                                 frame);
8882 }
8883
8884 void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor,
8885                       u8 *ver_patch)
8886 {
8887         u32 frame;
8888
8889         read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame);
8890         *ver_major = (frame >> STS_FM_VERSION_MAJOR_SHIFT) &
8891                 STS_FM_VERSION_MAJOR_MASK;
8892         *ver_minor = (frame >> STS_FM_VERSION_MINOR_SHIFT) &
8893                 STS_FM_VERSION_MINOR_MASK;
8894
8895         read_8051_config(dd, VERSION_PATCH, GENERAL_CONFIG, &frame);
8896         *ver_patch = (frame >> STS_FM_VERSION_PATCH_SHIFT) &
8897                 STS_FM_VERSION_PATCH_MASK;
8898 }
8899
8900 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
8901                                u8 *continuous)
8902 {
8903         u32 frame;
8904
8905         read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame);
8906         *power_management = (frame >> POWER_MANAGEMENT_SHIFT)
8907                                         & POWER_MANAGEMENT_MASK;
8908         *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT)
8909                                         & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK;
8910 }
8911
8912 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
8913                                   u8 *vcu, u16 *vl15buf, u8 *crc_sizes)
8914 {
8915         u32 frame;
8916
8917         read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame);
8918         *vau = (frame >> VAU_SHIFT) & VAU_MASK;
8919         *z = (frame >> Z_SHIFT) & Z_MASK;
8920         *vcu = (frame >> VCU_SHIFT) & VCU_MASK;
8921         *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK;
8922         *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK;
8923 }
8924
8925 static void read_vc_remote_link_width(struct hfi1_devdata *dd,
8926                                       u8 *remote_tx_rate,
8927                                       u16 *link_widths)
8928 {
8929         u32 frame;
8930
8931         read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG,
8932                          &frame);
8933         *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT)
8934                                 & REMOTE_TX_RATE_MASK;
8935         *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8936 }
8937
8938 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx)
8939 {
8940         u32 frame;
8941
8942         read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame);
8943         *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK;
8944 }
8945
8946 static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls)
8947 {
8948         read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls);
8949 }
8950
8951 static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs)
8952 {
8953         read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs);
8954 }
8955
8956 void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality)
8957 {
8958         u32 frame;
8959         int ret;
8960
8961         *link_quality = 0;
8962         if (dd->pport->host_link_state & HLS_UP) {
8963                 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG,
8964                                        &frame);
8965                 if (ret == 0)
8966                         *link_quality = (frame >> LINK_QUALITY_SHIFT)
8967                                                 & LINK_QUALITY_MASK;
8968         }
8969 }
8970
8971 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc)
8972 {
8973         u32 frame;
8974
8975         read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame);
8976         *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK;
8977 }
8978
8979 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr)
8980 {
8981         u32 frame;
8982
8983         read_8051_config(dd, LINK_DOWN_REASON, GENERAL_CONFIG, &frame);
8984         *ldr = (frame & 0xff);
8985 }
8986
8987 static int read_tx_settings(struct hfi1_devdata *dd,
8988                             u8 *enable_lane_tx,
8989                             u8 *tx_polarity_inversion,
8990                             u8 *rx_polarity_inversion,
8991                             u8 *max_rate)
8992 {
8993         u32 frame;
8994         int ret;
8995
8996         ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame);
8997         *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT)
8998                                 & ENABLE_LANE_TX_MASK;
8999         *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT)
9000                                 & TX_POLARITY_INVERSION_MASK;
9001         *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT)
9002                                 & RX_POLARITY_INVERSION_MASK;
9003         *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK;
9004         return ret;
9005 }
9006
9007 static int write_tx_settings(struct hfi1_devdata *dd,
9008                              u8 enable_lane_tx,
9009                              u8 tx_polarity_inversion,
9010                              u8 rx_polarity_inversion,
9011                              u8 max_rate)
9012 {
9013         u32 frame;
9014
9015         /* no need to mask, all variable sizes match field widths */
9016         frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT
9017                 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT
9018                 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT
9019                 | max_rate << MAX_RATE_SHIFT;
9020         return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame);
9021 }
9022
9023 /*
9024  * Read an idle LCB message.
9025  *
9026  * Returns 0 on success, -EINVAL on error
9027  */
9028 static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out)
9029 {
9030         int ret;
9031
9032         ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out);
9033         if (ret != HCMD_SUCCESS) {
9034                 dd_dev_err(dd, "read idle message: type %d, err %d\n",
9035                            (u32)type, ret);
9036                 return -EINVAL;
9037         }
9038         dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out);
9039         /* return only the payload as we already know the type */
9040         *data_out >>= IDLE_PAYLOAD_SHIFT;
9041         return 0;
9042 }
9043
9044 /*
9045  * Read an idle SMA message.  To be done in response to a notification from
9046  * the 8051.
9047  *
9048  * Returns 0 on success, -EINVAL on error
9049  */
9050 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data)
9051 {
9052         return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT,
9053                                  data);
9054 }
9055
9056 /*
9057  * Send an idle LCB message.
9058  *
9059  * Returns 0 on success, -EINVAL on error
9060  */
9061 static int send_idle_message(struct hfi1_devdata *dd, u64 data)
9062 {
9063         int ret;
9064
9065         dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data);
9066         ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL);
9067         if (ret != HCMD_SUCCESS) {
9068                 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n",
9069                            data, ret);
9070                 return -EINVAL;
9071         }
9072         return 0;
9073 }
9074
9075 /*
9076  * Send an idle SMA message.
9077  *
9078  * Returns 0 on success, -EINVAL on error
9079  */
9080 int send_idle_sma(struct hfi1_devdata *dd, u64 message)
9081 {
9082         u64 data;
9083
9084         data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) |
9085                 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT);
9086         return send_idle_message(dd, data);
9087 }
9088
9089 /*
9090  * Initialize the LCB then do a quick link up.  This may or may not be
9091  * in loopback.
9092  *
9093  * return 0 on success, -errno on error
9094  */
9095 static int do_quick_linkup(struct hfi1_devdata *dd)
9096 {
9097         int ret;
9098
9099         lcb_shutdown(dd, 0);
9100
9101         if (loopback) {
9102                 /* LCB_CFG_LOOPBACK.VAL = 2 */
9103                 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
9104                 write_csr(dd, DC_LCB_CFG_LOOPBACK,
9105                           IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT);
9106                 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
9107         }
9108
9109         /* start the LCBs */
9110         /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
9111         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
9112
9113         /* simulator only loopback steps */
9114         if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
9115                 /* LCB_CFG_RUN.EN = 1 */
9116                 write_csr(dd, DC_LCB_CFG_RUN,
9117                           1ull << DC_LCB_CFG_RUN_EN_SHIFT);
9118
9119                 ret = wait_link_transfer_active(dd, 10);
9120                 if (ret)
9121                         return ret;
9122
9123                 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
9124                           1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT);
9125         }
9126
9127         if (!loopback) {
9128                 /*
9129                  * When doing quick linkup and not in loopback, both
9130                  * sides must be done with LCB set-up before either
9131                  * starts the quick linkup.  Put a delay here so that
9132                  * both sides can be started and have a chance to be
9133                  * done with LCB set up before resuming.
9134                  */
9135                 dd_dev_err(dd,
9136                            "Pausing for peer to be finished with LCB set up\n");
9137                 msleep(5000);
9138                 dd_dev_err(dd, "Continuing with quick linkup\n");
9139         }
9140
9141         write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
9142         set_8051_lcb_access(dd);
9143
9144         /*
9145          * State "quick" LinkUp request sets the physical link state to
9146          * LinkUp without a verify capability sequence.
9147          * This state is in simulator v37 and later.
9148          */
9149         ret = set_physical_link_state(dd, PLS_QUICK_LINKUP);
9150         if (ret != HCMD_SUCCESS) {
9151                 dd_dev_err(dd,
9152                            "%s: set physical link state to quick LinkUp failed with return %d\n",
9153                            __func__, ret);
9154
9155                 set_host_lcb_access(dd);
9156                 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
9157
9158                 if (ret >= 0)
9159                         ret = -EINVAL;
9160                 return ret;
9161         }
9162
9163         return 0; /* success */
9164 }
9165
9166 /*
9167  * Do all special steps to set up loopback.
9168  */
9169 static int init_loopback(struct hfi1_devdata *dd)
9170 {
9171         dd_dev_info(dd, "Entering loopback mode\n");
9172
9173         /* all loopbacks should disable self GUID check */
9174         write_csr(dd, DC_DC8051_CFG_MODE,
9175                   (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));
9176
9177         /*
9178          * The simulator has only one loopback option - LCB.  Switch
9179          * to that option, which includes quick link up.
9180          *
9181          * Accept all valid loopback values.
9182          */
9183         if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) &&
9184             (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB ||
9185              loopback == LOOPBACK_CABLE)) {
9186                 loopback = LOOPBACK_LCB;
9187                 quick_linkup = 1;
9188                 return 0;
9189         }
9190
9191         /*
9192          * SerDes loopback init sequence is handled in set_local_link_attributes
9193          */
9194         if (loopback == LOOPBACK_SERDES)
9195                 return 0;
9196
9197         /* LCB loopback - handled at poll time */
9198         if (loopback == LOOPBACK_LCB) {
9199                 quick_linkup = 1; /* LCB is always quick linkup */
9200
9201                 /* not supported in emulation due to emulation RTL changes */
9202                 if (dd->icode == ICODE_FPGA_EMULATION) {
9203                         dd_dev_err(dd,
9204                                    "LCB loopback not supported in emulation\n");
9205                         return -EINVAL;
9206                 }
9207                 return 0;
9208         }
9209
9210         /* external cable loopback requires no extra steps */
9211         if (loopback == LOOPBACK_CABLE)
9212                 return 0;
9213
9214         dd_dev_err(dd, "Invalid loopback mode %d\n", loopback);
9215         return -EINVAL;
9216 }
9217
9218 /*
9219  * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
9220  * used in the Verify Capability link width attribute.
9221  */
9222 static u16 opa_to_vc_link_widths(u16 opa_widths)
9223 {
9224         int i;
9225         u16 result = 0;
9226
9227         static const struct link_bits {
9228                 u16 from;
9229                 u16 to;
9230         } opa_link_xlate[] = {
9231                 { OPA_LINK_WIDTH_1X, 1 << (1 - 1)  },
9232                 { OPA_LINK_WIDTH_2X, 1 << (2 - 1)  },
9233                 { OPA_LINK_WIDTH_3X, 1 << (3 - 1)  },
9234                 { OPA_LINK_WIDTH_4X, 1 << (4 - 1)  },
9235         };
9236
9237         for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) {
9238                 if (opa_widths & opa_link_xlate[i].from)
9239                         result |= opa_link_xlate[i].to;
9240         }
9241         return result;
9242 }
9243
9244 /*
9245  * Set link attributes before moving to polling.
9246  */
9247 static int set_local_link_attributes(struct hfi1_pportdata *ppd)
9248 {
9249         struct hfi1_devdata *dd = ppd->dd;
9250         u8 enable_lane_tx;
9251         u8 tx_polarity_inversion;
9252         u8 rx_polarity_inversion;
9253         int ret;
9254         u32 misc_bits = 0;
9255         /* reset our fabric serdes to clear any lingering problems */
9256         fabric_serdes_reset(dd);
9257
9258         /* set the local tx rate - need to read-modify-write */
9259         ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
9260                                &rx_polarity_inversion, &ppd->local_tx_rate);
9261         if (ret)
9262                 goto set_local_link_attributes_fail;
9263
9264         if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) {
9265                 /* set the tx rate to the fastest enabled */
9266                 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9267                         ppd->local_tx_rate = 1;
9268                 else
9269                         ppd->local_tx_rate = 0;
9270         } else {
9271                 /* set the tx rate to all enabled */
9272                 ppd->local_tx_rate = 0;
9273                 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9274                         ppd->local_tx_rate |= 2;
9275                 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G)
9276                         ppd->local_tx_rate |= 1;
9277         }
9278
9279         enable_lane_tx = 0xF; /* enable all four lanes */
9280         ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion,
9281                                 rx_polarity_inversion, ppd->local_tx_rate);
9282         if (ret != HCMD_SUCCESS)
9283                 goto set_local_link_attributes_fail;
9284
9285         ret = write_host_interface_version(dd, HOST_INTERFACE_VERSION);
9286         if (ret != HCMD_SUCCESS) {
9287                 dd_dev_err(dd,
9288                            "Failed to set host interface version, return 0x%x\n",
9289                            ret);
9290                 goto set_local_link_attributes_fail;
9291         }
9292
9293         /*
9294          * DC supports continuous updates.
9295          */
9296         ret = write_vc_local_phy(dd,
9297                                  0 /* no power management */,
9298                                  1 /* continuous updates */);
9299         if (ret != HCMD_SUCCESS)
9300                 goto set_local_link_attributes_fail;
9301
9302         /* z=1 in the next call: AU of 0 is not supported by the hardware */
9303         ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init,
9304                                     ppd->port_crc_mode_enabled);
9305         if (ret != HCMD_SUCCESS)
9306                 goto set_local_link_attributes_fail;
9307
9308         /*
9309          * SerDes loopback init sequence requires
9310          * setting bit 0 of MISC_CONFIG_BITS
9311          */
9312         if (loopback == LOOPBACK_SERDES)
9313                 misc_bits |= 1 << LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT;
9314
9315         ret = write_vc_local_link_width(dd, misc_bits, 0,
9316                                         opa_to_vc_link_widths(
9317                                                 ppd->link_width_enabled));
9318         if (ret != HCMD_SUCCESS)
9319                 goto set_local_link_attributes_fail;
9320
9321         /* let peer know who we are */
9322         ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev);
9323         if (ret == HCMD_SUCCESS)
9324                 return 0;
9325
9326 set_local_link_attributes_fail:
9327         dd_dev_err(dd,
9328                    "Failed to set local link attributes, return 0x%x\n",
9329                    ret);
9330         return ret;
9331 }
9332
9333 /*
9334  * Call this to start the link.
9335  * Do not do anything if the link is disabled.
9336  * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
9337  */
9338 int start_link(struct hfi1_pportdata *ppd)
9339 {
9340         /*
9341          * Tune the SerDes to a ballpark setting for optimal signal and bit
9342          * error rate.  Needs to be done before starting the link.
9343          */
9344         tune_serdes(ppd);
9345
9346         if (!ppd->driver_link_ready) {
9347                 dd_dev_info(ppd->dd,
9348                             "%s: stopping link start because driver is not ready\n",
9349                             __func__);
9350                 return 0;
9351         }
9352
9353         /*
9354          * FULL_MGMT_P_KEY is cleared from the pkey table, so that the
9355          * pkey table can be configured properly if the HFI unit is connected
9356          * to switch port with MgmtAllowed=NO
9357          */
9358         clear_full_mgmt_pkey(ppd);
9359
9360         return set_link_state(ppd, HLS_DN_POLL);
9361 }
9362
9363 static void wait_for_qsfp_init(struct hfi1_pportdata *ppd)
9364 {
9365         struct hfi1_devdata *dd = ppd->dd;
9366         u64 mask;
9367         unsigned long timeout;
9368
9369         /*
9370          * Some QSFP cables have a quirk that asserts the IntN line as a side
9371          * effect of power up on plug-in. We ignore this false positive
9372          * interrupt until the module has finished powering up by waiting for
9373          * a minimum timeout of the module inrush initialization time of
9374          * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the
9375          * module have stabilized.
9376          */
9377         msleep(500);
9378
9379         /*
9380          * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1)
9381          */
9382         timeout = jiffies + msecs_to_jiffies(2000);
9383         while (1) {
9384                 mask = read_csr(dd, dd->hfi1_id ?
9385                                 ASIC_QSFP2_IN : ASIC_QSFP1_IN);
9386                 if (!(mask & QSFP_HFI0_INT_N))
9387                         break;
9388                 if (time_after(jiffies, timeout)) {
9389                         dd_dev_info(dd, "%s: No IntN detected, reset complete\n",
9390                                     __func__);
9391                         break;
9392                 }
9393                 udelay(2);
9394         }
9395 }
9396
9397 static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable)
9398 {
9399         struct hfi1_devdata *dd = ppd->dd;
9400         u64 mask;
9401
9402         mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
9403         if (enable) {
9404                 /*
9405                  * Clear the status register to avoid an immediate interrupt
9406                  * when we re-enable the IntN pin
9407                  */
9408                 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9409                           QSFP_HFI0_INT_N);
9410                 mask |= (u64)QSFP_HFI0_INT_N;
9411         } else {
9412                 mask &= ~(u64)QSFP_HFI0_INT_N;
9413         }
9414         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
9415 }
9416
9417 int reset_qsfp(struct hfi1_pportdata *ppd)
9418 {
9419         struct hfi1_devdata *dd = ppd->dd;
9420         u64 mask, qsfp_mask;
9421
9422         /* Disable INT_N from triggering QSFP interrupts */
9423         set_qsfp_int_n(ppd, 0);
9424
9425         /* Reset the QSFP */
9426         mask = (u64)QSFP_HFI0_RESET_N;
9427
9428         qsfp_mask = read_csr(dd,
9429                              dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT);
9430         qsfp_mask &= ~mask;
9431         write_csr(dd,
9432                   dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
9433
9434         udelay(10);
9435
9436         qsfp_mask |= mask;
9437         write_csr(dd,
9438                   dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
9439
9440         wait_for_qsfp_init(ppd);
9441
9442         /*
9443          * Allow INT_N to trigger the QSFP interrupt to watch
9444          * for alarms and warnings
9445          */
9446         set_qsfp_int_n(ppd, 1);
9447
9448         /*
9449          * After the reset, AOC transmitters are enabled by default. They need
9450          * to be turned off to complete the QSFP setup before they can be
9451          * enabled again.
9452          */
9453         return set_qsfp_tx(ppd, 0);
9454 }
9455
9456 static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd,
9457                                         u8 *qsfp_interrupt_status)
9458 {
9459         struct hfi1_devdata *dd = ppd->dd;
9460
9461         if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) ||
9462             (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING))
9463                 dd_dev_err(dd, "%s: QSFP cable temperature too high\n",
9464                            __func__);
9465
9466         if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) ||
9467             (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING))
9468                 dd_dev_err(dd, "%s: QSFP cable temperature too low\n",
9469                            __func__);
9470
9471         /*
9472          * The remaining alarms/warnings don't matter if the link is down.
9473          */
9474         if (ppd->host_link_state & HLS_DOWN)
9475                 return 0;
9476
9477         if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) ||
9478             (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING))
9479                 dd_dev_err(dd, "%s: QSFP supply voltage too high\n",
9480                            __func__);
9481
9482         if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) ||
9483             (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING))
9484                 dd_dev_err(dd, "%s: QSFP supply voltage too low\n",
9485                            __func__);
9486
9487         /* Byte 2 is vendor specific */
9488
9489         if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) ||
9490             (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING))
9491                 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too high\n",
9492                            __func__);
9493
9494         if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) ||
9495             (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING))
9496                 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too low\n",
9497                            __func__);
9498
9499         if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) ||
9500             (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING))
9501                 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too high\n",
9502                            __func__);
9503
9504         if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) ||
9505             (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING))
9506                 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too low\n",
9507                            __func__);
9508
9509         if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) ||
9510             (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING))
9511                 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too high\n",
9512                            __func__);
9513
9514         if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) ||
9515             (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING))
9516                 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too low\n",
9517                            __func__);
9518
9519         if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) ||
9520             (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING))
9521                 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too high\n",
9522                            __func__);
9523
9524         if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) ||
9525             (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING))
9526                 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too low\n",
9527                            __func__);
9528
9529         if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) ||
9530             (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING))
9531                 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too high\n",
9532                            __func__);
9533
9534         if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) ||
9535             (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING))
9536                 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too low\n",
9537                            __func__);
9538
9539         if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) ||
9540             (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING))
9541                 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too high\n",
9542                            __func__);
9543
9544         if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) ||
9545             (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING))
9546                 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too low\n",
9547                            __func__);
9548
9549         /* Bytes 9-10 and 11-12 are reserved */
9550         /* Bytes 13-15 are vendor specific */
9551
9552         return 0;
9553 }
9554
9555 /* This routine will only be scheduled if the QSFP module present is asserted */
9556 void qsfp_event(struct work_struct *work)
9557 {
9558         struct qsfp_data *qd;
9559         struct hfi1_pportdata *ppd;
9560         struct hfi1_devdata *dd;
9561
9562         qd = container_of(work, struct qsfp_data, qsfp_work);
9563         ppd = qd->ppd;
9564         dd = ppd->dd;
9565
9566         /* Sanity check */
9567         if (!qsfp_mod_present(ppd))
9568                 return;
9569
9570         if (ppd->host_link_state == HLS_DN_DISABLE) {
9571                 dd_dev_info(ppd->dd,
9572                             "%s: stopping link start because link is disabled\n",
9573                             __func__);
9574                 return;
9575         }
9576
9577         /*
9578          * Turn DC back on after cable has been re-inserted. Up until
9579          * now, the DC has been in reset to save power.
9580          */
9581         dc_start(dd);
9582
9583         if (qd->cache_refresh_required) {
9584                 set_qsfp_int_n(ppd, 0);
9585
9586                 wait_for_qsfp_init(ppd);
9587
9588                 /*
9589                  * Allow INT_N to trigger the QSFP interrupt to watch
9590                  * for alarms and warnings
9591                  */
9592                 set_qsfp_int_n(ppd, 1);
9593
9594                 start_link(ppd);
9595         }
9596
9597         if (qd->check_interrupt_flags) {
9598                 u8 qsfp_interrupt_status[16] = {0,};
9599
9600                 if (one_qsfp_read(ppd, dd->hfi1_id, 6,
9601                                   &qsfp_interrupt_status[0], 16) != 16) {
9602                         dd_dev_info(dd,
9603                                     "%s: Failed to read status of QSFP module\n",
9604                                     __func__);
9605                 } else {
9606                         unsigned long flags;
9607
9608                         handle_qsfp_error_conditions(
9609                                         ppd, qsfp_interrupt_status);
9610                         spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
9611                         ppd->qsfp_info.check_interrupt_flags = 0;
9612                         spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
9613                                                flags);
9614                 }
9615         }
9616 }
9617
9618 static void init_qsfp_int(struct hfi1_devdata *dd)
9619 {
9620         struct hfi1_pportdata *ppd = dd->pport;
9621         u64 qsfp_mask, cce_int_mask;
9622         const int qsfp1_int_smask = QSFP1_INT % 64;
9623         const int qsfp2_int_smask = QSFP2_INT % 64;
9624
9625         /*
9626          * disable QSFP1 interrupts for HFI1, QSFP2 interrupts for HFI0
9627          * Qsfp1Int and Qsfp2Int are adjacent bits in the same CSR,
9628          * therefore just one of QSFP1_INT/QSFP2_INT can be used to find
9629          * the index of the appropriate CSR in the CCEIntMask CSR array
9630          */
9631         cce_int_mask = read_csr(dd, CCE_INT_MASK +
9632                                 (8 * (QSFP1_INT / 64)));
9633         if (dd->hfi1_id) {
9634                 cce_int_mask &= ~((u64)1 << qsfp1_int_smask);
9635                 write_csr(dd, CCE_INT_MASK + (8 * (QSFP1_INT / 64)),
9636                           cce_int_mask);
9637         } else {
9638                 cce_int_mask &= ~((u64)1 << qsfp2_int_smask);
9639                 write_csr(dd, CCE_INT_MASK + (8 * (QSFP2_INT / 64)),
9640                           cce_int_mask);
9641         }
9642
9643         qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
9644         /* Clear current status to avoid spurious interrupts */
9645         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9646                   qsfp_mask);
9647         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
9648                   qsfp_mask);
9649
9650         set_qsfp_int_n(ppd, 0);
9651
9652         /* Handle active low nature of INT_N and MODPRST_N pins */
9653         if (qsfp_mod_present(ppd))
9654                 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N;
9655         write_csr(dd,
9656                   dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT,
9657                   qsfp_mask);
9658 }
9659
9660 /*
9661  * Do a one-time initialize of the LCB block.
9662  */
9663 static void init_lcb(struct hfi1_devdata *dd)
9664 {
9665         /* simulator does not correctly handle LCB cclk loopback, skip */
9666         if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
9667                 return;
9668
9669         /* the DC has been reset earlier in the driver load */
9670
9671         /* set LCB for cclk loopback on the port */
9672         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
9673         write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
9674         write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
9675         write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
9676         write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
9677         write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
9678         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
9679 }
9680
9681 /*
9682  * Perform a test read on the QSFP.  Return 0 on success, -ERRNO
9683  * on error.
9684  */
9685 static int test_qsfp_read(struct hfi1_pportdata *ppd)
9686 {
9687         int ret;
9688         u8 status;
9689
9690         /*
9691          * Report success if not a QSFP or, if it is a QSFP, but the cable is
9692          * not present
9693          */
9694         if (ppd->port_type != PORT_TYPE_QSFP || !qsfp_mod_present(ppd))
9695                 return 0;
9696
9697         /* read byte 2, the status byte */
9698         ret = one_qsfp_read(ppd, ppd->dd->hfi1_id, 2, &status, 1);
9699         if (ret < 0)
9700                 return ret;
9701         if (ret != 1)
9702                 return -EIO;
9703
9704         return 0; /* success */
9705 }
9706
9707 /*
9708  * Values for QSFP retry.
9709  *
9710  * Give up after 10s (20 x 500ms).  The overall timeout was empirically
9711  * arrived at from experience on a large cluster.
9712  */
9713 #define MAX_QSFP_RETRIES 20
9714 #define QSFP_RETRY_WAIT 500 /* msec */
9715
9716 /*
9717  * Try a QSFP read.  If it fails, schedule a retry for later.
9718  * Called on first link activation after driver load.
9719  */
9720 static void try_start_link(struct hfi1_pportdata *ppd)
9721 {
9722         if (test_qsfp_read(ppd)) {
9723                 /* read failed */
9724                 if (ppd->qsfp_retry_count >= MAX_QSFP_RETRIES) {
9725                         dd_dev_err(ppd->dd, "QSFP not responding, giving up\n");
9726                         return;
9727                 }
9728                 dd_dev_info(ppd->dd,
9729                             "QSFP not responding, waiting and retrying %d\n",
9730                             (int)ppd->qsfp_retry_count);
9731                 ppd->qsfp_retry_count++;
9732                 queue_delayed_work(ppd->link_wq, &ppd->start_link_work,
9733                                    msecs_to_jiffies(QSFP_RETRY_WAIT));
9734                 return;
9735         }
9736         ppd->qsfp_retry_count = 0;
9737
9738         start_link(ppd);
9739 }
9740
9741 /*
9742  * Workqueue function to start the link after a delay.
9743  */
9744 void handle_start_link(struct work_struct *work)
9745 {
9746         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
9747                                                   start_link_work.work);
9748         try_start_link(ppd);
9749 }
9750
9751 int bringup_serdes(struct hfi1_pportdata *ppd)
9752 {
9753         struct hfi1_devdata *dd = ppd->dd;
9754         u64 guid;
9755         int ret;
9756
9757         if (HFI1_CAP_IS_KSET(EXTENDED_PSN))
9758                 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK);
9759
9760         guid = ppd->guids[HFI1_PORT_GUID_INDEX];
9761         if (!guid) {
9762                 if (dd->base_guid)
9763                         guid = dd->base_guid + ppd->port - 1;
9764                 ppd->guids[HFI1_PORT_GUID_INDEX] = guid;
9765         }
9766
9767         /* Set linkinit_reason on power up per OPA spec */
9768         ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP;
9769
9770         /* one-time init of the LCB */
9771         init_lcb(dd);
9772
9773         if (loopback) {
9774                 ret = init_loopback(dd);
9775                 if (ret < 0)
9776                         return ret;
9777         }
9778
9779         get_port_type(ppd);
9780         if (ppd->port_type == PORT_TYPE_QSFP) {
9781                 set_qsfp_int_n(ppd, 0);
9782                 wait_for_qsfp_init(ppd);
9783                 set_qsfp_int_n(ppd, 1);
9784         }
9785
9786         try_start_link(ppd);
9787         return 0;
9788 }
9789
9790 void hfi1_quiet_serdes(struct hfi1_pportdata *ppd)
9791 {
9792         struct hfi1_devdata *dd = ppd->dd;
9793
9794         /*
9795          * Shut down the link and keep it down.   First turn off that the
9796          * driver wants to allow the link to be up (driver_link_ready).
9797          * Then make sure the link is not automatically restarted
9798          * (link_enabled).  Cancel any pending restart.  And finally
9799          * go offline.
9800          */
9801         ppd->driver_link_ready = 0;
9802         ppd->link_enabled = 0;
9803
9804         ppd->qsfp_retry_count = MAX_QSFP_RETRIES; /* prevent more retries */
9805         flush_delayed_work(&ppd->start_link_work);
9806         cancel_delayed_work_sync(&ppd->start_link_work);
9807
9808         ppd->offline_disabled_reason =
9809                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_REBOOT);
9810         set_link_down_reason(ppd, OPA_LINKDOWN_REASON_REBOOT, 0,
9811                              OPA_LINKDOWN_REASON_REBOOT);
9812         set_link_state(ppd, HLS_DN_OFFLINE);
9813
9814         /* disable the port */
9815         clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
9816 }
9817
9818 static inline int init_cpu_counters(struct hfi1_devdata *dd)
9819 {
9820         struct hfi1_pportdata *ppd;
9821         int i;
9822
9823         ppd = (struct hfi1_pportdata *)(dd + 1);
9824         for (i = 0; i < dd->num_pports; i++, ppd++) {
9825                 ppd->ibport_data.rvp.rc_acks = NULL;
9826                 ppd->ibport_data.rvp.rc_qacks = NULL;
9827                 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64);
9828                 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64);
9829                 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64);
9830                 if (!ppd->ibport_data.rvp.rc_acks ||
9831                     !ppd->ibport_data.rvp.rc_delayed_comp ||
9832                     !ppd->ibport_data.rvp.rc_qacks)
9833                         return -ENOMEM;
9834         }
9835
9836         return 0;
9837 }
9838
9839 /*
9840  * index is the index into the receive array
9841  */
9842 void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
9843                   u32 type, unsigned long pa, u16 order)
9844 {
9845         u64 reg;
9846
9847         if (!(dd->flags & HFI1_PRESENT))
9848                 goto done;
9849
9850         if (type == PT_INVALID || type == PT_INVALID_FLUSH) {
9851                 pa = 0;
9852                 order = 0;
9853         } else if (type > PT_INVALID) {
9854                 dd_dev_err(dd,
9855                            "unexpected receive array type %u for index %u, not handled\n",
9856                            type, index);
9857                 goto done;
9858         }
9859         trace_hfi1_put_tid(dd, index, type, pa, order);
9860
9861 #define RT_ADDR_SHIFT 12        /* 4KB kernel address boundary */
9862         reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9863                 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT
9864                 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK)
9865                                         << RCV_ARRAY_RT_ADDR_SHIFT;
9866         trace_hfi1_write_rcvarray(dd->rcvarray_wc + (index * 8), reg);
9867         writeq(reg, dd->rcvarray_wc + (index * 8));
9868
9869         if (type == PT_EAGER || type == PT_INVALID_FLUSH || (index & 3) == 3)
9870                 /*
9871                  * Eager entries are written and flushed
9872                  *
9873                  * Expected entries are flushed every 4 writes
9874                  */
9875                 flush_wc();
9876 done:
9877         return;
9878 }
9879
9880 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd)
9881 {
9882         struct hfi1_devdata *dd = rcd->dd;
9883         u32 i;
9884
9885         /* this could be optimized */
9886         for (i = rcd->eager_base; i < rcd->eager_base +
9887                      rcd->egrbufs.alloced; i++)
9888                 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9889
9890         for (i = rcd->expected_base;
9891                         i < rcd->expected_base + rcd->expected_count; i++)
9892                 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9893 }
9894
9895 static const char * const ib_cfg_name_strings[] = {
9896         "HFI1_IB_CFG_LIDLMC",
9897         "HFI1_IB_CFG_LWID_DG_ENB",
9898         "HFI1_IB_CFG_LWID_ENB",
9899         "HFI1_IB_CFG_LWID",
9900         "HFI1_IB_CFG_SPD_ENB",
9901         "HFI1_IB_CFG_SPD",
9902         "HFI1_IB_CFG_RXPOL_ENB",
9903         "HFI1_IB_CFG_LREV_ENB",
9904         "HFI1_IB_CFG_LINKLATENCY",
9905         "HFI1_IB_CFG_HRTBT",
9906         "HFI1_IB_CFG_OP_VLS",
9907         "HFI1_IB_CFG_VL_HIGH_CAP",
9908         "HFI1_IB_CFG_VL_LOW_CAP",
9909         "HFI1_IB_CFG_OVERRUN_THRESH",
9910         "HFI1_IB_CFG_PHYERR_THRESH",
9911         "HFI1_IB_CFG_LINKDEFAULT",
9912         "HFI1_IB_CFG_PKEYS",
9913         "HFI1_IB_CFG_MTU",
9914         "HFI1_IB_CFG_LSTATE",
9915         "HFI1_IB_CFG_VL_HIGH_LIMIT",
9916         "HFI1_IB_CFG_PMA_TICKS",
9917         "HFI1_IB_CFG_PORT"
9918 };
9919
9920 static const char *ib_cfg_name(int which)
9921 {
9922         if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings))
9923                 return "invalid";
9924         return ib_cfg_name_strings[which];
9925 }
9926
9927 int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which)
9928 {
9929         struct hfi1_devdata *dd = ppd->dd;
9930         int val = 0;
9931
9932         switch (which) {
9933         case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */
9934                 val = ppd->link_width_enabled;
9935                 break;
9936         case HFI1_IB_CFG_LWID: /* currently active Link-width */
9937                 val = ppd->link_width_active;
9938                 break;
9939         case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
9940                 val = ppd->link_speed_enabled;
9941                 break;
9942         case HFI1_IB_CFG_SPD: /* current Link speed */
9943                 val = ppd->link_speed_active;
9944                 break;
9945
9946         case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */
9947         case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */
9948         case HFI1_IB_CFG_LINKLATENCY:
9949                 goto unimplemented;
9950
9951         case HFI1_IB_CFG_OP_VLS:
9952                 val = ppd->actual_vls_operational;
9953                 break;
9954         case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */
9955                 val = VL_ARB_HIGH_PRIO_TABLE_SIZE;
9956                 break;
9957         case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */
9958                 val = VL_ARB_LOW_PRIO_TABLE_SIZE;
9959                 break;
9960         case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
9961                 val = ppd->overrun_threshold;
9962                 break;
9963         case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
9964                 val = ppd->phy_error_threshold;
9965                 break;
9966         case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
9967                 val = HLS_DEFAULT;
9968                 break;
9969
9970         case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */
9971         case HFI1_IB_CFG_PMA_TICKS:
9972         default:
9973 unimplemented:
9974                 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
9975                         dd_dev_info(
9976                                 dd,
9977                                 "%s: which %s: not implemented\n",
9978                                 __func__,
9979                                 ib_cfg_name(which));
9980                 break;
9981         }
9982
9983         return val;
9984 }
9985
9986 /*
9987  * The largest MAD packet size.
9988  */
9989 #define MAX_MAD_PACKET 2048
9990
9991 /*
9992  * Return the maximum header bytes that can go on the _wire_
9993  * for this device. This count includes the ICRC which is
9994  * not part of the packet held in memory but it is appended
9995  * by the HW.
9996  * This is dependent on the device's receive header entry size.
9997  * HFI allows this to be set per-receive context, but the
9998  * driver presently enforces a global value.
9999  */
10000 u32 lrh_max_header_bytes(struct hfi1_devdata *dd)
10001 {
10002         /*
10003          * The maximum non-payload (MTU) bytes in LRH.PktLen are
10004          * the Receive Header Entry Size minus the PBC (or RHF) size
10005          * plus one DW for the ICRC appended by HW.
10006          *
10007          * dd->rcd[0].rcvhdrqentsize is in DW.
10008          * We use rcd[0] as all context will have the same value. Also,
10009          * the first kernel context would have been allocated by now so
10010          * we are guaranteed a valid value.
10011          */
10012         return (dd->rcd[0]->rcvhdrqentsize - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2;
10013 }
10014
10015 /*
10016  * Set Send Length
10017  * @ppd - per port data
10018  *
10019  * Set the MTU by limiting how many DWs may be sent.  The SendLenCheck*
10020  * registers compare against LRH.PktLen, so use the max bytes included
10021  * in the LRH.
10022  *
10023  * This routine changes all VL values except VL15, which it maintains at
10024  * the same value.
10025  */
10026 static void set_send_length(struct hfi1_pportdata *ppd)
10027 {
10028         struct hfi1_devdata *dd = ppd->dd;
10029         u32 max_hb = lrh_max_header_bytes(dd), dcmtu;
10030         u32 maxvlmtu = dd->vld[15].mtu;
10031         u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2)
10032                               & SEND_LEN_CHECK1_LEN_VL15_MASK) <<
10033                 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
10034         int i, j;
10035         u32 thres;
10036
10037         for (i = 0; i < ppd->vls_supported; i++) {
10038                 if (dd->vld[i].mtu > maxvlmtu)
10039                         maxvlmtu = dd->vld[i].mtu;
10040                 if (i <= 3)
10041                         len1 |= (((dd->vld[i].mtu + max_hb) >> 2)
10042                                  & SEND_LEN_CHECK0_LEN_VL0_MASK) <<
10043                                 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT);
10044                 else
10045                         len2 |= (((dd->vld[i].mtu + max_hb) >> 2)
10046                                  & SEND_LEN_CHECK1_LEN_VL4_MASK) <<
10047                                 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT);
10048         }
10049         write_csr(dd, SEND_LEN_CHECK0, len1);
10050         write_csr(dd, SEND_LEN_CHECK1, len2);
10051         /* adjust kernel credit return thresholds based on new MTUs */
10052         /* all kernel receive contexts have the same hdrqentsize */
10053         for (i = 0; i < ppd->vls_supported; i++) {
10054                 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50),
10055                             sc_mtu_to_threshold(dd->vld[i].sc,
10056                                                 dd->vld[i].mtu,
10057                                                 dd->rcd[0]->rcvhdrqentsize));
10058                 for (j = 0; j < INIT_SC_PER_VL; j++)
10059                         sc_set_cr_threshold(
10060                                         pio_select_send_context_vl(dd, j, i),
10061                                             thres);
10062         }
10063         thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50),
10064                     sc_mtu_to_threshold(dd->vld[15].sc,
10065                                         dd->vld[15].mtu,
10066                                         dd->rcd[0]->rcvhdrqentsize));
10067         sc_set_cr_threshold(dd->vld[15].sc, thres);
10068
10069         /* Adjust maximum MTU for the port in DC */
10070         dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 :
10071                 (ilog2(maxvlmtu >> 8) + 1);
10072         len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);
10073         len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK;
10074         len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) <<
10075                 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
10076         write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
10077 }
10078
10079 static void set_lidlmc(struct hfi1_pportdata *ppd)
10080 {
10081         int i;
10082         u64 sreg = 0;
10083         struct hfi1_devdata *dd = ppd->dd;
10084         u32 mask = ~((1U << ppd->lmc) - 1);
10085         u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
10086         u32 lid;
10087
10088         /*
10089          * Program 0 in CSR if port lid is extended. This prevents
10090          * 9B packets being sent out for large lids.
10091          */
10092         lid = (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ? 0 : ppd->lid;
10093         c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
10094                 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK);
10095         c1 |= ((lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK)
10096                         << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) |
10097               ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK)
10098                         << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT);
10099         write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
10100
10101         /*
10102          * Iterate over all the send contexts and set their SLID check
10103          */
10104         sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) <<
10105                         SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
10106                (((lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) <<
10107                         SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
10108
10109         for (i = 0; i < dd->chip_send_contexts; i++) {
10110                 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x",
10111                           i, (u32)sreg);
10112                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg);
10113         }
10114
10115         /* Now we have to do the same thing for the sdma engines */
10116         sdma_update_lmc(dd, mask, lid);
10117 }
10118
10119 static const char *state_completed_string(u32 completed)
10120 {
10121         static const char * const state_completed[] = {
10122                 "EstablishComm",
10123                 "OptimizeEQ",
10124                 "VerifyCap"
10125         };
10126
10127         if (completed < ARRAY_SIZE(state_completed))
10128                 return state_completed[completed];
10129
10130         return "unknown";
10131 }
10132
10133 static const char all_lanes_dead_timeout_expired[] =
10134         "All lanes were inactive – was the interconnect media removed?";
10135 static const char tx_out_of_policy[] =
10136         "Passing lanes on local port do not meet the local link width policy";
10137 static const char no_state_complete[] =
10138         "State timeout occurred before link partner completed the state";
10139 static const char * const state_complete_reasons[] = {
10140         [0x00] = "Reason unknown",
10141         [0x01] = "Link was halted by driver, refer to LinkDownReason",
10142         [0x02] = "Link partner reported failure",
10143         [0x10] = "Unable to achieve frame sync on any lane",
10144         [0x11] =
10145           "Unable to find a common bit rate with the link partner",
10146         [0x12] =
10147           "Unable to achieve frame sync on sufficient lanes to meet the local link width policy",
10148         [0x13] =
10149           "Unable to identify preset equalization on sufficient lanes to meet the local link width policy",
10150         [0x14] = no_state_complete,
10151         [0x15] =
10152           "State timeout occurred before link partner identified equalization presets",
10153         [0x16] =
10154           "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy",
10155         [0x17] = tx_out_of_policy,
10156         [0x20] = all_lanes_dead_timeout_expired,
10157         [0x21] =
10158           "Unable to achieve acceptable BER on sufficient lanes to meet the local link width policy",
10159         [0x22] = no_state_complete,
10160         [0x23] =
10161           "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy",
10162         [0x24] = tx_out_of_policy,
10163         [0x30] = all_lanes_dead_timeout_expired,
10164         [0x31] =
10165           "State timeout occurred waiting for host to process received frames",
10166         [0x32] = no_state_complete,
10167         [0x33] =
10168           "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy",
10169         [0x34] = tx_out_of_policy,
10170         [0x35] = "Negotiated link width is mutually exclusive",
10171         [0x36] =
10172           "Timed out before receiving verifycap frames in VerifyCap.Exchange",
10173         [0x37] = "Unable to resolve secure data exchange",
10174 };
10175
10176 static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd,
10177                                                      u32 code)
10178 {
10179         const char *str = NULL;
10180
10181         if (code < ARRAY_SIZE(state_complete_reasons))
10182                 str = state_complete_reasons[code];
10183
10184         if (str)
10185                 return str;
10186         return "Reserved";
10187 }
10188
10189 /* describe the given last state complete frame */
10190 static void decode_state_complete(struct hfi1_pportdata *ppd, u32 frame,
10191                                   const char *prefix)
10192 {
10193         struct hfi1_devdata *dd = ppd->dd;
10194         u32 success;
10195         u32 state;
10196         u32 reason;
10197         u32 lanes;
10198
10199         /*
10200          * Decode frame:
10201          *  [ 0: 0] - success
10202          *  [ 3: 1] - state
10203          *  [ 7: 4] - next state timeout
10204          *  [15: 8] - reason code
10205          *  [31:16] - lanes
10206          */
10207         success = frame & 0x1;
10208         state = (frame >> 1) & 0x7;
10209         reason = (frame >> 8) & 0xff;
10210         lanes = (frame >> 16) & 0xffff;
10211
10212         dd_dev_err(dd, "Last %s LNI state complete frame 0x%08x:\n",
10213                    prefix, frame);
10214         dd_dev_err(dd, "    last reported state state: %s (0x%x)\n",
10215                    state_completed_string(state), state);
10216         dd_dev_err(dd, "    state successfully completed: %s\n",
10217                    success ? "yes" : "no");
10218         dd_dev_err(dd, "    fail reason 0x%x: %s\n",
10219                    reason, state_complete_reason_code_string(ppd, reason));
10220         dd_dev_err(dd, "    passing lane mask: 0x%x", lanes);
10221 }
10222
10223 /*
10224  * Read the last state complete frames and explain them.  This routine
10225  * expects to be called if the link went down during link negotiation
10226  * and initialization (LNI).  That is, anywhere between polling and link up.
10227  */
10228 static void check_lni_states(struct hfi1_pportdata *ppd)
10229 {
10230         u32 last_local_state;
10231         u32 last_remote_state;
10232
10233         read_last_local_state(ppd->dd, &last_local_state);
10234         read_last_remote_state(ppd->dd, &last_remote_state);
10235
10236         /*
10237          * Don't report anything if there is nothing to report.  A value of
10238          * 0 means the link was taken down while polling and there was no
10239          * training in-process.
10240          */
10241         if (last_local_state == 0 && last_remote_state == 0)
10242                 return;
10243
10244         decode_state_complete(ppd, last_local_state, "transmitted");
10245         decode_state_complete(ppd, last_remote_state, "received");
10246 }
10247
10248 /* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */
10249 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms)
10250 {
10251         u64 reg;
10252         unsigned long timeout;
10253
10254         /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
10255         timeout = jiffies + msecs_to_jiffies(wait_ms);
10256         while (1) {
10257                 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE);
10258                 if (reg)
10259                         break;
10260                 if (time_after(jiffies, timeout)) {
10261                         dd_dev_err(dd,
10262                                    "timeout waiting for LINK_TRANSFER_ACTIVE\n");
10263                         return -ETIMEDOUT;
10264                 }
10265                 udelay(2);
10266         }
10267         return 0;
10268 }
10269
10270 /* called when the logical link state is not down as it should be */
10271 static void force_logical_link_state_down(struct hfi1_pportdata *ppd)
10272 {
10273         struct hfi1_devdata *dd = ppd->dd;
10274
10275         /*
10276          * Bring link up in LCB loopback
10277          */
10278         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10279         write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
10280                   DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
10281
10282         write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
10283         write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0);
10284         write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
10285         write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2);
10286
10287         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
10288         (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET);
10289         udelay(3);
10290         write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1);
10291         write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
10292
10293         wait_link_transfer_active(dd, 100);
10294
10295         /*
10296          * Bring the link down again.
10297          */
10298         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10299         write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0);
10300         write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0);
10301
10302         dd_dev_info(ppd->dd, "logical state forced to LINK_DOWN\n");
10303 }
10304
10305 /*
10306  * Helper for set_link_state().  Do not call except from that routine.
10307  * Expects ppd->hls_mutex to be held.
10308  *
10309  * @rem_reason value to be sent to the neighbor
10310  *
10311  * LinkDownReasons only set if transition succeeds.
10312  */
10313 static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason)
10314 {
10315         struct hfi1_devdata *dd = ppd->dd;
10316         u32 previous_state;
10317         int offline_state_ret;
10318         int ret;
10319
10320         update_lcb_cache(dd);
10321
10322         previous_state = ppd->host_link_state;
10323         ppd->host_link_state = HLS_GOING_OFFLINE;
10324
10325         /* start offline transition */
10326         ret = set_physical_link_state(dd, (rem_reason << 8) | PLS_OFFLINE);
10327
10328         if (ret != HCMD_SUCCESS) {
10329                 dd_dev_err(dd,
10330                            "Failed to transition to Offline link state, return %d\n",
10331                            ret);
10332                 return -EINVAL;
10333         }
10334         if (ppd->offline_disabled_reason ==
10335                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))
10336                 ppd->offline_disabled_reason =
10337                 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
10338
10339         offline_state_ret = wait_phys_link_offline_substates(ppd, 10000);
10340         if (offline_state_ret < 0)
10341                 return offline_state_ret;
10342
10343         /* Disabling AOC transmitters */
10344         if (ppd->port_type == PORT_TYPE_QSFP &&
10345             ppd->qsfp_info.limiting_active &&
10346             qsfp_mod_present(ppd)) {
10347                 int ret;
10348
10349                 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT);
10350                 if (ret == 0) {
10351                         set_qsfp_tx(ppd, 0);
10352                         release_chip_resource(dd, qsfp_resource(dd));
10353                 } else {
10354                         /* not fatal, but should warn */
10355                         dd_dev_err(dd,
10356                                    "Unable to acquire lock to turn off QSFP TX\n");
10357                 }
10358         }
10359
10360         /*
10361          * Wait for the offline.Quiet transition if it hasn't happened yet. It
10362          * can take a while for the link to go down.
10363          */
10364         if (offline_state_ret != PLS_OFFLINE_QUIET) {
10365                 ret = wait_physical_linkstate(ppd, PLS_OFFLINE, 30000);
10366                 if (ret < 0)
10367                         return ret;
10368         }
10369
10370         /*
10371          * Now in charge of LCB - must be after the physical state is
10372          * offline.quiet and before host_link_state is changed.
10373          */
10374         set_host_lcb_access(dd);
10375         write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
10376
10377         /* make sure the logical state is also down */
10378         ret = wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000);
10379         if (ret)
10380                 force_logical_link_state_down(ppd);
10381
10382         ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */
10383         update_statusp(ppd, IB_PORT_DOWN);
10384
10385         /*
10386          * The LNI has a mandatory wait time after the physical state
10387          * moves to Offline.Quiet.  The wait time may be different
10388          * depending on how the link went down.  The 8051 firmware
10389          * will observe the needed wait time and only move to ready
10390          * when that is completed.  The largest of the quiet timeouts
10391          * is 6s, so wait that long and then at least 0.5s more for
10392          * other transitions, and another 0.5s for a buffer.
10393          */
10394         ret = wait_fm_ready(dd, 7000);
10395         if (ret) {
10396                 dd_dev_err(dd,
10397                            "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
10398                 /* state is really offline, so make it so */
10399                 ppd->host_link_state = HLS_DN_OFFLINE;
10400                 return ret;
10401         }
10402
10403         /*
10404          * The state is now offline and the 8051 is ready to accept host
10405          * requests.
10406          *      - change our state
10407          *      - notify others if we were previously in a linkup state
10408          */
10409         ppd->host_link_state = HLS_DN_OFFLINE;
10410         if (previous_state & HLS_UP) {
10411                 /* went down while link was up */
10412                 handle_linkup_change(dd, 0);
10413         } else if (previous_state
10414                         & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
10415                 /* went down while attempting link up */
10416                 check_lni_states(ppd);
10417
10418                 /* The QSFP doesn't need to be reset on LNI failure */
10419                 ppd->qsfp_info.reset_needed = 0;
10420         }
10421
10422         /* the active link width (downgrade) is 0 on link down */
10423         ppd->link_width_active = 0;
10424         ppd->link_width_downgrade_tx_active = 0;
10425         ppd->link_width_downgrade_rx_active = 0;
10426         ppd->current_egress_rate = 0;
10427         return 0;
10428 }
10429
10430 /* return the link state name */
10431 static const char *link_state_name(u32 state)
10432 {
10433         const char *name;
10434         int n = ilog2(state);
10435         static const char * const names[] = {
10436                 [__HLS_UP_INIT_BP]       = "INIT",
10437                 [__HLS_UP_ARMED_BP]      = "ARMED",
10438                 [__HLS_UP_ACTIVE_BP]     = "ACTIVE",
10439                 [__HLS_DN_DOWNDEF_BP]    = "DOWNDEF",
10440                 [__HLS_DN_POLL_BP]       = "POLL",
10441                 [__HLS_DN_DISABLE_BP]    = "DISABLE",
10442                 [__HLS_DN_OFFLINE_BP]    = "OFFLINE",
10443                 [__HLS_VERIFY_CAP_BP]    = "VERIFY_CAP",
10444                 [__HLS_GOING_UP_BP]      = "GOING_UP",
10445                 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE",
10446                 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN"
10447         };
10448
10449         name = n < ARRAY_SIZE(names) ? names[n] : NULL;
10450         return name ? name : "unknown";
10451 }
10452
10453 /* return the link state reason name */
10454 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state)
10455 {
10456         if (state == HLS_UP_INIT) {
10457                 switch (ppd->linkinit_reason) {
10458                 case OPA_LINKINIT_REASON_LINKUP:
10459                         return "(LINKUP)";
10460                 case OPA_LINKINIT_REASON_FLAPPING:
10461                         return "(FLAPPING)";
10462                 case OPA_LINKINIT_OUTSIDE_POLICY:
10463                         return "(OUTSIDE_POLICY)";
10464                 case OPA_LINKINIT_QUARANTINED:
10465                         return "(QUARANTINED)";
10466                 case OPA_LINKINIT_INSUFIC_CAPABILITY:
10467                         return "(INSUFIC_CAPABILITY)";
10468                 default:
10469                         break;
10470                 }
10471         }
10472         return "";
10473 }
10474
10475 /*
10476  * driver_pstate - convert the driver's notion of a port's
10477  * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
10478  * Return -1 (converted to a u32) to indicate error.
10479  */
10480 u32 driver_pstate(struct hfi1_pportdata *ppd)
10481 {
10482         switch (ppd->host_link_state) {
10483         case HLS_UP_INIT:
10484         case HLS_UP_ARMED:
10485         case HLS_UP_ACTIVE:
10486                 return IB_PORTPHYSSTATE_LINKUP;
10487         case HLS_DN_POLL:
10488                 return IB_PORTPHYSSTATE_POLLING;
10489         case HLS_DN_DISABLE:
10490                 return IB_PORTPHYSSTATE_DISABLED;
10491         case HLS_DN_OFFLINE:
10492                 return OPA_PORTPHYSSTATE_OFFLINE;
10493         case HLS_VERIFY_CAP:
10494                 return IB_PORTPHYSSTATE_POLLING;
10495         case HLS_GOING_UP:
10496                 return IB_PORTPHYSSTATE_POLLING;
10497         case HLS_GOING_OFFLINE:
10498                 return OPA_PORTPHYSSTATE_OFFLINE;
10499         case HLS_LINK_COOLDOWN:
10500                 return OPA_PORTPHYSSTATE_OFFLINE;
10501         case HLS_DN_DOWNDEF:
10502         default:
10503                 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10504                            ppd->host_link_state);
10505                 return  -1;
10506         }
10507 }
10508
10509 /*
10510  * driver_lstate - convert the driver's notion of a port's
10511  * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
10512  * (converted to a u32) to indicate error.
10513  */
10514 u32 driver_lstate(struct hfi1_pportdata *ppd)
10515 {
10516         if (ppd->host_link_state && (ppd->host_link_state & HLS_DOWN))
10517                 return IB_PORT_DOWN;
10518
10519         switch (ppd->host_link_state & HLS_UP) {
10520         case HLS_UP_INIT:
10521                 return IB_PORT_INIT;
10522         case HLS_UP_ARMED:
10523                 return IB_PORT_ARMED;
10524         case HLS_UP_ACTIVE:
10525                 return IB_PORT_ACTIVE;
10526         default:
10527                 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10528                            ppd->host_link_state);
10529         return -1;
10530         }
10531 }
10532
10533 void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
10534                           u8 neigh_reason, u8 rem_reason)
10535 {
10536         if (ppd->local_link_down_reason.latest == 0 &&
10537             ppd->neigh_link_down_reason.latest == 0) {
10538                 ppd->local_link_down_reason.latest = lcl_reason;
10539                 ppd->neigh_link_down_reason.latest = neigh_reason;
10540                 ppd->remote_link_down_reason = rem_reason;
10541         }
10542 }
10543
10544 /*
10545  * Verify if BCT for data VLs is non-zero.
10546  */
10547 static inline bool data_vls_operational(struct hfi1_pportdata *ppd)
10548 {
10549         return !!ppd->actual_vls_operational;
10550 }
10551
10552 /*
10553  * Change the physical and/or logical link state.
10554  *
10555  * Do not call this routine while inside an interrupt.  It contains
10556  * calls to routines that can take multiple seconds to finish.
10557  *
10558  * Returns 0 on success, -errno on failure.
10559  */
10560 int set_link_state(struct hfi1_pportdata *ppd, u32 state)
10561 {
10562         struct hfi1_devdata *dd = ppd->dd;
10563         struct ib_event event = {.device = NULL};
10564         int ret1, ret = 0;
10565         int orig_new_state, poll_bounce;
10566
10567         mutex_lock(&ppd->hls_lock);
10568
10569         orig_new_state = state;
10570         if (state == HLS_DN_DOWNDEF)
10571                 state = HLS_DEFAULT;
10572
10573         /* interpret poll -> poll as a link bounce */
10574         poll_bounce = ppd->host_link_state == HLS_DN_POLL &&
10575                       state == HLS_DN_POLL;
10576
10577         dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__,
10578                     link_state_name(ppd->host_link_state),
10579                     link_state_name(orig_new_state),
10580                     poll_bounce ? "(bounce) " : "",
10581                     link_state_reason_name(ppd, state));
10582
10583         /*
10584          * If we're going to a (HLS_*) link state that implies the logical
10585          * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10586          * reset is_sm_config_started to 0.
10587          */
10588         if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE)))
10589                 ppd->is_sm_config_started = 0;
10590
10591         /*
10592          * Do nothing if the states match.  Let a poll to poll link bounce
10593          * go through.
10594          */
10595         if (ppd->host_link_state == state && !poll_bounce)
10596                 goto done;
10597
10598         switch (state) {
10599         case HLS_UP_INIT:
10600                 if (ppd->host_link_state == HLS_DN_POLL &&
10601                     (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) {
10602                         /*
10603                          * Quick link up jumps from polling to here.
10604                          *
10605                          * Whether in normal or loopback mode, the
10606                          * simulator jumps from polling to link up.
10607                          * Accept that here.
10608                          */
10609                         /* OK */
10610                 } else if (ppd->host_link_state != HLS_GOING_UP) {
10611                         goto unexpected;
10612                 }
10613
10614                 /*
10615                  * Wait for Link_Up physical state.
10616                  * Physical and Logical states should already be
10617                  * be transitioned to LinkUp and LinkInit respectively.
10618                  */
10619                 ret = wait_physical_linkstate(ppd, PLS_LINKUP, 1000);
10620                 if (ret) {
10621                         dd_dev_err(dd,
10622                                    "%s: physical state did not change to LINK-UP\n",
10623                                    __func__);
10624                         break;
10625                 }
10626
10627                 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000);
10628                 if (ret) {
10629                         dd_dev_err(dd,
10630                                    "%s: logical state did not change to INIT\n",
10631                                    __func__);
10632                         break;
10633                 }
10634
10635                 /* clear old transient LINKINIT_REASON code */
10636                 if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR)
10637                         ppd->linkinit_reason =
10638                                 OPA_LINKINIT_REASON_LINKUP;
10639
10640                 /* enable the port */
10641                 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
10642
10643                 handle_linkup_change(dd, 1);
10644
10645                 /*
10646                  * After link up, a new link width will have been set.
10647                  * Update the xmit counters with regards to the new
10648                  * link width.
10649                  */
10650                 update_xmit_counters(ppd, ppd->link_width_active);
10651
10652                 ppd->host_link_state = HLS_UP_INIT;
10653                 update_statusp(ppd, IB_PORT_INIT);
10654                 break;
10655         case HLS_UP_ARMED:
10656                 if (ppd->host_link_state != HLS_UP_INIT)
10657                         goto unexpected;
10658
10659                 if (!data_vls_operational(ppd)) {
10660                         dd_dev_err(dd,
10661                                    "%s: data VLs not operational\n", __func__);
10662                         ret = -EINVAL;
10663                         break;
10664                 }
10665
10666                 set_logical_state(dd, LSTATE_ARMED);
10667                 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000);
10668                 if (ret) {
10669                         dd_dev_err(dd,
10670                                    "%s: logical state did not change to ARMED\n",
10671                                    __func__);
10672                         break;
10673                 }
10674                 ppd->host_link_state = HLS_UP_ARMED;
10675                 update_statusp(ppd, IB_PORT_ARMED);
10676                 /*
10677                  * The simulator does not currently implement SMA messages,
10678                  * so neighbor_normal is not set.  Set it here when we first
10679                  * move to Armed.
10680                  */
10681                 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
10682                         ppd->neighbor_normal = 1;
10683                 break;
10684         case HLS_UP_ACTIVE:
10685                 if (ppd->host_link_state != HLS_UP_ARMED)
10686                         goto unexpected;
10687
10688                 set_logical_state(dd, LSTATE_ACTIVE);
10689                 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000);
10690                 if (ret) {
10691                         dd_dev_err(dd,
10692                                    "%s: logical state did not change to ACTIVE\n",
10693                                    __func__);
10694                 } else {
10695                         /* tell all engines to go running */
10696                         sdma_all_running(dd);
10697                         ppd->host_link_state = HLS_UP_ACTIVE;
10698                         update_statusp(ppd, IB_PORT_ACTIVE);
10699
10700                         /* Signal the IB layer that the port has went active */
10701                         event.device = &dd->verbs_dev.rdi.ibdev;
10702                         event.element.port_num = ppd->port;
10703                         event.event = IB_EVENT_PORT_ACTIVE;
10704                 }
10705                 break;
10706         case HLS_DN_POLL:
10707                 if ((ppd->host_link_state == HLS_DN_DISABLE ||
10708                      ppd->host_link_state == HLS_DN_OFFLINE) &&
10709                     dd->dc_shutdown)
10710                         dc_start(dd);
10711                 /* Hand LED control to the DC */
10712                 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
10713
10714                 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10715                         u8 tmp = ppd->link_enabled;
10716
10717                         ret = goto_offline(ppd, ppd->remote_link_down_reason);
10718                         if (ret) {
10719                                 ppd->link_enabled = tmp;
10720                                 break;
10721                         }
10722                         ppd->remote_link_down_reason = 0;
10723
10724                         if (ppd->driver_link_ready)
10725                                 ppd->link_enabled = 1;
10726                 }
10727
10728                 set_all_slowpath(ppd->dd);
10729                 ret = set_local_link_attributes(ppd);
10730                 if (ret)
10731                         break;
10732
10733                 ppd->port_error_action = 0;
10734                 ppd->host_link_state = HLS_DN_POLL;
10735
10736                 if (quick_linkup) {
10737                         /* quick linkup does not go into polling */
10738                         ret = do_quick_linkup(dd);
10739                 } else {
10740                         ret1 = set_physical_link_state(dd, PLS_POLLING);
10741                         if (ret1 != HCMD_SUCCESS) {
10742                                 dd_dev_err(dd,
10743                                            "Failed to transition to Polling link state, return 0x%x\n",
10744                                            ret1);
10745                                 ret = -EINVAL;
10746                         }
10747                 }
10748                 ppd->offline_disabled_reason =
10749                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE);
10750                 /*
10751                  * If an error occurred above, go back to offline.  The
10752                  * caller may reschedule another attempt.
10753                  */
10754                 if (ret)
10755                         goto_offline(ppd, 0);
10756                 else
10757                         log_physical_state(ppd, PLS_POLLING);
10758                 break;
10759         case HLS_DN_DISABLE:
10760                 /* link is disabled */
10761                 ppd->link_enabled = 0;
10762
10763                 /* allow any state to transition to disabled */
10764
10765                 /* must transition to offline first */
10766                 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10767                         ret = goto_offline(ppd, ppd->remote_link_down_reason);
10768                         if (ret)
10769                                 break;
10770                         ppd->remote_link_down_reason = 0;
10771                 }
10772
10773                 if (!dd->dc_shutdown) {
10774                         ret1 = set_physical_link_state(dd, PLS_DISABLED);
10775                         if (ret1 != HCMD_SUCCESS) {
10776                                 dd_dev_err(dd,
10777                                            "Failed to transition to Disabled link state, return 0x%x\n",
10778                                            ret1);
10779                                 ret = -EINVAL;
10780                                 break;
10781                         }
10782                         ret = wait_physical_linkstate(ppd, PLS_DISABLED, 10000);
10783                         if (ret) {
10784                                 dd_dev_err(dd,
10785                                            "%s: physical state did not change to DISABLED\n",
10786                                            __func__);
10787                                 break;
10788                         }
10789                         dc_shutdown(dd);
10790                 }
10791                 ppd->host_link_state = HLS_DN_DISABLE;
10792                 break;
10793         case HLS_DN_OFFLINE:
10794                 if (ppd->host_link_state == HLS_DN_DISABLE)
10795                         dc_start(dd);
10796
10797                 /* allow any state to transition to offline */
10798                 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10799                 if (!ret)
10800                         ppd->remote_link_down_reason = 0;
10801                 break;
10802         case HLS_VERIFY_CAP:
10803                 if (ppd->host_link_state != HLS_DN_POLL)
10804                         goto unexpected;
10805                 ppd->host_link_state = HLS_VERIFY_CAP;
10806                 log_physical_state(ppd, PLS_CONFIGPHY_VERIFYCAP);
10807                 break;
10808         case HLS_GOING_UP:
10809                 if (ppd->host_link_state != HLS_VERIFY_CAP)
10810                         goto unexpected;
10811
10812                 ret1 = set_physical_link_state(dd, PLS_LINKUP);
10813                 if (ret1 != HCMD_SUCCESS) {
10814                         dd_dev_err(dd,
10815                                    "Failed to transition to link up state, return 0x%x\n",
10816                                    ret1);
10817                         ret = -EINVAL;
10818                         break;
10819                 }
10820                 ppd->host_link_state = HLS_GOING_UP;
10821                 break;
10822
10823         case HLS_GOING_OFFLINE:         /* transient within goto_offline() */
10824         case HLS_LINK_COOLDOWN:         /* transient within goto_offline() */
10825         default:
10826                 dd_dev_info(dd, "%s: state 0x%x: not supported\n",
10827                             __func__, state);
10828                 ret = -EINVAL;
10829                 break;
10830         }
10831
10832         goto done;
10833
10834 unexpected:
10835         dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n",
10836                    __func__, link_state_name(ppd->host_link_state),
10837                    link_state_name(state));
10838         ret = -EINVAL;
10839
10840 done:
10841         mutex_unlock(&ppd->hls_lock);
10842
10843         if (event.device)
10844                 ib_dispatch_event(&event);
10845
10846         return ret;
10847 }
10848
10849 int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val)
10850 {
10851         u64 reg;
10852         int ret = 0;
10853
10854         switch (which) {
10855         case HFI1_IB_CFG_LIDLMC:
10856                 set_lidlmc(ppd);
10857                 break;
10858         case HFI1_IB_CFG_VL_HIGH_LIMIT:
10859                 /*
10860                  * The VL Arbitrator high limit is sent in units of 4k
10861                  * bytes, while HFI stores it in units of 64 bytes.
10862                  */
10863                 val *= 4096 / 64;
10864                 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK)
10865                         << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT;
10866                 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
10867                 break;
10868         case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
10869                 /* HFI only supports POLL as the default link down state */
10870                 if (val != HLS_DN_POLL)
10871                         ret = -EINVAL;
10872                 break;
10873         case HFI1_IB_CFG_OP_VLS:
10874                 if (ppd->vls_operational != val) {
10875                         ppd->vls_operational = val;
10876                         if (!ppd->port)
10877                                 ret = -EINVAL;
10878                 }
10879                 break;
10880         /*
10881          * For link width, link width downgrade, and speed enable, always AND
10882          * the setting with what is actually supported.  This has two benefits.
10883          * First, enabled can't have unsupported values, no matter what the
10884          * SM or FM might want.  Second, the ALL_SUPPORTED wildcards that mean
10885          * "fill in with your supported value" have all the bits in the
10886          * field set, so simply ANDing with supported has the desired result.
10887          */
10888         case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */
10889                 ppd->link_width_enabled = val & ppd->link_width_supported;
10890                 break;
10891         case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */
10892                 ppd->link_width_downgrade_enabled =
10893                                 val & ppd->link_width_downgrade_supported;
10894                 break;
10895         case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
10896                 ppd->link_speed_enabled = val & ppd->link_speed_supported;
10897                 break;
10898         case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
10899                 /*
10900                  * HFI does not follow IB specs, save this value
10901                  * so we can report it, if asked.
10902                  */
10903                 ppd->overrun_threshold = val;
10904                 break;
10905         case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
10906                 /*
10907                  * HFI does not follow IB specs, save this value
10908                  * so we can report it, if asked.
10909                  */
10910                 ppd->phy_error_threshold = val;
10911                 break;
10912
10913         case HFI1_IB_CFG_MTU:
10914                 set_send_length(ppd);
10915                 break;
10916
10917         case HFI1_IB_CFG_PKEYS:
10918                 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
10919                         set_partition_keys(ppd);
10920                 break;
10921
10922         default:
10923                 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
10924                         dd_dev_info(ppd->dd,
10925                                     "%s: which %s, val 0x%x: not implemented\n",
10926                                     __func__, ib_cfg_name(which), val);
10927                 break;
10928         }
10929         return ret;
10930 }
10931
10932 /* begin functions related to vl arbitration table caching */
10933 static void init_vl_arb_caches(struct hfi1_pportdata *ppd)
10934 {
10935         int i;
10936
10937         BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10938                         VL_ARB_LOW_PRIO_TABLE_SIZE);
10939         BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10940                         VL_ARB_HIGH_PRIO_TABLE_SIZE);
10941
10942         /*
10943          * Note that we always return values directly from the
10944          * 'vl_arb_cache' (and do no CSR reads) in response to a
10945          * 'Get(VLArbTable)'. This is obviously correct after a
10946          * 'Set(VLArbTable)', since the cache will then be up to
10947          * date. But it's also correct prior to any 'Set(VLArbTable)'
10948          * since then both the cache, and the relevant h/w registers
10949          * will be zeroed.
10950          */
10951
10952         for (i = 0; i < MAX_PRIO_TABLE; i++)
10953                 spin_lock_init(&ppd->vl_arb_cache[i].lock);
10954 }
10955
10956 /*
10957  * vl_arb_lock_cache
10958  *
10959  * All other vl_arb_* functions should be called only after locking
10960  * the cache.
10961  */
10962 static inline struct vl_arb_cache *
10963 vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx)
10964 {
10965         if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE)
10966                 return NULL;
10967         spin_lock(&ppd->vl_arb_cache[idx].lock);
10968         return &ppd->vl_arb_cache[idx];
10969 }
10970
10971 static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx)
10972 {
10973         spin_unlock(&ppd->vl_arb_cache[idx].lock);
10974 }
10975
10976 static void vl_arb_get_cache(struct vl_arb_cache *cache,
10977                              struct ib_vl_weight_elem *vl)
10978 {
10979         memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl));
10980 }
10981
10982 static void vl_arb_set_cache(struct vl_arb_cache *cache,
10983                              struct ib_vl_weight_elem *vl)
10984 {
10985         memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10986 }
10987
10988 static int vl_arb_match_cache(struct vl_arb_cache *cache,
10989                               struct ib_vl_weight_elem *vl)
10990 {
10991         return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10992 }
10993
10994 /* end functions related to vl arbitration table caching */
10995
10996 static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target,
10997                           u32 size, struct ib_vl_weight_elem *vl)
10998 {
10999         struct hfi1_devdata *dd = ppd->dd;
11000         u64 reg;
11001         unsigned int i, is_up = 0;
11002         int drain, ret = 0;
11003
11004         mutex_lock(&ppd->hls_lock);
11005
11006         if (ppd->host_link_state & HLS_UP)
11007                 is_up = 1;
11008
11009         drain = !is_ax(dd) && is_up;
11010
11011         if (drain)
11012                 /*
11013                  * Before adjusting VL arbitration weights, empty per-VL
11014                  * FIFOs, otherwise a packet whose VL weight is being
11015                  * set to 0 could get stuck in a FIFO with no chance to
11016                  * egress.
11017                  */
11018                 ret = stop_drain_data_vls(dd);
11019
11020         if (ret) {
11021                 dd_dev_err(
11022                         dd,
11023                         "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n",
11024                         __func__);
11025                 goto err;
11026         }
11027
11028         for (i = 0; i < size; i++, vl++) {
11029                 /*
11030                  * NOTE: The low priority shift and mask are used here, but
11031                  * they are the same for both the low and high registers.
11032                  */
11033                 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK)
11034                                 << SEND_LOW_PRIORITY_LIST_VL_SHIFT)
11035                       | (((u64)vl->weight
11036                                 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK)
11037                                 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT);
11038                 write_csr(dd, target + (i * 8), reg);
11039         }
11040         pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE);
11041
11042         if (drain)
11043                 open_fill_data_vls(dd); /* reopen all VLs */
11044
11045 err:
11046         mutex_unlock(&ppd->hls_lock);
11047
11048         return ret;
11049 }
11050
11051 /*
11052  * Read one credit merge VL register.
11053  */
11054 static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr,
11055                            struct vl_limit *vll)
11056 {
11057         u64 reg = read_csr(dd, csr);
11058
11059         vll->dedicated = cpu_to_be16(
11060                 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT)
11061                 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK);
11062         vll->shared = cpu_to_be16(
11063                 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT)
11064                 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK);
11065 }
11066
11067 /*
11068  * Read the current credit merge limits.
11069  */
11070 static int get_buffer_control(struct hfi1_devdata *dd,
11071                               struct buffer_control *bc, u16 *overall_limit)
11072 {
11073         u64 reg;
11074         int i;
11075
11076         /* not all entries are filled in */
11077         memset(bc, 0, sizeof(*bc));
11078
11079         /* OPA and HFI have a 1-1 mapping */
11080         for (i = 0; i < TXE_NUM_DATA_VL; i++)
11081                 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]);
11082
11083         /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
11084         read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]);
11085
11086         reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11087         bc->overall_shared_limit = cpu_to_be16(
11088                 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT)
11089                 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK);
11090         if (overall_limit)
11091                 *overall_limit = (reg
11092                         >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT)
11093                         & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK;
11094         return sizeof(struct buffer_control);
11095 }
11096
11097 static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
11098 {
11099         u64 reg;
11100         int i;
11101
11102         /* each register contains 16 SC->VLnt mappings, 4 bits each */
11103         reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);
11104         for (i = 0; i < sizeof(u64); i++) {
11105                 u8 byte = *(((u8 *)&reg) + i);
11106
11107                 dp->vlnt[2 * i] = byte & 0xf;
11108                 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4;
11109         }
11110
11111         reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);
11112         for (i = 0; i < sizeof(u64); i++) {
11113                 u8 byte = *(((u8 *)&reg) + i);
11114
11115                 dp->vlnt[16 + (2 * i)] = byte & 0xf;
11116                 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4;
11117         }
11118         return sizeof(struct sc2vlnt);
11119 }
11120
11121 static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems,
11122                               struct ib_vl_weight_elem *vl)
11123 {
11124         unsigned int i;
11125
11126         for (i = 0; i < nelems; i++, vl++) {
11127                 vl->vl = 0xf;
11128                 vl->weight = 0;
11129         }
11130 }
11131
11132 static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
11133 {
11134         write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
11135                   DC_SC_VL_VAL(15_0,
11136                                0, dp->vlnt[0] & 0xf,
11137                                1, dp->vlnt[1] & 0xf,
11138                                2, dp->vlnt[2] & 0xf,
11139                                3, dp->vlnt[3] & 0xf,
11140                                4, dp->vlnt[4] & 0xf,
11141                                5, dp->vlnt[5] & 0xf,
11142                                6, dp->vlnt[6] & 0xf,
11143                                7, dp->vlnt[7] & 0xf,
11144                                8, dp->vlnt[8] & 0xf,
11145                                9, dp->vlnt[9] & 0xf,
11146                                10, dp->vlnt[10] & 0xf,
11147                                11, dp->vlnt[11] & 0xf,
11148                                12, dp->vlnt[12] & 0xf,
11149                                13, dp->vlnt[13] & 0xf,
11150                                14, dp->vlnt[14] & 0xf,
11151                                15, dp->vlnt[15] & 0xf));
11152         write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
11153                   DC_SC_VL_VAL(31_16,
11154                                16, dp->vlnt[16] & 0xf,
11155                                17, dp->vlnt[17] & 0xf,
11156                                18, dp->vlnt[18] & 0xf,
11157                                19, dp->vlnt[19] & 0xf,
11158                                20, dp->vlnt[20] & 0xf,
11159                                21, dp->vlnt[21] & 0xf,
11160                                22, dp->vlnt[22] & 0xf,
11161                                23, dp->vlnt[23] & 0xf,
11162                                24, dp->vlnt[24] & 0xf,
11163                                25, dp->vlnt[25] & 0xf,
11164                                26, dp->vlnt[26] & 0xf,
11165                                27, dp->vlnt[27] & 0xf,
11166                                28, dp->vlnt[28] & 0xf,
11167                                29, dp->vlnt[29] & 0xf,
11168                                30, dp->vlnt[30] & 0xf,
11169                                31, dp->vlnt[31] & 0xf));
11170 }
11171
11172 static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what,
11173                         u16 limit)
11174 {
11175         if (limit != 0)
11176                 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n",
11177                             what, (int)limit, idx);
11178 }
11179
11180 /* change only the shared limit portion of SendCmGLobalCredit */
11181 static void set_global_shared(struct hfi1_devdata *dd, u16 limit)
11182 {
11183         u64 reg;
11184
11185         reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11186         reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK;
11187         reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT;
11188         write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11189 }
11190
11191 /* change only the total credit limit portion of SendCmGLobalCredit */
11192 static void set_global_limit(struct hfi1_devdata *dd, u16 limit)
11193 {
11194         u64 reg;
11195
11196         reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11197         reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK;
11198         reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
11199         write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11200 }
11201
11202 /* set the given per-VL shared limit */
11203 static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit)
11204 {
11205         u64 reg;
11206         u32 addr;
11207
11208         if (vl < TXE_NUM_DATA_VL)
11209                 addr = SEND_CM_CREDIT_VL + (8 * vl);
11210         else
11211                 addr = SEND_CM_CREDIT_VL15;
11212
11213         reg = read_csr(dd, addr);
11214         reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK;
11215         reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT;
11216         write_csr(dd, addr, reg);
11217 }
11218
11219 /* set the given per-VL dedicated limit */
11220 static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit)
11221 {
11222         u64 reg;
11223         u32 addr;
11224
11225         if (vl < TXE_NUM_DATA_VL)
11226                 addr = SEND_CM_CREDIT_VL + (8 * vl);
11227         else
11228                 addr = SEND_CM_CREDIT_VL15;
11229
11230         reg = read_csr(dd, addr);
11231         reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK;
11232         reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT;
11233         write_csr(dd, addr, reg);
11234 }
11235
11236 /* spin until the given per-VL status mask bits clear */
11237 static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask,
11238                                      const char *which)
11239 {
11240         unsigned long timeout;
11241         u64 reg;
11242
11243         timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT);
11244         while (1) {
11245                 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
11246
11247                 if (reg == 0)
11248                         return; /* success */
11249                 if (time_after(jiffies, timeout))
11250                         break;          /* timed out */
11251                 udelay(1);
11252         }
11253
11254         dd_dev_err(dd,
11255                    "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
11256                    which, VL_STATUS_CLEAR_TIMEOUT, mask, reg);
11257         /*
11258          * If this occurs, it is likely there was a credit loss on the link.
11259          * The only recovery from that is a link bounce.
11260          */
11261         dd_dev_err(dd,
11262                    "Continuing anyway.  A credit loss may occur.  Suggest a link bounce\n");
11263 }
11264
11265 /*
11266  * The number of credits on the VLs may be changed while everything
11267  * is "live", but the following algorithm must be followed due to
11268  * how the hardware is actually implemented.  In particular,
11269  * Return_Credit_Status[] is the only correct status check.
11270  *
11271  * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
11272  *     set Global_Shared_Credit_Limit = 0
11273  *     use_all_vl = 1
11274  * mask0 = all VLs that are changing either dedicated or shared limits
11275  * set Shared_Limit[mask0] = 0
11276  * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
11277  * if (changing any dedicated limit)
11278  *     mask1 = all VLs that are lowering dedicated limits
11279  *     lower Dedicated_Limit[mask1]
11280  *     spin until Return_Credit_Status[mask1] == 0
11281  *     raise Dedicated_Limits
11282  * raise Shared_Limits
11283  * raise Global_Shared_Credit_Limit
11284  *
11285  * lower = if the new limit is lower, set the limit to the new value
11286  * raise = if the new limit is higher than the current value (may be changed
11287  *      earlier in the algorithm), set the new limit to the new value
11288  */
11289 int set_buffer_control(struct hfi1_pportdata *ppd,
11290                        struct buffer_control *new_bc)
11291 {
11292         struct hfi1_devdata *dd = ppd->dd;
11293         u64 changing_mask, ld_mask, stat_mask;
11294         int change_count;
11295         int i, use_all_mask;
11296         int this_shared_changing;
11297         int vl_count = 0, ret;
11298         /*
11299          * A0: add the variable any_shared_limit_changing below and in the
11300          * algorithm above.  If removing A0 support, it can be removed.
11301          */
11302         int any_shared_limit_changing;
11303         struct buffer_control cur_bc;
11304         u8 changing[OPA_MAX_VLS];
11305         u8 lowering_dedicated[OPA_MAX_VLS];
11306         u16 cur_total;
11307         u32 new_total = 0;
11308         const u64 all_mask =
11309         SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
11310          | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
11311          | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
11312          | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
11313          | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
11314          | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
11315          | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
11316          | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
11317          | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK;
11318
11319 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
11320 #define NUM_USABLE_VLS 16       /* look at VL15 and less */
11321
11322         /* find the new total credits, do sanity check on unused VLs */
11323         for (i = 0; i < OPA_MAX_VLS; i++) {
11324                 if (valid_vl(i)) {
11325                         new_total += be16_to_cpu(new_bc->vl[i].dedicated);
11326                         continue;
11327                 }
11328                 nonzero_msg(dd, i, "dedicated",
11329                             be16_to_cpu(new_bc->vl[i].dedicated));
11330                 nonzero_msg(dd, i, "shared",
11331                             be16_to_cpu(new_bc->vl[i].shared));
11332                 new_bc->vl[i].dedicated = 0;
11333                 new_bc->vl[i].shared = 0;
11334         }
11335         new_total += be16_to_cpu(new_bc->overall_shared_limit);
11336
11337         /* fetch the current values */
11338         get_buffer_control(dd, &cur_bc, &cur_total);
11339
11340         /*
11341          * Create the masks we will use.
11342          */
11343         memset(changing, 0, sizeof(changing));
11344         memset(lowering_dedicated, 0, sizeof(lowering_dedicated));
11345         /*
11346          * NOTE: Assumes that the individual VL bits are adjacent and in
11347          * increasing order
11348          */
11349         stat_mask =
11350                 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
11351         changing_mask = 0;
11352         ld_mask = 0;
11353         change_count = 0;
11354         any_shared_limit_changing = 0;
11355         for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) {
11356                 if (!valid_vl(i))
11357                         continue;
11358                 this_shared_changing = new_bc->vl[i].shared
11359                                                 != cur_bc.vl[i].shared;
11360                 if (this_shared_changing)
11361                         any_shared_limit_changing = 1;
11362                 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated ||
11363                     this_shared_changing) {
11364                         changing[i] = 1;
11365                         changing_mask |= stat_mask;
11366                         change_count++;
11367                 }
11368                 if (be16_to_cpu(new_bc->vl[i].dedicated) <
11369                                         be16_to_cpu(cur_bc.vl[i].dedicated)) {
11370                         lowering_dedicated[i] = 1;
11371                         ld_mask |= stat_mask;
11372                 }
11373         }
11374
11375         /* bracket the credit change with a total adjustment */
11376         if (new_total > cur_total)
11377                 set_global_limit(dd, new_total);
11378
11379         /*
11380          * Start the credit change algorithm.
11381          */
11382         use_all_mask = 0;
11383         if ((be16_to_cpu(new_bc->overall_shared_limit) <
11384              be16_to_cpu(cur_bc.overall_shared_limit)) ||
11385             (is_ax(dd) && any_shared_limit_changing)) {
11386                 set_global_shared(dd, 0);
11387                 cur_bc.overall_shared_limit = 0;
11388                 use_all_mask = 1;
11389         }
11390
11391         for (i = 0; i < NUM_USABLE_VLS; i++) {
11392                 if (!valid_vl(i))
11393                         continue;
11394
11395                 if (changing[i]) {
11396                         set_vl_shared(dd, i, 0);
11397                         cur_bc.vl[i].shared = 0;
11398                 }
11399         }
11400
11401         wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask,
11402                                  "shared");
11403
11404         if (change_count > 0) {
11405                 for (i = 0; i < NUM_USABLE_VLS; i++) {
11406                         if (!valid_vl(i))
11407                                 continue;
11408
11409                         if (lowering_dedicated[i]) {
11410                                 set_vl_dedicated(dd, i,
11411                                                  be16_to_cpu(new_bc->
11412                                                              vl[i].dedicated));
11413                                 cur_bc.vl[i].dedicated =
11414                                                 new_bc->vl[i].dedicated;
11415                         }
11416                 }
11417
11418                 wait_for_vl_status_clear(dd, ld_mask, "dedicated");
11419
11420                 /* now raise all dedicated that are going up */
11421                 for (i = 0; i < NUM_USABLE_VLS; i++) {
11422                         if (!valid_vl(i))
11423                                 continue;
11424
11425                         if (be16_to_cpu(new_bc->vl[i].dedicated) >
11426                                         be16_to_cpu(cur_bc.vl[i].dedicated))
11427                                 set_vl_dedicated(dd, i,
11428                                                  be16_to_cpu(new_bc->
11429                                                              vl[i].dedicated));
11430                 }
11431         }
11432
11433         /* next raise all shared that are going up */
11434         for (i = 0; i < NUM_USABLE_VLS; i++) {
11435                 if (!valid_vl(i))
11436                         continue;
11437
11438                 if (be16_to_cpu(new_bc->vl[i].shared) >
11439                                 be16_to_cpu(cur_bc.vl[i].shared))
11440                         set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared));
11441         }
11442
11443         /* finally raise the global shared */
11444         if (be16_to_cpu(new_bc->overall_shared_limit) >
11445             be16_to_cpu(cur_bc.overall_shared_limit))
11446                 set_global_shared(dd,
11447                                   be16_to_cpu(new_bc->overall_shared_limit));
11448
11449         /* bracket the credit change with a total adjustment */
11450         if (new_total < cur_total)
11451                 set_global_limit(dd, new_total);
11452
11453         /*
11454          * Determine the actual number of operational VLS using the number of
11455          * dedicated and shared credits for each VL.
11456          */
11457         if (change_count > 0) {
11458                 for (i = 0; i < TXE_NUM_DATA_VL; i++)
11459                         if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 ||
11460                             be16_to_cpu(new_bc->vl[i].shared) > 0)
11461                                 vl_count++;
11462                 ppd->actual_vls_operational = vl_count;
11463                 ret = sdma_map_init(dd, ppd->port - 1, vl_count ?
11464                                     ppd->actual_vls_operational :
11465                                     ppd->vls_operational,
11466                                     NULL);
11467                 if (ret == 0)
11468                         ret = pio_map_init(dd, ppd->port - 1, vl_count ?
11469                                            ppd->actual_vls_operational :
11470                                            ppd->vls_operational, NULL);
11471                 if (ret)
11472                         return ret;
11473         }
11474         return 0;
11475 }
11476
11477 /*
11478  * Read the given fabric manager table. Return the size of the
11479  * table (in bytes) on success, and a negative error code on
11480  * failure.
11481  */
11482 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t)
11483
11484 {
11485         int size;
11486         struct vl_arb_cache *vlc;
11487
11488         switch (which) {
11489         case FM_TBL_VL_HIGH_ARB:
11490                 size = 256;
11491                 /*
11492                  * OPA specifies 128 elements (of 2 bytes each), though
11493                  * HFI supports only 16 elements in h/w.
11494                  */
11495                 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11496                 vl_arb_get_cache(vlc, t);
11497                 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11498                 break;
11499         case FM_TBL_VL_LOW_ARB:
11500                 size = 256;
11501                 /*
11502                  * OPA specifies 128 elements (of 2 bytes each), though
11503                  * HFI supports only 16 elements in h/w.
11504                  */
11505                 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11506                 vl_arb_get_cache(vlc, t);
11507                 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11508                 break;
11509         case FM_TBL_BUFFER_CONTROL:
11510                 size = get_buffer_control(ppd->dd, t, NULL);
11511                 break;
11512         case FM_TBL_SC2VLNT:
11513                 size = get_sc2vlnt(ppd->dd, t);
11514                 break;
11515         case FM_TBL_VL_PREEMPT_ELEMS:
11516                 size = 256;
11517                 /* OPA specifies 128 elements, of 2 bytes each */
11518                 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t);
11519                 break;
11520         case FM_TBL_VL_PREEMPT_MATRIX:
11521                 size = 256;
11522                 /*
11523                  * OPA specifies that this is the same size as the VL
11524                  * arbitration tables (i.e., 256 bytes).
11525                  */
11526                 break;
11527         default:
11528                 return -EINVAL;
11529         }
11530         return size;
11531 }
11532
11533 /*
11534  * Write the given fabric manager table.
11535  */
11536 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t)
11537 {
11538         int ret = 0;
11539         struct vl_arb_cache *vlc;
11540
11541         switch (which) {
11542         case FM_TBL_VL_HIGH_ARB:
11543                 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11544                 if (vl_arb_match_cache(vlc, t)) {
11545                         vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11546                         break;
11547                 }
11548                 vl_arb_set_cache(vlc, t);
11549                 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11550                 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST,
11551                                      VL_ARB_HIGH_PRIO_TABLE_SIZE, t);
11552                 break;
11553         case FM_TBL_VL_LOW_ARB:
11554                 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11555                 if (vl_arb_match_cache(vlc, t)) {
11556                         vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11557                         break;
11558                 }
11559                 vl_arb_set_cache(vlc, t);
11560                 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11561                 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST,
11562                                      VL_ARB_LOW_PRIO_TABLE_SIZE, t);
11563                 break;
11564         case FM_TBL_BUFFER_CONTROL:
11565                 ret = set_buffer_control(ppd, t);
11566                 break;
11567         case FM_TBL_SC2VLNT:
11568                 set_sc2vlnt(ppd->dd, t);
11569                 break;
11570         default:
11571                 ret = -EINVAL;
11572         }
11573         return ret;
11574 }
11575
11576 /*
11577  * Disable all data VLs.
11578  *
11579  * Return 0 if disabled, non-zero if the VLs cannot be disabled.
11580  */
11581 static int disable_data_vls(struct hfi1_devdata *dd)
11582 {
11583         if (is_ax(dd))
11584                 return 1;
11585
11586         pio_send_control(dd, PSC_DATA_VL_DISABLE);
11587
11588         return 0;
11589 }
11590
11591 /*
11592  * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
11593  * Just re-enables all data VLs (the "fill" part happens
11594  * automatically - the name was chosen for symmetry with
11595  * stop_drain_data_vls()).
11596  *
11597  * Return 0 if successful, non-zero if the VLs cannot be enabled.
11598  */
11599 int open_fill_data_vls(struct hfi1_devdata *dd)
11600 {
11601         if (is_ax(dd))
11602                 return 1;
11603
11604         pio_send_control(dd, PSC_DATA_VL_ENABLE);
11605
11606         return 0;
11607 }
11608
11609 /*
11610  * drain_data_vls() - assumes that disable_data_vls() has been called,
11611  * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11612  * engines to drop to 0.
11613  */
11614 static void drain_data_vls(struct hfi1_devdata *dd)
11615 {
11616         sc_wait(dd);
11617         sdma_wait(dd);
11618         pause_for_credit_return(dd);
11619 }
11620
11621 /*
11622  * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11623  *
11624  * Use open_fill_data_vls() to resume using data VLs.  This pair is
11625  * meant to be used like this:
11626  *
11627  * stop_drain_data_vls(dd);
11628  * // do things with per-VL resources
11629  * open_fill_data_vls(dd);
11630  */
11631 int stop_drain_data_vls(struct hfi1_devdata *dd)
11632 {
11633         int ret;
11634
11635         ret = disable_data_vls(dd);
11636         if (ret == 0)
11637                 drain_data_vls(dd);
11638
11639         return ret;
11640 }
11641
11642 /*
11643  * Convert a nanosecond time to a cclock count.  No matter how slow
11644  * the cclock, a non-zero ns will always have a non-zero result.
11645  */
11646 u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns)
11647 {
11648         u32 cclocks;
11649
11650         if (dd->icode == ICODE_FPGA_EMULATION)
11651                 cclocks = (ns * 1000) / FPGA_CCLOCK_PS;
11652         else  /* simulation pretends to be ASIC */
11653                 cclocks = (ns * 1000) / ASIC_CCLOCK_PS;
11654         if (ns && !cclocks)     /* if ns nonzero, must be at least 1 */
11655                 cclocks = 1;
11656         return cclocks;
11657 }
11658
11659 /*
11660  * Convert a cclock count to nanoseconds. Not matter how slow
11661  * the cclock, a non-zero cclocks will always have a non-zero result.
11662  */
11663 u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks)
11664 {
11665         u32 ns;
11666
11667         if (dd->icode == ICODE_FPGA_EMULATION)
11668                 ns = (cclocks * FPGA_CCLOCK_PS) / 1000;
11669         else  /* simulation pretends to be ASIC */
11670                 ns = (cclocks * ASIC_CCLOCK_PS) / 1000;
11671         if (cclocks && !ns)
11672                 ns = 1;
11673         return ns;
11674 }
11675
11676 /*
11677  * Dynamically adjust the receive interrupt timeout for a context based on
11678  * incoming packet rate.
11679  *
11680  * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11681  */
11682 static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts)
11683 {
11684         struct hfi1_devdata *dd = rcd->dd;
11685         u32 timeout = rcd->rcvavail_timeout;
11686
11687         /*
11688          * This algorithm doubles or halves the timeout depending on whether
11689          * the number of packets received in this interrupt were less than or
11690          * greater equal the interrupt count.
11691          *
11692          * The calculations below do not allow a steady state to be achieved.
11693          * Only at the endpoints it is possible to have an unchanging
11694          * timeout.
11695          */
11696         if (npkts < rcv_intr_count) {
11697                 /*
11698                  * Not enough packets arrived before the timeout, adjust
11699                  * timeout downward.
11700                  */
11701                 if (timeout < 2) /* already at minimum? */
11702                         return;
11703                 timeout >>= 1;
11704         } else {
11705                 /*
11706                  * More than enough packets arrived before the timeout, adjust
11707                  * timeout upward.
11708                  */
11709                 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */
11710                         return;
11711                 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr);
11712         }
11713
11714         rcd->rcvavail_timeout = timeout;
11715         /*
11716          * timeout cannot be larger than rcv_intr_timeout_csr which has already
11717          * been verified to be in range
11718          */
11719         write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
11720                         (u64)timeout <<
11721                         RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11722 }
11723
11724 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
11725                     u32 intr_adjust, u32 npkts)
11726 {
11727         struct hfi1_devdata *dd = rcd->dd;
11728         u64 reg;
11729         u32 ctxt = rcd->ctxt;
11730
11731         /*
11732          * Need to write timeout register before updating RcvHdrHead to ensure
11733          * that a new value is used when the HW decides to restart counting.
11734          */
11735         if (intr_adjust)
11736                 adjust_rcv_timeout(rcd, npkts);
11737         if (updegr) {
11738                 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK)
11739                         << RCV_EGR_INDEX_HEAD_HEAD_SHIFT;
11740                 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg);
11741         }
11742         mmiowb();
11743         reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) |
11744                 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK)
11745                         << RCV_HDR_HEAD_HEAD_SHIFT);
11746         write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11747         mmiowb();
11748 }
11749
11750 u32 hdrqempty(struct hfi1_ctxtdata *rcd)
11751 {
11752         u32 head, tail;
11753
11754         head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11755                 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT;
11756
11757         if (rcd->rcvhdrtail_kvaddr)
11758                 tail = get_rcvhdrtail(rcd);
11759         else
11760                 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
11761
11762         return head == tail;
11763 }
11764
11765 /*
11766  * Context Control and Receive Array encoding for buffer size:
11767  *      0x0 invalid
11768  *      0x1   4 KB
11769  *      0x2   8 KB
11770  *      0x3  16 KB
11771  *      0x4  32 KB
11772  *      0x5  64 KB
11773  *      0x6 128 KB
11774  *      0x7 256 KB
11775  *      0x8 512 KB (Receive Array only)
11776  *      0x9   1 MB (Receive Array only)
11777  *      0xa   2 MB (Receive Array only)
11778  *
11779  *      0xB-0xF - reserved (Receive Array only)
11780  *
11781  *
11782  * This routine assumes that the value has already been sanity checked.
11783  */
11784 static u32 encoded_size(u32 size)
11785 {
11786         switch (size) {
11787         case   4 * 1024: return 0x1;
11788         case   8 * 1024: return 0x2;
11789         case  16 * 1024: return 0x3;
11790         case  32 * 1024: return 0x4;
11791         case  64 * 1024: return 0x5;
11792         case 128 * 1024: return 0x6;
11793         case 256 * 1024: return 0x7;
11794         case 512 * 1024: return 0x8;
11795         case   1 * 1024 * 1024: return 0x9;
11796         case   2 * 1024 * 1024: return 0xa;
11797         }
11798         return 0x1;     /* if invalid, go with the minimum size */
11799 }
11800
11801 void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op,
11802                   struct hfi1_ctxtdata *rcd)
11803 {
11804         u64 rcvctrl, reg;
11805         int did_enable = 0;
11806         u16 ctxt;
11807
11808         if (!rcd)
11809                 return;
11810
11811         ctxt = rcd->ctxt;
11812
11813         hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
11814
11815         rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
11816         /* if the context already enabled, don't do the extra steps */
11817         if ((op & HFI1_RCVCTRL_CTXT_ENB) &&
11818             !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) {
11819                 /* reset the tail and hdr addresses, and sequence count */
11820                 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
11821                                 rcd->rcvhdrq_dma);
11822                 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL))
11823                         write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11824                                         rcd->rcvhdrqtailaddr_dma);
11825                 rcd->seq_cnt = 1;
11826
11827                 /* reset the cached receive header queue head value */
11828                 rcd->head = 0;
11829
11830                 /*
11831                  * Zero the receive header queue so we don't get false
11832                  * positives when checking the sequence number.  The
11833                  * sequence numbers could land exactly on the same spot.
11834                  * E.g. a rcd restart before the receive header wrapped.
11835                  */
11836                 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
11837
11838                 /* starting timeout */
11839                 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr;
11840
11841                 /* enable the context */
11842                 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK;
11843
11844                 /* clean the egr buffer size first */
11845                 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11846                 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size)
11847                                 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK)
11848                                         << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT;
11849
11850                 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
11851                 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0);
11852                 did_enable = 1;
11853
11854                 /* zero RcvEgrIndexHead */
11855                 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0);
11856
11857                 /* set eager count and base index */
11858                 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT)
11859                         & RCV_EGR_CTRL_EGR_CNT_MASK)
11860                        << RCV_EGR_CTRL_EGR_CNT_SHIFT) |
11861                         (((rcd->eager_base >> RCV_SHIFT)
11862                           & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK)
11863                          << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT);
11864                 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg);
11865
11866                 /*
11867                  * Set TID (expected) count and base index.
11868                  * rcd->expected_count is set to individual RcvArray entries,
11869                  * not pairs, and the CSR takes a pair-count in groups of
11870                  * four, so divide by 8.
11871                  */
11872                 reg = (((rcd->expected_count >> RCV_SHIFT)
11873                                         & RCV_TID_CTRL_TID_PAIR_CNT_MASK)
11874                                 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) |
11875                       (((rcd->expected_base >> RCV_SHIFT)
11876                                         & RCV_TID_CTRL_TID_BASE_INDEX_MASK)
11877                                 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT);
11878                 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg);
11879                 if (ctxt == HFI1_CTRL_CTXT)
11880                         write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
11881         }
11882         if (op & HFI1_RCVCTRL_CTXT_DIS) {
11883                 write_csr(dd, RCV_VL15, 0);
11884                 /*
11885                  * When receive context is being disabled turn on tail
11886                  * update with a dummy tail address and then disable
11887                  * receive context.
11888                  */
11889                 if (dd->rcvhdrtail_dummy_dma) {
11890                         write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11891                                         dd->rcvhdrtail_dummy_dma);
11892                         /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
11893                         rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11894                 }
11895
11896                 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK;
11897         }
11898         if (op & HFI1_RCVCTRL_INTRAVAIL_ENB)
11899                 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11900         if (op & HFI1_RCVCTRL_INTRAVAIL_DIS)
11901                 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11902         if (op & HFI1_RCVCTRL_TAILUPD_ENB && rcd->rcvhdrqtailaddr_dma)
11903                 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11904         if (op & HFI1_RCVCTRL_TAILUPD_DIS) {
11905                 /* See comment on RcvCtxtCtrl.TailUpd above */
11906                 if (!(op & HFI1_RCVCTRL_CTXT_DIS))
11907                         rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11908         }
11909         if (op & HFI1_RCVCTRL_TIDFLOW_ENB)
11910                 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11911         if (op & HFI1_RCVCTRL_TIDFLOW_DIS)
11912                 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11913         if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) {
11914                 /*
11915                  * In one-packet-per-eager mode, the size comes from
11916                  * the RcvArray entry.
11917                  */
11918                 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11919                 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11920         }
11921         if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS)
11922                 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11923         if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB)
11924                 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11925         if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS)
11926                 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11927         if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB)
11928                 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11929         if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS)
11930                 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11931         rcd->rcvctrl = rcvctrl;
11932         hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl);
11933         write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcd->rcvctrl);
11934
11935         /* work around sticky RcvCtxtStatus.BlockedRHQFull */
11936         if (did_enable &&
11937             (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) {
11938                 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11939                 if (reg != 0) {
11940                         dd_dev_info(dd, "ctxt %d status %lld (blocked)\n",
11941                                     ctxt, reg);
11942                         read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11943                         write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10);
11944                         write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00);
11945                         read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11946                         reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11947                         dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n",
11948                                     ctxt, reg, reg == 0 ? "not" : "still");
11949                 }
11950         }
11951
11952         if (did_enable) {
11953                 /*
11954                  * The interrupt timeout and count must be set after
11955                  * the context is enabled to take effect.
11956                  */
11957                 /* set interrupt timeout */
11958                 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT,
11959                                 (u64)rcd->rcvavail_timeout <<
11960                                 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11961
11962                 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
11963                 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT;
11964                 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11965         }
11966
11967         if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS))
11968                 /*
11969                  * If the context has been disabled and the Tail Update has
11970                  * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
11971                  * so it doesn't contain an address that is invalid.
11972                  */
11973                 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11974                                 dd->rcvhdrtail_dummy_dma);
11975 }
11976
11977 u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp)
11978 {
11979         int ret;
11980         u64 val = 0;
11981
11982         if (namep) {
11983                 ret = dd->cntrnameslen;
11984                 *namep = dd->cntrnames;
11985         } else {
11986                 const struct cntr_entry *entry;
11987                 int i, j;
11988
11989                 ret = (dd->ndevcntrs) * sizeof(u64);
11990
11991                 /* Get the start of the block of counters */
11992                 *cntrp = dd->cntrs;
11993
11994                 /*
11995                  * Now go and fill in each counter in the block.
11996                  */
11997                 for (i = 0; i < DEV_CNTR_LAST; i++) {
11998                         entry = &dev_cntrs[i];
11999                         hfi1_cdbg(CNTR, "reading %s", entry->name);
12000                         if (entry->flags & CNTR_DISABLED) {
12001                                 /* Nothing */
12002                                 hfi1_cdbg(CNTR, "\tDisabled\n");
12003                         } else {
12004                                 if (entry->flags & CNTR_VL) {
12005                                         hfi1_cdbg(CNTR, "\tPer VL\n");
12006                                         for (j = 0; j < C_VL_COUNT; j++) {
12007                                                 val = entry->rw_cntr(entry,
12008                                                                   dd, j,
12009                                                                   CNTR_MODE_R,
12010                                                                   0);
12011                                                 hfi1_cdbg(
12012                                                    CNTR,
12013                                                    "\t\tRead 0x%llx for %d\n",
12014                                                    val, j);
12015                                                 dd->cntrs[entry->offset + j] =
12016                                                                             val;
12017                                         }
12018                                 } else if (entry->flags & CNTR_SDMA) {
12019                                         hfi1_cdbg(CNTR,
12020                                                   "\t Per SDMA Engine\n");
12021                                         for (j = 0; j < dd->chip_sdma_engines;
12022                                              j++) {
12023                                                 val =
12024                                                 entry->rw_cntr(entry, dd, j,
12025                                                                CNTR_MODE_R, 0);
12026                                                 hfi1_cdbg(CNTR,
12027                                                           "\t\tRead 0x%llx for %d\n",
12028                                                           val, j);
12029                                                 dd->cntrs[entry->offset + j] =
12030                                                                         val;
12031                                         }
12032                                 } else {
12033                                         val = entry->rw_cntr(entry, dd,
12034                                                         CNTR_INVALID_VL,
12035                                                         CNTR_MODE_R, 0);
12036                                         dd->cntrs[entry->offset] = val;
12037                                         hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
12038                                 }
12039                         }
12040                 }
12041         }
12042         return ret;
12043 }
12044
12045 /*
12046  * Used by sysfs to create files for hfi stats to read
12047  */
12048 u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp)
12049 {
12050         int ret;
12051         u64 val = 0;
12052
12053         if (namep) {
12054                 ret = ppd->dd->portcntrnameslen;
12055                 *namep = ppd->dd->portcntrnames;
12056         } else {
12057                 const struct cntr_entry *entry;
12058                 int i, j;
12059
12060                 ret = ppd->dd->nportcntrs * sizeof(u64);
12061                 *cntrp = ppd->cntrs;
12062
12063                 for (i = 0; i < PORT_CNTR_LAST; i++) {
12064                         entry = &port_cntrs[i];
12065                         hfi1_cdbg(CNTR, "reading %s", entry->name);
12066                         if (entry->flags & CNTR_DISABLED) {
12067                                 /* Nothing */
12068                                 hfi1_cdbg(CNTR, "\tDisabled\n");
12069                                 continue;
12070                         }
12071
12072                         if (entry->flags & CNTR_VL) {
12073                                 hfi1_cdbg(CNTR, "\tPer VL");
12074                                 for (j = 0; j < C_VL_COUNT; j++) {
12075                                         val = entry->rw_cntr(entry, ppd, j,
12076                                                                CNTR_MODE_R,
12077                                                                0);
12078                                         hfi1_cdbg(
12079                                            CNTR,
12080                                            "\t\tRead 0x%llx for %d",
12081                                            val, j);
12082                                         ppd->cntrs[entry->offset + j] = val;
12083                                 }
12084                         } else {
12085                                 val = entry->rw_cntr(entry, ppd,
12086                                                        CNTR_INVALID_VL,
12087                                                        CNTR_MODE_R,
12088                                                        0);
12089                                 ppd->cntrs[entry->offset] = val;
12090                                 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
12091                         }
12092                 }
12093         }
12094         return ret;
12095 }
12096
12097 static void free_cntrs(struct hfi1_devdata *dd)
12098 {
12099         struct hfi1_pportdata *ppd;
12100         int i;
12101
12102         if (dd->synth_stats_timer.function)
12103                 del_timer_sync(&dd->synth_stats_timer);
12104         ppd = (struct hfi1_pportdata *)(dd + 1);
12105         for (i = 0; i < dd->num_pports; i++, ppd++) {
12106                 kfree(ppd->cntrs);
12107                 kfree(ppd->scntrs);
12108                 free_percpu(ppd->ibport_data.rvp.rc_acks);
12109                 free_percpu(ppd->ibport_data.rvp.rc_qacks);
12110                 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp);
12111                 ppd->cntrs = NULL;
12112                 ppd->scntrs = NULL;
12113                 ppd->ibport_data.rvp.rc_acks = NULL;
12114                 ppd->ibport_data.rvp.rc_qacks = NULL;
12115                 ppd->ibport_data.rvp.rc_delayed_comp = NULL;
12116         }
12117         kfree(dd->portcntrnames);
12118         dd->portcntrnames = NULL;
12119         kfree(dd->cntrs);
12120         dd->cntrs = NULL;
12121         kfree(dd->scntrs);
12122         dd->scntrs = NULL;
12123         kfree(dd->cntrnames);
12124         dd->cntrnames = NULL;
12125         if (dd->update_cntr_wq) {
12126                 destroy_workqueue(dd->update_cntr_wq);
12127                 dd->update_cntr_wq = NULL;
12128         }
12129 }
12130
12131 static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry,
12132                               u64 *psval, void *context, int vl)
12133 {
12134         u64 val;
12135         u64 sval = *psval;
12136
12137         if (entry->flags & CNTR_DISABLED) {
12138                 dd_dev_err(dd, "Counter %s not enabled", entry->name);
12139                 return 0;
12140         }
12141
12142         hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
12143
12144         val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0);
12145
12146         /* If its a synthetic counter there is more work we need to do */
12147         if (entry->flags & CNTR_SYNTH) {
12148                 if (sval == CNTR_MAX) {
12149                         /* No need to read already saturated */
12150                         return CNTR_MAX;
12151                 }
12152
12153                 if (entry->flags & CNTR_32BIT) {
12154                         /* 32bit counters can wrap multiple times */
12155                         u64 upper = sval >> 32;
12156                         u64 lower = (sval << 32) >> 32;
12157
12158                         if (lower > val) { /* hw wrapped */
12159                                 if (upper == CNTR_32BIT_MAX)
12160                                         val = CNTR_MAX;
12161                                 else
12162                                         upper++;
12163                         }
12164
12165                         if (val != CNTR_MAX)
12166                                 val = (upper << 32) | val;
12167
12168                 } else {
12169                         /* If we rolled we are saturated */
12170                         if ((val < sval) || (val > CNTR_MAX))
12171                                 val = CNTR_MAX;
12172                 }
12173         }
12174
12175         *psval = val;
12176
12177         hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
12178
12179         return val;
12180 }
12181
12182 static u64 write_dev_port_cntr(struct hfi1_devdata *dd,
12183                                struct cntr_entry *entry,
12184                                u64 *psval, void *context, int vl, u64 data)
12185 {
12186         u64 val;
12187
12188         if (entry->flags & CNTR_DISABLED) {
12189                 dd_dev_err(dd, "Counter %s not enabled", entry->name);
12190                 return 0;
12191         }
12192
12193         hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
12194
12195         if (entry->flags & CNTR_SYNTH) {
12196                 *psval = data;
12197                 if (entry->flags & CNTR_32BIT) {
12198                         val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
12199                                              (data << 32) >> 32);
12200                         val = data; /* return the full 64bit value */
12201                 } else {
12202                         val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
12203                                              data);
12204                 }
12205         } else {
12206                 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data);
12207         }
12208
12209         *psval = val;
12210
12211         hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
12212
12213         return val;
12214 }
12215
12216 u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl)
12217 {
12218         struct cntr_entry *entry;
12219         u64 *sval;
12220
12221         entry = &dev_cntrs[index];
12222         sval = dd->scntrs + entry->offset;
12223
12224         if (vl != CNTR_INVALID_VL)
12225                 sval += vl;
12226
12227         return read_dev_port_cntr(dd, entry, sval, dd, vl);
12228 }
12229
12230 u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data)
12231 {
12232         struct cntr_entry *entry;
12233         u64 *sval;
12234
12235         entry = &dev_cntrs[index];
12236         sval = dd->scntrs + entry->offset;
12237
12238         if (vl != CNTR_INVALID_VL)
12239                 sval += vl;
12240
12241         return write_dev_port_cntr(dd, entry, sval, dd, vl, data);
12242 }
12243
12244 u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl)
12245 {
12246         struct cntr_entry *entry;
12247         u64 *sval;
12248
12249         entry = &port_cntrs[index];
12250         sval = ppd->scntrs + entry->offset;
12251
12252         if (vl != CNTR_INVALID_VL)
12253                 sval += vl;
12254
12255         if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
12256             (index <= C_RCV_HDR_OVF_LAST)) {
12257                 /* We do not want to bother for disabled contexts */
12258                 return 0;
12259         }
12260
12261         return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl);
12262 }
12263
12264 u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data)
12265 {
12266         struct cntr_entry *entry;
12267         u64 *sval;
12268
12269         entry = &port_cntrs[index];
12270         sval = ppd->scntrs + entry->offset;
12271
12272         if (vl != CNTR_INVALID_VL)
12273                 sval += vl;
12274
12275         if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
12276             (index <= C_RCV_HDR_OVF_LAST)) {
12277                 /* We do not want to bother for disabled contexts */
12278                 return 0;
12279         }
12280
12281         return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data);
12282 }
12283
12284 static void do_update_synth_timer(struct work_struct *work)
12285 {
12286         u64 cur_tx;
12287         u64 cur_rx;
12288         u64 total_flits;
12289         u8 update = 0;
12290         int i, j, vl;
12291         struct hfi1_pportdata *ppd;
12292         struct cntr_entry *entry;
12293         struct hfi1_devdata *dd = container_of(work, struct hfi1_devdata,
12294                                                update_cntr_work);
12295
12296         /*
12297          * Rather than keep beating on the CSRs pick a minimal set that we can
12298          * check to watch for potential roll over. We can do this by looking at
12299          * the number of flits sent/recv. If the total flits exceeds 32bits then
12300          * we have to iterate all the counters and update.
12301          */
12302         entry = &dev_cntrs[C_DC_RCV_FLITS];
12303         cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
12304
12305         entry = &dev_cntrs[C_DC_XMIT_FLITS];
12306         cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
12307
12308         hfi1_cdbg(
12309             CNTR,
12310             "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n",
12311             dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx);
12312
12313         if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) {
12314                 /*
12315                  * May not be strictly necessary to update but it won't hurt and
12316                  * simplifies the logic here.
12317                  */
12318                 update = 1;
12319                 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",
12320                           dd->unit);
12321         } else {
12322                 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx);
12323                 hfi1_cdbg(CNTR,
12324                           "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit,
12325                           total_flits, (u64)CNTR_32BIT_MAX);
12326                 if (total_flits >= CNTR_32BIT_MAX) {
12327                         hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",
12328                                   dd->unit);
12329                         update = 1;
12330                 }
12331         }
12332
12333         if (update) {
12334                 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);
12335                 for (i = 0; i < DEV_CNTR_LAST; i++) {
12336                         entry = &dev_cntrs[i];
12337                         if (entry->flags & CNTR_VL) {
12338                                 for (vl = 0; vl < C_VL_COUNT; vl++)
12339                                         read_dev_cntr(dd, i, vl);
12340                         } else {
12341                                 read_dev_cntr(dd, i, CNTR_INVALID_VL);
12342                         }
12343                 }
12344                 ppd = (struct hfi1_pportdata *)(dd + 1);
12345                 for (i = 0; i < dd->num_pports; i++, ppd++) {
12346                         for (j = 0; j < PORT_CNTR_LAST; j++) {
12347                                 entry = &port_cntrs[j];
12348                                 if (entry->flags & CNTR_VL) {
12349                                         for (vl = 0; vl < C_VL_COUNT; vl++)
12350                                                 read_port_cntr(ppd, j, vl);
12351                                 } else {
12352                                         read_port_cntr(ppd, j, CNTR_INVALID_VL);
12353                                 }
12354                         }
12355                 }
12356
12357                 /*
12358                  * We want the value in the register. The goal is to keep track
12359                  * of the number of "ticks" not the counter value. In other
12360                  * words if the register rolls we want to notice it and go ahead
12361                  * and force an update.
12362                  */
12363                 entry = &dev_cntrs[C_DC_XMIT_FLITS];
12364                 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12365                                                 CNTR_MODE_R, 0);
12366
12367                 entry = &dev_cntrs[C_DC_RCV_FLITS];
12368                 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12369                                                 CNTR_MODE_R, 0);
12370
12371                 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",
12372                           dd->unit, dd->last_tx, dd->last_rx);
12373
12374         } else {
12375                 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);
12376         }
12377 }
12378
12379 static void update_synth_timer(struct timer_list *t)
12380 {
12381         struct hfi1_devdata *dd = from_timer(dd, t, synth_stats_timer);
12382
12383         queue_work(dd->update_cntr_wq, &dd->update_cntr_work);
12384         mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12385 }
12386
12387 #define C_MAX_NAME 16 /* 15 chars + one for /0 */
12388 static int init_cntrs(struct hfi1_devdata *dd)
12389 {
12390         int i, rcv_ctxts, j;
12391         size_t sz;
12392         char *p;
12393         char name[C_MAX_NAME];
12394         struct hfi1_pportdata *ppd;
12395         const char *bit_type_32 = ",32";
12396         const int bit_type_32_sz = strlen(bit_type_32);
12397
12398         /* set up the stats timer; the add_timer is done at the end */
12399         timer_setup(&dd->synth_stats_timer, update_synth_timer, 0);
12400
12401         /***********************/
12402         /* per device counters */
12403         /***********************/
12404
12405         /* size names and determine how many we have*/
12406         dd->ndevcntrs = 0;
12407         sz = 0;
12408
12409         for (i = 0; i < DEV_CNTR_LAST; i++) {
12410                 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12411                         hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name);
12412                         continue;
12413                 }
12414
12415                 if (dev_cntrs[i].flags & CNTR_VL) {
12416                         dev_cntrs[i].offset = dd->ndevcntrs;
12417                         for (j = 0; j < C_VL_COUNT; j++) {
12418                                 snprintf(name, C_MAX_NAME, "%s%d",
12419                                          dev_cntrs[i].name, vl_from_idx(j));
12420                                 sz += strlen(name);
12421                                 /* Add ",32" for 32-bit counters */
12422                                 if (dev_cntrs[i].flags & CNTR_32BIT)
12423                                         sz += bit_type_32_sz;
12424                                 sz++;
12425                                 dd->ndevcntrs++;
12426                         }
12427                 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
12428                         dev_cntrs[i].offset = dd->ndevcntrs;
12429                         for (j = 0; j < dd->chip_sdma_engines; j++) {
12430                                 snprintf(name, C_MAX_NAME, "%s%d",
12431                                          dev_cntrs[i].name, j);
12432                                 sz += strlen(name);
12433                                 /* Add ",32" for 32-bit counters */
12434                                 if (dev_cntrs[i].flags & CNTR_32BIT)
12435                                         sz += bit_type_32_sz;
12436                                 sz++;
12437                                 dd->ndevcntrs++;
12438                         }
12439                 } else {
12440                         /* +1 for newline. */
12441                         sz += strlen(dev_cntrs[i].name) + 1;
12442                         /* Add ",32" for 32-bit counters */
12443                         if (dev_cntrs[i].flags & CNTR_32BIT)
12444                                 sz += bit_type_32_sz;
12445                         dev_cntrs[i].offset = dd->ndevcntrs;
12446                         dd->ndevcntrs++;
12447                 }
12448         }
12449
12450         /* allocate space for the counter values */
12451         dd->cntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
12452         if (!dd->cntrs)
12453                 goto bail;
12454
12455         dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
12456         if (!dd->scntrs)
12457                 goto bail;
12458
12459         /* allocate space for the counter names */
12460         dd->cntrnameslen = sz;
12461         dd->cntrnames = kmalloc(sz, GFP_KERNEL);
12462         if (!dd->cntrnames)
12463                 goto bail;
12464
12465         /* fill in the names */
12466         for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) {
12467                 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12468                         /* Nothing */
12469                 } else if (dev_cntrs[i].flags & CNTR_VL) {
12470                         for (j = 0; j < C_VL_COUNT; j++) {
12471                                 snprintf(name, C_MAX_NAME, "%s%d",
12472                                          dev_cntrs[i].name,
12473                                          vl_from_idx(j));
12474                                 memcpy(p, name, strlen(name));
12475                                 p += strlen(name);
12476
12477                                 /* Counter is 32 bits */
12478                                 if (dev_cntrs[i].flags & CNTR_32BIT) {
12479                                         memcpy(p, bit_type_32, bit_type_32_sz);
12480                                         p += bit_type_32_sz;
12481                                 }
12482
12483                                 *p++ = '\n';
12484                         }
12485                 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
12486                         for (j = 0; j < dd->chip_sdma_engines; j++) {
12487                                 snprintf(name, C_MAX_NAME, "%s%d",
12488                                          dev_cntrs[i].name, j);
12489                                 memcpy(p, name, strlen(name));
12490                                 p += strlen(name);
12491
12492                                 /* Counter is 32 bits */
12493                                 if (dev_cntrs[i].flags & CNTR_32BIT) {
12494                                         memcpy(p, bit_type_32, bit_type_32_sz);
12495                                         p += bit_type_32_sz;
12496                                 }
12497
12498                                 *p++ = '\n';
12499                         }
12500                 } else {
12501                         memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name));
12502                         p += strlen(dev_cntrs[i].name);
12503
12504                         /* Counter is 32 bits */
12505                         if (dev_cntrs[i].flags & CNTR_32BIT) {
12506                                 memcpy(p, bit_type_32, bit_type_32_sz);
12507                                 p += bit_type_32_sz;
12508                         }
12509
12510                         *p++ = '\n';
12511                 }
12512         }
12513
12514         /*********************/
12515         /* per port counters */
12516         /*********************/
12517
12518         /*
12519          * Go through the counters for the overflows and disable the ones we
12520          * don't need. This varies based on platform so we need to do it
12521          * dynamically here.
12522          */
12523         rcv_ctxts = dd->num_rcv_contexts;
12524         for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts;
12525              i <= C_RCV_HDR_OVF_LAST; i++) {
12526                 port_cntrs[i].flags |= CNTR_DISABLED;
12527         }
12528
12529         /* size port counter names and determine how many we have*/
12530         sz = 0;
12531         dd->nportcntrs = 0;
12532         for (i = 0; i < PORT_CNTR_LAST; i++) {
12533                 if (port_cntrs[i].flags & CNTR_DISABLED) {
12534                         hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name);
12535                         continue;
12536                 }
12537
12538                 if (port_cntrs[i].flags & CNTR_VL) {
12539                         port_cntrs[i].offset = dd->nportcntrs;
12540                         for (j = 0; j < C_VL_COUNT; j++) {
12541                                 snprintf(name, C_MAX_NAME, "%s%d",
12542                                          port_cntrs[i].name, vl_from_idx(j));
12543                                 sz += strlen(name);
12544                                 /* Add ",32" for 32-bit counters */
12545                                 if (port_cntrs[i].flags & CNTR_32BIT)
12546                                         sz += bit_type_32_sz;
12547                                 sz++;
12548                                 dd->nportcntrs++;
12549                         }
12550                 } else {
12551                         /* +1 for newline */
12552                         sz += strlen(port_cntrs[i].name) + 1;
12553                         /* Add ",32" for 32-bit counters */
12554                         if (port_cntrs[i].flags & CNTR_32BIT)
12555                                 sz += bit_type_32_sz;
12556                         port_cntrs[i].offset = dd->nportcntrs;
12557                         dd->nportcntrs++;
12558                 }
12559         }
12560
12561         /* allocate space for the counter names */
12562         dd->portcntrnameslen = sz;
12563         dd->portcntrnames = kmalloc(sz, GFP_KERNEL);
12564         if (!dd->portcntrnames)
12565                 goto bail;
12566
12567         /* fill in port cntr names */
12568         for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) {
12569                 if (port_cntrs[i].flags & CNTR_DISABLED)
12570                         continue;
12571
12572                 if (port_cntrs[i].flags & CNTR_VL) {
12573                         for (j = 0; j < C_VL_COUNT; j++) {
12574                                 snprintf(name, C_MAX_NAME, "%s%d",
12575                                          port_cntrs[i].name, vl_from_idx(j));
12576                                 memcpy(p, name, strlen(name));
12577                                 p += strlen(name);
12578
12579                                 /* Counter is 32 bits */
12580                                 if (port_cntrs[i].flags & CNTR_32BIT) {
12581                                         memcpy(p, bit_type_32, bit_type_32_sz);
12582                                         p += bit_type_32_sz;
12583                                 }
12584
12585                                 *p++ = '\n';
12586                         }
12587                 } else {
12588                         memcpy(p, port_cntrs[i].name,
12589                                strlen(port_cntrs[i].name));
12590                         p += strlen(port_cntrs[i].name);
12591
12592                         /* Counter is 32 bits */
12593                         if (port_cntrs[i].flags & CNTR_32BIT) {
12594                                 memcpy(p, bit_type_32, bit_type_32_sz);
12595                                 p += bit_type_32_sz;
12596                         }
12597
12598                         *p++ = '\n';
12599                 }
12600         }
12601
12602         /* allocate per port storage for counter values */
12603         ppd = (struct hfi1_pportdata *)(dd + 1);
12604         for (i = 0; i < dd->num_pports; i++, ppd++) {
12605                 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12606                 if (!ppd->cntrs)
12607                         goto bail;
12608
12609                 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12610                 if (!ppd->scntrs)
12611                         goto bail;
12612         }
12613
12614         /* CPU counters need to be allocated and zeroed */
12615         if (init_cpu_counters(dd))
12616                 goto bail;
12617
12618         dd->update_cntr_wq = alloc_ordered_workqueue("hfi1_update_cntr_%d",
12619                                                      WQ_MEM_RECLAIM, dd->unit);
12620         if (!dd->update_cntr_wq)
12621                 goto bail;
12622
12623         INIT_WORK(&dd->update_cntr_work, do_update_synth_timer);
12624
12625         mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12626         return 0;
12627 bail:
12628         free_cntrs(dd);
12629         return -ENOMEM;
12630 }
12631
12632 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate)
12633 {
12634         switch (chip_lstate) {
12635         default:
12636                 dd_dev_err(dd,
12637                            "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n",
12638                            chip_lstate);
12639                 /* fall through */
12640         case LSTATE_DOWN:
12641                 return IB_PORT_DOWN;
12642         case LSTATE_INIT:
12643                 return IB_PORT_INIT;
12644         case LSTATE_ARMED:
12645                 return IB_PORT_ARMED;
12646         case LSTATE_ACTIVE:
12647                 return IB_PORT_ACTIVE;
12648         }
12649 }
12650
12651 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate)
12652 {
12653         /* look at the HFI meta-states only */
12654         switch (chip_pstate & 0xf0) {
12655         default:
12656                 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n",
12657                            chip_pstate);
12658                 /* fall through */
12659         case PLS_DISABLED:
12660                 return IB_PORTPHYSSTATE_DISABLED;
12661         case PLS_OFFLINE:
12662                 return OPA_PORTPHYSSTATE_OFFLINE;
12663         case PLS_POLLING:
12664                 return IB_PORTPHYSSTATE_POLLING;
12665         case PLS_CONFIGPHY:
12666                 return IB_PORTPHYSSTATE_TRAINING;
12667         case PLS_LINKUP:
12668                 return IB_PORTPHYSSTATE_LINKUP;
12669         case PLS_PHYTEST:
12670                 return IB_PORTPHYSSTATE_PHY_TEST;
12671         }
12672 }
12673
12674 /* return the OPA port logical state name */
12675 const char *opa_lstate_name(u32 lstate)
12676 {
12677         static const char * const port_logical_names[] = {
12678                 "PORT_NOP",
12679                 "PORT_DOWN",
12680                 "PORT_INIT",
12681                 "PORT_ARMED",
12682                 "PORT_ACTIVE",
12683                 "PORT_ACTIVE_DEFER",
12684         };
12685         if (lstate < ARRAY_SIZE(port_logical_names))
12686                 return port_logical_names[lstate];
12687         return "unknown";
12688 }
12689
12690 /* return the OPA port physical state name */
12691 const char *opa_pstate_name(u32 pstate)
12692 {
12693         static const char * const port_physical_names[] = {
12694                 "PHYS_NOP",
12695                 "reserved1",
12696                 "PHYS_POLL",
12697                 "PHYS_DISABLED",
12698                 "PHYS_TRAINING",
12699                 "PHYS_LINKUP",
12700                 "PHYS_LINK_ERR_RECOVER",
12701                 "PHYS_PHY_TEST",
12702                 "reserved8",
12703                 "PHYS_OFFLINE",
12704                 "PHYS_GANGED",
12705                 "PHYS_TEST",
12706         };
12707         if (pstate < ARRAY_SIZE(port_physical_names))
12708                 return port_physical_names[pstate];
12709         return "unknown";
12710 }
12711
12712 /**
12713  * update_statusp - Update userspace status flag
12714  * @ppd: Port data structure
12715  * @state: port state information
12716  *
12717  * Actual port status is determined by the host_link_state value
12718  * in the ppd.
12719  *
12720  * host_link_state MUST be updated before updating the user space
12721  * statusp.
12722  */
12723 static void update_statusp(struct hfi1_pportdata *ppd, u32 state)
12724 {
12725         /*
12726          * Set port status flags in the page mapped into userspace
12727          * memory. Do it here to ensure a reliable state - this is
12728          * the only function called by all state handling code.
12729          * Always set the flags due to the fact that the cache value
12730          * might have been changed explicitly outside of this
12731          * function.
12732          */
12733         if (ppd->statusp) {
12734                 switch (state) {
12735                 case IB_PORT_DOWN:
12736                 case IB_PORT_INIT:
12737                         *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
12738                                            HFI1_STATUS_IB_READY);
12739                         break;
12740                 case IB_PORT_ARMED:
12741                         *ppd->statusp |= HFI1_STATUS_IB_CONF;
12742                         break;
12743                 case IB_PORT_ACTIVE:
12744                         *ppd->statusp |= HFI1_STATUS_IB_READY;
12745                         break;
12746                 }
12747         }
12748         dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n",
12749                     opa_lstate_name(state), state);
12750 }
12751
12752 /**
12753  * wait_logical_linkstate - wait for an IB link state change to occur
12754  * @ppd: port device
12755  * @state: the state to wait for
12756  * @msecs: the number of milliseconds to wait
12757  *
12758  * Wait up to msecs milliseconds for IB link state change to occur.
12759  * For now, take the easy polling route.
12760  * Returns 0 if state reached, otherwise -ETIMEDOUT.
12761  */
12762 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
12763                                   int msecs)
12764 {
12765         unsigned long timeout;
12766         u32 new_state;
12767
12768         timeout = jiffies + msecs_to_jiffies(msecs);
12769         while (1) {
12770                 new_state = chip_to_opa_lstate(ppd->dd,
12771                                                read_logical_state(ppd->dd));
12772                 if (new_state == state)
12773                         break;
12774                 if (time_after(jiffies, timeout)) {
12775                         dd_dev_err(ppd->dd,
12776                                    "timeout waiting for link state 0x%x\n",
12777                                    state);
12778                         return -ETIMEDOUT;
12779                 }
12780                 msleep(20);
12781         }
12782
12783         return 0;
12784 }
12785
12786 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state)
12787 {
12788         u32 ib_pstate = chip_to_opa_pstate(ppd->dd, state);
12789
12790         dd_dev_info(ppd->dd,
12791                     "physical state changed to %s (0x%x), phy 0x%x\n",
12792                     opa_pstate_name(ib_pstate), ib_pstate, state);
12793 }
12794
12795 /*
12796  * Read the physical hardware link state and check if it matches host
12797  * drivers anticipated state.
12798  */
12799 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state)
12800 {
12801         u32 read_state = read_physical_state(ppd->dd);
12802
12803         if (read_state == state) {
12804                 log_state_transition(ppd, state);
12805         } else {
12806                 dd_dev_err(ppd->dd,
12807                            "anticipated phy link state 0x%x, read 0x%x\n",
12808                            state, read_state);
12809         }
12810 }
12811
12812 /*
12813  * wait_physical_linkstate - wait for an physical link state change to occur
12814  * @ppd: port device
12815  * @state: the state to wait for
12816  * @msecs: the number of milliseconds to wait
12817  *
12818  * Wait up to msecs milliseconds for physical link state change to occur.
12819  * Returns 0 if state reached, otherwise -ETIMEDOUT.
12820  */
12821 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state,
12822                                    int msecs)
12823 {
12824         u32 read_state;
12825         unsigned long timeout;
12826
12827         timeout = jiffies + msecs_to_jiffies(msecs);
12828         while (1) {
12829                 read_state = read_physical_state(ppd->dd);
12830                 if (read_state == state)
12831                         break;
12832                 if (time_after(jiffies, timeout)) {
12833                         dd_dev_err(ppd->dd,
12834                                    "timeout waiting for phy link state 0x%x\n",
12835                                    state);
12836                         return -ETIMEDOUT;
12837                 }
12838                 usleep_range(1950, 2050); /* sleep 2ms-ish */
12839         }
12840
12841         log_state_transition(ppd, state);
12842         return 0;
12843 }
12844
12845 /*
12846  * wait_phys_link_offline_quiet_substates - wait for any offline substate
12847  * @ppd: port device
12848  * @msecs: the number of milliseconds to wait
12849  *
12850  * Wait up to msecs milliseconds for any offline physical link
12851  * state change to occur.
12852  * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT.
12853  */
12854 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd,
12855                                             int msecs)
12856 {
12857         u32 read_state;
12858         unsigned long timeout;
12859
12860         timeout = jiffies + msecs_to_jiffies(msecs);
12861         while (1) {
12862                 read_state = read_physical_state(ppd->dd);
12863                 if ((read_state & 0xF0) == PLS_OFFLINE)
12864                         break;
12865                 if (time_after(jiffies, timeout)) {
12866                         dd_dev_err(ppd->dd,
12867                                    "timeout waiting for phy link offline.quiet substates. Read state 0x%x, %dms\n",
12868                                    read_state, msecs);
12869                         return -ETIMEDOUT;
12870                 }
12871                 usleep_range(1950, 2050); /* sleep 2ms-ish */
12872         }
12873
12874         log_state_transition(ppd, read_state);
12875         return read_state;
12876 }
12877
12878 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
12879 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12880
12881 #define SET_STATIC_RATE_CONTROL_SMASK(r) \
12882 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12883
12884 void hfi1_init_ctxt(struct send_context *sc)
12885 {
12886         if (sc) {
12887                 struct hfi1_devdata *dd = sc->dd;
12888                 u64 reg;
12889                 u8 set = (sc->type == SC_USER ?
12890                           HFI1_CAP_IS_USET(STATIC_RATE_CTRL) :
12891                           HFI1_CAP_IS_KSET(STATIC_RATE_CTRL));
12892                 reg = read_kctxt_csr(dd, sc->hw_context,
12893                                      SEND_CTXT_CHECK_ENABLE);
12894                 if (set)
12895                         CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
12896                 else
12897                         SET_STATIC_RATE_CONTROL_SMASK(reg);
12898                 write_kctxt_csr(dd, sc->hw_context,
12899                                 SEND_CTXT_CHECK_ENABLE, reg);
12900         }
12901 }
12902
12903 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp)
12904 {
12905         int ret = 0;
12906         u64 reg;
12907
12908         if (dd->icode != ICODE_RTL_SILICON) {
12909                 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
12910                         dd_dev_info(dd, "%s: tempsense not supported by HW\n",
12911                                     __func__);
12912                 return -EINVAL;
12913         }
12914         reg = read_csr(dd, ASIC_STS_THERM);
12915         temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) &
12916                       ASIC_STS_THERM_CURR_TEMP_MASK);
12917         temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) &
12918                         ASIC_STS_THERM_LO_TEMP_MASK);
12919         temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) &
12920                         ASIC_STS_THERM_HI_TEMP_MASK);
12921         temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) &
12922                           ASIC_STS_THERM_CRIT_TEMP_MASK);
12923         /* triggers is a 3-bit value - 1 bit per trigger. */
12924         temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7);
12925
12926         return ret;
12927 }
12928
12929 /**
12930  * get_int_mask - get 64 bit int mask
12931  * @dd - the devdata
12932  * @i - the csr (relative to CCE_INT_MASK)
12933  *
12934  * Returns the mask with the urgent interrupt mask
12935  * bit clear for kernel receive contexts.
12936  */
12937 static u64 get_int_mask(struct hfi1_devdata *dd, u32 i)
12938 {
12939         u64 mask = U64_MAX; /* default to no change */
12940
12941         if (i >= (IS_RCVURGENT_START / 64) && i < (IS_RCVURGENT_END / 64)) {
12942                 int j = (i - (IS_RCVURGENT_START / 64)) * 64;
12943                 int k = !j ? IS_RCVURGENT_START % 64 : 0;
12944
12945                 if (j)
12946                         j -= IS_RCVURGENT_START % 64;
12947                 /* j = 0..dd->first_dyn_alloc_ctxt - 1,k = 0..63 */
12948                 for (; j < dd->first_dyn_alloc_ctxt && k < 64; j++, k++)
12949                         /* convert to bit in mask and clear */
12950                         mask &= ~BIT_ULL(k);
12951         }
12952         return mask;
12953 }
12954
12955 /* ========================================================================= */
12956
12957 /*
12958  * Enable/disable chip from delivering interrupts.
12959  */
12960 void set_intr_state(struct hfi1_devdata *dd, u32 enable)
12961 {
12962         int i;
12963
12964         /*
12965          * In HFI, the mask needs to be 1 to allow interrupts.
12966          */
12967         if (enable) {
12968                 /* enable all interrupts but urgent on kernel contexts */
12969                 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
12970                         u64 mask = get_int_mask(dd, i);
12971
12972                         write_csr(dd, CCE_INT_MASK + (8 * i), mask);
12973                 }
12974
12975                 init_qsfp_int(dd);
12976         } else {
12977                 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12978                         write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
12979         }
12980 }
12981
12982 /*
12983  * Clear all interrupt sources on the chip.
12984  */
12985 static void clear_all_interrupts(struct hfi1_devdata *dd)
12986 {
12987         int i;
12988
12989         for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12990                 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
12991
12992         write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
12993         write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
12994         write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
12995         write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
12996         write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
12997         write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
12998         write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
12999         for (i = 0; i < dd->chip_send_contexts; i++)
13000                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0);
13001         for (i = 0; i < dd->chip_sdma_engines; i++)
13002                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0);
13003
13004         write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
13005         write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
13006         write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
13007 }
13008
13009 /* Move to pcie.c? */
13010 static void disable_intx(struct pci_dev *pdev)
13011 {
13012         pci_intx(pdev, 0);
13013 }
13014
13015 /**
13016  * hfi1_clean_up_interrupts() - Free all IRQ resources
13017  * @dd: valid device data data structure
13018  *
13019  * Free the MSI or INTx IRQs and assoicated PCI resources,
13020  * if they have been allocated.
13021  */
13022 void hfi1_clean_up_interrupts(struct hfi1_devdata *dd)
13023 {
13024         int i;
13025
13026         /* remove irqs - must happen before disabling/turning off */
13027         if (dd->num_msix_entries) {
13028                 /* MSI-X */
13029                 struct hfi1_msix_entry *me = dd->msix_entries;
13030
13031                 for (i = 0; i < dd->num_msix_entries; i++, me++) {
13032                         if (!me->arg) /* => no irq, no affinity */
13033                                 continue;
13034                         hfi1_put_irq_affinity(dd, me);
13035                         pci_free_irq(dd->pcidev, i, me->arg);
13036                 }
13037
13038                 /* clean structures */
13039                 kfree(dd->msix_entries);
13040                 dd->msix_entries = NULL;
13041                 dd->num_msix_entries = 0;
13042         } else {
13043                 /* INTx */
13044                 if (dd->requested_intx_irq) {
13045                         pci_free_irq(dd->pcidev, 0, dd);
13046                         dd->requested_intx_irq = 0;
13047                 }
13048                 disable_intx(dd->pcidev);
13049         }
13050
13051         pci_free_irq_vectors(dd->pcidev);
13052 }
13053
13054 /*
13055  * Remap the interrupt source from the general handler to the given MSI-X
13056  * interrupt.
13057  */
13058 static void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr)
13059 {
13060         u64 reg;
13061         int m, n;
13062
13063         /* clear from the handled mask of the general interrupt */
13064         m = isrc / 64;
13065         n = isrc % 64;
13066         if (likely(m < CCE_NUM_INT_CSRS)) {
13067                 dd->gi_mask[m] &= ~((u64)1 << n);
13068         } else {
13069                 dd_dev_err(dd, "remap interrupt err\n");
13070                 return;
13071         }
13072
13073         /* direct the chip source to the given MSI-X interrupt */
13074         m = isrc / 8;
13075         n = isrc % 8;
13076         reg = read_csr(dd, CCE_INT_MAP + (8 * m));
13077         reg &= ~((u64)0xff << (8 * n));
13078         reg |= ((u64)msix_intr & 0xff) << (8 * n);
13079         write_csr(dd, CCE_INT_MAP + (8 * m), reg);
13080 }
13081
13082 static void remap_sdma_interrupts(struct hfi1_devdata *dd,
13083                                   int engine, int msix_intr)
13084 {
13085         /*
13086          * SDMA engine interrupt sources grouped by type, rather than
13087          * engine.  Per-engine interrupts are as follows:
13088          *      SDMA
13089          *      SDMAProgress
13090          *      SDMAIdle
13091          */
13092         remap_intr(dd, IS_SDMA_START + 0 * TXE_NUM_SDMA_ENGINES + engine,
13093                    msix_intr);
13094         remap_intr(dd, IS_SDMA_START + 1 * TXE_NUM_SDMA_ENGINES + engine,
13095                    msix_intr);
13096         remap_intr(dd, IS_SDMA_START + 2 * TXE_NUM_SDMA_ENGINES + engine,
13097                    msix_intr);
13098 }
13099
13100 static int request_intx_irq(struct hfi1_devdata *dd)
13101 {
13102         int ret;
13103
13104         ret = pci_request_irq(dd->pcidev, 0, general_interrupt, NULL, dd,
13105                               DRIVER_NAME "_%d", dd->unit);
13106         if (ret)
13107                 dd_dev_err(dd, "unable to request INTx interrupt, err %d\n",
13108                            ret);
13109         else
13110                 dd->requested_intx_irq = 1;
13111         return ret;
13112 }
13113
13114 static int request_msix_irqs(struct hfi1_devdata *dd)
13115 {
13116         int first_general, last_general;
13117         int first_sdma, last_sdma;
13118         int first_rx, last_rx;
13119         int i, ret = 0;
13120
13121         /* calculate the ranges we are going to use */
13122         first_general = 0;
13123         last_general = first_general + 1;
13124         first_sdma = last_general;
13125         last_sdma = first_sdma + dd->num_sdma;
13126         first_rx = last_sdma;
13127         last_rx = first_rx + dd->n_krcv_queues + dd->num_vnic_contexts;
13128
13129         /* VNIC MSIx interrupts get mapped when VNIC contexts are created */
13130         dd->first_dyn_msix_idx = first_rx + dd->n_krcv_queues;
13131
13132         /*
13133          * Sanity check - the code expects all SDMA chip source
13134          * interrupts to be in the same CSR, starting at bit 0.  Verify
13135          * that this is true by checking the bit location of the start.
13136          */
13137         BUILD_BUG_ON(IS_SDMA_START % 64);
13138
13139         for (i = 0; i < dd->num_msix_entries; i++) {
13140                 struct hfi1_msix_entry *me = &dd->msix_entries[i];
13141                 const char *err_info;
13142                 irq_handler_t handler;
13143                 irq_handler_t thread = NULL;
13144                 void *arg = NULL;
13145                 int idx;
13146                 struct hfi1_ctxtdata *rcd = NULL;
13147                 struct sdma_engine *sde = NULL;
13148                 char name[MAX_NAME_SIZE];
13149
13150                 /* obtain the arguments to pci_request_irq */
13151                 if (first_general <= i && i < last_general) {
13152                         idx = i - first_general;
13153                         handler = general_interrupt;
13154                         arg = dd;
13155                         snprintf(name, sizeof(name),
13156                                  DRIVER_NAME "_%d", dd->unit);
13157                         err_info = "general";
13158                         me->type = IRQ_GENERAL;
13159                 } else if (first_sdma <= i && i < last_sdma) {
13160                         idx = i - first_sdma;
13161                         sde = &dd->per_sdma[idx];
13162                         handler = sdma_interrupt;
13163                         arg = sde;
13164                         snprintf(name, sizeof(name),
13165                                  DRIVER_NAME "_%d sdma%d", dd->unit, idx);
13166                         err_info = "sdma";
13167                         remap_sdma_interrupts(dd, idx, i);
13168                         me->type = IRQ_SDMA;
13169                 } else if (first_rx <= i && i < last_rx) {
13170                         idx = i - first_rx;
13171                         rcd = hfi1_rcd_get_by_index_safe(dd, idx);
13172                         if (rcd) {
13173                                 /*
13174                                  * Set the interrupt register and mask for this
13175                                  * context's interrupt.
13176                                  */
13177                                 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64;
13178                                 rcd->imask = ((u64)1) <<
13179                                           ((IS_RCVAVAIL_START + idx) % 64);
13180                                 handler = receive_context_interrupt;
13181                                 thread = receive_context_thread;
13182                                 arg = rcd;
13183                                 snprintf(name, sizeof(name),
13184                                          DRIVER_NAME "_%d kctxt%d",
13185                                          dd->unit, idx);
13186                                 err_info = "receive context";
13187                                 remap_intr(dd, IS_RCVAVAIL_START + idx, i);
13188                                 me->type = IRQ_RCVCTXT;
13189                                 rcd->msix_intr = i;
13190                                 hfi1_rcd_put(rcd);
13191                         }
13192                 } else {
13193                         /* not in our expected range - complain, then
13194                          * ignore it
13195                          */
13196                         dd_dev_err(dd,
13197                                    "Unexpected extra MSI-X interrupt %d\n", i);
13198                         continue;
13199                 }
13200                 /* no argument, no interrupt */
13201                 if (!arg)
13202                         continue;
13203                 /* make sure the name is terminated */
13204                 name[sizeof(name) - 1] = 0;
13205                 me->irq = pci_irq_vector(dd->pcidev, i);
13206                 ret = pci_request_irq(dd->pcidev, i, handler, thread, arg,
13207                                       name);
13208                 if (ret) {
13209                         dd_dev_err(dd,
13210                                    "unable to allocate %s interrupt, irq %d, index %d, err %d\n",
13211                                    err_info, me->irq, idx, ret);
13212                         return ret;
13213                 }
13214                 /*
13215                  * assign arg after pci_request_irq call, so it will be
13216                  * cleaned up
13217                  */
13218                 me->arg = arg;
13219
13220                 ret = hfi1_get_irq_affinity(dd, me);
13221                 if (ret)
13222                         dd_dev_err(dd, "unable to pin IRQ %d\n", ret);
13223         }
13224
13225         return ret;
13226 }
13227
13228 void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd)
13229 {
13230         int i;
13231
13232         if (!dd->num_msix_entries) {
13233                 synchronize_irq(pci_irq_vector(dd->pcidev, 0));
13234                 return;
13235         }
13236
13237         for (i = 0; i < dd->vnic.num_ctxt; i++) {
13238                 struct hfi1_ctxtdata *rcd = dd->vnic.ctxt[i];
13239                 struct hfi1_msix_entry *me = &dd->msix_entries[rcd->msix_intr];
13240
13241                 synchronize_irq(me->irq);
13242         }
13243 }
13244
13245 void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd)
13246 {
13247         struct hfi1_devdata *dd = rcd->dd;
13248         struct hfi1_msix_entry *me = &dd->msix_entries[rcd->msix_intr];
13249
13250         if (!me->arg) /* => no irq, no affinity */
13251                 return;
13252
13253         hfi1_put_irq_affinity(dd, me);
13254         pci_free_irq(dd->pcidev, rcd->msix_intr, me->arg);
13255
13256         me->arg = NULL;
13257 }
13258
13259 void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd)
13260 {
13261         struct hfi1_devdata *dd = rcd->dd;
13262         struct hfi1_msix_entry *me;
13263         int idx = rcd->ctxt;
13264         void *arg = rcd;
13265         int ret;
13266
13267         rcd->msix_intr = dd->vnic.msix_idx++;
13268         me = &dd->msix_entries[rcd->msix_intr];
13269
13270         /*
13271          * Set the interrupt register and mask for this
13272          * context's interrupt.
13273          */
13274         rcd->ireg = (IS_RCVAVAIL_START + idx) / 64;
13275         rcd->imask = ((u64)1) <<
13276                   ((IS_RCVAVAIL_START + idx) % 64);
13277         me->type = IRQ_RCVCTXT;
13278         me->irq = pci_irq_vector(dd->pcidev, rcd->msix_intr);
13279         remap_intr(dd, IS_RCVAVAIL_START + idx, rcd->msix_intr);
13280
13281         ret = pci_request_irq(dd->pcidev, rcd->msix_intr,
13282                               receive_context_interrupt,
13283                               receive_context_thread, arg,
13284                               DRIVER_NAME "_%d kctxt%d", dd->unit, idx);
13285         if (ret) {
13286                 dd_dev_err(dd, "vnic irq request (irq %d, idx %d) fail %d\n",
13287                            me->irq, idx, ret);
13288                 return;
13289         }
13290         /*
13291          * assign arg after pci_request_irq call, so it will be
13292          * cleaned up
13293          */
13294         me->arg = arg;
13295
13296         ret = hfi1_get_irq_affinity(dd, me);
13297         if (ret) {
13298                 dd_dev_err(dd,
13299                            "unable to pin IRQ %d\n", ret);
13300                 pci_free_irq(dd->pcidev, rcd->msix_intr, me->arg);
13301         }
13302 }
13303
13304 /*
13305  * Set the general handler to accept all interrupts, remap all
13306  * chip interrupts back to MSI-X 0.
13307  */
13308 static void reset_interrupts(struct hfi1_devdata *dd)
13309 {
13310         int i;
13311
13312         /* all interrupts handled by the general handler */
13313         for (i = 0; i < CCE_NUM_INT_CSRS; i++)
13314                 dd->gi_mask[i] = ~(u64)0;
13315
13316         /* all chip interrupts map to MSI-X 0 */
13317         for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13318                 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
13319 }
13320
13321 static int set_up_interrupts(struct hfi1_devdata *dd)
13322 {
13323         u32 total;
13324         int ret, request;
13325         int single_interrupt = 0; /* we expect to have all the interrupts */
13326
13327         /*
13328          * Interrupt count:
13329          *      1 general, "slow path" interrupt (includes the SDMA engines
13330          *              slow source, SDMACleanupDone)
13331          *      N interrupts - one per used SDMA engine
13332          *      M interrupt - one per kernel receive context
13333          *      V interrupt - one for each VNIC context
13334          */
13335         total = 1 + dd->num_sdma + dd->n_krcv_queues + dd->num_vnic_contexts;
13336
13337         /* ask for MSI-X interrupts */
13338         request = request_msix(dd, total);
13339         if (request < 0) {
13340                 ret = request;
13341                 goto fail;
13342         } else if (request == 0) {
13343                 /* using INTx */
13344                 /* dd->num_msix_entries already zero */
13345                 single_interrupt = 1;
13346                 dd_dev_err(dd, "MSI-X failed, using INTx interrupts\n");
13347         } else if (request < total) {
13348                 /* using MSI-X, with reduced interrupts */
13349                 dd_dev_err(dd, "reduced interrupt found, wanted %u, got %u\n",
13350                            total, request);
13351                 ret = -EINVAL;
13352                 goto fail;
13353         } else {
13354                 dd->msix_entries = kcalloc(total, sizeof(*dd->msix_entries),
13355                                            GFP_KERNEL);
13356                 if (!dd->msix_entries) {
13357                         ret = -ENOMEM;
13358                         goto fail;
13359                 }
13360                 /* using MSI-X */
13361                 dd->num_msix_entries = total;
13362                 dd_dev_info(dd, "%u MSI-X interrupts allocated\n", total);
13363         }
13364
13365         /* mask all interrupts */
13366         set_intr_state(dd, 0);
13367         /* clear all pending interrupts */
13368         clear_all_interrupts(dd);
13369
13370         /* reset general handler mask, chip MSI-X mappings */
13371         reset_interrupts(dd);
13372
13373         if (single_interrupt)
13374                 ret = request_intx_irq(dd);
13375         else
13376                 ret = request_msix_irqs(dd);
13377         if (ret)
13378                 goto fail;
13379
13380         return 0;
13381
13382 fail:
13383         hfi1_clean_up_interrupts(dd);
13384         return ret;
13385 }
13386
13387 /*
13388  * Set up context values in dd.  Sets:
13389  *
13390  *      num_rcv_contexts - number of contexts being used
13391  *      n_krcv_queues - number of kernel contexts
13392  *      first_dyn_alloc_ctxt - first dynamically allocated context
13393  *                             in array of contexts
13394  *      freectxts  - number of free user contexts
13395  *      num_send_contexts - number of PIO send contexts being used
13396  *      num_vnic_contexts - number of contexts reserved for VNIC
13397  */
13398 static int set_up_context_variables(struct hfi1_devdata *dd)
13399 {
13400         unsigned long num_kernel_contexts;
13401         u16 num_vnic_contexts = HFI1_NUM_VNIC_CTXT;
13402         int total_contexts;
13403         int ret;
13404         unsigned ngroups;
13405         int qos_rmt_count;
13406         int user_rmt_reduced;
13407         u32 n_usr_ctxts;
13408
13409         /*
13410          * Kernel receive contexts:
13411          * - Context 0 - control context (VL15/multicast/error)
13412          * - Context 1 - first kernel context
13413          * - Context 2 - second kernel context
13414          * ...
13415          */
13416         if (n_krcvqs)
13417                 /*
13418                  * n_krcvqs is the sum of module parameter kernel receive
13419                  * contexts, krcvqs[].  It does not include the control
13420                  * context, so add that.
13421                  */
13422                 num_kernel_contexts = n_krcvqs + 1;
13423         else
13424                 num_kernel_contexts = DEFAULT_KRCVQS + 1;
13425         /*
13426          * Every kernel receive context needs an ACK send context.
13427          * one send context is allocated for each VL{0-7} and VL15
13428          */
13429         if (num_kernel_contexts > (dd->chip_send_contexts - num_vls - 1)) {
13430                 dd_dev_err(dd,
13431                            "Reducing # kernel rcv contexts to: %d, from %lu\n",
13432                            (int)(dd->chip_send_contexts - num_vls - 1),
13433                            num_kernel_contexts);
13434                 num_kernel_contexts = dd->chip_send_contexts - num_vls - 1;
13435         }
13436
13437         /* Accommodate VNIC contexts if possible */
13438         if ((num_kernel_contexts + num_vnic_contexts) > dd->chip_rcv_contexts) {
13439                 dd_dev_err(dd, "No receive contexts available for VNIC\n");
13440                 num_vnic_contexts = 0;
13441         }
13442         total_contexts = num_kernel_contexts + num_vnic_contexts;
13443
13444         /*
13445          * User contexts:
13446          *      - default to 1 user context per real (non-HT) CPU core if
13447          *        num_user_contexts is negative
13448          */
13449         if (num_user_contexts < 0)
13450                 n_usr_ctxts = cpumask_weight(&node_affinity.real_cpu_mask);
13451         else
13452                 n_usr_ctxts = num_user_contexts;
13453         /*
13454          * Adjust the counts given a global max.
13455          */
13456         if (total_contexts + n_usr_ctxts > dd->chip_rcv_contexts) {
13457                 dd_dev_err(dd,
13458                            "Reducing # user receive contexts to: %d, from %u\n",
13459                            (int)(dd->chip_rcv_contexts - total_contexts),
13460                            n_usr_ctxts);
13461                 /* recalculate */
13462                 n_usr_ctxts = dd->chip_rcv_contexts - total_contexts;
13463         }
13464
13465         /* each user context requires an entry in the RMT */
13466         qos_rmt_count = qos_rmt_entries(dd, NULL, NULL);
13467         if (qos_rmt_count + n_usr_ctxts > NUM_MAP_ENTRIES) {
13468                 user_rmt_reduced = NUM_MAP_ENTRIES - qos_rmt_count;
13469                 dd_dev_err(dd,
13470                            "RMT size is reducing the number of user receive contexts from %u to %d\n",
13471                            n_usr_ctxts,
13472                            user_rmt_reduced);
13473                 /* recalculate */
13474                 n_usr_ctxts = user_rmt_reduced;
13475         }
13476
13477         total_contexts += n_usr_ctxts;
13478
13479         /* the first N are kernel contexts, the rest are user/vnic contexts */
13480         dd->num_rcv_contexts = total_contexts;
13481         dd->n_krcv_queues = num_kernel_contexts;
13482         dd->first_dyn_alloc_ctxt = num_kernel_contexts;
13483         dd->num_vnic_contexts = num_vnic_contexts;
13484         dd->num_user_contexts = n_usr_ctxts;
13485         dd->freectxts = n_usr_ctxts;
13486         dd_dev_info(dd,
13487                     "rcv contexts: chip %d, used %d (kernel %d, vnic %u, user %u)\n",
13488                     (int)dd->chip_rcv_contexts,
13489                     (int)dd->num_rcv_contexts,
13490                     (int)dd->n_krcv_queues,
13491                     dd->num_vnic_contexts,
13492                     dd->num_user_contexts);
13493
13494         /*
13495          * Receive array allocation:
13496          *   All RcvArray entries are divided into groups of 8. This
13497          *   is required by the hardware and will speed up writes to
13498          *   consecutive entries by using write-combining of the entire
13499          *   cacheline.
13500          *
13501          *   The number of groups are evenly divided among all contexts.
13502          *   any left over groups will be given to the first N user
13503          *   contexts.
13504          */
13505         dd->rcv_entries.group_size = RCV_INCREMENT;
13506         ngroups = dd->chip_rcv_array_count / dd->rcv_entries.group_size;
13507         dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts;
13508         dd->rcv_entries.nctxt_extra = ngroups -
13509                 (dd->num_rcv_contexts * dd->rcv_entries.ngroups);
13510         dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n",
13511                     dd->rcv_entries.ngroups,
13512                     dd->rcv_entries.nctxt_extra);
13513         if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size >
13514             MAX_EAGER_ENTRIES * 2) {
13515                 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) /
13516                         dd->rcv_entries.group_size;
13517                 dd_dev_info(dd,
13518                             "RcvArray group count too high, change to %u\n",
13519                             dd->rcv_entries.ngroups);
13520                 dd->rcv_entries.nctxt_extra = 0;
13521         }
13522         /*
13523          * PIO send contexts
13524          */
13525         ret = init_sc_pools_and_sizes(dd);
13526         if (ret >= 0) { /* success */
13527                 dd->num_send_contexts = ret;
13528                 dd_dev_info(
13529                         dd,
13530                         "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n",
13531                         dd->chip_send_contexts,
13532                         dd->num_send_contexts,
13533                         dd->sc_sizes[SC_KERNEL].count,
13534                         dd->sc_sizes[SC_ACK].count,
13535                         dd->sc_sizes[SC_USER].count,
13536                         dd->sc_sizes[SC_VL15].count);
13537                 ret = 0;        /* success */
13538         }
13539
13540         return ret;
13541 }
13542
13543 /*
13544  * Set the device/port partition key table. The MAD code
13545  * will ensure that, at least, the partial management
13546  * partition key is present in the table.
13547  */
13548 static void set_partition_keys(struct hfi1_pportdata *ppd)
13549 {
13550         struct hfi1_devdata *dd = ppd->dd;
13551         u64 reg = 0;
13552         int i;
13553
13554         dd_dev_info(dd, "Setting partition keys\n");
13555         for (i = 0; i < hfi1_get_npkeys(dd); i++) {
13556                 reg |= (ppd->pkeys[i] &
13557                         RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
13558                         ((i % 4) *
13559                          RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
13560                 /* Each register holds 4 PKey values. */
13561                 if ((i % 4) == 3) {
13562                         write_csr(dd, RCV_PARTITION_KEY +
13563                                   ((i - 3) * 2), reg);
13564                         reg = 0;
13565                 }
13566         }
13567
13568         /* Always enable HW pkeys check when pkeys table is set */
13569         add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK);
13570 }
13571
13572 /*
13573  * These CSRs and memories are uninitialized on reset and must be
13574  * written before reading to set the ECC/parity bits.
13575  *
13576  * NOTE: All user context CSRs that are not mmaped write-only
13577  * (e.g. the TID flows) must be initialized even if the driver never
13578  * reads them.
13579  */
13580 static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd)
13581 {
13582         int i, j;
13583
13584         /* CceIntMap */
13585         for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13586                 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
13587
13588         /* SendCtxtCreditReturnAddr */
13589         for (i = 0; i < dd->chip_send_contexts; i++)
13590                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13591
13592         /* PIO Send buffers */
13593         /* SDMA Send buffers */
13594         /*
13595          * These are not normally read, and (presently) have no method
13596          * to be read, so are not pre-initialized
13597          */
13598
13599         /* RcvHdrAddr */
13600         /* RcvHdrTailAddr */
13601         /* RcvTidFlowTable */
13602         for (i = 0; i < dd->chip_rcv_contexts; i++) {
13603                 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13604                 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13605                 for (j = 0; j < RXE_NUM_TID_FLOWS; j++)
13606                         write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0);
13607         }
13608
13609         /* RcvArray */
13610         for (i = 0; i < dd->chip_rcv_array_count; i++)
13611                 hfi1_put_tid(dd, i, PT_INVALID_FLUSH, 0, 0);
13612
13613         /* RcvQPMapTable */
13614         for (i = 0; i < 32; i++)
13615                 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13616 }
13617
13618 /*
13619  * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13620  */
13621 static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits,
13622                              u64 ctrl_bits)
13623 {
13624         unsigned long timeout;
13625         u64 reg;
13626
13627         /* is the condition present? */
13628         reg = read_csr(dd, CCE_STATUS);
13629         if ((reg & status_bits) == 0)
13630                 return;
13631
13632         /* clear the condition */
13633         write_csr(dd, CCE_CTRL, ctrl_bits);
13634
13635         /* wait for the condition to clear */
13636         timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT);
13637         while (1) {
13638                 reg = read_csr(dd, CCE_STATUS);
13639                 if ((reg & status_bits) == 0)
13640                         return;
13641                 if (time_after(jiffies, timeout)) {
13642                         dd_dev_err(dd,
13643                                    "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
13644                                    status_bits, reg & status_bits);
13645                         return;
13646                 }
13647                 udelay(1);
13648         }
13649 }
13650
13651 /* set CCE CSRs to chip reset defaults */
13652 static void reset_cce_csrs(struct hfi1_devdata *dd)
13653 {
13654         int i;
13655
13656         /* CCE_REVISION read-only */
13657         /* CCE_REVISION2 read-only */
13658         /* CCE_CTRL - bits clear automatically */
13659         /* CCE_STATUS read-only, use CceCtrl to clear */
13660         clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK);
13661         clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK);
13662         clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK);
13663         for (i = 0; i < CCE_NUM_SCRATCH; i++)
13664                 write_csr(dd, CCE_SCRATCH + (8 * i), 0);
13665         /* CCE_ERR_STATUS read-only */
13666         write_csr(dd, CCE_ERR_MASK, 0);
13667         write_csr(dd, CCE_ERR_CLEAR, ~0ull);
13668         /* CCE_ERR_FORCE leave alone */
13669         for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++)
13670                 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
13671         write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
13672         /* CCE_PCIE_CTRL leave alone */
13673         for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) {
13674                 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
13675                 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
13676                           CCE_MSIX_TABLE_UPPER_RESETCSR);
13677         }
13678         for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) {
13679                 /* CCE_MSIX_PBA read-only */
13680                 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
13681                 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
13682         }
13683         for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13684                 write_csr(dd, CCE_INT_MAP, 0);
13685         for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
13686                 /* CCE_INT_STATUS read-only */
13687                 write_csr(dd, CCE_INT_MASK + (8 * i), 0);
13688                 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
13689                 /* CCE_INT_FORCE leave alone */
13690                 /* CCE_INT_BLOCKED read-only */
13691         }
13692         for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++)
13693                 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
13694 }
13695
13696 /* set MISC CSRs to chip reset defaults */
13697 static void reset_misc_csrs(struct hfi1_devdata *dd)
13698 {
13699         int i;
13700
13701         for (i = 0; i < 32; i++) {
13702                 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
13703                 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
13704                 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
13705         }
13706         /*
13707          * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
13708          * only be written 128-byte chunks
13709          */
13710         /* init RSA engine to clear lingering errors */
13711         write_csr(dd, MISC_CFG_RSA_CMD, 1);
13712         write_csr(dd, MISC_CFG_RSA_MU, 0);
13713         write_csr(dd, MISC_CFG_FW_CTRL, 0);
13714         /* MISC_STS_8051_DIGEST read-only */
13715         /* MISC_STS_SBM_DIGEST read-only */
13716         /* MISC_STS_PCIE_DIGEST read-only */
13717         /* MISC_STS_FAB_DIGEST read-only */
13718         /* MISC_ERR_STATUS read-only */
13719         write_csr(dd, MISC_ERR_MASK, 0);
13720         write_csr(dd, MISC_ERR_CLEAR, ~0ull);
13721         /* MISC_ERR_FORCE leave alone */
13722 }
13723
13724 /* set TXE CSRs to chip reset defaults */
13725 static void reset_txe_csrs(struct hfi1_devdata *dd)
13726 {
13727         int i;
13728
13729         /*
13730          * TXE Kernel CSRs
13731          */
13732         write_csr(dd, SEND_CTRL, 0);
13733         __cm_reset(dd, 0);      /* reset CM internal state */
13734         /* SEND_CONTEXTS read-only */
13735         /* SEND_DMA_ENGINES read-only */
13736         /* SEND_PIO_MEM_SIZE read-only */
13737         /* SEND_DMA_MEM_SIZE read-only */
13738         write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
13739         pio_reset_all(dd);      /* SEND_PIO_INIT_CTXT */
13740         /* SEND_PIO_ERR_STATUS read-only */
13741         write_csr(dd, SEND_PIO_ERR_MASK, 0);
13742         write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
13743         /* SEND_PIO_ERR_FORCE leave alone */
13744         /* SEND_DMA_ERR_STATUS read-only */
13745         write_csr(dd, SEND_DMA_ERR_MASK, 0);
13746         write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
13747         /* SEND_DMA_ERR_FORCE leave alone */
13748         /* SEND_EGRESS_ERR_STATUS read-only */
13749         write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
13750         write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
13751         /* SEND_EGRESS_ERR_FORCE leave alone */
13752         write_csr(dd, SEND_BTH_QP, 0);
13753         write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
13754         write_csr(dd, SEND_SC2VLT0, 0);
13755         write_csr(dd, SEND_SC2VLT1, 0);
13756         write_csr(dd, SEND_SC2VLT2, 0);
13757         write_csr(dd, SEND_SC2VLT3, 0);
13758         write_csr(dd, SEND_LEN_CHECK0, 0);
13759         write_csr(dd, SEND_LEN_CHECK1, 0);
13760         /* SEND_ERR_STATUS read-only */
13761         write_csr(dd, SEND_ERR_MASK, 0);
13762         write_csr(dd, SEND_ERR_CLEAR, ~0ull);
13763         /* SEND_ERR_FORCE read-only */
13764         for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++)
13765                 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
13766         for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++)
13767                 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
13768         for (i = 0; i < dd->chip_send_contexts / NUM_CONTEXTS_PER_SET; i++)
13769                 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
13770         for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++)
13771                 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
13772         for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++)
13773                 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
13774         write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
13775         write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR);
13776         /* SEND_CM_CREDIT_USED_STATUS read-only */
13777         write_csr(dd, SEND_CM_TIMER_CTRL, 0);
13778         write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
13779         write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
13780         write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
13781         write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
13782         for (i = 0; i < TXE_NUM_DATA_VL; i++)
13783                 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
13784         write_csr(dd, SEND_CM_CREDIT_VL15, 0);
13785         /* SEND_CM_CREDIT_USED_VL read-only */
13786         /* SEND_CM_CREDIT_USED_VL15 read-only */
13787         /* SEND_EGRESS_CTXT_STATUS read-only */
13788         /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13789         write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
13790         /* SEND_EGRESS_ERR_INFO read-only */
13791         /* SEND_EGRESS_ERR_SOURCE read-only */
13792
13793         /*
13794          * TXE Per-Context CSRs
13795          */
13796         for (i = 0; i < dd->chip_send_contexts; i++) {
13797                 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13798                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0);
13799                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13800                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0);
13801                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0);
13802                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull);
13803                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0);
13804                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0);
13805                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0);
13806                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0);
13807                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0);
13808                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0);
13809         }
13810
13811         /*
13812          * TXE Per-SDMA CSRs
13813          */
13814         for (i = 0; i < dd->chip_sdma_engines; i++) {
13815                 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13816                 /* SEND_DMA_STATUS read-only */
13817                 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0);
13818                 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0);
13819                 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0);
13820                 /* SEND_DMA_HEAD read-only */
13821                 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0);
13822                 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0);
13823                 /* SEND_DMA_IDLE_CNT read-only */
13824                 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0);
13825                 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0);
13826                 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13827                 /* SEND_DMA_ENG_ERR_STATUS read-only */
13828                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0);
13829                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull);
13830                 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13831                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0);
13832                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0);
13833                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0);
13834                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0);
13835                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0);
13836                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0);
13837                 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0);
13838         }
13839 }
13840
13841 /*
13842  * Expect on entry:
13843  * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13844  */
13845 static void init_rbufs(struct hfi1_devdata *dd)
13846 {
13847         u64 reg;
13848         int count;
13849
13850         /*
13851          * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13852          * clear.
13853          */
13854         count = 0;
13855         while (1) {
13856                 reg = read_csr(dd, RCV_STATUS);
13857                 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK
13858                             | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0)
13859                         break;
13860                 /*
13861                  * Give up after 1ms - maximum wait time.
13862                  *
13863                  * RBuf size is 136KiB.  Slowest possible is PCIe Gen1 x1 at
13864                  * 250MB/s bandwidth.  Lower rate to 66% for overhead to get:
13865                  *      136 KB / (66% * 250MB/s) = 844us
13866                  */
13867                 if (count++ > 500) {
13868                         dd_dev_err(dd,
13869                                    "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n",
13870                                    __func__, reg);
13871                         break;
13872                 }
13873                 udelay(2); /* do not busy-wait the CSR */
13874         }
13875
13876         /* start the init - expect RcvCtrl to be 0 */
13877         write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
13878
13879         /*
13880          * Read to force the write of Rcvtrl.RxRbufInit.  There is a brief
13881          * period after the write before RcvStatus.RxRbufInitDone is valid.
13882          * The delay in the first run through the loop below is sufficient and
13883          * required before the first read of RcvStatus.RxRbufInintDone.
13884          */
13885         read_csr(dd, RCV_CTRL);
13886
13887         /* wait for the init to finish */
13888         count = 0;
13889         while (1) {
13890                 /* delay is required first time through - see above */
13891                 udelay(2); /* do not busy-wait the CSR */
13892                 reg = read_csr(dd, RCV_STATUS);
13893                 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK))
13894                         break;
13895
13896                 /* give up after 100us - slowest possible at 33MHz is 73us */
13897                 if (count++ > 50) {
13898                         dd_dev_err(dd,
13899                                    "%s: RcvStatus.RxRbufInit not set, continuing\n",
13900                                    __func__);
13901                         break;
13902                 }
13903         }
13904 }
13905
13906 /* set RXE CSRs to chip reset defaults */
13907 static void reset_rxe_csrs(struct hfi1_devdata *dd)
13908 {
13909         int i, j;
13910
13911         /*
13912          * RXE Kernel CSRs
13913          */
13914         write_csr(dd, RCV_CTRL, 0);
13915         init_rbufs(dd);
13916         /* RCV_STATUS read-only */
13917         /* RCV_CONTEXTS read-only */
13918         /* RCV_ARRAY_CNT read-only */
13919         /* RCV_BUF_SIZE read-only */
13920         write_csr(dd, RCV_BTH_QP, 0);
13921         write_csr(dd, RCV_MULTICAST, 0);
13922         write_csr(dd, RCV_BYPASS, 0);
13923         write_csr(dd, RCV_VL15, 0);
13924         /* this is a clear-down */
13925         write_csr(dd, RCV_ERR_INFO,
13926                   RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
13927         /* RCV_ERR_STATUS read-only */
13928         write_csr(dd, RCV_ERR_MASK, 0);
13929         write_csr(dd, RCV_ERR_CLEAR, ~0ull);
13930         /* RCV_ERR_FORCE leave alone */
13931         for (i = 0; i < 32; i++)
13932                 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13933         for (i = 0; i < 4; i++)
13934                 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
13935         for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++)
13936                 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
13937         for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++)
13938                 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
13939         for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++)
13940                 clear_rsm_rule(dd, i);
13941         for (i = 0; i < 32; i++)
13942                 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
13943
13944         /*
13945          * RXE Kernel and User Per-Context CSRs
13946          */
13947         for (i = 0; i < dd->chip_rcv_contexts; i++) {
13948                 /* kernel */
13949                 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0);
13950                 /* RCV_CTXT_STATUS read-only */
13951                 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0);
13952                 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0);
13953                 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0);
13954                 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13955                 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0);
13956                 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0);
13957                 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0);
13958                 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13959                 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0);
13960                 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0);
13961
13962                 /* user */
13963                 /* RCV_HDR_TAIL read-only */
13964                 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0);
13965                 /* RCV_EGR_INDEX_TAIL read-only */
13966                 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0);
13967                 /* RCV_EGR_OFFSET_TAIL read-only */
13968                 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) {
13969                         write_uctxt_csr(dd, i,
13970                                         RCV_TID_FLOW_TABLE + (8 * j), 0);
13971                 }
13972         }
13973 }
13974
13975 /*
13976  * Set sc2vl tables.
13977  *
13978  * They power on to zeros, so to avoid send context errors
13979  * they need to be set:
13980  *
13981  * SC 0-7 -> VL 0-7 (respectively)
13982  * SC 15  -> VL 15
13983  * otherwise
13984  *        -> VL 0
13985  */
13986 static void init_sc2vl_tables(struct hfi1_devdata *dd)
13987 {
13988         int i;
13989         /* init per architecture spec, constrained by hardware capability */
13990
13991         /* HFI maps sent packets */
13992         write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
13993                 0,
13994                 0, 0, 1, 1,
13995                 2, 2, 3, 3,
13996                 4, 4, 5, 5,
13997                 6, 6, 7, 7));
13998         write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
13999                 1,
14000                 8, 0, 9, 0,
14001                 10, 0, 11, 0,
14002                 12, 0, 13, 0,
14003                 14, 0, 15, 15));
14004         write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
14005                 2,
14006                 16, 0, 17, 0,
14007                 18, 0, 19, 0,
14008                 20, 0, 21, 0,
14009                 22, 0, 23, 0));
14010         write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
14011                 3,
14012                 24, 0, 25, 0,
14013                 26, 0, 27, 0,
14014                 28, 0, 29, 0,
14015                 30, 0, 31, 0));
14016
14017         /* DC maps received packets */
14018         write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
14019                 15_0,
14020                 0, 0, 1, 1,  2, 2,  3, 3,  4, 4,  5, 5,  6, 6,  7,  7,
14021                 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15));
14022         write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
14023                 31_16,
14024                 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0,
14025                 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0));
14026
14027         /* initialize the cached sc2vl values consistently with h/w */
14028         for (i = 0; i < 32; i++) {
14029                 if (i < 8 || i == 15)
14030                         *((u8 *)(dd->sc2vl) + i) = (u8)i;
14031                 else
14032                         *((u8 *)(dd->sc2vl) + i) = 0;
14033         }
14034 }
14035
14036 /*
14037  * Read chip sizes and then reset parts to sane, disabled, values.  We cannot
14038  * depend on the chip going through a power-on reset - a driver may be loaded
14039  * and unloaded many times.
14040  *
14041  * Do not write any CSR values to the chip in this routine - there may be
14042  * a reset following the (possible) FLR in this routine.
14043  *
14044  */
14045 static int init_chip(struct hfi1_devdata *dd)
14046 {
14047         int i;
14048         int ret = 0;
14049
14050         /*
14051          * Put the HFI CSRs in a known state.
14052          * Combine this with a DC reset.
14053          *
14054          * Stop the device from doing anything while we do a
14055          * reset.  We know there are no other active users of
14056          * the device since we are now in charge.  Turn off
14057          * off all outbound and inbound traffic and make sure
14058          * the device does not generate any interrupts.
14059          */
14060
14061         /* disable send contexts and SDMA engines */
14062         write_csr(dd, SEND_CTRL, 0);
14063         for (i = 0; i < dd->chip_send_contexts; i++)
14064                 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
14065         for (i = 0; i < dd->chip_sdma_engines; i++)
14066                 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
14067         /* disable port (turn off RXE inbound traffic) and contexts */
14068         write_csr(dd, RCV_CTRL, 0);
14069         for (i = 0; i < dd->chip_rcv_contexts; i++)
14070                 write_csr(dd, RCV_CTXT_CTRL, 0);
14071         /* mask all interrupt sources */
14072         for (i = 0; i < CCE_NUM_INT_CSRS; i++)
14073                 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
14074
14075         /*
14076          * DC Reset: do a full DC reset before the register clear.
14077          * A recommended length of time to hold is one CSR read,
14078          * so reread the CceDcCtrl.  Then, hold the DC in reset
14079          * across the clear.
14080          */
14081         write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
14082         (void)read_csr(dd, CCE_DC_CTRL);
14083
14084         if (use_flr) {
14085                 /*
14086                  * A FLR will reset the SPC core and part of the PCIe.
14087                  * The parts that need to be restored have already been
14088                  * saved.
14089                  */
14090                 dd_dev_info(dd, "Resetting CSRs with FLR\n");
14091
14092                 /* do the FLR, the DC reset will remain */
14093                 pcie_flr(dd->pcidev);
14094
14095                 /* restore command and BARs */
14096                 ret = restore_pci_variables(dd);
14097                 if (ret) {
14098                         dd_dev_err(dd, "%s: Could not restore PCI variables\n",
14099                                    __func__);
14100                         return ret;
14101                 }
14102
14103                 if (is_ax(dd)) {
14104                         dd_dev_info(dd, "Resetting CSRs with FLR\n");
14105                         pcie_flr(dd->pcidev);
14106                         ret = restore_pci_variables(dd);
14107                         if (ret) {
14108                                 dd_dev_err(dd, "%s: Could not restore PCI variables\n",
14109                                            __func__);
14110                                 return ret;
14111                         }
14112                 }
14113         } else {
14114                 dd_dev_info(dd, "Resetting CSRs with writes\n");
14115                 reset_cce_csrs(dd);
14116                 reset_txe_csrs(dd);
14117                 reset_rxe_csrs(dd);
14118                 reset_misc_csrs(dd);
14119         }
14120         /* clear the DC reset */
14121         write_csr(dd, CCE_DC_CTRL, 0);
14122
14123         /* Set the LED off */
14124         setextled(dd, 0);
14125
14126         /*
14127          * Clear the QSFP reset.
14128          * An FLR enforces a 0 on all out pins. The driver does not touch
14129          * ASIC_QSFPn_OUT otherwise.  This leaves RESET_N low and
14130          * anything plugged constantly in reset, if it pays attention
14131          * to RESET_N.
14132          * Prime examples of this are optical cables. Set all pins high.
14133          * I2CCLK and I2CDAT will change per direction, and INT_N and
14134          * MODPRS_N are input only and their value is ignored.
14135          */
14136         write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
14137         write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
14138         init_chip_resources(dd);
14139         return ret;
14140 }
14141
14142 static void init_early_variables(struct hfi1_devdata *dd)
14143 {
14144         int i;
14145
14146         /* assign link credit variables */
14147         dd->vau = CM_VAU;
14148         dd->link_credits = CM_GLOBAL_CREDITS;
14149         if (is_ax(dd))
14150                 dd->link_credits--;
14151         dd->vcu = cu_to_vcu(hfi1_cu);
14152         /* enough room for 8 MAD packets plus header - 17K */
14153         dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau);
14154         if (dd->vl15_init > dd->link_credits)
14155                 dd->vl15_init = dd->link_credits;
14156
14157         write_uninitialized_csrs_and_memories(dd);
14158
14159         if (HFI1_CAP_IS_KSET(PKEY_CHECK))
14160                 for (i = 0; i < dd->num_pports; i++) {
14161                         struct hfi1_pportdata *ppd = &dd->pport[i];
14162
14163                         set_partition_keys(ppd);
14164                 }
14165         init_sc2vl_tables(dd);
14166 }
14167
14168 static void init_kdeth_qp(struct hfi1_devdata *dd)
14169 {
14170         /* user changed the KDETH_QP */
14171         if (kdeth_qp != 0 && kdeth_qp >= 0xff) {
14172                 /* out of range or illegal value */
14173                 dd_dev_err(dd, "Invalid KDETH queue pair prefix, ignoring");
14174                 kdeth_qp = 0;
14175         }
14176         if (kdeth_qp == 0)      /* not set, or failed range check */
14177                 kdeth_qp = DEFAULT_KDETH_QP;
14178
14179         write_csr(dd, SEND_BTH_QP,
14180                   (kdeth_qp & SEND_BTH_QP_KDETH_QP_MASK) <<
14181                   SEND_BTH_QP_KDETH_QP_SHIFT);
14182
14183         write_csr(dd, RCV_BTH_QP,
14184                   (kdeth_qp & RCV_BTH_QP_KDETH_QP_MASK) <<
14185                   RCV_BTH_QP_KDETH_QP_SHIFT);
14186 }
14187
14188 /**
14189  * init_qpmap_table
14190  * @dd - device data
14191  * @first_ctxt - first context
14192  * @last_ctxt - first context
14193  *
14194  * This return sets the qpn mapping table that
14195  * is indexed by qpn[8:1].
14196  *
14197  * The routine will round robin the 256 settings
14198  * from first_ctxt to last_ctxt.
14199  *
14200  * The first/last looks ahead to having specialized
14201  * receive contexts for mgmt and bypass.  Normal
14202  * verbs traffic will assumed to be on a range
14203  * of receive contexts.
14204  */
14205 static void init_qpmap_table(struct hfi1_devdata *dd,
14206                              u32 first_ctxt,
14207                              u32 last_ctxt)
14208 {
14209         u64 reg = 0;
14210         u64 regno = RCV_QP_MAP_TABLE;
14211         int i;
14212         u64 ctxt = first_ctxt;
14213
14214         for (i = 0; i < 256; i++) {
14215                 reg |= ctxt << (8 * (i % 8));
14216                 ctxt++;
14217                 if (ctxt > last_ctxt)
14218                         ctxt = first_ctxt;
14219                 if (i % 8 == 7) {
14220                         write_csr(dd, regno, reg);
14221                         reg = 0;
14222                         regno += 8;
14223                 }
14224         }
14225
14226         add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK
14227                         | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK);
14228 }
14229
14230 struct rsm_map_table {
14231         u64 map[NUM_MAP_REGS];
14232         unsigned int used;
14233 };
14234
14235 struct rsm_rule_data {
14236         u8 offset;
14237         u8 pkt_type;
14238         u32 field1_off;
14239         u32 field2_off;
14240         u32 index1_off;
14241         u32 index1_width;
14242         u32 index2_off;
14243         u32 index2_width;
14244         u32 mask1;
14245         u32 value1;
14246         u32 mask2;
14247         u32 value2;
14248 };
14249
14250 /*
14251  * Return an initialized RMT map table for users to fill in.  OK if it
14252  * returns NULL, indicating no table.
14253  */
14254 static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd)
14255 {
14256         struct rsm_map_table *rmt;
14257         u8 rxcontext = is_ax(dd) ? 0 : 0xff;  /* 0 is default if a0 ver. */
14258
14259         rmt = kmalloc(sizeof(*rmt), GFP_KERNEL);
14260         if (rmt) {
14261                 memset(rmt->map, rxcontext, sizeof(rmt->map));
14262                 rmt->used = 0;
14263         }
14264
14265         return rmt;
14266 }
14267
14268 /*
14269  * Write the final RMT map table to the chip and free the table.  OK if
14270  * table is NULL.
14271  */
14272 static void complete_rsm_map_table(struct hfi1_devdata *dd,
14273                                    struct rsm_map_table *rmt)
14274 {
14275         int i;
14276
14277         if (rmt) {
14278                 /* write table to chip */
14279                 for (i = 0; i < NUM_MAP_REGS; i++)
14280                         write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]);
14281
14282                 /* enable RSM */
14283                 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
14284         }
14285 }
14286
14287 /*
14288  * Add a receive side mapping rule.
14289  */
14290 static void add_rsm_rule(struct hfi1_devdata *dd, u8 rule_index,
14291                          struct rsm_rule_data *rrd)
14292 {
14293         write_csr(dd, RCV_RSM_CFG + (8 * rule_index),
14294                   (u64)rrd->offset << RCV_RSM_CFG_OFFSET_SHIFT |
14295                   1ull << rule_index | /* enable bit */
14296                   (u64)rrd->pkt_type << RCV_RSM_CFG_PACKET_TYPE_SHIFT);
14297         write_csr(dd, RCV_RSM_SELECT + (8 * rule_index),
14298                   (u64)rrd->field1_off << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT |
14299                   (u64)rrd->field2_off << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT |
14300                   (u64)rrd->index1_off << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT |
14301                   (u64)rrd->index1_width << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT |
14302                   (u64)rrd->index2_off << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT |
14303                   (u64)rrd->index2_width << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT);
14304         write_csr(dd, RCV_RSM_MATCH + (8 * rule_index),
14305                   (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT |
14306                   (u64)rrd->value1 << RCV_RSM_MATCH_VALUE1_SHIFT |
14307                   (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT |
14308                   (u64)rrd->value2 << RCV_RSM_MATCH_VALUE2_SHIFT);
14309 }
14310
14311 /*
14312  * Clear a receive side mapping rule.
14313  */
14314 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index)
14315 {
14316         write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0);
14317         write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0);
14318         write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0);
14319 }
14320
14321 /* return the number of RSM map table entries that will be used for QOS */
14322 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
14323                            unsigned int *np)
14324 {
14325         int i;
14326         unsigned int m, n;
14327         u8 max_by_vl = 0;
14328
14329         /* is QOS active at all? */
14330         if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS ||
14331             num_vls == 1 ||
14332             krcvqsset <= 1)
14333                 goto no_qos;
14334
14335         /* determine bits for qpn */
14336         for (i = 0; i < min_t(unsigned int, num_vls, krcvqsset); i++)
14337                 if (krcvqs[i] > max_by_vl)
14338                         max_by_vl = krcvqs[i];
14339         if (max_by_vl > 32)
14340                 goto no_qos;
14341         m = ilog2(__roundup_pow_of_two(max_by_vl));
14342
14343         /* determine bits for vl */
14344         n = ilog2(__roundup_pow_of_two(num_vls));
14345
14346         /* reject if too much is used */
14347         if ((m + n) > 7)
14348                 goto no_qos;
14349
14350         if (mp)
14351                 *mp = m;
14352         if (np)
14353                 *np = n;
14354
14355         return 1 << (m + n);
14356
14357 no_qos:
14358         if (mp)
14359                 *mp = 0;
14360         if (np)
14361                 *np = 0;
14362         return 0;
14363 }
14364
14365 /**
14366  * init_qos - init RX qos
14367  * @dd - device data
14368  * @rmt - RSM map table
14369  *
14370  * This routine initializes Rule 0 and the RSM map table to implement
14371  * quality of service (qos).
14372  *
14373  * If all of the limit tests succeed, qos is applied based on the array
14374  * interpretation of krcvqs where entry 0 is VL0.
14375  *
14376  * The number of vl bits (n) and the number of qpn bits (m) are computed to
14377  * feed both the RSM map table and the single rule.
14378  */
14379 static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt)
14380 {
14381         struct rsm_rule_data rrd;
14382         unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m;
14383         unsigned int rmt_entries;
14384         u64 reg;
14385
14386         if (!rmt)
14387                 goto bail;
14388         rmt_entries = qos_rmt_entries(dd, &m, &n);
14389         if (rmt_entries == 0)
14390                 goto bail;
14391         qpns_per_vl = 1 << m;
14392
14393         /* enough room in the map table? */
14394         rmt_entries = 1 << (m + n);
14395         if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES)
14396                 goto bail;
14397
14398         /* add qos entries to the the RSM map table */
14399         for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) {
14400                 unsigned tctxt;
14401
14402                 for (qpn = 0, tctxt = ctxt;
14403                      krcvqs[i] && qpn < qpns_per_vl; qpn++) {
14404                         unsigned idx, regoff, regidx;
14405
14406                         /* generate the index the hardware will produce */
14407                         idx = rmt->used + ((qpn << n) ^ i);
14408                         regoff = (idx % 8) * 8;
14409                         regidx = idx / 8;
14410                         /* replace default with context number */
14411                         reg = rmt->map[regidx];
14412                         reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
14413                                 << regoff);
14414                         reg |= (u64)(tctxt++) << regoff;
14415                         rmt->map[regidx] = reg;
14416                         if (tctxt == ctxt + krcvqs[i])
14417                                 tctxt = ctxt;
14418                 }
14419                 ctxt += krcvqs[i];
14420         }
14421
14422         rrd.offset = rmt->used;
14423         rrd.pkt_type = 2;
14424         rrd.field1_off = LRH_BTH_MATCH_OFFSET;
14425         rrd.field2_off = LRH_SC_MATCH_OFFSET;
14426         rrd.index1_off = LRH_SC_SELECT_OFFSET;
14427         rrd.index1_width = n;
14428         rrd.index2_off = QPN_SELECT_OFFSET;
14429         rrd.index2_width = m + n;
14430         rrd.mask1 = LRH_BTH_MASK;
14431         rrd.value1 = LRH_BTH_VALUE;
14432         rrd.mask2 = LRH_SC_MASK;
14433         rrd.value2 = LRH_SC_VALUE;
14434
14435         /* add rule 0 */
14436         add_rsm_rule(dd, RSM_INS_VERBS, &rrd);
14437
14438         /* mark RSM map entries as used */
14439         rmt->used += rmt_entries;
14440         /* map everything else to the mcast/err/vl15 context */
14441         init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT);
14442         dd->qos_shift = n + 1;
14443         return;
14444 bail:
14445         dd->qos_shift = 1;
14446         init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1);
14447 }
14448
14449 static void init_user_fecn_handling(struct hfi1_devdata *dd,
14450                                     struct rsm_map_table *rmt)
14451 {
14452         struct rsm_rule_data rrd;
14453         u64 reg;
14454         int i, idx, regoff, regidx;
14455         u8 offset;
14456
14457         /* there needs to be enough room in the map table */
14458         if (rmt->used + dd->num_user_contexts >= NUM_MAP_ENTRIES) {
14459                 dd_dev_err(dd, "User FECN handling disabled - too many user contexts allocated\n");
14460                 return;
14461         }
14462
14463         /*
14464          * RSM will extract the destination context as an index into the
14465          * map table.  The destination contexts are a sequential block
14466          * in the range first_dyn_alloc_ctxt...num_rcv_contexts-1 (inclusive).
14467          * Map entries are accessed as offset + extracted value.  Adjust
14468          * the added offset so this sequence can be placed anywhere in
14469          * the table - as long as the entries themselves do not wrap.
14470          * There are only enough bits in offset for the table size, so
14471          * start with that to allow for a "negative" offset.
14472          */
14473         offset = (u8)(NUM_MAP_ENTRIES + (int)rmt->used -
14474                                                 (int)dd->first_dyn_alloc_ctxt);
14475
14476         for (i = dd->first_dyn_alloc_ctxt, idx = rmt->used;
14477                                 i < dd->num_rcv_contexts; i++, idx++) {
14478                 /* replace with identity mapping */
14479                 regoff = (idx % 8) * 8;
14480                 regidx = idx / 8;
14481                 reg = rmt->map[regidx];
14482                 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff);
14483                 reg |= (u64)i << regoff;
14484                 rmt->map[regidx] = reg;
14485         }
14486
14487         /*
14488          * For RSM intercept of Expected FECN packets:
14489          * o packet type 0 - expected
14490          * o match on F (bit 95), using select/match 1, and
14491          * o match on SH (bit 133), using select/match 2.
14492          *
14493          * Use index 1 to extract the 8-bit receive context from DestQP
14494          * (start at bit 64).  Use that as the RSM map table index.
14495          */
14496         rrd.offset = offset;
14497         rrd.pkt_type = 0;
14498         rrd.field1_off = 95;
14499         rrd.field2_off = 133;
14500         rrd.index1_off = 64;
14501         rrd.index1_width = 8;
14502         rrd.index2_off = 0;
14503         rrd.index2_width = 0;
14504         rrd.mask1 = 1;
14505         rrd.value1 = 1;
14506         rrd.mask2 = 1;
14507         rrd.value2 = 1;
14508
14509         /* add rule 1 */
14510         add_rsm_rule(dd, RSM_INS_FECN, &rrd);
14511
14512         rmt->used += dd->num_user_contexts;
14513 }
14514
14515 /* Initialize RSM for VNIC */
14516 void hfi1_init_vnic_rsm(struct hfi1_devdata *dd)
14517 {
14518         u8 i, j;
14519         u8 ctx_id = 0;
14520         u64 reg;
14521         u32 regoff;
14522         struct rsm_rule_data rrd;
14523
14524         if (hfi1_vnic_is_rsm_full(dd, NUM_VNIC_MAP_ENTRIES)) {
14525                 dd_dev_err(dd, "Vnic RSM disabled, rmt entries used = %d\n",
14526                            dd->vnic.rmt_start);
14527                 return;
14528         }
14529
14530         dev_dbg(&(dd)->pcidev->dev, "Vnic rsm start = %d, end %d\n",
14531                 dd->vnic.rmt_start,
14532                 dd->vnic.rmt_start + NUM_VNIC_MAP_ENTRIES);
14533
14534         /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */
14535         regoff = RCV_RSM_MAP_TABLE + (dd->vnic.rmt_start / 8) * 8;
14536         reg = read_csr(dd, regoff);
14537         for (i = 0; i < NUM_VNIC_MAP_ENTRIES; i++) {
14538                 /* Update map register with vnic context */
14539                 j = (dd->vnic.rmt_start + i) % 8;
14540                 reg &= ~(0xffllu << (j * 8));
14541                 reg |= (u64)dd->vnic.ctxt[ctx_id++]->ctxt << (j * 8);
14542                 /* Wrap up vnic ctx index */
14543                 ctx_id %= dd->vnic.num_ctxt;
14544                 /* Write back map register */
14545                 if (j == 7 || ((i + 1) == NUM_VNIC_MAP_ENTRIES)) {
14546                         dev_dbg(&(dd)->pcidev->dev,
14547                                 "Vnic rsm map reg[%d] =0x%llx\n",
14548                                 regoff - RCV_RSM_MAP_TABLE, reg);
14549
14550                         write_csr(dd, regoff, reg);
14551                         regoff += 8;
14552                         if (i < (NUM_VNIC_MAP_ENTRIES - 1))
14553                                 reg = read_csr(dd, regoff);
14554                 }
14555         }
14556
14557         /* Add rule for vnic */
14558         rrd.offset = dd->vnic.rmt_start;
14559         rrd.pkt_type = 4;
14560         /* Match 16B packets */
14561         rrd.field1_off = L2_TYPE_MATCH_OFFSET;
14562         rrd.mask1 = L2_TYPE_MASK;
14563         rrd.value1 = L2_16B_VALUE;
14564         /* Match ETH L4 packets */
14565         rrd.field2_off = L4_TYPE_MATCH_OFFSET;
14566         rrd.mask2 = L4_16B_TYPE_MASK;
14567         rrd.value2 = L4_16B_ETH_VALUE;
14568         /* Calc context from veswid and entropy */
14569         rrd.index1_off = L4_16B_HDR_VESWID_OFFSET;
14570         rrd.index1_width = ilog2(NUM_VNIC_MAP_ENTRIES);
14571         rrd.index2_off = L2_16B_ENTROPY_OFFSET;
14572         rrd.index2_width = ilog2(NUM_VNIC_MAP_ENTRIES);
14573         add_rsm_rule(dd, RSM_INS_VNIC, &rrd);
14574
14575         /* Enable RSM if not already enabled */
14576         add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
14577 }
14578
14579 void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd)
14580 {
14581         clear_rsm_rule(dd, RSM_INS_VNIC);
14582
14583         /* Disable RSM if used only by vnic */
14584         if (dd->vnic.rmt_start == 0)
14585                 clear_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
14586 }
14587
14588 static void init_rxe(struct hfi1_devdata *dd)
14589 {
14590         struct rsm_map_table *rmt;
14591         u64 val;
14592
14593         /* enable all receive errors */
14594         write_csr(dd, RCV_ERR_MASK, ~0ull);
14595
14596         rmt = alloc_rsm_map_table(dd);
14597         /* set up QOS, including the QPN map table */
14598         init_qos(dd, rmt);
14599         init_user_fecn_handling(dd, rmt);
14600         complete_rsm_map_table(dd, rmt);
14601         /* record number of used rsm map entries for vnic */
14602         dd->vnic.rmt_start = rmt->used;
14603         kfree(rmt);
14604
14605         /*
14606          * make sure RcvCtrl.RcvWcb <= PCIe Device Control
14607          * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
14608          * space, PciCfgCap2.MaxPayloadSize in HFI).  There is only one
14609          * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
14610          * Max_PayLoad_Size set to its minimum of 128.
14611          *
14612          * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
14613          * (64 bytes).  Max_Payload_Size is possibly modified upward in
14614          * tune_pcie_caps() which is called after this routine.
14615          */
14616
14617         /* Have 16 bytes (4DW) of bypass header available in header queue */
14618         val = read_csr(dd, RCV_BYPASS);
14619         val |= (4ull << 16);
14620         write_csr(dd, RCV_BYPASS, val);
14621 }
14622
14623 static void init_other(struct hfi1_devdata *dd)
14624 {
14625         /* enable all CCE errors */
14626         write_csr(dd, CCE_ERR_MASK, ~0ull);
14627         /* enable *some* Misc errors */
14628         write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
14629         /* enable all DC errors, except LCB */
14630         write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
14631         write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
14632 }
14633
14634 /*
14635  * Fill out the given AU table using the given CU.  A CU is defined in terms
14636  * AUs.  The table is a an encoding: given the index, how many AUs does that
14637  * represent?
14638  *
14639  * NOTE: Assumes that the register layout is the same for the
14640  * local and remote tables.
14641  */
14642 static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu,
14643                                u32 csr0to3, u32 csr4to7)
14644 {
14645         write_csr(dd, csr0to3,
14646                   0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT |
14647                   1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT |
14648                   2ull * cu <<
14649                   SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT |
14650                   4ull * cu <<
14651                   SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
14652         write_csr(dd, csr4to7,
14653                   8ull * cu <<
14654                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT |
14655                   16ull * cu <<
14656                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT |
14657                   32ull * cu <<
14658                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT |
14659                   64ull * cu <<
14660                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
14661 }
14662
14663 static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14664 {
14665         assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3,
14666                            SEND_CM_LOCAL_AU_TABLE4_TO7);
14667 }
14668
14669 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14670 {
14671         assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3,
14672                            SEND_CM_REMOTE_AU_TABLE4_TO7);
14673 }
14674
14675 static void init_txe(struct hfi1_devdata *dd)
14676 {
14677         int i;
14678
14679         /* enable all PIO, SDMA, general, and Egress errors */
14680         write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
14681         write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
14682         write_csr(dd, SEND_ERR_MASK, ~0ull);
14683         write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
14684
14685         /* enable all per-context and per-SDMA engine errors */
14686         for (i = 0; i < dd->chip_send_contexts; i++)
14687                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull);
14688         for (i = 0; i < dd->chip_sdma_engines; i++)
14689                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull);
14690
14691         /* set the local CU to AU mapping */
14692         assign_local_cm_au_table(dd, dd->vcu);
14693
14694         /*
14695          * Set reasonable default for Credit Return Timer
14696          * Don't set on Simulator - causes it to choke.
14697          */
14698         if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
14699                 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
14700 }
14701
14702 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd,
14703                        u16 jkey)
14704 {
14705         u8 hw_ctxt;
14706         u64 reg;
14707
14708         if (!rcd || !rcd->sc)
14709                 return -EINVAL;
14710
14711         hw_ctxt = rcd->sc->hw_context;
14712         reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */
14713                 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) <<
14714                  SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
14715         /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
14716         if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY))
14717                 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK;
14718         write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, reg);
14719         /*
14720          * Enable send-side J_KEY integrity check, unless this is A0 h/w
14721          */
14722         if (!is_ax(dd)) {
14723                 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE);
14724                 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14725                 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg);
14726         }
14727
14728         /* Enable J_KEY check on receive context. */
14729         reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK |
14730                 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) <<
14731                  RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
14732         write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, reg);
14733
14734         return 0;
14735 }
14736
14737 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
14738 {
14739         u8 hw_ctxt;
14740         u64 reg;
14741
14742         if (!rcd || !rcd->sc)
14743                 return -EINVAL;
14744
14745         hw_ctxt = rcd->sc->hw_context;
14746         write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, 0);
14747         /*
14748          * Disable send-side J_KEY integrity check, unless this is A0 h/w.
14749          * This check would not have been enabled for A0 h/w, see
14750          * set_ctxt_jkey().
14751          */
14752         if (!is_ax(dd)) {
14753                 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE);
14754                 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14755                 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg);
14756         }
14757         /* Turn off the J_KEY on the receive side */
14758         write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, 0);
14759
14760         return 0;
14761 }
14762
14763 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd,
14764                        u16 pkey)
14765 {
14766         u8 hw_ctxt;
14767         u64 reg;
14768
14769         if (!rcd || !rcd->sc)
14770                 return -EINVAL;
14771
14772         hw_ctxt = rcd->sc->hw_context;
14773         reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) <<
14774                 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
14775         write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg);
14776         reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE);
14777         reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
14778         reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK;
14779         write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg);
14780
14781         return 0;
14782 }
14783
14784 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt)
14785 {
14786         u8 hw_ctxt;
14787         u64 reg;
14788
14789         if (!ctxt || !ctxt->sc)
14790                 return -EINVAL;
14791
14792         hw_ctxt = ctxt->sc->hw_context;
14793         reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE);
14794         reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
14795         write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg);
14796         write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0);
14797
14798         return 0;
14799 }
14800
14801 /*
14802  * Start doing the clean up the the chip. Our clean up happens in multiple
14803  * stages and this is just the first.
14804  */
14805 void hfi1_start_cleanup(struct hfi1_devdata *dd)
14806 {
14807         aspm_exit(dd);
14808         free_cntrs(dd);
14809         free_rcverr(dd);
14810         finish_chip_resources(dd);
14811 }
14812
14813 #define HFI_BASE_GUID(dev) \
14814         ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
14815
14816 /*
14817  * Information can be shared between the two HFIs on the same ASIC
14818  * in the same OS.  This function finds the peer device and sets
14819  * up a shared structure.
14820  */
14821 static int init_asic_data(struct hfi1_devdata *dd)
14822 {
14823         unsigned long flags;
14824         struct hfi1_devdata *tmp, *peer = NULL;
14825         struct hfi1_asic_data *asic_data;
14826         int ret = 0;
14827
14828         /* pre-allocate the asic structure in case we are the first device */
14829         asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL);
14830         if (!asic_data)
14831                 return -ENOMEM;
14832
14833         spin_lock_irqsave(&hfi1_devs_lock, flags);
14834         /* Find our peer device */
14835         list_for_each_entry(tmp, &hfi1_dev_list, list) {
14836                 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(tmp)) &&
14837                     dd->unit != tmp->unit) {
14838                         peer = tmp;
14839                         break;
14840                 }
14841         }
14842
14843         if (peer) {
14844                 /* use already allocated structure */
14845                 dd->asic_data = peer->asic_data;
14846                 kfree(asic_data);
14847         } else {
14848                 dd->asic_data = asic_data;
14849                 mutex_init(&dd->asic_data->asic_resource_mutex);
14850         }
14851         dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */
14852         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
14853
14854         /* first one through - set up i2c devices */
14855         if (!peer)
14856                 ret = set_up_i2c(dd, dd->asic_data);
14857
14858         return ret;
14859 }
14860
14861 /*
14862  * Set dd->boardname.  Use a generic name if a name is not returned from
14863  * EFI variable space.
14864  *
14865  * Return 0 on success, -ENOMEM if space could not be allocated.
14866  */
14867 static int obtain_boardname(struct hfi1_devdata *dd)
14868 {
14869         /* generic board description */
14870         const char generic[] =
14871                 "Intel Omni-Path Host Fabric Interface Adapter 100 Series";
14872         unsigned long size;
14873         int ret;
14874
14875         ret = read_hfi1_efi_var(dd, "description", &size,
14876                                 (void **)&dd->boardname);
14877         if (ret) {
14878                 dd_dev_info(dd, "Board description not found\n");
14879                 /* use generic description */
14880                 dd->boardname = kstrdup(generic, GFP_KERNEL);
14881                 if (!dd->boardname)
14882                         return -ENOMEM;
14883         }
14884         return 0;
14885 }
14886
14887 /*
14888  * Check the interrupt registers to make sure that they are mapped correctly.
14889  * It is intended to help user identify any mismapping by VMM when the driver
14890  * is running in a VM. This function should only be called before interrupt
14891  * is set up properly.
14892  *
14893  * Return 0 on success, -EINVAL on failure.
14894  */
14895 static int check_int_registers(struct hfi1_devdata *dd)
14896 {
14897         u64 reg;
14898         u64 all_bits = ~(u64)0;
14899         u64 mask;
14900
14901         /* Clear CceIntMask[0] to avoid raising any interrupts */
14902         mask = read_csr(dd, CCE_INT_MASK);
14903         write_csr(dd, CCE_INT_MASK, 0ull);
14904         reg = read_csr(dd, CCE_INT_MASK);
14905         if (reg)
14906                 goto err_exit;
14907
14908         /* Clear all interrupt status bits */
14909         write_csr(dd, CCE_INT_CLEAR, all_bits);
14910         reg = read_csr(dd, CCE_INT_STATUS);
14911         if (reg)
14912                 goto err_exit;
14913
14914         /* Set all interrupt status bits */
14915         write_csr(dd, CCE_INT_FORCE, all_bits);
14916         reg = read_csr(dd, CCE_INT_STATUS);
14917         if (reg != all_bits)
14918                 goto err_exit;
14919
14920         /* Restore the interrupt mask */
14921         write_csr(dd, CCE_INT_CLEAR, all_bits);
14922         write_csr(dd, CCE_INT_MASK, mask);
14923
14924         return 0;
14925 err_exit:
14926         write_csr(dd, CCE_INT_MASK, mask);
14927         dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n");
14928         return -EINVAL;
14929 }
14930
14931 /**
14932  * Allocate and initialize the device structure for the hfi.
14933  * @dev: the pci_dev for hfi1_ib device
14934  * @ent: pci_device_id struct for this dev
14935  *
14936  * Also allocates, initializes, and returns the devdata struct for this
14937  * device instance
14938  *
14939  * This is global, and is called directly at init to set up the
14940  * chip-specific function pointers for later use.
14941  */
14942 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
14943                                   const struct pci_device_id *ent)
14944 {
14945         struct hfi1_devdata *dd;
14946         struct hfi1_pportdata *ppd;
14947         u64 reg;
14948         int i, ret;
14949         static const char * const inames[] = { /* implementation names */
14950                 "RTL silicon",
14951                 "RTL VCS simulation",
14952                 "RTL FPGA emulation",
14953                 "Functional simulator"
14954         };
14955         struct pci_dev *parent = pdev->bus->self;
14956
14957         dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS *
14958                                 sizeof(struct hfi1_pportdata));
14959         if (IS_ERR(dd))
14960                 goto bail;
14961         ppd = dd->pport;
14962         for (i = 0; i < dd->num_pports; i++, ppd++) {
14963                 int vl;
14964                 /* init common fields */
14965                 hfi1_init_pportdata(pdev, ppd, dd, 0, 1);
14966                 /* DC supports 4 link widths */
14967                 ppd->link_width_supported =
14968                         OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X |
14969                         OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X;
14970                 ppd->link_width_downgrade_supported =
14971                         ppd->link_width_supported;
14972                 /* start out enabling only 4X */
14973                 ppd->link_width_enabled = OPA_LINK_WIDTH_4X;
14974                 ppd->link_width_downgrade_enabled =
14975                                         ppd->link_width_downgrade_supported;
14976                 /* link width active is 0 when link is down */
14977                 /* link width downgrade active is 0 when link is down */
14978
14979                 if (num_vls < HFI1_MIN_VLS_SUPPORTED ||
14980                     num_vls > HFI1_MAX_VLS_SUPPORTED) {
14981                         dd_dev_err(dd, "Invalid num_vls %u, using %u VLs\n",
14982                                    num_vls, HFI1_MAX_VLS_SUPPORTED);
14983                         num_vls = HFI1_MAX_VLS_SUPPORTED;
14984                 }
14985                 ppd->vls_supported = num_vls;
14986                 ppd->vls_operational = ppd->vls_supported;
14987                 /* Set the default MTU. */
14988                 for (vl = 0; vl < num_vls; vl++)
14989                         dd->vld[vl].mtu = hfi1_max_mtu;
14990                 dd->vld[15].mtu = MAX_MAD_PACKET;
14991                 /*
14992                  * Set the initial values to reasonable default, will be set
14993                  * for real when link is up.
14994                  */
14995                 ppd->overrun_threshold = 0x4;
14996                 ppd->phy_error_threshold = 0xf;
14997                 ppd->port_crc_mode_enabled = link_crc_mask;
14998                 /* initialize supported LTP CRC mode */
14999                 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
15000                 /* initialize enabled LTP CRC mode */
15001                 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4;
15002                 /* start in offline */
15003                 ppd->host_link_state = HLS_DN_OFFLINE;
15004                 init_vl_arb_caches(ppd);
15005         }
15006
15007         /*
15008          * Do remaining PCIe setup and save PCIe values in dd.
15009          * Any error printing is already done by the init code.
15010          * On return, we have the chip mapped.
15011          */
15012         ret = hfi1_pcie_ddinit(dd, pdev);
15013         if (ret < 0)
15014                 goto bail_free;
15015
15016         /* Save PCI space registers to rewrite after device reset */
15017         ret = save_pci_variables(dd);
15018         if (ret < 0)
15019                 goto bail_cleanup;
15020
15021         /* verify that reads actually work, save revision for reset check */
15022         dd->revision = read_csr(dd, CCE_REVISION);
15023         if (dd->revision == ~(u64)0) {
15024                 dd_dev_err(dd, "cannot read chip CSRs\n");
15025                 ret = -EINVAL;
15026                 goto bail_cleanup;
15027         }
15028         dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT)
15029                         & CCE_REVISION_CHIP_REV_MAJOR_MASK;
15030         dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT)
15031                         & CCE_REVISION_CHIP_REV_MINOR_MASK;
15032
15033         /*
15034          * Check interrupt registers mapping if the driver has no access to
15035          * the upstream component. In this case, it is likely that the driver
15036          * is running in a VM.
15037          */
15038         if (!parent) {
15039                 ret = check_int_registers(dd);
15040                 if (ret)
15041                         goto bail_cleanup;
15042         }
15043
15044         /*
15045          * obtain the hardware ID - NOT related to unit, which is a
15046          * software enumeration
15047          */
15048         reg = read_csr(dd, CCE_REVISION2);
15049         dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT)
15050                                         & CCE_REVISION2_HFI_ID_MASK;
15051         /* the variable size will remove unwanted bits */
15052         dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT;
15053         dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT;
15054         dd_dev_info(dd, "Implementation: %s, revision 0x%x\n",
15055                     dd->icode < ARRAY_SIZE(inames) ?
15056                     inames[dd->icode] : "unknown", (int)dd->irev);
15057
15058         /* speeds the hardware can support */
15059         dd->pport->link_speed_supported = OPA_LINK_SPEED_25G;
15060         /* speeds allowed to run at */
15061         dd->pport->link_speed_enabled = dd->pport->link_speed_supported;
15062         /* give a reasonable active value, will be set on link up */
15063         dd->pport->link_speed_active = OPA_LINK_SPEED_25G;
15064
15065         dd->chip_rcv_contexts = read_csr(dd, RCV_CONTEXTS);
15066         dd->chip_send_contexts = read_csr(dd, SEND_CONTEXTS);
15067         dd->chip_sdma_engines = read_csr(dd, SEND_DMA_ENGINES);
15068         dd->chip_pio_mem_size = read_csr(dd, SEND_PIO_MEM_SIZE);
15069         dd->chip_sdma_mem_size = read_csr(dd, SEND_DMA_MEM_SIZE);
15070         /* fix up link widths for emulation _p */
15071         ppd = dd->pport;
15072         if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) {
15073                 ppd->link_width_supported =
15074                         ppd->link_width_enabled =
15075                         ppd->link_width_downgrade_supported =
15076                         ppd->link_width_downgrade_enabled =
15077                                 OPA_LINK_WIDTH_1X;
15078         }
15079         /* insure num_vls isn't larger than number of sdma engines */
15080         if (HFI1_CAP_IS_KSET(SDMA) && num_vls > dd->chip_sdma_engines) {
15081                 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n",
15082                            num_vls, dd->chip_sdma_engines);
15083                 num_vls = dd->chip_sdma_engines;
15084                 ppd->vls_supported = dd->chip_sdma_engines;
15085                 ppd->vls_operational = ppd->vls_supported;
15086         }
15087
15088         /*
15089          * Convert the ns parameter to the 64 * cclocks used in the CSR.
15090          * Limit the max if larger than the field holds.  If timeout is
15091          * non-zero, then the calculated field will be at least 1.
15092          *
15093          * Must be after icode is set up - the cclock rate depends
15094          * on knowing the hardware being used.
15095          */
15096         dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64;
15097         if (dd->rcv_intr_timeout_csr >
15098                         RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
15099                 dd->rcv_intr_timeout_csr =
15100                         RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
15101         else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout)
15102                 dd->rcv_intr_timeout_csr = 1;
15103
15104         /* needs to be done before we look for the peer device */
15105         read_guid(dd);
15106
15107         /* set up shared ASIC data with peer device */
15108         ret = init_asic_data(dd);
15109         if (ret)
15110                 goto bail_cleanup;
15111
15112         /* obtain chip sizes, reset chip CSRs */
15113         ret = init_chip(dd);
15114         if (ret)
15115                 goto bail_cleanup;
15116
15117         /* read in the PCIe link speed information */
15118         ret = pcie_speeds(dd);
15119         if (ret)
15120                 goto bail_cleanup;
15121
15122         /* call before get_platform_config(), after init_chip_resources() */
15123         ret = eprom_init(dd);
15124         if (ret)
15125                 goto bail_free_rcverr;
15126
15127         /* Needs to be called before hfi1_firmware_init */
15128         get_platform_config(dd);
15129
15130         /* read in firmware */
15131         ret = hfi1_firmware_init(dd);
15132         if (ret)
15133                 goto bail_cleanup;
15134
15135         /*
15136          * In general, the PCIe Gen3 transition must occur after the
15137          * chip has been idled (so it won't initiate any PCIe transactions
15138          * e.g. an interrupt) and before the driver changes any registers
15139          * (the transition will reset the registers).
15140          *
15141          * In particular, place this call after:
15142          * - init_chip()     - the chip will not initiate any PCIe transactions
15143          * - pcie_speeds()   - reads the current link speed
15144          * - hfi1_firmware_init() - the needed firmware is ready to be
15145          *                          downloaded
15146          */
15147         ret = do_pcie_gen3_transition(dd);
15148         if (ret)
15149                 goto bail_cleanup;
15150
15151         /* start setting dd values and adjusting CSRs */
15152         init_early_variables(dd);
15153
15154         parse_platform_config(dd);
15155
15156         ret = obtain_boardname(dd);
15157         if (ret)
15158                 goto bail_cleanup;
15159
15160         snprintf(dd->boardversion, BOARD_VERS_MAX,
15161                  "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n",
15162                  HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN,
15163                  (u32)dd->majrev,
15164                  (u32)dd->minrev,
15165                  (dd->revision >> CCE_REVISION_SW_SHIFT)
15166                     & CCE_REVISION_SW_MASK);
15167
15168         ret = set_up_context_variables(dd);
15169         if (ret)
15170                 goto bail_cleanup;
15171
15172         /* set initial RXE CSRs */
15173         init_rxe(dd);
15174         /* set initial TXE CSRs */
15175         init_txe(dd);
15176         /* set initial non-RXE, non-TXE CSRs */
15177         init_other(dd);
15178         /* set up KDETH QP prefix in both RX and TX CSRs */
15179         init_kdeth_qp(dd);
15180
15181         ret = hfi1_dev_affinity_init(dd);
15182         if (ret)
15183                 goto bail_cleanup;
15184
15185         /* send contexts must be set up before receive contexts */
15186         ret = init_send_contexts(dd);
15187         if (ret)
15188                 goto bail_cleanup;
15189
15190         ret = hfi1_create_kctxts(dd);
15191         if (ret)
15192                 goto bail_cleanup;
15193
15194         /*
15195          * Initialize aspm, to be done after gen3 transition and setting up
15196          * contexts and before enabling interrupts
15197          */
15198         aspm_init(dd);
15199
15200         dd->rcvhdrsize = DEFAULT_RCVHDRSIZE;
15201         /*
15202          * rcd[0] is guaranteed to be valid by this point. Also, all
15203          * context are using the same value, as per the module parameter.
15204          */
15205         dd->rhf_offset = dd->rcd[0]->rcvhdrqentsize - sizeof(u64) / sizeof(u32);
15206
15207         ret = init_pervl_scs(dd);
15208         if (ret)
15209                 goto bail_cleanup;
15210
15211         /* sdma init */
15212         for (i = 0; i < dd->num_pports; ++i) {
15213                 ret = sdma_init(dd, i);
15214                 if (ret)
15215                         goto bail_cleanup;
15216         }
15217
15218         /* use contexts created by hfi1_create_kctxts */
15219         ret = set_up_interrupts(dd);
15220         if (ret)
15221                 goto bail_cleanup;
15222
15223         /* set up LCB access - must be after set_up_interrupts() */
15224         init_lcb_access(dd);
15225
15226         /*
15227          * Serial number is created from the base guid:
15228          * [27:24] = base guid [38:35]
15229          * [23: 0] = base guid [23: 0]
15230          */
15231         snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n",
15232                  (dd->base_guid & 0xFFFFFF) |
15233                      ((dd->base_guid >> 11) & 0xF000000));
15234
15235         dd->oui1 = dd->base_guid >> 56 & 0xFF;
15236         dd->oui2 = dd->base_guid >> 48 & 0xFF;
15237         dd->oui3 = dd->base_guid >> 40 & 0xFF;
15238
15239         ret = load_firmware(dd); /* asymmetric with dispose_firmware() */
15240         if (ret)
15241                 goto bail_clear_intr;
15242
15243         thermal_init(dd);
15244
15245         ret = init_cntrs(dd);
15246         if (ret)
15247                 goto bail_clear_intr;
15248
15249         ret = init_rcverr(dd);
15250         if (ret)
15251                 goto bail_free_cntrs;
15252
15253         init_completion(&dd->user_comp);
15254
15255         /* The user refcount starts with one to inidicate an active device */
15256         atomic_set(&dd->user_refcount, 1);
15257
15258         goto bail;
15259
15260 bail_free_rcverr:
15261         free_rcverr(dd);
15262 bail_free_cntrs:
15263         free_cntrs(dd);
15264 bail_clear_intr:
15265         hfi1_clean_up_interrupts(dd);
15266 bail_cleanup:
15267         hfi1_pcie_ddcleanup(dd);
15268 bail_free:
15269         hfi1_free_devdata(dd);
15270         dd = ERR_PTR(ret);
15271 bail:
15272         return dd;
15273 }
15274
15275 static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate,
15276                         u32 dw_len)
15277 {
15278         u32 delta_cycles;
15279         u32 current_egress_rate = ppd->current_egress_rate;
15280         /* rates here are in units of 10^6 bits/sec */
15281
15282         if (desired_egress_rate == -1)
15283                 return 0; /* shouldn't happen */
15284
15285         if (desired_egress_rate >= current_egress_rate)
15286                 return 0; /* we can't help go faster, only slower */
15287
15288         delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) -
15289                         egress_cycles(dw_len * 4, current_egress_rate);
15290
15291         return (u16)delta_cycles;
15292 }
15293
15294 /**
15295  * create_pbc - build a pbc for transmission
15296  * @flags: special case flags or-ed in built pbc
15297  * @srate: static rate
15298  * @vl: vl
15299  * @dwlen: dword length (header words + data words + pbc words)
15300  *
15301  * Create a PBC with the given flags, rate, VL, and length.
15302  *
15303  * NOTE: The PBC created will not insert any HCRC - all callers but one are
15304  * for verbs, which does not use this PSM feature.  The lone other caller
15305  * is for the diagnostic interface which calls this if the user does not
15306  * supply their own PBC.
15307  */
15308 u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
15309                u32 dw_len)
15310 {
15311         u64 pbc, delay = 0;
15312
15313         if (unlikely(srate_mbs))
15314                 delay = delay_cycles(ppd, srate_mbs, dw_len);
15315
15316         pbc = flags
15317                 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
15318                 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT)
15319                 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT
15320                 | (dw_len & PBC_LENGTH_DWS_MASK)
15321                         << PBC_LENGTH_DWS_SHIFT;
15322
15323         return pbc;
15324 }
15325
15326 #define SBUS_THERMAL    0x4f
15327 #define SBUS_THERM_MONITOR_MODE 0x1
15328
15329 #define THERM_FAILURE(dev, ret, reason) \
15330         dd_dev_err((dd),                                                \
15331                    "Thermal sensor initialization failed: %s (%d)\n",   \
15332                    (reason), (ret))
15333
15334 /*
15335  * Initialize the thermal sensor.
15336  *
15337  * After initialization, enable polling of thermal sensor through
15338  * SBus interface. In order for this to work, the SBus Master
15339  * firmware has to be loaded due to the fact that the HW polling
15340  * logic uses SBus interrupts, which are not supported with
15341  * default firmware. Otherwise, no data will be returned through
15342  * the ASIC_STS_THERM CSR.
15343  */
15344 static int thermal_init(struct hfi1_devdata *dd)
15345 {
15346         int ret = 0;
15347
15348         if (dd->icode != ICODE_RTL_SILICON ||
15349             check_chip_resource(dd, CR_THERM_INIT, NULL))
15350                 return ret;
15351
15352         ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
15353         if (ret) {
15354                 THERM_FAILURE(dd, ret, "Acquire SBus");
15355                 return ret;
15356         }
15357
15358         dd_dev_info(dd, "Initializing thermal sensor\n");
15359         /* Disable polling of thermal readings */
15360         write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
15361         msleep(100);
15362         /* Thermal Sensor Initialization */
15363         /*    Step 1: Reset the Thermal SBus Receiver */
15364         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
15365                                 RESET_SBUS_RECEIVER, 0);
15366         if (ret) {
15367                 THERM_FAILURE(dd, ret, "Bus Reset");
15368                 goto done;
15369         }
15370         /*    Step 2: Set Reset bit in Thermal block */
15371         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
15372                                 WRITE_SBUS_RECEIVER, 0x1);
15373         if (ret) {
15374                 THERM_FAILURE(dd, ret, "Therm Block Reset");
15375                 goto done;
15376         }
15377         /*    Step 3: Write clock divider value (100MHz -> 2MHz) */
15378         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1,
15379                                 WRITE_SBUS_RECEIVER, 0x32);
15380         if (ret) {
15381                 THERM_FAILURE(dd, ret, "Write Clock Div");
15382                 goto done;
15383         }
15384         /*    Step 4: Select temperature mode */
15385         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3,
15386                                 WRITE_SBUS_RECEIVER,
15387                                 SBUS_THERM_MONITOR_MODE);
15388         if (ret) {
15389                 THERM_FAILURE(dd, ret, "Write Mode Sel");
15390                 goto done;
15391         }
15392         /*    Step 5: De-assert block reset and start conversion */
15393         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
15394                                 WRITE_SBUS_RECEIVER, 0x2);
15395         if (ret) {
15396                 THERM_FAILURE(dd, ret, "Write Reset Deassert");
15397                 goto done;
15398         }
15399         /*    Step 5.1: Wait for first conversion (21.5ms per spec) */
15400         msleep(22);
15401
15402         /* Enable polling of thermal readings */
15403         write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
15404
15405         /* Set initialized flag */
15406         ret = acquire_chip_resource(dd, CR_THERM_INIT, 0);
15407         if (ret)
15408                 THERM_FAILURE(dd, ret, "Unable to set thermal init flag");
15409
15410 done:
15411         release_chip_resource(dd, CR_SBUS);
15412         return ret;
15413 }
15414
15415 static void handle_temp_err(struct hfi1_devdata *dd)
15416 {
15417         struct hfi1_pportdata *ppd = &dd->pport[0];
15418         /*
15419          * Thermal Critical Interrupt
15420          * Put the device into forced freeze mode, take link down to
15421          * offline, and put DC into reset.
15422          */
15423         dd_dev_emerg(dd,
15424                      "Critical temperature reached! Forcing device into freeze mode!\n");
15425         dd->flags |= HFI1_FORCED_FREEZE;
15426         start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT);
15427         /*
15428          * Shut DC down as much and as quickly as possible.
15429          *
15430          * Step 1: Take the link down to OFFLINE. This will cause the
15431          *         8051 to put the Serdes in reset. However, we don't want to
15432          *         go through the entire link state machine since we want to
15433          *         shutdown ASAP. Furthermore, this is not a graceful shutdown
15434          *         but rather an attempt to save the chip.
15435          *         Code below is almost the same as quiet_serdes() but avoids
15436          *         all the extra work and the sleeps.
15437          */
15438         ppd->driver_link_ready = 0;
15439         ppd->link_enabled = 0;
15440         set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) |
15441                                 PLS_OFFLINE);
15442         /*
15443          * Step 2: Shutdown LCB and 8051
15444          *         After shutdown, do not restore DC_CFG_RESET value.
15445          */
15446         dc_shutdown(dd);
15447 }