drivers/infiniband/hw/cxgb4/qp.c

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34
  35 #include "iw_cxgb4.h"
  36
  37 static int db_delay_usecs = 1;
  38 module_param(db_delay_usecs, int, 0644);
  39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
  40
  41 static int ocqp_support = 1;
  42 module_param(ocqp_support, int, 0644);
  43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
  44
  45 int db_fc_threshold = 1000;
  46 module_param(db_fc_threshold, int, 0644);
  47 MODULE_PARM_DESC(db_fc_threshold,
  48                  "QP count/threshold that triggers"
  49                  " automatic db flow control mode (default = 1000)");
  50
  51 int db_coalescing_threshold;
  52 module_param(db_coalescing_threshold, int, 0644);
  53 MODULE_PARM_DESC(db_coalescing_threshold,
  54                  "QP count/threshold that triggers"
  55                  " disabling db coalescing (default = 0)");
  56
  57 static int max_fr_immd = T4_MAX_FR_IMMD;
  58 module_param(max_fr_immd, int, 0644);
  59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
  60
  61 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
  62 {
  63         unsigned long flag;
  64         spin_lock_irqsave(&qhp->lock, flag);
  65         qhp->attr.state = state;
  66         spin_unlock_irqrestore(&qhp->lock, flag);
  67 }
  68
  69 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  70 {
  71         c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
  72 }
  73
  74 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  75 {
  76         dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
  77                           pci_unmap_addr(sq, mapping));
  78 }
  79
  80 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  81 {
  82         if (t4_sq_onchip(sq))
  83                 dealloc_oc_sq(rdev, sq);
  84         else
  85                 dealloc_host_sq(rdev, sq);
  86 }
  87
  88 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  89 {
  90         if (!ocqp_support || !ocqp_supported(&rdev->lldi))
  91                 return -ENOSYS;
  92         sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
  93         if (!sq->dma_addr)
  94                 return -ENOMEM;
  95         sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
  96                         rdev->lldi.vr->ocq.start;
  97         sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
  98                                             rdev->lldi.vr->ocq.start);
  99         sq->flags |= T4_SQ_ONCHIP;
 100         return 0;
 101 }
 102
 103 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 104 {
 105         sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
 106                                        &(sq->dma_addr), GFP_KERNEL);
 107         if (!sq->queue)
 108                 return -ENOMEM;
 109         sq->phys_addr = virt_to_phys(sq->queue);
 110         pci_unmap_addr_set(sq, mapping, sq->dma_addr);
 111         return 0;
 112 }
 113
 114 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
 115 {
 116         int ret = -ENOSYS;
 117         if (user)
 118                 ret = alloc_oc_sq(rdev, sq);
 119         if (ret)
 120                 ret = alloc_host_sq(rdev, sq);
 121         return ret;
 122 }
 123
 124 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 125                       struct c4iw_dev_ucontext *uctx)
 126 {
 127         /*
 128          * uP clears EQ contexts when the connection exits rdma mode,
 129          * so no need to post a RESET WR for these EQs.
 130          */
 131         dma_free_coherent(&(rdev->lldi.pdev->dev),
 132                           wq->rq.memsize, wq->rq.queue,
 133                           dma_unmap_addr(&wq->rq, mapping));
 134         dealloc_sq(rdev, &wq->sq);
 135         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 136         kfree(wq->rq.sw_rq);
 137         kfree(wq->sq.sw_sq);
 138         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 139         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 140         return 0;
 141 }
 142
 143 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 144                      struct t4_cq *rcq, struct t4_cq *scq,
 145                      struct c4iw_dev_ucontext *uctx)
 146 {
 147         int user = (uctx != &rdev->uctx);
 148         struct fw_ri_res_wr *res_wr;
 149         struct fw_ri_res *res;
 150         int wr_len;
 151         struct c4iw_wr_wait wr_wait;
 152         struct sk_buff *skb;
 153         int ret = 0;
 154         int eqsize;
 155
 156         wq->sq.qid = c4iw_get_qpid(rdev, uctx);
 157         if (!wq->sq.qid)
 158                 return -ENOMEM;
 159
 160         wq->rq.qid = c4iw_get_qpid(rdev, uctx);
 161         if (!wq->rq.qid) {
 162                 ret = -ENOMEM;
 163                 goto free_sq_qid;
 164         }
 165
 166         if (!user) {
 167                 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
 168                                  GFP_KERNEL);
 169                 if (!wq->sq.sw_sq) {
 170                         ret = -ENOMEM;
 171                         goto free_rq_qid;
 172                 }
 173
 174                 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
 175                                  GFP_KERNEL);
 176                 if (!wq->rq.sw_rq) {
 177                         ret = -ENOMEM;
 178                         goto free_sw_sq;
 179                 }
 180         }
 181
 182         /*
 183          * RQT must be a power of 2.
 184          */
 185         wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
 186         wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
 187         if (!wq->rq.rqt_hwaddr) {
 188                 ret = -ENOMEM;
 189                 goto free_sw_rq;
 190         }
 191
 192         ret = alloc_sq(rdev, &wq->sq, user);
 193         if (ret)
 194                 goto free_hwaddr;
 195         memset(wq->sq.queue, 0, wq->sq.memsize);
 196         dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
 197
 198         wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
 199                                           wq->rq.memsize, &(wq->rq.dma_addr),
 200                                           GFP_KERNEL);
 201         if (!wq->rq.queue) {
 202                 ret = -ENOMEM;
 203                 goto free_sq;
 204         }
 205         PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
 206                 __func__, wq->sq.queue,
 207                 (unsigned long long)virt_to_phys(wq->sq.queue),
 208                 wq->rq.queue,
 209                 (unsigned long long)virt_to_phys(wq->rq.queue));
 210         memset(wq->rq.queue, 0, wq->rq.memsize);
 211         dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
 212
 213         wq->db = rdev->lldi.db_reg;
 214         wq->gts = rdev->lldi.gts_reg;
 215         if (user || is_t5(rdev->lldi.adapter_type)) {
 216                 u32 off;
 217
 218                 off = (wq->sq.qid << rdev->qpshift) & PAGE_MASK;
 219                 if (user) {
 220                         wq->sq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
 221                 } else {
 222                         off += 128 * (wq->sq.qid & rdev->qpmask) + 8;
 223                         wq->sq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
 224                 }
 225                 off = (wq->rq.qid << rdev->qpshift) & PAGE_MASK;
 226                 if (user) {
 227                         wq->rq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
 228                 } else {
 229                         off += 128 * (wq->rq.qid & rdev->qpmask) + 8;
 230                         wq->rq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
 231                 }
 232         }
 233         wq->rdev = rdev;
 234         wq->rq.msn = 1;
 235
 236         /* build fw_ri_res_wr */
 237         wr_len = sizeof *res_wr + 2 * sizeof *res;
 238
 239         skb = alloc_skb(wr_len, GFP_KERNEL);
 240         if (!skb) {
 241                 ret = -ENOMEM;
 242                 goto free_dma;
 243         }
 244         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
 245
 246         res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
 247         memset(res_wr, 0, wr_len);
 248         res_wr->op_nres = cpu_to_be32(
 249                         FW_WR_OP(FW_RI_RES_WR) |
 250                         V_FW_RI_RES_WR_NRES(2) |
 251                         FW_WR_COMPL(1));
 252         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
 253         res_wr->cookie = (unsigned long) &wr_wait;
 254         res = res_wr->res;
 255         res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
 256         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 257
 258         /*
 259          * eqsize is the number of 64B entries plus the status page size.
 260          */
 261         eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
 262
 263         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 264                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 265                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 266                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 267                 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
 268                 V_FW_RI_RES_WR_IQID(scq->cqid));
 269         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 270                 V_FW_RI_RES_WR_DCAEN(0) |
 271                 V_FW_RI_RES_WR_DCACPU(0) |
 272                 V_FW_RI_RES_WR_FBMIN(2) |
 273                 V_FW_RI_RES_WR_FBMAX(2) |
 274                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 275                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 276                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 277         res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
 278         res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
 279         res++;
 280         res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
 281         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 282
 283         /*
 284          * eqsize is the number of 64B entries plus the status page size.
 285          */
 286         eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
 287         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 288                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 289                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 290                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 291                 V_FW_RI_RES_WR_IQID(rcq->cqid));
 292         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 293                 V_FW_RI_RES_WR_DCAEN(0) |
 294                 V_FW_RI_RES_WR_DCACPU(0) |
 295                 V_FW_RI_RES_WR_FBMIN(2) |
 296                 V_FW_RI_RES_WR_FBMAX(2) |
 297                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 298                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 299                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 300         res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
 301         res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
 302
 303         c4iw_init_wr_wait(&wr_wait);
 304
 305         ret = c4iw_ofld_send(rdev, skb);
 306         if (ret)
 307                 goto free_dma;
 308         ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
 309         if (ret)
 310                 goto free_dma;
 311
 312         PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%lx rqudb 0x%lx\n",
 313              __func__, wq->sq.qid, wq->rq.qid, wq->db,
 314              (__force unsigned long) wq->sq.udb,
 315              (__force unsigned long) wq->rq.udb);
 316
 317         return 0;
 318 free_dma:
 319         dma_free_coherent(&(rdev->lldi.pdev->dev),
 320                           wq->rq.memsize, wq->rq.queue,
 321                           dma_unmap_addr(&wq->rq, mapping));
 322 free_sq:
 323         dealloc_sq(rdev, &wq->sq);
 324 free_hwaddr:
 325         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 326 free_sw_rq:
 327         kfree(wq->rq.sw_rq);
 328 free_sw_sq:
 329         kfree(wq->sq.sw_sq);
 330 free_rq_qid:
 331         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 332 free_sq_qid:
 333         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 334         return ret;
 335 }
 336
 337 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
 338                       struct ib_send_wr *wr, int max, u32 *plenp)
 339 {
 340         u8 *dstp, *srcp;
 341         u32 plen = 0;
 342         int i;
 343         int rem, len;
 344
 345         dstp = (u8 *)immdp->data;
 346         for (i = 0; i < wr->num_sge; i++) {
 347                 if ((plen + wr->sg_list[i].length) > max)
 348                         return -EMSGSIZE;
 349                 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
 350                 plen += wr->sg_list[i].length;
 351                 rem = wr->sg_list[i].length;
 352                 while (rem) {
 353                         if (dstp == (u8 *)&sq->queue[sq->size])
 354                                 dstp = (u8 *)sq->queue;
 355                         if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
 356                                 len = rem;
 357                         else
 358                                 len = (u8 *)&sq->queue[sq->size] - dstp;
 359                         memcpy(dstp, srcp, len);
 360                         dstp += len;
 361                         srcp += len;
 362                         rem -= len;
 363                 }
 364         }
 365         len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
 366         if (len)
 367                 memset(dstp, 0, len);
 368         immdp->op = FW_RI_DATA_IMMD;
 369         immdp->r1 = 0;
 370         immdp->r2 = 0;
 371         immdp->immdlen = cpu_to_be32(plen);
 372         *plenp = plen;
 373         return 0;
 374 }
 375
 376 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
 377                       struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
 378                       int num_sge, u32 *plenp)
 379
 380 {
 381         int i;
 382         u32 plen = 0;
 383         __be64 *flitp = (__be64 *)isglp->sge;
 384
 385         for (i = 0; i < num_sge; i++) {
 386                 if ((plen + sg_list[i].length) < plen)
 387                         return -EMSGSIZE;
 388                 plen += sg_list[i].length;
 389                 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
 390                                      sg_list[i].length);
 391                 if (++flitp == queue_end)
 392                         flitp = queue_start;
 393                 *flitp = cpu_to_be64(sg_list[i].addr);
 394                 if (++flitp == queue_end)
 395                         flitp = queue_start;
 396         }
 397         *flitp = (__force __be64)0;
 398         isglp->op = FW_RI_DATA_ISGL;
 399         isglp->r1 = 0;
 400         isglp->nsge = cpu_to_be16(num_sge);
 401         isglp->r2 = 0;
 402         if (plenp)
 403                 *plenp = plen;
 404         return 0;
 405 }
 406
 407 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
 408                            struct ib_send_wr *wr, u8 *len16)
 409 {
 410         u32 plen;
 411         int size;
 412         int ret;
 413
 414         if (wr->num_sge > T4_MAX_SEND_SGE)
 415                 return -EINVAL;
 416         switch (wr->opcode) {
 417         case IB_WR_SEND:
 418                 if (wr->send_flags & IB_SEND_SOLICITED)
 419                         wqe->send.sendop_pkd = cpu_to_be32(
 420                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
 421                 else
 422                         wqe->send.sendop_pkd = cpu_to_be32(
 423                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
 424                 wqe->send.stag_inv = 0;
 425                 break;
 426         case IB_WR_SEND_WITH_INV:
 427                 if (wr->send_flags & IB_SEND_SOLICITED)
 428                         wqe->send.sendop_pkd = cpu_to_be32(
 429                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
 430                 else
 431                         wqe->send.sendop_pkd = cpu_to_be32(
 432                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
 433                 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 434                 break;
 435
 436         default:
 437                 return -EINVAL;
 438         }
 439
 440         plen = 0;
 441         if (wr->num_sge) {
 442                 if (wr->send_flags & IB_SEND_INLINE) {
 443                         ret = build_immd(sq, wqe->send.u.immd_src, wr,
 444                                          T4_MAX_SEND_INLINE, &plen);
 445                         if (ret)
 446                                 return ret;
 447                         size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
 448                                plen;
 449                 } else {
 450                         ret = build_isgl((__be64 *)sq->queue,
 451                                          (__be64 *)&sq->queue[sq->size],
 452                                          wqe->send.u.isgl_src,
 453                                          wr->sg_list, wr->num_sge, &plen);
 454                         if (ret)
 455                                 return ret;
 456                         size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
 457                                wr->num_sge * sizeof(struct fw_ri_sge);
 458                 }
 459         } else {
 460                 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
 461                 wqe->send.u.immd_src[0].r1 = 0;
 462                 wqe->send.u.immd_src[0].r2 = 0;
 463                 wqe->send.u.immd_src[0].immdlen = 0;
 464                 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
 465                 plen = 0;
 466         }
 467         *len16 = DIV_ROUND_UP(size, 16);
 468         wqe->send.plen = cpu_to_be32(plen);
 469         return 0;
 470 }
 471
 472 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
 473                             struct ib_send_wr *wr, u8 *len16)
 474 {
 475         u32 plen;
 476         int size;
 477         int ret;
 478
 479         if (wr->num_sge > T4_MAX_SEND_SGE)
 480                 return -EINVAL;
 481         wqe->write.r2 = 0;
 482         wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
 483         wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
 484         if (wr->num_sge) {
 485                 if (wr->send_flags & IB_SEND_INLINE) {
 486                         ret = build_immd(sq, wqe->write.u.immd_src, wr,
 487                                          T4_MAX_WRITE_INLINE, &plen);
 488                         if (ret)
 489                                 return ret;
 490                         size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
 491                                plen;
 492                 } else {
 493                         ret = build_isgl((__be64 *)sq->queue,
 494                                          (__be64 *)&sq->queue[sq->size],
 495                                          wqe->write.u.isgl_src,
 496                                          wr->sg_list, wr->num_sge, &plen);
 497                         if (ret)
 498                                 return ret;
 499                         size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
 500                                wr->num_sge * sizeof(struct fw_ri_sge);
 501                 }
 502         } else {
 503                 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
 504                 wqe->write.u.immd_src[0].r1 = 0;
 505                 wqe->write.u.immd_src[0].r2 = 0;
 506                 wqe->write.u.immd_src[0].immdlen = 0;
 507                 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
 508                 plen = 0;
 509         }
 510         *len16 = DIV_ROUND_UP(size, 16);
 511         wqe->write.plen = cpu_to_be32(plen);
 512         return 0;
 513 }
 514
 515 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
 516 {
 517         if (wr->num_sge > 1)
 518                 return -EINVAL;
 519         if (wr->num_sge) {
 520                 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
 521                 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
 522                                                         >> 32));
 523                 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
 524                 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
 525                 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
 526                 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
 527                                                          >> 32));
 528                 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
 529         } else {
 530                 wqe->read.stag_src = cpu_to_be32(2);
 531                 wqe->read.to_src_hi = 0;
 532                 wqe->read.to_src_lo = 0;
 533                 wqe->read.stag_sink = cpu_to_be32(2);
 534                 wqe->read.plen = 0;
 535                 wqe->read.to_sink_hi = 0;
 536                 wqe->read.to_sink_lo = 0;
 537         }
 538         wqe->read.r2 = 0;
 539         wqe->read.r5 = 0;
 540         *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
 541         return 0;
 542 }
 543
 544 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
 545                            struct ib_recv_wr *wr, u8 *len16)
 546 {
 547         int ret;
 548
 549         ret = build_isgl((__be64 *)qhp->wq.rq.queue,
 550                          (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
 551                          &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
 552         if (ret)
 553                 return ret;
 554         *len16 = DIV_ROUND_UP(sizeof wqe->recv +
 555                               wr->num_sge * sizeof(struct fw_ri_sge), 16);
 556         return 0;
 557 }
 558
 559 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
 560                          struct ib_send_wr *wr, u8 *len16, u8 t5dev)
 561 {
 562
 563         struct fw_ri_immd *imdp;
 564         __be64 *p;
 565         int i;
 566         int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
 567         int rem;
 568
 569         if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
 570                 return -EINVAL;
 571
 572         wqe->fr.qpbinde_to_dcacpu = 0;
 573         wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
 574         wqe->fr.addr_type = FW_RI_VA_BASED_TO;
 575         wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
 576         wqe->fr.len_hi = 0;
 577         wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
 578         wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
 579         wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
 580         wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
 581                                         0xffffffff);
 582
 583         if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
 584                 struct c4iw_fr_page_list *c4pl =
 585                         to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
 586                 struct fw_ri_dsgl *sglp;
 587
 588                 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
 589                         wr->wr.fast_reg.page_list->page_list[i] = (__force u64)
 590                                 cpu_to_be64((u64)
 591                                 wr->wr.fast_reg.page_list->page_list[i]);
 592                 }
 593
 594                 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
 595                 sglp->op = FW_RI_DATA_DSGL;
 596                 sglp->r1 = 0;
 597                 sglp->nsge = cpu_to_be16(1);
 598                 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
 599                 sglp->len0 = cpu_to_be32(pbllen);
 600
 601                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
 602         } else {
 603                 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
 604                 imdp->op = FW_RI_DATA_IMMD;
 605                 imdp->r1 = 0;
 606                 imdp->r2 = 0;
 607                 imdp->immdlen = cpu_to_be32(pbllen);
 608                 p = (__be64 *)(imdp + 1);
 609                 rem = pbllen;
 610                 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
 611                         *p = cpu_to_be64(
 612                                 (u64)wr->wr.fast_reg.page_list->page_list[i]);
 613                         rem -= sizeof(*p);
 614                         if (++p == (__be64 *)&sq->queue[sq->size])
 615                                 p = (__be64 *)sq->queue;
 616                 }
 617                 BUG_ON(rem < 0);
 618                 while (rem) {
 619                         *p = 0;
 620                         rem -= sizeof(*p);
 621                         if (++p == (__be64 *)&sq->queue[sq->size])
 622                                 p = (__be64 *)sq->queue;
 623                 }
 624                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
 625                                       + pbllen, 16);
 626         }
 627         return 0;
 628 }
 629
 630 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
 631                           u8 *len16)
 632 {
 633         wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 634         wqe->inv.r2 = 0;
 635         *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
 636         return 0;
 637 }
 638
 639 void c4iw_qp_add_ref(struct ib_qp *qp)
 640 {
 641         PDBG("%s ib_qp %p\n", __func__, qp);
 642         atomic_inc(&(to_c4iw_qp(qp)->refcnt));
 643 }
 644
 645 void c4iw_qp_rem_ref(struct ib_qp *qp)
 646 {
 647         PDBG("%s ib_qp %p\n", __func__, qp);
 648         if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
 649                 wake_up(&(to_c4iw_qp(qp)->wait));
 650 }
 651
 652 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
 653 {
 654         if (list_empty(entry))
 655                 list_add_tail(entry, head);
 656 }
 657
 658 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
 659 {
 660         unsigned long flags;
 661
 662         spin_lock_irqsave(&qhp->rhp->lock, flags);
 663         spin_lock(&qhp->lock);
 664         if (qhp->rhp->db_state == NORMAL)
 665                 t4_ring_sq_db(&qhp->wq, inc,
 666                               is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
 667         else {
 668                 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
 669                 qhp->wq.sq.wq_pidx_inc += inc;
 670         }
 671         spin_unlock(&qhp->lock);
 672         spin_unlock_irqrestore(&qhp->rhp->lock, flags);
 673         return 0;
 674 }
 675
 676 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
 677 {
 678         unsigned long flags;
 679
 680         spin_lock_irqsave(&qhp->rhp->lock, flags);
 681         spin_lock(&qhp->lock);
 682         if (qhp->rhp->db_state == NORMAL)
 683                 t4_ring_rq_db(&qhp->wq, inc,
 684                               is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
 685         else {
 686                 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
 687                 qhp->wq.rq.wq_pidx_inc += inc;
 688         }
 689         spin_unlock(&qhp->lock);
 690         spin_unlock_irqrestore(&qhp->rhp->lock, flags);
 691         return 0;
 692 }
 693
 694 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 695                    struct ib_send_wr **bad_wr)
 696 {
 697         int err = 0;
 698         u8 len16 = 0;
 699         enum fw_wr_opcodes fw_opcode = 0;
 700         enum fw_ri_wr_flags fw_flags;
 701         struct c4iw_qp *qhp;
 702         union t4_wr *wqe = NULL;
 703         u32 num_wrs;
 704         struct t4_swsqe *swsqe;
 705         unsigned long flag;
 706         u16 idx = 0;
 707
 708         qhp = to_c4iw_qp(ibqp);
 709         spin_lock_irqsave(&qhp->lock, flag);
 710         if (t4_wq_in_error(&qhp->wq)) {
 711                 spin_unlock_irqrestore(&qhp->lock, flag);
 712                 return -EINVAL;
 713         }
 714         num_wrs = t4_sq_avail(&qhp->wq);
 715         if (num_wrs == 0) {
 716                 spin_unlock_irqrestore(&qhp->lock, flag);
 717                 return -ENOMEM;
 718         }
 719         while (wr) {
 720                 if (num_wrs == 0) {
 721                         err = -ENOMEM;
 722                         *bad_wr = wr;
 723                         break;
 724                 }
 725                 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
 726                       qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
 727
 728                 fw_flags = 0;
 729                 if (wr->send_flags & IB_SEND_SOLICITED)
 730                         fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
 731                 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
 732                         fw_flags |= FW_RI_COMPLETION_FLAG;
 733                 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
 734                 switch (wr->opcode) {
 735                 case IB_WR_SEND_WITH_INV:
 736                 case IB_WR_SEND:
 737                         if (wr->send_flags & IB_SEND_FENCE)
 738                                 fw_flags |= FW_RI_READ_FENCE_FLAG;
 739                         fw_opcode = FW_RI_SEND_WR;
 740                         if (wr->opcode == IB_WR_SEND)
 741                                 swsqe->opcode = FW_RI_SEND;
 742                         else
 743                                 swsqe->opcode = FW_RI_SEND_WITH_INV;
 744                         err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
 745                         break;
 746                 case IB_WR_RDMA_WRITE:
 747                         fw_opcode = FW_RI_RDMA_WRITE_WR;
 748                         swsqe->opcode = FW_RI_RDMA_WRITE;
 749                         err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
 750                         break;
 751                 case IB_WR_RDMA_READ:
 752                 case IB_WR_RDMA_READ_WITH_INV:
 753                         fw_opcode = FW_RI_RDMA_READ_WR;
 754                         swsqe->opcode = FW_RI_READ_REQ;
 755                         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
 756                                 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
 757                         else
 758                                 fw_flags = 0;
 759                         err = build_rdma_read(wqe, wr, &len16);
 760                         if (err)
 761                                 break;
 762                         swsqe->read_len = wr->sg_list[0].length;
 763                         if (!qhp->wq.sq.oldest_read)
 764                                 qhp->wq.sq.oldest_read = swsqe;
 765                         break;
 766                 case IB_WR_FAST_REG_MR:
 767                         fw_opcode = FW_RI_FR_NSMR_WR;
 768                         swsqe->opcode = FW_RI_FAST_REGISTER;
 769                         err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16,
 770                                             is_t5(
 771                                             qhp->rhp->rdev.lldi.adapter_type) ?
 772                                             1 : 0);
 773                         break;
 774                 case IB_WR_LOCAL_INV:
 775                         if (wr->send_flags & IB_SEND_FENCE)
 776                                 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
 777                         fw_opcode = FW_RI_INV_LSTAG_WR;
 778                         swsqe->opcode = FW_RI_LOCAL_INV;
 779                         err = build_inv_stag(wqe, wr, &len16);
 780                         break;
 781                 default:
 782                         PDBG("%s post of type=%d TBD!\n", __func__,
 783                              wr->opcode);
 784                         err = -EINVAL;
 785                 }
 786                 if (err) {
 787                         *bad_wr = wr;
 788                         break;
 789                 }
 790                 swsqe->idx = qhp->wq.sq.pidx;
 791                 swsqe->complete = 0;
 792                 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
 793                                   qhp->sq_sig_all;
 794                 swsqe->flushed = 0;
 795                 swsqe->wr_id = wr->wr_id;
 796
 797                 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
 798
 799                 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
 800                      __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
 801                      swsqe->opcode, swsqe->read_len);
 802                 wr = wr->next;
 803                 num_wrs--;
 804                 t4_sq_produce(&qhp->wq, len16);
 805                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 806         }
 807         if (!qhp->rhp->rdev.status_page->db_off) {
 808                 t4_ring_sq_db(&qhp->wq, idx,
 809                               is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
 810                 spin_unlock_irqrestore(&qhp->lock, flag);
 811         } else {
 812                 spin_unlock_irqrestore(&qhp->lock, flag);
 813                 ring_kernel_sq_db(qhp, idx);
 814         }
 815         return err;
 816 }
 817
 818 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 819                       struct ib_recv_wr **bad_wr)
 820 {
 821         int err = 0;
 822         struct c4iw_qp *qhp;
 823         union t4_recv_wr *wqe = NULL;
 824         u32 num_wrs;
 825         u8 len16 = 0;
 826         unsigned long flag;
 827         u16 idx = 0;
 828
 829         qhp = to_c4iw_qp(ibqp);
 830         spin_lock_irqsave(&qhp->lock, flag);
 831         if (t4_wq_in_error(&qhp->wq)) {
 832                 spin_unlock_irqrestore(&qhp->lock, flag);
 833                 return -EINVAL;
 834         }
 835         num_wrs = t4_rq_avail(&qhp->wq);
 836         if (num_wrs == 0) {
 837                 spin_unlock_irqrestore(&qhp->lock, flag);
 838                 return -ENOMEM;
 839         }
 840         while (wr) {
 841                 if (wr->num_sge > T4_MAX_RECV_SGE) {
 842                         err = -EINVAL;
 843                         *bad_wr = wr;
 844                         break;
 845                 }
 846                 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
 847                                            qhp->wq.rq.wq_pidx *
 848                                            T4_EQ_ENTRY_SIZE);
 849                 if (num_wrs)
 850                         err = build_rdma_recv(qhp, wqe, wr, &len16);
 851                 else
 852                         err = -ENOMEM;
 853                 if (err) {
 854                         *bad_wr = wr;
 855                         break;
 856                 }
 857
 858                 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
 859
 860                 wqe->recv.opcode = FW_RI_RECV_WR;
 861                 wqe->recv.r1 = 0;
 862                 wqe->recv.wrid = qhp->wq.rq.pidx;
 863                 wqe->recv.r2[0] = 0;
 864                 wqe->recv.r2[1] = 0;
 865                 wqe->recv.r2[2] = 0;
 866                 wqe->recv.len16 = len16;
 867                 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
 868                      (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
 869                 t4_rq_produce(&qhp->wq, len16);
 870                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 871                 wr = wr->next;
 872                 num_wrs--;
 873         }
 874         if (!qhp->rhp->rdev.status_page->db_off) {
 875                 t4_ring_rq_db(&qhp->wq, idx,
 876                               is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
 877                 spin_unlock_irqrestore(&qhp->lock, flag);
 878         } else {
 879                 spin_unlock_irqrestore(&qhp->lock, flag);
 880                 ring_kernel_rq_db(qhp, idx);
 881         }
 882         return err;
 883 }
 884
 885 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
 886 {
 887         return -ENOSYS;
 888 }
 889
 890 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
 891                                     u8 *ecode)
 892 {
 893         int status;
 894         int tagged;
 895         int opcode;
 896         int rqtype;
 897         int send_inv;
 898
 899         if (!err_cqe) {
 900                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 901                 *ecode = 0;
 902                 return;
 903         }
 904
 905         status = CQE_STATUS(err_cqe);
 906         opcode = CQE_OPCODE(err_cqe);
 907         rqtype = RQ_TYPE(err_cqe);
 908         send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
 909                    (opcode == FW_RI_SEND_WITH_SE_INV);
 910         tagged = (opcode == FW_RI_RDMA_WRITE) ||
 911                  (rqtype && (opcode == FW_RI_READ_RESP));
 912
 913         switch (status) {
 914         case T4_ERR_STAG:
 915                 if (send_inv) {
 916                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 917                         *ecode = RDMAP_CANT_INV_STAG;
 918                 } else {
 919                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 920                         *ecode = RDMAP_INV_STAG;
 921                 }
 922                 break;
 923         case T4_ERR_PDID:
 924                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 925                 if ((opcode == FW_RI_SEND_WITH_INV) ||
 926                     (opcode == FW_RI_SEND_WITH_SE_INV))
 927                         *ecode = RDMAP_CANT_INV_STAG;
 928                 else
 929                         *ecode = RDMAP_STAG_NOT_ASSOC;
 930                 break;
 931         case T4_ERR_QPID:
 932                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 933                 *ecode = RDMAP_STAG_NOT_ASSOC;
 934                 break;
 935         case T4_ERR_ACCESS:
 936                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 937                 *ecode = RDMAP_ACC_VIOL;
 938                 break;
 939         case T4_ERR_WRAP:
 940                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 941                 *ecode = RDMAP_TO_WRAP;
 942                 break;
 943         case T4_ERR_BOUND:
 944                 if (tagged) {
 945                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 946                         *ecode = DDPT_BASE_BOUNDS;
 947                 } else {
 948                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 949                         *ecode = RDMAP_BASE_BOUNDS;
 950                 }
 951                 break;
 952         case T4_ERR_INVALIDATE_SHARED_MR:
 953         case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
 954                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 955                 *ecode = RDMAP_CANT_INV_STAG;
 956                 break;
 957         case T4_ERR_ECC:
 958         case T4_ERR_ECC_PSTAG:
 959         case T4_ERR_INTERNAL_ERR:
 960                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
 961                 *ecode = 0;
 962                 break;
 963         case T4_ERR_OUT_OF_RQE:
 964                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 965                 *ecode = DDPU_INV_MSN_NOBUF;
 966                 break;
 967         case T4_ERR_PBL_ADDR_BOUND:
 968                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 969                 *ecode = DDPT_BASE_BOUNDS;
 970                 break;
 971         case T4_ERR_CRC:
 972                 *layer_type = LAYER_MPA|DDP_LLP;
 973                 *ecode = MPA_CRC_ERR;
 974                 break;
 975         case T4_ERR_MARKER:
 976                 *layer_type = LAYER_MPA|DDP_LLP;
 977                 *ecode = MPA_MARKER_ERR;
 978                 break;
 979         case T4_ERR_PDU_LEN_ERR:
 980                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 981                 *ecode = DDPU_MSG_TOOBIG;
 982                 break;
 983         case T4_ERR_DDP_VERSION:
 984                 if (tagged) {
 985                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 986                         *ecode = DDPT_INV_VERS;
 987                 } else {
 988                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 989                         *ecode = DDPU_INV_VERS;
 990                 }
 991                 break;
 992         case T4_ERR_RDMA_VERSION:
 993                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 994                 *ecode = RDMAP_INV_VERS;
 995                 break;
 996         case T4_ERR_OPCODE:
 997                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 998                 *ecode = RDMAP_INV_OPCODE;
 999                 break;
1000         case T4_ERR_DDP_QUEUE_NUM:
1001                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1002                 *ecode = DDPU_INV_QN;
1003                 break;
1004         case T4_ERR_MSN:
1005         case T4_ERR_MSN_GAP:
1006         case T4_ERR_MSN_RANGE:
1007         case T4_ERR_IRD_OVERFLOW:
1008                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1009                 *ecode = DDPU_INV_MSN_RANGE;
1010                 break;
1011         case T4_ERR_TBIT:
1012                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1013                 *ecode = 0;
1014                 break;
1015         case T4_ERR_MO:
1016                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1017                 *ecode = DDPU_INV_MO;
1018                 break;
1019         default:
1020                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1021                 *ecode = 0;
1022                 break;
1023         }
1024 }
1025
1026 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1027                            gfp_t gfp)
1028 {
1029         struct fw_ri_wr *wqe;
1030         struct sk_buff *skb;
1031         struct terminate_message *term;
1032
1033         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1034              qhp->ep->hwtid);
1035
1036         skb = alloc_skb(sizeof *wqe, gfp);
1037         if (!skb)
1038                 return;
1039         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1040
1041         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1042         memset(wqe, 0, sizeof *wqe);
1043         wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
1044         wqe->flowid_len16 = cpu_to_be32(
1045                 FW_WR_FLOWID(qhp->ep->hwtid) |
1046                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1047
1048         wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1049         wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1050         term = (struct terminate_message *)wqe->u.terminate.termmsg;
1051         if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1052                 term->layer_etype = qhp->attr.layer_etype;
1053                 term->ecode = qhp->attr.ecode;
1054         } else
1055                 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1056         c4iw_ofld_send(&qhp->rhp->rdev, skb);
1057 }
1058
1059 /*
1060  * Assumes qhp lock is held.
1061  */
1062 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1063                        struct c4iw_cq *schp)
1064 {
1065         int count;
1066         int flushed;
1067         unsigned long flag;
1068
1069         PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
1070
1071         /* locking hierarchy: cq lock first, then qp lock. */
1072         spin_lock_irqsave(&rchp->lock, flag);
1073         spin_lock(&qhp->lock);
1074
1075         if (qhp->wq.flushed) {
1076                 spin_unlock(&qhp->lock);
1077                 spin_unlock_irqrestore(&rchp->lock, flag);
1078                 return;
1079         }
1080         qhp->wq.flushed = 1;
1081
1082         c4iw_flush_hw_cq(rchp);
1083         c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1084         flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1085         spin_unlock(&qhp->lock);
1086         spin_unlock_irqrestore(&rchp->lock, flag);
1087         if (flushed) {
1088                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1089                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1090                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1091         }
1092
1093         /* locking hierarchy: cq lock first, then qp lock. */
1094         spin_lock_irqsave(&schp->lock, flag);
1095         spin_lock(&qhp->lock);
1096         if (schp != rchp)
1097                 c4iw_flush_hw_cq(schp);
1098         flushed = c4iw_flush_sq(qhp);
1099         spin_unlock(&qhp->lock);
1100         spin_unlock_irqrestore(&schp->lock, flag);
1101         if (flushed) {
1102                 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1103                 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
1104                 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1105         }
1106 }
1107
1108 static void flush_qp(struct c4iw_qp *qhp)
1109 {
1110         struct c4iw_cq *rchp, *schp;
1111         unsigned long flag;
1112
1113         rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1114         schp = to_c4iw_cq(qhp->ibqp.send_cq);
1115
1116         t4_set_wq_in_error(&qhp->wq);
1117         if (qhp->ibqp.uobject) {
1118                 t4_set_cq_in_error(&rchp->cq);
1119                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1120                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1121                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1122                 if (schp != rchp) {
1123                         t4_set_cq_in_error(&schp->cq);
1124                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
1125                         (*schp->ibcq.comp_handler)(&schp->ibcq,
1126                                         schp->ibcq.cq_context);
1127                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1128                 }
1129                 return;
1130         }
1131         __flush_qp(qhp, rchp, schp);
1132 }
1133
1134 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1135                      struct c4iw_ep *ep)
1136 {
1137         struct fw_ri_wr *wqe;
1138         int ret;
1139         struct sk_buff *skb;
1140
1141         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1142              ep->hwtid);
1143
1144         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1145         if (!skb)
1146                 return -ENOMEM;
1147         set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1148
1149         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1150         memset(wqe, 0, sizeof *wqe);
1151         wqe->op_compl = cpu_to_be32(
1152                 FW_WR_OP(FW_RI_INIT_WR) |
1153                 FW_WR_COMPL(1));
1154         wqe->flowid_len16 = cpu_to_be32(
1155                 FW_WR_FLOWID(ep->hwtid) |
1156                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1157         wqe->cookie = (unsigned long) &ep->com.wr_wait;
1158
1159         wqe->u.fini.type = FW_RI_TYPE_FINI;
1160         ret = c4iw_ofld_send(&rhp->rdev, skb);
1161         if (ret)
1162                 goto out;
1163
1164         ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1165                              qhp->wq.sq.qid, __func__);
1166 out:
1167         PDBG("%s ret %d\n", __func__, ret);
1168         return ret;
1169 }
1170
1171 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1172 {
1173         PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1174         memset(&init->u, 0, sizeof init->u);
1175         switch (p2p_type) {
1176         case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1177                 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1178                 init->u.write.stag_sink = cpu_to_be32(1);
1179                 init->u.write.to_sink = cpu_to_be64(1);
1180                 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1181                 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1182                                                    sizeof(struct fw_ri_immd),
1183                                                    16);
1184                 break;
1185         case FW_RI_INIT_P2PTYPE_READ_REQ:
1186                 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1187                 init->u.read.stag_src = cpu_to_be32(1);
1188                 init->u.read.to_src_lo = cpu_to_be32(1);
1189                 init->u.read.stag_sink = cpu_to_be32(1);
1190                 init->u.read.to_sink_lo = cpu_to_be32(1);
1191                 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1192                 break;
1193         }
1194 }
1195
1196 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1197 {
1198         struct fw_ri_wr *wqe;
1199         int ret;
1200         struct sk_buff *skb;
1201
1202         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1203              qhp->ep->hwtid);
1204
1205         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1206         if (!skb)
1207                 return -ENOMEM;
1208         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1209
1210         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1211         memset(wqe, 0, sizeof *wqe);
1212         wqe->op_compl = cpu_to_be32(
1213                 FW_WR_OP(FW_RI_INIT_WR) |
1214                 FW_WR_COMPL(1));
1215         wqe->flowid_len16 = cpu_to_be32(
1216                 FW_WR_FLOWID(qhp->ep->hwtid) |
1217                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1218
1219         wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
1220
1221         wqe->u.init.type = FW_RI_TYPE_INIT;
1222         wqe->u.init.mpareqbit_p2ptype =
1223                 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1224                 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1225         wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1226         if (qhp->attr.mpa_attr.recv_marker_enabled)
1227                 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1228         if (qhp->attr.mpa_attr.xmit_marker_enabled)
1229                 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1230         if (qhp->attr.mpa_attr.crc_enabled)
1231                 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1232
1233         wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1234                             FW_RI_QP_RDMA_WRITE_ENABLE |
1235                             FW_RI_QP_BIND_ENABLE;
1236         if (!qhp->ibqp.uobject)
1237                 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1238                                      FW_RI_QP_STAG0_ENABLE;
1239         wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1240         wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1241         wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1242         wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1243         wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1244         wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1245         wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1246         wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1247         wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1248         wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1249         wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1250         wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1251         wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1252                                          rhp->rdev.lldi.vr->rq.start);
1253         if (qhp->attr.mpa_attr.initiator)
1254                 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1255
1256         ret = c4iw_ofld_send(&rhp->rdev, skb);
1257         if (ret)
1258                 goto out;
1259
1260         ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1261                                   qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1262 out:
1263         PDBG("%s ret %d\n", __func__, ret);
1264         return ret;
1265 }
1266
1267 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1268                    enum c4iw_qp_attr_mask mask,
1269                    struct c4iw_qp_attributes *attrs,
1270                    int internal)
1271 {
1272         int ret = 0;
1273         struct c4iw_qp_attributes newattr = qhp->attr;
1274         int disconnect = 0;
1275         int terminate = 0;
1276         int abort = 0;
1277         int free = 0;
1278         struct c4iw_ep *ep = NULL;
1279
1280         PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1281              qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1282              (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1283
1284         mutex_lock(&qhp->mutex);
1285
1286         /* Process attr changes if in IDLE */
1287         if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1288                 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1289                         ret = -EIO;
1290                         goto out;
1291                 }
1292                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1293                         newattr.enable_rdma_read = attrs->enable_rdma_read;
1294                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1295                         newattr.enable_rdma_write = attrs->enable_rdma_write;
1296                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1297                         newattr.enable_bind = attrs->enable_bind;
1298                 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1299                         if (attrs->max_ord > c4iw_max_read_depth) {
1300                                 ret = -EINVAL;
1301                                 goto out;
1302                         }
1303                         newattr.max_ord = attrs->max_ord;
1304                 }
1305                 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1306                         if (attrs->max_ird > c4iw_max_read_depth) {
1307                                 ret = -EINVAL;
1308                                 goto out;
1309                         }
1310                         newattr.max_ird = attrs->max_ird;
1311                 }
1312                 qhp->attr = newattr;
1313         }
1314
1315         if (mask & C4IW_QP_ATTR_SQ_DB) {
1316                 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1317                 goto out;
1318         }
1319         if (mask & C4IW_QP_ATTR_RQ_DB) {
1320                 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1321                 goto out;
1322         }
1323
1324         if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1325                 goto out;
1326         if (qhp->attr.state == attrs->next_state)
1327                 goto out;
1328
1329         switch (qhp->attr.state) {
1330         case C4IW_QP_STATE_IDLE:
1331                 switch (attrs->next_state) {
1332                 case C4IW_QP_STATE_RTS:
1333                         if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1334                                 ret = -EINVAL;
1335                                 goto out;
1336                         }
1337                         if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1338                                 ret = -EINVAL;
1339                                 goto out;
1340                         }
1341                         qhp->attr.mpa_attr = attrs->mpa_attr;
1342                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1343                         qhp->ep = qhp->attr.llp_stream_handle;
1344                         set_state(qhp, C4IW_QP_STATE_RTS);
1345
1346                         /*
1347                          * Ref the endpoint here and deref when we
1348                          * disassociate the endpoint from the QP.  This
1349                          * happens in CLOSING->IDLE transition or *->ERROR
1350                          * transition.
1351                          */
1352                         c4iw_get_ep(&qhp->ep->com);
1353                         ret = rdma_init(rhp, qhp);
1354                         if (ret)
1355                                 goto err;
1356                         break;
1357                 case C4IW_QP_STATE_ERROR:
1358                         set_state(qhp, C4IW_QP_STATE_ERROR);
1359                         flush_qp(qhp);
1360                         break;
1361                 default:
1362                         ret = -EINVAL;
1363                         goto out;
1364                 }
1365                 break;
1366         case C4IW_QP_STATE_RTS:
1367                 switch (attrs->next_state) {
1368                 case C4IW_QP_STATE_CLOSING:
1369                         BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1370                         t4_set_wq_in_error(&qhp->wq);
1371                         set_state(qhp, C4IW_QP_STATE_CLOSING);
1372                         ep = qhp->ep;
1373                         if (!internal) {
1374                                 abort = 0;
1375                                 disconnect = 1;
1376                                 c4iw_get_ep(&qhp->ep->com);
1377                         }
1378                         ret = rdma_fini(rhp, qhp, ep);
1379                         if (ret)
1380                                 goto err;
1381                         break;
1382                 case C4IW_QP_STATE_TERMINATE:
1383                         t4_set_wq_in_error(&qhp->wq);
1384                         set_state(qhp, C4IW_QP_STATE_TERMINATE);
1385                         qhp->attr.layer_etype = attrs->layer_etype;
1386                         qhp->attr.ecode = attrs->ecode;
1387                         ep = qhp->ep;
1388                         disconnect = 1;
1389                         if (!internal)
1390                                 terminate = 1;
1391                         else {
1392                                 ret = rdma_fini(rhp, qhp, ep);
1393                                 if (ret)
1394                                         goto err;
1395                         }
1396                         c4iw_get_ep(&qhp->ep->com);
1397                         break;
1398                 case C4IW_QP_STATE_ERROR:
1399                         t4_set_wq_in_error(&qhp->wq);
1400                         set_state(qhp, C4IW_QP_STATE_ERROR);
1401                         if (!internal) {
1402                                 abort = 1;
1403                                 disconnect = 1;
1404                                 ep = qhp->ep;
1405                                 c4iw_get_ep(&qhp->ep->com);
1406                         }
1407                         goto err;
1408                         break;
1409                 default:
1410                         ret = -EINVAL;
1411                         goto out;
1412                 }
1413                 break;
1414         case C4IW_QP_STATE_CLOSING:
1415                 if (!internal) {
1416                         ret = -EINVAL;
1417                         goto out;
1418                 }
1419                 switch (attrs->next_state) {
1420                 case C4IW_QP_STATE_IDLE:
1421                         flush_qp(qhp);
1422                         set_state(qhp, C4IW_QP_STATE_IDLE);
1423                         qhp->attr.llp_stream_handle = NULL;
1424                         c4iw_put_ep(&qhp->ep->com);
1425                         qhp->ep = NULL;
1426                         wake_up(&qhp->wait);
1427                         break;
1428                 case C4IW_QP_STATE_ERROR:
1429                         goto err;
1430                 default:
1431                         ret = -EINVAL;
1432                         goto err;
1433                 }
1434                 break;
1435         case C4IW_QP_STATE_ERROR:
1436                 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1437                         ret = -EINVAL;
1438                         goto out;
1439                 }
1440                 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1441                         ret = -EINVAL;
1442                         goto out;
1443                 }
1444                 set_state(qhp, C4IW_QP_STATE_IDLE);
1445                 break;
1446         case C4IW_QP_STATE_TERMINATE:
1447                 if (!internal) {
1448                         ret = -EINVAL;
1449                         goto out;
1450                 }
1451                 goto err;
1452                 break;
1453         default:
1454                 printk(KERN_ERR "%s in a bad state %d\n",
1455                        __func__, qhp->attr.state);
1456                 ret = -EINVAL;
1457                 goto err;
1458                 break;
1459         }
1460         goto out;
1461 err:
1462         PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1463              qhp->wq.sq.qid);
1464
1465         /* disassociate the LLP connection */
1466         qhp->attr.llp_stream_handle = NULL;
1467         if (!ep)
1468                 ep = qhp->ep;
1469         qhp->ep = NULL;
1470         set_state(qhp, C4IW_QP_STATE_ERROR);
1471         free = 1;
1472         abort = 1;
1473         wake_up(&qhp->wait);
1474         BUG_ON(!ep);
1475         flush_qp(qhp);
1476 out:
1477         mutex_unlock(&qhp->mutex);
1478
1479         if (terminate)
1480                 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1481
1482         /*
1483          * If disconnect is 1, then we need to initiate a disconnect
1484          * on the EP.  This can be a normal close (RTS->CLOSING) or
1485          * an abnormal close (RTS/CLOSING->ERROR).
1486          */
1487         if (disconnect) {
1488                 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1489                                                          GFP_KERNEL);
1490                 c4iw_put_ep(&ep->com);
1491         }
1492
1493         /*
1494          * If free is 1, then we've disassociated the EP from the QP
1495          * and we need to dereference the EP.
1496          */
1497         if (free)
1498                 c4iw_put_ep(&ep->com);
1499         PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1500         return ret;
1501 }
1502
1503 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1504 {
1505         struct c4iw_dev *rhp;
1506         struct c4iw_qp *qhp;
1507         struct c4iw_qp_attributes attrs;
1508         struct c4iw_ucontext *ucontext;
1509
1510         qhp = to_c4iw_qp(ib_qp);
1511         rhp = qhp->rhp;
1512
1513         attrs.next_state = C4IW_QP_STATE_ERROR;
1514         if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1515                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1516         else
1517                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1518         wait_event(qhp->wait, !qhp->ep);
1519
1520         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1521         atomic_dec(&qhp->refcnt);
1522         wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1523
1524         spin_lock_irq(&rhp->lock);
1525         if (!list_empty(&qhp->db_fc_entry))
1526                 list_del_init(&qhp->db_fc_entry);
1527         spin_unlock_irq(&rhp->lock);
1528
1529         ucontext = ib_qp->uobject ?
1530                    to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1531         destroy_qp(&rhp->rdev, &qhp->wq,
1532                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1533
1534         PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1535         kfree(qhp);
1536         return 0;
1537 }
1538
1539 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1540                              struct ib_udata *udata)
1541 {
1542         struct c4iw_dev *rhp;
1543         struct c4iw_qp *qhp;
1544         struct c4iw_pd *php;
1545         struct c4iw_cq *schp;
1546         struct c4iw_cq *rchp;
1547         struct c4iw_create_qp_resp uresp;
1548         unsigned int sqsize, rqsize;
1549         struct c4iw_ucontext *ucontext;
1550         int ret;
1551         struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1552
1553         PDBG("%s ib_pd %p\n", __func__, pd);
1554
1555         if (attrs->qp_type != IB_QPT_RC)
1556                 return ERR_PTR(-EINVAL);
1557
1558         php = to_c4iw_pd(pd);
1559         rhp = php->rhp;
1560         schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1561         rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1562         if (!schp || !rchp)
1563                 return ERR_PTR(-EINVAL);
1564
1565         if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1566                 return ERR_PTR(-EINVAL);
1567
1568         rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1569         if (rqsize > T4_MAX_RQ_SIZE)
1570                 return ERR_PTR(-E2BIG);
1571
1572         sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1573         if (sqsize > T4_MAX_SQ_SIZE)
1574                 return ERR_PTR(-E2BIG);
1575
1576         ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1577
1578         qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1579         if (!qhp)
1580                 return ERR_PTR(-ENOMEM);
1581         qhp->wq.sq.size = sqsize;
1582         qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1583         qhp->wq.sq.flush_cidx = -1;
1584         qhp->wq.rq.size = rqsize;
1585         qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1586
1587         if (ucontext) {
1588                 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1589                 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1590         }
1591
1592         PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1593              __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1594
1595         ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1596                         ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1597         if (ret)
1598                 goto err1;
1599
1600         attrs->cap.max_recv_wr = rqsize - 1;
1601         attrs->cap.max_send_wr = sqsize - 1;
1602         attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1603
1604         qhp->rhp = rhp;
1605         qhp->attr.pd = php->pdid;
1606         qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1607         qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1608         qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1609         qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1610         qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1611         qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1612         qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1613         qhp->attr.state = C4IW_QP_STATE_IDLE;
1614         qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1615         qhp->attr.enable_rdma_read = 1;
1616         qhp->attr.enable_rdma_write = 1;
1617         qhp->attr.enable_bind = 1;
1618         qhp->attr.max_ord = 1;
1619         qhp->attr.max_ird = 1;
1620         qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1621         spin_lock_init(&qhp->lock);
1622         mutex_init(&qhp->mutex);
1623         init_waitqueue_head(&qhp->wait);
1624         atomic_set(&qhp->refcnt, 1);
1625
1626         ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1627         if (ret)
1628                 goto err2;
1629
1630         if (udata) {
1631                 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1632                 if (!mm1) {
1633                         ret = -ENOMEM;
1634                         goto err3;
1635                 }
1636                 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1637                 if (!mm2) {
1638                         ret = -ENOMEM;
1639                         goto err4;
1640                 }
1641                 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1642                 if (!mm3) {
1643                         ret = -ENOMEM;
1644                         goto err5;
1645                 }
1646                 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1647                 if (!mm4) {
1648                         ret = -ENOMEM;
1649                         goto err6;
1650                 }
1651                 if (t4_sq_onchip(&qhp->wq.sq)) {
1652                         mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1653                         if (!mm5) {
1654                                 ret = -ENOMEM;
1655                                 goto err7;
1656                         }
1657                         uresp.flags = C4IW_QPF_ONCHIP;
1658                 } else
1659                         uresp.flags = 0;
1660                 uresp.qid_mask = rhp->rdev.qpmask;
1661                 uresp.sqid = qhp->wq.sq.qid;
1662                 uresp.sq_size = qhp->wq.sq.size;
1663                 uresp.sq_memsize = qhp->wq.sq.memsize;
1664                 uresp.rqid = qhp->wq.rq.qid;
1665                 uresp.rq_size = qhp->wq.rq.size;
1666                 uresp.rq_memsize = qhp->wq.rq.memsize;
1667                 spin_lock(&ucontext->mmap_lock);
1668                 if (mm5) {
1669                         uresp.ma_sync_key = ucontext->key;
1670                         ucontext->key += PAGE_SIZE;
1671                 } else {
1672                         uresp.ma_sync_key =  0;
1673                 }
1674                 uresp.sq_key = ucontext->key;
1675                 ucontext->key += PAGE_SIZE;
1676                 uresp.rq_key = ucontext->key;
1677                 ucontext->key += PAGE_SIZE;
1678                 uresp.sq_db_gts_key = ucontext->key;
1679                 ucontext->key += PAGE_SIZE;
1680                 uresp.rq_db_gts_key = ucontext->key;
1681                 ucontext->key += PAGE_SIZE;
1682                 spin_unlock(&ucontext->mmap_lock);
1683                 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1684                 if (ret)
1685                         goto err8;
1686                 mm1->key = uresp.sq_key;
1687                 mm1->addr = qhp->wq.sq.phys_addr;
1688                 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1689                 insert_mmap(ucontext, mm1);
1690                 mm2->key = uresp.rq_key;
1691                 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1692                 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1693                 insert_mmap(ucontext, mm2);
1694                 mm3->key = uresp.sq_db_gts_key;
1695                 mm3->addr = (__force unsigned long) qhp->wq.sq.udb;
1696                 mm3->len = PAGE_SIZE;
1697                 insert_mmap(ucontext, mm3);
1698                 mm4->key = uresp.rq_db_gts_key;
1699                 mm4->addr = (__force unsigned long) qhp->wq.rq.udb;
1700                 mm4->len = PAGE_SIZE;
1701                 insert_mmap(ucontext, mm4);
1702                 if (mm5) {
1703                         mm5->key = uresp.ma_sync_key;
1704                         mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1705                                     + A_PCIE_MA_SYNC) & PAGE_MASK;
1706                         mm5->len = PAGE_SIZE;
1707                         insert_mmap(ucontext, mm5);
1708                 }
1709         }
1710         qhp->ibqp.qp_num = qhp->wq.sq.qid;
1711         init_timer(&(qhp->timer));
1712         INIT_LIST_HEAD(&qhp->db_fc_entry);
1713         PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1714              __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1715              qhp->wq.sq.qid);
1716         return &qhp->ibqp;
1717 err8:
1718         kfree(mm5);
1719 err7:
1720         kfree(mm4);
1721 err6:
1722         kfree(mm3);
1723 err5:
1724         kfree(mm2);
1725 err4:
1726         kfree(mm1);
1727 err3:
1728         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1729 err2:
1730         destroy_qp(&rhp->rdev, &qhp->wq,
1731                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1732 err1:
1733         kfree(qhp);
1734         return ERR_PTR(ret);
1735 }
1736
1737 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1738                       int attr_mask, struct ib_udata *udata)
1739 {
1740         struct c4iw_dev *rhp;
1741         struct c4iw_qp *qhp;
1742         enum c4iw_qp_attr_mask mask = 0;
1743         struct c4iw_qp_attributes attrs;
1744
1745         PDBG("%s ib_qp %p\n", __func__, ibqp);
1746
1747         /* iwarp does not support the RTR state */
1748         if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1749                 attr_mask &= ~IB_QP_STATE;
1750
1751         /* Make sure we still have something left to do */
1752         if (!attr_mask)
1753                 return 0;
1754
1755         memset(&attrs, 0, sizeof attrs);
1756         qhp = to_c4iw_qp(ibqp);
1757         rhp = qhp->rhp;
1758
1759         attrs.next_state = c4iw_convert_state(attr->qp_state);
1760         attrs.enable_rdma_read = (attr->qp_access_flags &
1761                                IB_ACCESS_REMOTE_READ) ?  1 : 0;
1762         attrs.enable_rdma_write = (attr->qp_access_flags &
1763                                 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1764         attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1765
1766
1767         mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1768         mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1769                         (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1770                          C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1771                          C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1772
1773         /*
1774          * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1775          * ringing the queue db when we're in DB_FULL mode.
1776          */
1777         attrs.sq_db_inc = attr->sq_psn;
1778         attrs.rq_db_inc = attr->rq_psn;
1779         mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1780         mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1781
1782         return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1783 }
1784
1785 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1786 {
1787         PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1788         return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1789 }
1790
1791 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1792                      int attr_mask, struct ib_qp_init_attr *init_attr)
1793 {
1794         struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1795
1796         memset(attr, 0, sizeof *attr);
1797         memset(init_attr, 0, sizeof *init_attr);
1798         attr->qp_state = to_ib_qp_state(qhp->attr.state);
1799         return 0;
1800 }