drivers/infiniband/hw/cxgb4/qp.c

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34
  35 #include "iw_cxgb4.h"
  36
  37 static int db_delay_usecs = 1;
  38 module_param(db_delay_usecs, int, 0644);
  39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
  40
  41 static int ocqp_support = 1;
  42 module_param(ocqp_support, int, 0644);
  43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
  44
  45 int db_fc_threshold = 1000;
  46 module_param(db_fc_threshold, int, 0644);
  47 MODULE_PARM_DESC(db_fc_threshold,
  48                  "QP count/threshold that triggers"
  49                  " automatic db flow control mode (default = 1000)");
  50
  51 int db_coalescing_threshold;
  52 module_param(db_coalescing_threshold, int, 0644);
  53 MODULE_PARM_DESC(db_coalescing_threshold,
  54                  "QP count/threshold that triggers"
  55                  " disabling db coalescing (default = 0)");
  56
  57 static int max_fr_immd = T4_MAX_FR_IMMD;
  58 module_param(max_fr_immd, int, 0644);
  59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
  60
  61 static int alloc_ird(struct c4iw_dev *dev, u32 ird)
  62 {
  63         int ret = 0;
  64
  65         spin_lock_irq(&dev->lock);
  66         if (ird <= dev->avail_ird)
  67                 dev->avail_ird -= ird;
  68         else
  69                 ret = -ENOMEM;
  70         spin_unlock_irq(&dev->lock);
  71
  72         if (ret)
  73                 dev_warn(&dev->rdev.lldi.pdev->dev,
  74                          "device IRD resources exhausted\n");
  75
  76         return ret;
  77 }
  78
  79 static void free_ird(struct c4iw_dev *dev, int ird)
  80 {
  81         spin_lock_irq(&dev->lock);
  82         dev->avail_ird += ird;
  83         spin_unlock_irq(&dev->lock);
  84 }
  85
  86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
  87 {
  88         unsigned long flag;
  89         spin_lock_irqsave(&qhp->lock, flag);
  90         qhp->attr.state = state;
  91         spin_unlock_irqrestore(&qhp->lock, flag);
  92 }
  93
  94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  95 {
  96         c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
  97 }
  98
  99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 100 {
 101         dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
 102                           pci_unmap_addr(sq, mapping));
 103 }
 104
 105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 106 {
 107         if (t4_sq_onchip(sq))
 108                 dealloc_oc_sq(rdev, sq);
 109         else
 110                 dealloc_host_sq(rdev, sq);
 111 }
 112
 113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 114 {
 115         if (!ocqp_support || !ocqp_supported(&rdev->lldi))
 116                 return -ENOSYS;
 117         sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
 118         if (!sq->dma_addr)
 119                 return -ENOMEM;
 120         sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
 121                         rdev->lldi.vr->ocq.start;
 122         sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
 123                                             rdev->lldi.vr->ocq.start);
 124         sq->flags |= T4_SQ_ONCHIP;
 125         return 0;
 126 }
 127
 128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 129 {
 130         sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
 131                                        &(sq->dma_addr), GFP_KERNEL);
 132         if (!sq->queue)
 133                 return -ENOMEM;
 134         sq->phys_addr = virt_to_phys(sq->queue);
 135         pci_unmap_addr_set(sq, mapping, sq->dma_addr);
 136         return 0;
 137 }
 138
 139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
 140 {
 141         int ret = -ENOSYS;
 142         if (user)
 143                 ret = alloc_oc_sq(rdev, sq);
 144         if (ret)
 145                 ret = alloc_host_sq(rdev, sq);
 146         return ret;
 147 }
 148
 149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 150                       struct c4iw_dev_ucontext *uctx, int has_rq)
 151 {
 152         /*
 153          * uP clears EQ contexts when the connection exits rdma mode,
 154          * so no need to post a RESET WR for these EQs.
 155          */
 156         dealloc_sq(rdev, &wq->sq);
 157         kfree(wq->sq.sw_sq);
 158         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 159
 160         if (has_rq) {
 161                 dma_free_coherent(&rdev->lldi.pdev->dev,
 162                                   wq->rq.memsize, wq->rq.queue,
 163                                   dma_unmap_addr(&wq->rq, mapping));
 164                 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 165                 kfree(wq->rq.sw_rq);
 166                 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 167         }
 168         return 0;
 169 }
 170
 171 /*
 172  * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL,
 173  * then this is a user mapping so compute the page-aligned physical address
 174  * for mapping.
 175  */
 176 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
 177                               enum cxgb4_bar2_qtype qtype,
 178                               unsigned int *pbar2_qid, u64 *pbar2_pa)
 179 {
 180         u64 bar2_qoffset;
 181         int ret;
 182
 183         ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype,
 184                                    pbar2_pa ? 1 : 0,
 185                                    &bar2_qoffset, pbar2_qid);
 186         if (ret)
 187                 return NULL;
 188
 189         if (pbar2_pa)
 190                 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK;
 191
 192         if (is_t4(rdev->lldi.adapter_type))
 193                 return NULL;
 194
 195         return rdev->bar2_kva + bar2_qoffset;
 196 }
 197
 198 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 199                      struct t4_cq *rcq, struct t4_cq *scq,
 200                      struct c4iw_dev_ucontext *uctx,
 201                      struct c4iw_wr_wait *wr_waitp,
 202                      int need_rq)
 203 {
 204         int user = (uctx != &rdev->uctx);
 205         struct fw_ri_res_wr *res_wr;
 206         struct fw_ri_res *res;
 207         int wr_len;
 208         struct sk_buff *skb;
 209         int ret = 0;
 210         int eqsize;
 211
 212         wq->sq.qid = c4iw_get_qpid(rdev, uctx);
 213         if (!wq->sq.qid)
 214                 return -ENOMEM;
 215
 216         if (need_rq) {
 217                 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
 218                 if (!wq->rq.qid) {
 219                         ret = -ENOMEM;
 220                         goto free_sq_qid;
 221                 }
 222         }
 223
 224         if (!user) {
 225                 wq->sq.sw_sq = kcalloc(wq->sq.size, sizeof(*wq->sq.sw_sq),
 226                                        GFP_KERNEL);
 227                 if (!wq->sq.sw_sq) {
 228                         ret = -ENOMEM;
 229                         goto free_rq_qid;//FIXME
 230                 }
 231
 232                 if (need_rq) {
 233                         wq->rq.sw_rq = kcalloc(wq->rq.size,
 234                                                sizeof(*wq->rq.sw_rq),
 235                                                GFP_KERNEL);
 236                         if (!wq->rq.sw_rq) {
 237                                 ret = -ENOMEM;
 238                                 goto free_sw_sq;
 239                         }
 240                 }
 241         }
 242
 243         if (need_rq) {
 244                 /*
 245                  * RQT must be a power of 2 and at least 16 deep.
 246                  */
 247                 wq->rq.rqt_size =
 248                         roundup_pow_of_two(max_t(u16, wq->rq.size, 16));
 249                 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
 250                 if (!wq->rq.rqt_hwaddr) {
 251                         ret = -ENOMEM;
 252                         goto free_sw_rq;
 253                 }
 254         }
 255
 256         ret = alloc_sq(rdev, &wq->sq, user);
 257         if (ret)
 258                 goto free_hwaddr;
 259         memset(wq->sq.queue, 0, wq->sq.memsize);
 260         dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
 261
 262         if (need_rq) {
 263                 wq->rq.queue = dma_alloc_coherent(&rdev->lldi.pdev->dev,
 264                                                   wq->rq.memsize,
 265                                                   &wq->rq.dma_addr,
 266                                                   GFP_KERNEL);
 267                 if (!wq->rq.queue) {
 268                         ret = -ENOMEM;
 269                         goto free_sq;
 270                 }
 271                 pr_debug("sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
 272                          wq->sq.queue,
 273                          (unsigned long long)virt_to_phys(wq->sq.queue),
 274                          wq->rq.queue,
 275                          (unsigned long long)virt_to_phys(wq->rq.queue));
 276                 memset(wq->rq.queue, 0, wq->rq.memsize);
 277                 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
 278         }
 279
 280         wq->db = rdev->lldi.db_reg;
 281
 282         wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS,
 283                                          &wq->sq.bar2_qid,
 284                                          user ? &wq->sq.bar2_pa : NULL);
 285         if (need_rq)
 286                 wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid,
 287                                                  T4_BAR2_QTYPE_EGRESS,
 288                                                  &wq->rq.bar2_qid,
 289                                                  user ? &wq->rq.bar2_pa : NULL);
 290
 291         /*
 292          * User mode must have bar2 access.
 293          */
 294         if (user && (!wq->sq.bar2_pa || (need_rq && !wq->rq.bar2_pa))) {
 295                 pr_warn("%s: sqid %u or rqid %u not in BAR2 range\n",
 296                         pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid);
 297                 goto free_dma;
 298         }
 299
 300         wq->rdev = rdev;
 301         wq->rq.msn = 1;
 302
 303         /* build fw_ri_res_wr */
 304         wr_len = sizeof *res_wr + 2 * sizeof *res;
 305         if (need_rq)
 306                 wr_len += sizeof(*res);
 307         skb = alloc_skb(wr_len, GFP_KERNEL);
 308         if (!skb) {
 309                 ret = -ENOMEM;
 310                 goto free_dma;
 311         }
 312         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
 313
 314         res_wr = __skb_put_zero(skb, wr_len);
 315         res_wr->op_nres = cpu_to_be32(
 316                         FW_WR_OP_V(FW_RI_RES_WR) |
 317                         FW_RI_RES_WR_NRES_V(need_rq ? 2 : 1) |
 318                         FW_WR_COMPL_F);
 319         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
 320         res_wr->cookie = (uintptr_t)wr_waitp;
 321         res = res_wr->res;
 322         res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
 323         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 324
 325         /*
 326          * eqsize is the number of 64B entries plus the status page size.
 327          */
 328         eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
 329                 rdev->hw_queue.t4_eq_status_entries;
 330
 331         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 332                 FW_RI_RES_WR_HOSTFCMODE_V(0) |  /* no host cidx updates */
 333                 FW_RI_RES_WR_CPRIO_V(0) |       /* don't keep in chip cache */
 334                 FW_RI_RES_WR_PCIECHN_V(0) |     /* set by uP at ri_init time */
 335                 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) |
 336                 FW_RI_RES_WR_IQID_V(scq->cqid));
 337         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 338                 FW_RI_RES_WR_DCAEN_V(0) |
 339                 FW_RI_RES_WR_DCACPU_V(0) |
 340                 FW_RI_RES_WR_FBMIN_V(2) |
 341                 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_FBMAX_V(2) :
 342                                          FW_RI_RES_WR_FBMAX_V(3)) |
 343                 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
 344                 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
 345                 FW_RI_RES_WR_EQSIZE_V(eqsize));
 346         res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
 347         res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
 348
 349         if (need_rq) {
 350                 res++;
 351                 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
 352                 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 353
 354                 /*
 355                  * eqsize is the number of 64B entries plus the status page size
 356                  */
 357                 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
 358                         rdev->hw_queue.t4_eq_status_entries;
 359                 res->u.sqrq.fetchszm_to_iqid =
 360                         /* no host cidx updates */
 361                         cpu_to_be32(FW_RI_RES_WR_HOSTFCMODE_V(0) |
 362                         /* don't keep in chip cache */
 363                         FW_RI_RES_WR_CPRIO_V(0) |
 364                         /* set by uP at ri_init time */
 365                         FW_RI_RES_WR_PCIECHN_V(0) |
 366                         FW_RI_RES_WR_IQID_V(rcq->cqid));
 367                 res->u.sqrq.dcaen_to_eqsize =
 368                         cpu_to_be32(FW_RI_RES_WR_DCAEN_V(0) |
 369                         FW_RI_RES_WR_DCACPU_V(0) |
 370                         FW_RI_RES_WR_FBMIN_V(2) |
 371                         FW_RI_RES_WR_FBMAX_V(3) |
 372                         FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
 373                         FW_RI_RES_WR_CIDXFTHRESH_V(0) |
 374                         FW_RI_RES_WR_EQSIZE_V(eqsize));
 375                 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
 376                 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
 377         }
 378
 379         c4iw_init_wr_wait(wr_waitp);
 380         ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, wq->sq.qid, __func__);
 381         if (ret)
 382                 goto free_dma;
 383
 384         pr_debug("sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
 385                  wq->sq.qid, wq->rq.qid, wq->db,
 386                  wq->sq.bar2_va, wq->rq.bar2_va);
 387
 388         return 0;
 389 free_dma:
 390         if (need_rq)
 391                 dma_free_coherent(&rdev->lldi.pdev->dev,
 392                                   wq->rq.memsize, wq->rq.queue,
 393                                   dma_unmap_addr(&wq->rq, mapping));
 394 free_sq:
 395         dealloc_sq(rdev, &wq->sq);
 396 free_hwaddr:
 397         if (need_rq)
 398                 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 399 free_sw_rq:
 400         if (need_rq)
 401                 kfree(wq->rq.sw_rq);
 402 free_sw_sq:
 403         kfree(wq->sq.sw_sq);
 404 free_rq_qid:
 405         if (need_rq)
 406                 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 407 free_sq_qid:
 408         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 409         return ret;
 410 }
 411
 412 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
 413                       const struct ib_send_wr *wr, int max, u32 *plenp)
 414 {
 415         u8 *dstp, *srcp;
 416         u32 plen = 0;
 417         int i;
 418         int rem, len;
 419
 420         dstp = (u8 *)immdp->data;
 421         for (i = 0; i < wr->num_sge; i++) {
 422                 if ((plen + wr->sg_list[i].length) > max)
 423                         return -EMSGSIZE;
 424                 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
 425                 plen += wr->sg_list[i].length;
 426                 rem = wr->sg_list[i].length;
 427                 while (rem) {
 428                         if (dstp == (u8 *)&sq->queue[sq->size])
 429                                 dstp = (u8 *)sq->queue;
 430                         if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
 431                                 len = rem;
 432                         else
 433                                 len = (u8 *)&sq->queue[sq->size] - dstp;
 434                         memcpy(dstp, srcp, len);
 435                         dstp += len;
 436                         srcp += len;
 437                         rem -= len;
 438                 }
 439         }
 440         len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
 441         if (len)
 442                 memset(dstp, 0, len);
 443         immdp->op = FW_RI_DATA_IMMD;
 444         immdp->r1 = 0;
 445         immdp->r2 = 0;
 446         immdp->immdlen = cpu_to_be32(plen);
 447         *plenp = plen;
 448         return 0;
 449 }
 450
 451 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
 452                       struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
 453                       int num_sge, u32 *plenp)
 454
 455 {
 456         int i;
 457         u32 plen = 0;
 458         __be64 *flitp = (__be64 *)isglp->sge;
 459
 460         for (i = 0; i < num_sge; i++) {
 461                 if ((plen + sg_list[i].length) < plen)
 462                         return -EMSGSIZE;
 463                 plen += sg_list[i].length;
 464                 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
 465                                      sg_list[i].length);
 466                 if (++flitp == queue_end)
 467                         flitp = queue_start;
 468                 *flitp = cpu_to_be64(sg_list[i].addr);
 469                 if (++flitp == queue_end)
 470                         flitp = queue_start;
 471         }
 472         *flitp = (__force __be64)0;
 473         isglp->op = FW_RI_DATA_ISGL;
 474         isglp->r1 = 0;
 475         isglp->nsge = cpu_to_be16(num_sge);
 476         isglp->r2 = 0;
 477         if (plenp)
 478                 *plenp = plen;
 479         return 0;
 480 }
 481
 482 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
 483                            const struct ib_send_wr *wr, u8 *len16)
 484 {
 485         u32 plen;
 486         int size;
 487         int ret;
 488
 489         if (wr->num_sge > T4_MAX_SEND_SGE)
 490                 return -EINVAL;
 491         switch (wr->opcode) {
 492         case IB_WR_SEND:
 493                 if (wr->send_flags & IB_SEND_SOLICITED)
 494                         wqe->send.sendop_pkd = cpu_to_be32(
 495                                 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE));
 496                 else
 497                         wqe->send.sendop_pkd = cpu_to_be32(
 498                                 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND));
 499                 wqe->send.stag_inv = 0;
 500                 break;
 501         case IB_WR_SEND_WITH_INV:
 502                 if (wr->send_flags & IB_SEND_SOLICITED)
 503                         wqe->send.sendop_pkd = cpu_to_be32(
 504                                 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV));
 505                 else
 506                         wqe->send.sendop_pkd = cpu_to_be32(
 507                                 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV));
 508                 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 509                 break;
 510
 511         default:
 512                 return -EINVAL;
 513         }
 514         wqe->send.r3 = 0;
 515         wqe->send.r4 = 0;
 516
 517         plen = 0;
 518         if (wr->num_sge) {
 519                 if (wr->send_flags & IB_SEND_INLINE) {
 520                         ret = build_immd(sq, wqe->send.u.immd_src, wr,
 521                                          T4_MAX_SEND_INLINE, &plen);
 522                         if (ret)
 523                                 return ret;
 524                         size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
 525                                plen;
 526                 } else {
 527                         ret = build_isgl((__be64 *)sq->queue,
 528                                          (__be64 *)&sq->queue[sq->size],
 529                                          wqe->send.u.isgl_src,
 530                                          wr->sg_list, wr->num_sge, &plen);
 531                         if (ret)
 532                                 return ret;
 533                         size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
 534                                wr->num_sge * sizeof(struct fw_ri_sge);
 535                 }
 536         } else {
 537                 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
 538                 wqe->send.u.immd_src[0].r1 = 0;
 539                 wqe->send.u.immd_src[0].r2 = 0;
 540                 wqe->send.u.immd_src[0].immdlen = 0;
 541                 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
 542                 plen = 0;
 543         }
 544         *len16 = DIV_ROUND_UP(size, 16);
 545         wqe->send.plen = cpu_to_be32(plen);
 546         return 0;
 547 }
 548
 549 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
 550                             const struct ib_send_wr *wr, u8 *len16)
 551 {
 552         u32 plen;
 553         int size;
 554         int ret;
 555
 556         if (wr->num_sge > T4_MAX_SEND_SGE)
 557                 return -EINVAL;
 558         wqe->write.r2 = 0;
 559         wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
 560         wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
 561         if (wr->num_sge) {
 562                 if (wr->send_flags & IB_SEND_INLINE) {
 563                         ret = build_immd(sq, wqe->write.u.immd_src, wr,
 564                                          T4_MAX_WRITE_INLINE, &plen);
 565                         if (ret)
 566                                 return ret;
 567                         size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
 568                                plen;
 569                 } else {
 570                         ret = build_isgl((__be64 *)sq->queue,
 571                                          (__be64 *)&sq->queue[sq->size],
 572                                          wqe->write.u.isgl_src,
 573                                          wr->sg_list, wr->num_sge, &plen);
 574                         if (ret)
 575                                 return ret;
 576                         size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
 577                                wr->num_sge * sizeof(struct fw_ri_sge);
 578                 }
 579         } else {
 580                 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
 581                 wqe->write.u.immd_src[0].r1 = 0;
 582                 wqe->write.u.immd_src[0].r2 = 0;
 583                 wqe->write.u.immd_src[0].immdlen = 0;
 584                 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
 585                 plen = 0;
 586         }
 587         *len16 = DIV_ROUND_UP(size, 16);
 588         wqe->write.plen = cpu_to_be32(plen);
 589         return 0;
 590 }
 591
 592 static int build_rdma_read(union t4_wr *wqe, const struct ib_send_wr *wr,
 593                            u8 *len16)
 594 {
 595         if (wr->num_sge > 1)
 596                 return -EINVAL;
 597         if (wr->num_sge && wr->sg_list[0].length) {
 598                 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey);
 599                 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr
 600                                                         >> 32));
 601                 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr);
 602                 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
 603                 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
 604                 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
 605                                                          >> 32));
 606                 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
 607         } else {
 608                 wqe->read.stag_src = cpu_to_be32(2);
 609                 wqe->read.to_src_hi = 0;
 610                 wqe->read.to_src_lo = 0;
 611                 wqe->read.stag_sink = cpu_to_be32(2);
 612                 wqe->read.plen = 0;
 613                 wqe->read.to_sink_hi = 0;
 614                 wqe->read.to_sink_lo = 0;
 615         }
 616         wqe->read.r2 = 0;
 617         wqe->read.r5 = 0;
 618         *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
 619         return 0;
 620 }
 621
 622 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
 623                            const struct ib_recv_wr *wr, u8 *len16)
 624 {
 625         int ret;
 626
 627         ret = build_isgl((__be64 *)qhp->wq.rq.queue,
 628                          (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
 629                          &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
 630         if (ret)
 631                 return ret;
 632         *len16 = DIV_ROUND_UP(sizeof wqe->recv +
 633                               wr->num_sge * sizeof(struct fw_ri_sge), 16);
 634         return 0;
 635 }
 636
 637 static int build_srq_recv(union t4_recv_wr *wqe, const struct ib_recv_wr *wr,
 638                           u8 *len16)
 639 {
 640         int ret;
 641
 642         ret = build_isgl((__be64 *)wqe, (__be64 *)(wqe + 1),
 643                          &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
 644         if (ret)
 645                 return ret;
 646         *len16 = DIV_ROUND_UP(sizeof(wqe->recv) +
 647                               wr->num_sge * sizeof(struct fw_ri_sge), 16);
 648         return 0;
 649 }
 650
 651 static void build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr,
 652                               const struct ib_reg_wr *wr, struct c4iw_mr *mhp,
 653                               u8 *len16)
 654 {
 655         __be64 *p = (__be64 *)fr->pbl;
 656
 657         fr->r2 = cpu_to_be32(0);
 658         fr->stag = cpu_to_be32(mhp->ibmr.rkey);
 659
 660         fr->tpte.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
 661                 FW_RI_TPTE_STAGKEY_V((mhp->ibmr.rkey & FW_RI_TPTE_STAGKEY_M)) |
 662                 FW_RI_TPTE_STAGSTATE_V(1) |
 663                 FW_RI_TPTE_STAGTYPE_V(FW_RI_STAG_NSMR) |
 664                 FW_RI_TPTE_PDID_V(mhp->attr.pdid));
 665         fr->tpte.locread_to_qpid = cpu_to_be32(
 666                 FW_RI_TPTE_PERM_V(c4iw_ib_to_tpt_access(wr->access)) |
 667                 FW_RI_TPTE_ADDRTYPE_V(FW_RI_VA_BASED_TO) |
 668                 FW_RI_TPTE_PS_V(ilog2(wr->mr->page_size) - 12));
 669         fr->tpte.nosnoop_pbladdr = cpu_to_be32(FW_RI_TPTE_PBLADDR_V(
 670                 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3));
 671         fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0);
 672         fr->tpte.len_hi = cpu_to_be32(0);
 673         fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length);
 674         fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
 675         fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff);
 676
 677         p[0] = cpu_to_be64((u64)mhp->mpl[0]);
 678         p[1] = cpu_to_be64((u64)mhp->mpl[1]);
 679
 680         *len16 = DIV_ROUND_UP(sizeof(*fr), 16);
 681 }
 682
 683 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
 684                         const struct ib_reg_wr *wr, struct c4iw_mr *mhp,
 685                         u8 *len16, bool dsgl_supported)
 686 {
 687         struct fw_ri_immd *imdp;
 688         __be64 *p;
 689         int i;
 690         int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
 691         int rem;
 692
 693         if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl))
 694                 return -EINVAL;
 695
 696         wqe->fr.qpbinde_to_dcacpu = 0;
 697         wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12;
 698         wqe->fr.addr_type = FW_RI_VA_BASED_TO;
 699         wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access);
 700         wqe->fr.len_hi = 0;
 701         wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length);
 702         wqe->fr.stag = cpu_to_be32(wr->key);
 703         wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
 704         wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
 705                                         0xffffffff);
 706
 707         if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) {
 708                 struct fw_ri_dsgl *sglp;
 709
 710                 for (i = 0; i < mhp->mpl_len; i++)
 711                         mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]);
 712
 713                 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
 714                 sglp->op = FW_RI_DATA_DSGL;
 715                 sglp->r1 = 0;
 716                 sglp->nsge = cpu_to_be16(1);
 717                 sglp->addr0 = cpu_to_be64(mhp->mpl_addr);
 718                 sglp->len0 = cpu_to_be32(pbllen);
 719
 720                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
 721         } else {
 722                 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
 723                 imdp->op = FW_RI_DATA_IMMD;
 724                 imdp->r1 = 0;
 725                 imdp->r2 = 0;
 726                 imdp->immdlen = cpu_to_be32(pbllen);
 727                 p = (__be64 *)(imdp + 1);
 728                 rem = pbllen;
 729                 for (i = 0; i < mhp->mpl_len; i++) {
 730                         *p = cpu_to_be64((u64)mhp->mpl[i]);
 731                         rem -= sizeof(*p);
 732                         if (++p == (__be64 *)&sq->queue[sq->size])
 733                                 p = (__be64 *)sq->queue;
 734                 }
 735                 while (rem) {
 736                         *p = 0;
 737                         rem -= sizeof(*p);
 738                         if (++p == (__be64 *)&sq->queue[sq->size])
 739                                 p = (__be64 *)sq->queue;
 740                 }
 741                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
 742                                       + pbllen, 16);
 743         }
 744         return 0;
 745 }
 746
 747 static int build_inv_stag(union t4_wr *wqe, const struct ib_send_wr *wr,
 748                           u8 *len16)
 749 {
 750         wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 751         wqe->inv.r2 = 0;
 752         *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
 753         return 0;
 754 }
 755
 756 static void free_qp_work(struct work_struct *work)
 757 {
 758         struct c4iw_ucontext *ucontext;
 759         struct c4iw_qp *qhp;
 760         struct c4iw_dev *rhp;
 761
 762         qhp = container_of(work, struct c4iw_qp, free_work);
 763         ucontext = qhp->ucontext;
 764         rhp = qhp->rhp;
 765
 766         pr_debug("qhp %p ucontext %p\n", qhp, ucontext);
 767         destroy_qp(&rhp->rdev, &qhp->wq,
 768                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx, !qhp->srq);
 769
 770         if (ucontext)
 771                 c4iw_put_ucontext(ucontext);
 772         c4iw_put_wr_wait(qhp->wr_waitp);
 773         kfree(qhp);
 774 }
 775
 776 static void queue_qp_free(struct kref *kref)
 777 {
 778         struct c4iw_qp *qhp;
 779
 780         qhp = container_of(kref, struct c4iw_qp, kref);
 781         pr_debug("qhp %p\n", qhp);
 782         queue_work(qhp->rhp->rdev.free_workq, &qhp->free_work);
 783 }
 784
 785 void c4iw_qp_add_ref(struct ib_qp *qp)
 786 {
 787         pr_debug("ib_qp %p\n", qp);
 788         kref_get(&to_c4iw_qp(qp)->kref);
 789 }
 790
 791 void c4iw_qp_rem_ref(struct ib_qp *qp)
 792 {
 793         pr_debug("ib_qp %p\n", qp);
 794         kref_put(&to_c4iw_qp(qp)->kref, queue_qp_free);
 795 }
 796
 797 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
 798 {
 799         if (list_empty(entry))
 800                 list_add_tail(entry, head);
 801 }
 802
 803 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
 804 {
 805         unsigned long flags;
 806
 807         spin_lock_irqsave(&qhp->rhp->lock, flags);
 808         spin_lock(&qhp->lock);
 809         if (qhp->rhp->db_state == NORMAL)
 810                 t4_ring_sq_db(&qhp->wq, inc, NULL);
 811         else {
 812                 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
 813                 qhp->wq.sq.wq_pidx_inc += inc;
 814         }
 815         spin_unlock(&qhp->lock);
 816         spin_unlock_irqrestore(&qhp->rhp->lock, flags);
 817         return 0;
 818 }
 819
 820 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
 821 {
 822         unsigned long flags;
 823
 824         spin_lock_irqsave(&qhp->rhp->lock, flags);
 825         spin_lock(&qhp->lock);
 826         if (qhp->rhp->db_state == NORMAL)
 827                 t4_ring_rq_db(&qhp->wq, inc, NULL);
 828         else {
 829                 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
 830                 qhp->wq.rq.wq_pidx_inc += inc;
 831         }
 832         spin_unlock(&qhp->lock);
 833         spin_unlock_irqrestore(&qhp->rhp->lock, flags);
 834         return 0;
 835 }
 836
 837 static int ib_to_fw_opcode(int ib_opcode)
 838 {
 839         int opcode;
 840
 841         switch (ib_opcode) {
 842         case IB_WR_SEND_WITH_INV:
 843                 opcode = FW_RI_SEND_WITH_INV;
 844                 break;
 845         case IB_WR_SEND:
 846                 opcode = FW_RI_SEND;
 847                 break;
 848         case IB_WR_RDMA_WRITE:
 849                 opcode = FW_RI_RDMA_WRITE;
 850                 break;
 851         case IB_WR_RDMA_READ:
 852         case IB_WR_RDMA_READ_WITH_INV:
 853                 opcode = FW_RI_READ_REQ;
 854                 break;
 855         case IB_WR_REG_MR:
 856                 opcode = FW_RI_FAST_REGISTER;
 857                 break;
 858         case IB_WR_LOCAL_INV:
 859                 opcode = FW_RI_LOCAL_INV;
 860                 break;
 861         default:
 862                 opcode = -EINVAL;
 863         }
 864         return opcode;
 865 }
 866
 867 static int complete_sq_drain_wr(struct c4iw_qp *qhp,
 868                                 const struct ib_send_wr *wr)
 869 {
 870         struct t4_cqe cqe = {};
 871         struct c4iw_cq *schp;
 872         unsigned long flag;
 873         struct t4_cq *cq;
 874         int opcode;
 875
 876         schp = to_c4iw_cq(qhp->ibqp.send_cq);
 877         cq = &schp->cq;
 878
 879         opcode = ib_to_fw_opcode(wr->opcode);
 880         if (opcode < 0)
 881                 return opcode;
 882
 883         cqe.u.drain_cookie = wr->wr_id;
 884         cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
 885                                  CQE_OPCODE_V(opcode) |
 886                                  CQE_TYPE_V(1) |
 887                                  CQE_SWCQE_V(1) |
 888                                  CQE_DRAIN_V(1) |
 889                                  CQE_QPID_V(qhp->wq.sq.qid));
 890
 891         spin_lock_irqsave(&schp->lock, flag);
 892         cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
 893         cq->sw_queue[cq->sw_pidx] = cqe;
 894         t4_swcq_produce(cq);
 895         spin_unlock_irqrestore(&schp->lock, flag);
 896
 897         if (t4_clear_cq_armed(&schp->cq)) {
 898                 spin_lock_irqsave(&schp->comp_handler_lock, flag);
 899                 (*schp->ibcq.comp_handler)(&schp->ibcq,
 900                                            schp->ibcq.cq_context);
 901                 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
 902         }
 903         return 0;
 904 }
 905
 906 static int complete_sq_drain_wrs(struct c4iw_qp *qhp,
 907                                  const struct ib_send_wr *wr,
 908                                  const struct ib_send_wr **bad_wr)
 909 {
 910         int ret = 0;
 911
 912         while (wr) {
 913                 ret = complete_sq_drain_wr(qhp, wr);
 914                 if (ret) {
 915                         *bad_wr = wr;
 916                         break;
 917                 }
 918                 wr = wr->next;
 919         }
 920         return ret;
 921 }
 922
 923 static void complete_rq_drain_wr(struct c4iw_qp *qhp,
 924                                  const struct ib_recv_wr *wr)
 925 {
 926         struct t4_cqe cqe = {};
 927         struct c4iw_cq *rchp;
 928         unsigned long flag;
 929         struct t4_cq *cq;
 930
 931         rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
 932         cq = &rchp->cq;
 933
 934         cqe.u.drain_cookie = wr->wr_id;
 935         cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
 936                                  CQE_OPCODE_V(FW_RI_SEND) |
 937                                  CQE_TYPE_V(0) |
 938                                  CQE_SWCQE_V(1) |
 939                                  CQE_DRAIN_V(1) |
 940                                  CQE_QPID_V(qhp->wq.sq.qid));
 941
 942         spin_lock_irqsave(&rchp->lock, flag);
 943         cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
 944         cq->sw_queue[cq->sw_pidx] = cqe;
 945         t4_swcq_produce(cq);
 946         spin_unlock_irqrestore(&rchp->lock, flag);
 947
 948         if (t4_clear_cq_armed(&rchp->cq)) {
 949                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
 950                 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
 951                                            rchp->ibcq.cq_context);
 952                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
 953         }
 954 }
 955
 956 static void complete_rq_drain_wrs(struct c4iw_qp *qhp,
 957                                   const struct ib_recv_wr *wr)
 958 {
 959         while (wr) {
 960                 complete_rq_drain_wr(qhp, wr);
 961                 wr = wr->next;
 962         }
 963 }
 964
 965 int c4iw_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 966                    const struct ib_send_wr **bad_wr)
 967 {
 968         int err = 0;
 969         u8 len16 = 0;
 970         enum fw_wr_opcodes fw_opcode = 0;
 971         enum fw_ri_wr_flags fw_flags;
 972         struct c4iw_qp *qhp;
 973         union t4_wr *wqe = NULL;
 974         u32 num_wrs;
 975         struct t4_swsqe *swsqe;
 976         unsigned long flag;
 977         u16 idx = 0;
 978
 979         qhp = to_c4iw_qp(ibqp);
 980         spin_lock_irqsave(&qhp->lock, flag);
 981
 982         /*
 983          * If the qp has been flushed, then just insert a special
 984          * drain cqe.
 985          */
 986         if (qhp->wq.flushed) {
 987                 spin_unlock_irqrestore(&qhp->lock, flag);
 988                 err = complete_sq_drain_wrs(qhp, wr, bad_wr);
 989                 return err;
 990         }
 991         num_wrs = t4_sq_avail(&qhp->wq);
 992         if (num_wrs == 0) {
 993                 spin_unlock_irqrestore(&qhp->lock, flag);
 994                 *bad_wr = wr;
 995                 return -ENOMEM;
 996         }
 997         while (wr) {
 998                 if (num_wrs == 0) {
 999                         err = -ENOMEM;
1000                         *bad_wr = wr;
1001                         break;
1002                 }
1003                 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
1004                       qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
1005
1006                 fw_flags = 0;
1007                 if (wr->send_flags & IB_SEND_SOLICITED)
1008                         fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
1009                 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
1010                         fw_flags |= FW_RI_COMPLETION_FLAG;
1011                 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
1012                 switch (wr->opcode) {
1013                 case IB_WR_SEND_WITH_INV:
1014                 case IB_WR_SEND:
1015                         if (wr->send_flags & IB_SEND_FENCE)
1016                                 fw_flags |= FW_RI_READ_FENCE_FLAG;
1017                         fw_opcode = FW_RI_SEND_WR;
1018                         if (wr->opcode == IB_WR_SEND)
1019                                 swsqe->opcode = FW_RI_SEND;
1020                         else
1021                                 swsqe->opcode = FW_RI_SEND_WITH_INV;
1022                         err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
1023                         break;
1024                 case IB_WR_RDMA_WRITE:
1025                         fw_opcode = FW_RI_RDMA_WRITE_WR;
1026                         swsqe->opcode = FW_RI_RDMA_WRITE;
1027                         err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
1028                         break;
1029                 case IB_WR_RDMA_READ:
1030                 case IB_WR_RDMA_READ_WITH_INV:
1031                         fw_opcode = FW_RI_RDMA_READ_WR;
1032                         swsqe->opcode = FW_RI_READ_REQ;
1033                         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) {
1034                                 c4iw_invalidate_mr(qhp->rhp,
1035                                                    wr->sg_list[0].lkey);
1036                                 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
1037                         } else {
1038                                 fw_flags = 0;
1039                         }
1040                         err = build_rdma_read(wqe, wr, &len16);
1041                         if (err)
1042                                 break;
1043                         swsqe->read_len = wr->sg_list[0].length;
1044                         if (!qhp->wq.sq.oldest_read)
1045                                 qhp->wq.sq.oldest_read = swsqe;
1046                         break;
1047                 case IB_WR_REG_MR: {
1048                         struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr);
1049
1050                         swsqe->opcode = FW_RI_FAST_REGISTER;
1051                         if (qhp->rhp->rdev.lldi.fr_nsmr_tpte_wr_support &&
1052                             !mhp->attr.state && mhp->mpl_len <= 2) {
1053                                 fw_opcode = FW_RI_FR_NSMR_TPTE_WR;
1054                                 build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr),
1055                                                   mhp, &len16);
1056                         } else {
1057                                 fw_opcode = FW_RI_FR_NSMR_WR;
1058                                 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr),
1059                                        mhp, &len16,
1060                                        qhp->rhp->rdev.lldi.ulptx_memwrite_dsgl);
1061                                 if (err)
1062                                         break;
1063                         }
1064                         mhp->attr.state = 1;
1065                         break;
1066                 }
1067                 case IB_WR_LOCAL_INV:
1068                         if (wr->send_flags & IB_SEND_FENCE)
1069                                 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
1070                         fw_opcode = FW_RI_INV_LSTAG_WR;
1071                         swsqe->opcode = FW_RI_LOCAL_INV;
1072                         err = build_inv_stag(wqe, wr, &len16);
1073                         c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey);
1074                         break;
1075                 default:
1076                         pr_warn("%s post of type=%d TBD!\n", __func__,
1077                                 wr->opcode);
1078                         err = -EINVAL;
1079                 }
1080                 if (err) {
1081                         *bad_wr = wr;
1082                         break;
1083                 }
1084                 swsqe->idx = qhp->wq.sq.pidx;
1085                 swsqe->complete = 0;
1086                 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
1087                                   qhp->sq_sig_all;
1088                 swsqe->flushed = 0;
1089                 swsqe->wr_id = wr->wr_id;
1090                 if (c4iw_wr_log) {
1091                         swsqe->sge_ts = cxgb4_read_sge_timestamp(
1092                                         qhp->rhp->rdev.lldi.ports[0]);
1093                         swsqe->host_time = ktime_get();
1094                 }
1095
1096                 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
1097
1098                 pr_debug("cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
1099                          (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
1100                          swsqe->opcode, swsqe->read_len);
1101                 wr = wr->next;
1102                 num_wrs--;
1103                 t4_sq_produce(&qhp->wq, len16);
1104                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
1105         }
1106         if (!qhp->rhp->rdev.status_page->db_off) {
1107                 t4_ring_sq_db(&qhp->wq, idx, wqe);
1108                 spin_unlock_irqrestore(&qhp->lock, flag);
1109         } else {
1110                 spin_unlock_irqrestore(&qhp->lock, flag);
1111                 ring_kernel_sq_db(qhp, idx);
1112         }
1113         return err;
1114 }
1115
1116 int c4iw_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
1117                       const struct ib_recv_wr **bad_wr)
1118 {
1119         int err = 0;
1120         struct c4iw_qp *qhp;
1121         union t4_recv_wr *wqe = NULL;
1122         u32 num_wrs;
1123         u8 len16 = 0;
1124         unsigned long flag;
1125         u16 idx = 0;
1126
1127         qhp = to_c4iw_qp(ibqp);
1128         spin_lock_irqsave(&qhp->lock, flag);
1129
1130         /*
1131          * If the qp has been flushed, then just insert a special
1132          * drain cqe.
1133          */
1134         if (qhp->wq.flushed) {
1135                 spin_unlock_irqrestore(&qhp->lock, flag);
1136                 complete_rq_drain_wrs(qhp, wr);
1137                 return err;
1138         }
1139         num_wrs = t4_rq_avail(&qhp->wq);
1140         if (num_wrs == 0) {
1141                 spin_unlock_irqrestore(&qhp->lock, flag);
1142                 *bad_wr = wr;
1143                 return -ENOMEM;
1144         }
1145         while (wr) {
1146                 if (wr->num_sge > T4_MAX_RECV_SGE) {
1147                         err = -EINVAL;
1148                         *bad_wr = wr;
1149                         break;
1150                 }
1151                 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
1152                                            qhp->wq.rq.wq_pidx *
1153                                            T4_EQ_ENTRY_SIZE);
1154                 if (num_wrs)
1155                         err = build_rdma_recv(qhp, wqe, wr, &len16);
1156                 else
1157                         err = -ENOMEM;
1158                 if (err) {
1159                         *bad_wr = wr;
1160                         break;
1161                 }
1162
1163                 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
1164                 if (c4iw_wr_log) {
1165                         qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts =
1166                                 cxgb4_read_sge_timestamp(
1167                                                 qhp->rhp->rdev.lldi.ports[0]);
1168                         qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_time =
1169                                 ktime_get();
1170                 }
1171
1172                 wqe->recv.opcode = FW_RI_RECV_WR;
1173                 wqe->recv.r1 = 0;
1174                 wqe->recv.wrid = qhp->wq.rq.pidx;
1175                 wqe->recv.r2[0] = 0;
1176                 wqe->recv.r2[1] = 0;
1177                 wqe->recv.r2[2] = 0;
1178                 wqe->recv.len16 = len16;
1179                 pr_debug("cookie 0x%llx pidx %u\n",
1180                          (unsigned long long)wr->wr_id, qhp->wq.rq.pidx);
1181                 t4_rq_produce(&qhp->wq, len16);
1182                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
1183                 wr = wr->next;
1184                 num_wrs--;
1185         }
1186         if (!qhp->rhp->rdev.status_page->db_off) {
1187                 t4_ring_rq_db(&qhp->wq, idx, wqe);
1188                 spin_unlock_irqrestore(&qhp->lock, flag);
1189         } else {
1190                 spin_unlock_irqrestore(&qhp->lock, flag);
1191                 ring_kernel_rq_db(qhp, idx);
1192         }
1193         return err;
1194 }
1195
1196 static void defer_srq_wr(struct t4_srq *srq, union t4_recv_wr *wqe,
1197                          u64 wr_id, u8 len16)
1198 {
1199         struct t4_srq_pending_wr *pwr = &srq->pending_wrs[srq->pending_pidx];
1200
1201         pr_debug("%s cidx %u pidx %u wq_pidx %u in_use %u ooo_count %u wr_id 0x%llx pending_cidx %u pending_pidx %u pending_in_use %u\n",
1202                  __func__, srq->cidx, srq->pidx, srq->wq_pidx,
1203                  srq->in_use, srq->ooo_count,
1204                  (unsigned long long)wr_id, srq->pending_cidx,
1205                  srq->pending_pidx, srq->pending_in_use);
1206         pwr->wr_id = wr_id;
1207         pwr->len16 = len16;
1208         memcpy(&pwr->wqe, wqe, len16 * 16);
1209         t4_srq_produce_pending_wr(srq);
1210 }
1211
1212 int c4iw_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1213                        const struct ib_recv_wr **bad_wr)
1214 {
1215         union t4_recv_wr *wqe, lwqe;
1216         struct c4iw_srq *srq;
1217         unsigned long flag;
1218         u8 len16 = 0;
1219         u16 idx = 0;
1220         int err = 0;
1221         u32 num_wrs;
1222
1223         srq = to_c4iw_srq(ibsrq);
1224         spin_lock_irqsave(&srq->lock, flag);
1225         num_wrs = t4_srq_avail(&srq->wq);
1226         if (num_wrs == 0) {
1227                 spin_unlock_irqrestore(&srq->lock, flag);
1228                 return -ENOMEM;
1229         }
1230         while (wr) {
1231                 if (wr->num_sge > T4_MAX_RECV_SGE) {
1232                         err = -EINVAL;
1233                         *bad_wr = wr;
1234                         break;
1235                 }
1236                 wqe = &lwqe;
1237                 if (num_wrs)
1238                         err = build_srq_recv(wqe, wr, &len16);
1239                 else
1240                         err = -ENOMEM;
1241                 if (err) {
1242                         *bad_wr = wr;
1243                         break;
1244                 }
1245
1246                 wqe->recv.opcode = FW_RI_RECV_WR;
1247                 wqe->recv.r1 = 0;
1248                 wqe->recv.wrid = srq->wq.pidx;
1249                 wqe->recv.r2[0] = 0;
1250                 wqe->recv.r2[1] = 0;
1251                 wqe->recv.r2[2] = 0;
1252                 wqe->recv.len16 = len16;
1253
1254                 if (srq->wq.ooo_count ||
1255                     srq->wq.pending_in_use ||
1256                     srq->wq.sw_rq[srq->wq.pidx].valid) {
1257                         defer_srq_wr(&srq->wq, wqe, wr->wr_id, len16);
1258                 } else {
1259                         srq->wq.sw_rq[srq->wq.pidx].wr_id = wr->wr_id;
1260                         srq->wq.sw_rq[srq->wq.pidx].valid = 1;
1261                         c4iw_copy_wr_to_srq(&srq->wq, wqe, len16);
1262                         pr_debug("%s cidx %u pidx %u wq_pidx %u in_use %u wr_id 0x%llx\n",
1263                                  __func__, srq->wq.cidx,
1264                                  srq->wq.pidx, srq->wq.wq_pidx,
1265                                  srq->wq.in_use,
1266                                  (unsigned long long)wr->wr_id);
1267                         t4_srq_produce(&srq->wq, len16);
1268                         idx += DIV_ROUND_UP(len16 * 16, T4_EQ_ENTRY_SIZE);
1269                 }
1270                 wr = wr->next;
1271                 num_wrs--;
1272         }
1273         if (idx)
1274                 t4_ring_srq_db(&srq->wq, idx, len16, wqe);
1275         spin_unlock_irqrestore(&srq->lock, flag);
1276         return err;
1277 }
1278
1279 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
1280                                     u8 *ecode)
1281 {
1282         int status;
1283         int tagged;
1284         int opcode;
1285         int rqtype;
1286         int send_inv;
1287
1288         if (!err_cqe) {
1289                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1290                 *ecode = 0;
1291                 return;
1292         }
1293
1294         status = CQE_STATUS(err_cqe);
1295         opcode = CQE_OPCODE(err_cqe);
1296         rqtype = RQ_TYPE(err_cqe);
1297         send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
1298                    (opcode == FW_RI_SEND_WITH_SE_INV);
1299         tagged = (opcode == FW_RI_RDMA_WRITE) ||
1300                  (rqtype && (opcode == FW_RI_READ_RESP));
1301
1302         switch (status) {
1303         case T4_ERR_STAG:
1304                 if (send_inv) {
1305                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1306                         *ecode = RDMAP_CANT_INV_STAG;
1307                 } else {
1308                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1309                         *ecode = RDMAP_INV_STAG;
1310                 }
1311                 break;
1312         case T4_ERR_PDID:
1313                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1314                 if ((opcode == FW_RI_SEND_WITH_INV) ||
1315                     (opcode == FW_RI_SEND_WITH_SE_INV))
1316                         *ecode = RDMAP_CANT_INV_STAG;
1317                 else
1318                         *ecode = RDMAP_STAG_NOT_ASSOC;
1319                 break;
1320         case T4_ERR_QPID:
1321                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1322                 *ecode = RDMAP_STAG_NOT_ASSOC;
1323                 break;
1324         case T4_ERR_ACCESS:
1325                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1326                 *ecode = RDMAP_ACC_VIOL;
1327                 break;
1328         case T4_ERR_WRAP:
1329                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1330                 *ecode = RDMAP_TO_WRAP;
1331                 break;
1332         case T4_ERR_BOUND:
1333                 if (tagged) {
1334                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1335                         *ecode = DDPT_BASE_BOUNDS;
1336                 } else {
1337                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1338                         *ecode = RDMAP_BASE_BOUNDS;
1339                 }
1340                 break;
1341         case T4_ERR_INVALIDATE_SHARED_MR:
1342         case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
1343                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1344                 *ecode = RDMAP_CANT_INV_STAG;
1345                 break;
1346         case T4_ERR_ECC:
1347         case T4_ERR_ECC_PSTAG:
1348         case T4_ERR_INTERNAL_ERR:
1349                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1350                 *ecode = 0;
1351                 break;
1352         case T4_ERR_OUT_OF_RQE:
1353                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1354                 *ecode = DDPU_INV_MSN_NOBUF;
1355                 break;
1356         case T4_ERR_PBL_ADDR_BOUND:
1357                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1358                 *ecode = DDPT_BASE_BOUNDS;
1359                 break;
1360         case T4_ERR_CRC:
1361                 *layer_type = LAYER_MPA|DDP_LLP;
1362                 *ecode = MPA_CRC_ERR;
1363                 break;
1364         case T4_ERR_MARKER:
1365                 *layer_type = LAYER_MPA|DDP_LLP;
1366                 *ecode = MPA_MARKER_ERR;
1367                 break;
1368         case T4_ERR_PDU_LEN_ERR:
1369                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1370                 *ecode = DDPU_MSG_TOOBIG;
1371                 break;
1372         case T4_ERR_DDP_VERSION:
1373                 if (tagged) {
1374                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1375                         *ecode = DDPT_INV_VERS;
1376                 } else {
1377                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1378                         *ecode = DDPU_INV_VERS;
1379                 }
1380                 break;
1381         case T4_ERR_RDMA_VERSION:
1382                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1383                 *ecode = RDMAP_INV_VERS;
1384                 break;
1385         case T4_ERR_OPCODE:
1386                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1387                 *ecode = RDMAP_INV_OPCODE;
1388                 break;
1389         case T4_ERR_DDP_QUEUE_NUM:
1390                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1391                 *ecode = DDPU_INV_QN;
1392                 break;
1393         case T4_ERR_MSN:
1394         case T4_ERR_MSN_GAP:
1395         case T4_ERR_MSN_RANGE:
1396         case T4_ERR_IRD_OVERFLOW:
1397                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1398                 *ecode = DDPU_INV_MSN_RANGE;
1399                 break;
1400         case T4_ERR_TBIT:
1401                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1402                 *ecode = 0;
1403                 break;
1404         case T4_ERR_MO:
1405                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1406                 *ecode = DDPU_INV_MO;
1407                 break;
1408         default:
1409                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1410                 *ecode = 0;
1411                 break;
1412         }
1413 }
1414
1415 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1416                            gfp_t gfp)
1417 {
1418         struct fw_ri_wr *wqe;
1419         struct sk_buff *skb;
1420         struct terminate_message *term;
1421
1422         pr_debug("qhp %p qid 0x%x tid %u\n", qhp, qhp->wq.sq.qid,
1423                  qhp->ep->hwtid);
1424
1425         skb = skb_dequeue(&qhp->ep->com.ep_skb_list);
1426         if (WARN_ON(!skb))
1427                 return;
1428
1429         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1430
1431         wqe = __skb_put_zero(skb, sizeof(*wqe));
1432         wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR));
1433         wqe->flowid_len16 = cpu_to_be32(
1434                 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1435                 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1436
1437         wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1438         wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1439         term = (struct terminate_message *)wqe->u.terminate.termmsg;
1440         if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1441                 term->layer_etype = qhp->attr.layer_etype;
1442                 term->ecode = qhp->attr.ecode;
1443         } else
1444                 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1445         c4iw_ofld_send(&qhp->rhp->rdev, skb);
1446 }
1447
1448 /*
1449  * Assumes qhp lock is held.
1450  */
1451 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1452                        struct c4iw_cq *schp)
1453 {
1454         int count;
1455         int rq_flushed = 0, sq_flushed;
1456         unsigned long flag;
1457
1458         pr_debug("qhp %p rchp %p schp %p\n", qhp, rchp, schp);
1459
1460         /* locking hierarchy: cqs lock first, then qp lock. */
1461         spin_lock_irqsave(&rchp->lock, flag);
1462         if (schp != rchp)
1463                 spin_lock(&schp->lock);
1464         spin_lock(&qhp->lock);
1465
1466         if (qhp->wq.flushed) {
1467                 spin_unlock(&qhp->lock);
1468                 if (schp != rchp)
1469                         spin_unlock(&schp->lock);
1470                 spin_unlock_irqrestore(&rchp->lock, flag);
1471                 return;
1472         }
1473         qhp->wq.flushed = 1;
1474         t4_set_wq_in_error(&qhp->wq, 0);
1475
1476         c4iw_flush_hw_cq(rchp, qhp);
1477         if (!qhp->srq) {
1478                 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1479                 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1480         }
1481
1482         if (schp != rchp)
1483                 c4iw_flush_hw_cq(schp, qhp);
1484         sq_flushed = c4iw_flush_sq(qhp);
1485
1486         spin_unlock(&qhp->lock);
1487         if (schp != rchp)
1488                 spin_unlock(&schp->lock);
1489         spin_unlock_irqrestore(&rchp->lock, flag);
1490
1491         if (schp == rchp) {
1492                 if ((rq_flushed || sq_flushed) &&
1493                     t4_clear_cq_armed(&rchp->cq)) {
1494                         spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1495                         (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1496                                                    rchp->ibcq.cq_context);
1497                         spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1498                 }
1499         } else {
1500                 if (rq_flushed && t4_clear_cq_armed(&rchp->cq)) {
1501                         spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1502                         (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1503                                                    rchp->ibcq.cq_context);
1504                         spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1505                 }
1506                 if (sq_flushed && t4_clear_cq_armed(&schp->cq)) {
1507                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
1508                         (*schp->ibcq.comp_handler)(&schp->ibcq,
1509                                                    schp->ibcq.cq_context);
1510                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1511                 }
1512         }
1513 }
1514
1515 static void flush_qp(struct c4iw_qp *qhp)
1516 {
1517         struct c4iw_cq *rchp, *schp;
1518         unsigned long flag;
1519
1520         rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1521         schp = to_c4iw_cq(qhp->ibqp.send_cq);
1522
1523         if (qhp->ibqp.uobject) {
1524                 t4_set_wq_in_error(&qhp->wq, 0);
1525                 t4_set_cq_in_error(&rchp->cq);
1526                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1527                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1528                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1529                 if (schp != rchp) {
1530                         t4_set_cq_in_error(&schp->cq);
1531                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
1532                         (*schp->ibcq.comp_handler)(&schp->ibcq,
1533                                         schp->ibcq.cq_context);
1534                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1535                 }
1536                 return;
1537         }
1538         __flush_qp(qhp, rchp, schp);
1539 }
1540
1541 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1542                      struct c4iw_ep *ep)
1543 {
1544         struct fw_ri_wr *wqe;
1545         int ret;
1546         struct sk_buff *skb;
1547
1548         pr_debug("qhp %p qid 0x%x tid %u\n", qhp, qhp->wq.sq.qid, ep->hwtid);
1549
1550         skb = skb_dequeue(&ep->com.ep_skb_list);
1551         if (WARN_ON(!skb))
1552                 return -ENOMEM;
1553
1554         set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1555
1556         wqe = __skb_put_zero(skb, sizeof(*wqe));
1557         wqe->op_compl = cpu_to_be32(
1558                 FW_WR_OP_V(FW_RI_INIT_WR) |
1559                 FW_WR_COMPL_F);
1560         wqe->flowid_len16 = cpu_to_be32(
1561                 FW_WR_FLOWID_V(ep->hwtid) |
1562                 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1563         wqe->cookie = (uintptr_t)ep->com.wr_waitp;
1564
1565         wqe->u.fini.type = FW_RI_TYPE_FINI;
1566
1567         ret = c4iw_ref_send_wait(&rhp->rdev, skb, ep->com.wr_waitp,
1568                                  qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1569
1570         pr_debug("ret %d\n", ret);
1571         return ret;
1572 }
1573
1574 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1575 {
1576         pr_debug("p2p_type = %d\n", p2p_type);
1577         memset(&init->u, 0, sizeof init->u);
1578         switch (p2p_type) {
1579         case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1580                 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1581                 init->u.write.stag_sink = cpu_to_be32(1);
1582                 init->u.write.to_sink = cpu_to_be64(1);
1583                 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1584                 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1585                                                    sizeof(struct fw_ri_immd),
1586                                                    16);
1587                 break;
1588         case FW_RI_INIT_P2PTYPE_READ_REQ:
1589                 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1590                 init->u.read.stag_src = cpu_to_be32(1);
1591                 init->u.read.to_src_lo = cpu_to_be32(1);
1592                 init->u.read.stag_sink = cpu_to_be32(1);
1593                 init->u.read.to_sink_lo = cpu_to_be32(1);
1594                 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1595                 break;
1596         }
1597 }
1598
1599 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1600 {
1601         struct fw_ri_wr *wqe;
1602         int ret;
1603         struct sk_buff *skb;
1604
1605         pr_debug("qhp %p qid 0x%x tid %u ird %u ord %u\n", qhp,
1606                  qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord);
1607
1608         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1609         if (!skb) {
1610                 ret = -ENOMEM;
1611                 goto out;
1612         }
1613         ret = alloc_ird(rhp, qhp->attr.max_ird);
1614         if (ret) {
1615                 qhp->attr.max_ird = 0;
1616                 kfree_skb(skb);
1617                 goto out;
1618         }
1619         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1620
1621         wqe = __skb_put_zero(skb, sizeof(*wqe));
1622         wqe->op_compl = cpu_to_be32(
1623                 FW_WR_OP_V(FW_RI_INIT_WR) |
1624                 FW_WR_COMPL_F);
1625         wqe->flowid_len16 = cpu_to_be32(
1626                 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1627                 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1628
1629         wqe->cookie = (uintptr_t)qhp->ep->com.wr_waitp;
1630
1631         wqe->u.init.type = FW_RI_TYPE_INIT;
1632         wqe->u.init.mpareqbit_p2ptype =
1633                 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) |
1634                 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type);
1635         wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1636         if (qhp->attr.mpa_attr.recv_marker_enabled)
1637                 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1638         if (qhp->attr.mpa_attr.xmit_marker_enabled)
1639                 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1640         if (qhp->attr.mpa_attr.crc_enabled)
1641                 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1642
1643         wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1644                             FW_RI_QP_RDMA_WRITE_ENABLE |
1645                             FW_RI_QP_BIND_ENABLE;
1646         if (!qhp->ibqp.uobject)
1647                 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1648                                      FW_RI_QP_STAG0_ENABLE;
1649         wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1650         wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1651         wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1652         wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1653         if (qhp->srq) {
1654                 wqe->u.init.rq_eqid = cpu_to_be32(FW_RI_INIT_RQEQID_SRQ |
1655                                                   qhp->srq->idx);
1656         } else {
1657                 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1658                 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1659                 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1660                                                    rhp->rdev.lldi.vr->rq.start);
1661         }
1662         wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1663         wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1664         wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1665         wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1666         wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1667         wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1668         if (qhp->attr.mpa_attr.initiator)
1669                 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1670
1671         ret = c4iw_ref_send_wait(&rhp->rdev, skb, qhp->ep->com.wr_waitp,
1672                                  qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1673         if (!ret)
1674                 goto out;
1675
1676         free_ird(rhp, qhp->attr.max_ird);
1677 out:
1678         pr_debug("ret %d\n", ret);
1679         return ret;
1680 }
1681
1682 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1683                    enum c4iw_qp_attr_mask mask,
1684                    struct c4iw_qp_attributes *attrs,
1685                    int internal)
1686 {
1687         int ret = 0;
1688         struct c4iw_qp_attributes newattr = qhp->attr;
1689         int disconnect = 0;
1690         int terminate = 0;
1691         int abort = 0;
1692         int free = 0;
1693         struct c4iw_ep *ep = NULL;
1694
1695         pr_debug("qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n",
1696                  qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1697                  (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1698
1699         mutex_lock(&qhp->mutex);
1700
1701         /* Process attr changes if in IDLE */
1702         if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1703                 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1704                         ret = -EIO;
1705                         goto out;
1706                 }
1707                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1708                         newattr.enable_rdma_read = attrs->enable_rdma_read;
1709                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1710                         newattr.enable_rdma_write = attrs->enable_rdma_write;
1711                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1712                         newattr.enable_bind = attrs->enable_bind;
1713                 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1714                         if (attrs->max_ord > c4iw_max_read_depth) {
1715                                 ret = -EINVAL;
1716                                 goto out;
1717                         }
1718                         newattr.max_ord = attrs->max_ord;
1719                 }
1720                 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1721                         if (attrs->max_ird > cur_max_read_depth(rhp)) {
1722                                 ret = -EINVAL;
1723                                 goto out;
1724                         }
1725                         newattr.max_ird = attrs->max_ird;
1726                 }
1727                 qhp->attr = newattr;
1728         }
1729
1730         if (mask & C4IW_QP_ATTR_SQ_DB) {
1731                 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1732                 goto out;
1733         }
1734         if (mask & C4IW_QP_ATTR_RQ_DB) {
1735                 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1736                 goto out;
1737         }
1738
1739         if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1740                 goto out;
1741         if (qhp->attr.state == attrs->next_state)
1742                 goto out;
1743
1744         switch (qhp->attr.state) {
1745         case C4IW_QP_STATE_IDLE:
1746                 switch (attrs->next_state) {
1747                 case C4IW_QP_STATE_RTS:
1748                         if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1749                                 ret = -EINVAL;
1750                                 goto out;
1751                         }
1752                         if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1753                                 ret = -EINVAL;
1754                                 goto out;
1755                         }
1756                         qhp->attr.mpa_attr = attrs->mpa_attr;
1757                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1758                         qhp->ep = qhp->attr.llp_stream_handle;
1759                         set_state(qhp, C4IW_QP_STATE_RTS);
1760
1761                         /*
1762                          * Ref the endpoint here and deref when we
1763                          * disassociate the endpoint from the QP.  This
1764                          * happens in CLOSING->IDLE transition or *->ERROR
1765                          * transition.
1766                          */
1767                         c4iw_get_ep(&qhp->ep->com);
1768                         ret = rdma_init(rhp, qhp);
1769                         if (ret)
1770                                 goto err;
1771                         break;
1772                 case C4IW_QP_STATE_ERROR:
1773                         set_state(qhp, C4IW_QP_STATE_ERROR);
1774                         flush_qp(qhp);
1775                         break;
1776                 default:
1777                         ret = -EINVAL;
1778                         goto out;
1779                 }
1780                 break;
1781         case C4IW_QP_STATE_RTS:
1782                 switch (attrs->next_state) {
1783                 case C4IW_QP_STATE_CLOSING:
1784                         t4_set_wq_in_error(&qhp->wq, 0);
1785                         set_state(qhp, C4IW_QP_STATE_CLOSING);
1786                         ep = qhp->ep;
1787                         if (!internal) {
1788                                 abort = 0;
1789                                 disconnect = 1;
1790                                 c4iw_get_ep(&qhp->ep->com);
1791                         }
1792                         ret = rdma_fini(rhp, qhp, ep);
1793                         if (ret)
1794                                 goto err;
1795                         break;
1796                 case C4IW_QP_STATE_TERMINATE:
1797                         t4_set_wq_in_error(&qhp->wq, 0);
1798                         set_state(qhp, C4IW_QP_STATE_TERMINATE);
1799                         qhp->attr.layer_etype = attrs->layer_etype;
1800                         qhp->attr.ecode = attrs->ecode;
1801                         ep = qhp->ep;
1802                         if (!internal) {
1803                                 c4iw_get_ep(&qhp->ep->com);
1804                                 terminate = 1;
1805                                 disconnect = 1;
1806                         } else {
1807                                 terminate = qhp->attr.send_term;
1808                                 ret = rdma_fini(rhp, qhp, ep);
1809                                 if (ret)
1810                                         goto err;
1811                         }
1812                         break;
1813                 case C4IW_QP_STATE_ERROR:
1814                         t4_set_wq_in_error(&qhp->wq, 0);
1815                         set_state(qhp, C4IW_QP_STATE_ERROR);
1816                         if (!internal) {
1817                                 abort = 1;
1818                                 disconnect = 1;
1819                                 ep = qhp->ep;
1820                                 c4iw_get_ep(&qhp->ep->com);
1821                         }
1822                         goto err;
1823                         break;
1824                 default:
1825                         ret = -EINVAL;
1826                         goto out;
1827                 }
1828                 break;
1829         case C4IW_QP_STATE_CLOSING:
1830
1831                 /*
1832                  * Allow kernel users to move to ERROR for qp draining.
1833                  */
1834                 if (!internal && (qhp->ibqp.uobject || attrs->next_state !=
1835                                   C4IW_QP_STATE_ERROR)) {
1836                         ret = -EINVAL;
1837                         goto out;
1838                 }
1839                 switch (attrs->next_state) {
1840                 case C4IW_QP_STATE_IDLE:
1841                         flush_qp(qhp);
1842                         set_state(qhp, C4IW_QP_STATE_IDLE);
1843                         qhp->attr.llp_stream_handle = NULL;
1844                         c4iw_put_ep(&qhp->ep->com);
1845                         qhp->ep = NULL;
1846                         wake_up(&qhp->wait);
1847                         break;
1848                 case C4IW_QP_STATE_ERROR:
1849                         goto err;
1850                 default:
1851                         ret = -EINVAL;
1852                         goto err;
1853                 }
1854                 break;
1855         case C4IW_QP_STATE_ERROR:
1856                 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1857                         ret = -EINVAL;
1858                         goto out;
1859                 }
1860                 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1861                         ret = -EINVAL;
1862                         goto out;
1863                 }
1864                 set_state(qhp, C4IW_QP_STATE_IDLE);
1865                 break;
1866         case C4IW_QP_STATE_TERMINATE:
1867                 if (!internal) {
1868                         ret = -EINVAL;
1869                         goto out;
1870                 }
1871                 goto err;
1872                 break;
1873         default:
1874                 pr_err("%s in a bad state %d\n", __func__, qhp->attr.state);
1875                 ret = -EINVAL;
1876                 goto err;
1877                 break;
1878         }
1879         goto out;
1880 err:
1881         pr_debug("disassociating ep %p qpid 0x%x\n", qhp->ep,
1882                  qhp->wq.sq.qid);
1883
1884         /* disassociate the LLP connection */
1885         qhp->attr.llp_stream_handle = NULL;
1886         if (!ep)
1887                 ep = qhp->ep;
1888         qhp->ep = NULL;
1889         set_state(qhp, C4IW_QP_STATE_ERROR);
1890         free = 1;
1891         abort = 1;
1892         flush_qp(qhp);
1893         wake_up(&qhp->wait);
1894 out:
1895         mutex_unlock(&qhp->mutex);
1896
1897         if (terminate)
1898                 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1899
1900         /*
1901          * If disconnect is 1, then we need to initiate a disconnect
1902          * on the EP.  This can be a normal close (RTS->CLOSING) or
1903          * an abnormal close (RTS/CLOSING->ERROR).
1904          */
1905         if (disconnect) {
1906                 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1907                                                          GFP_KERNEL);
1908                 c4iw_put_ep(&ep->com);
1909         }
1910
1911         /*
1912          * If free is 1, then we've disassociated the EP from the QP
1913          * and we need to dereference the EP.
1914          */
1915         if (free)
1916                 c4iw_put_ep(&ep->com);
1917         pr_debug("exit state %d\n", qhp->attr.state);
1918         return ret;
1919 }
1920
1921 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1922 {
1923         struct c4iw_dev *rhp;
1924         struct c4iw_qp *qhp;
1925         struct c4iw_qp_attributes attrs;
1926
1927         qhp = to_c4iw_qp(ib_qp);
1928         rhp = qhp->rhp;
1929
1930         attrs.next_state = C4IW_QP_STATE_ERROR;
1931         if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1932                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1933         else
1934                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1935         wait_event(qhp->wait, !qhp->ep);
1936
1937         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1938
1939         spin_lock_irq(&rhp->lock);
1940         if (!list_empty(&qhp->db_fc_entry))
1941                 list_del_init(&qhp->db_fc_entry);
1942         spin_unlock_irq(&rhp->lock);
1943         free_ird(rhp, qhp->attr.max_ird);
1944
1945         c4iw_qp_rem_ref(ib_qp);
1946
1947         pr_debug("ib_qp %p qpid 0x%0x\n", ib_qp, qhp->wq.sq.qid);
1948         return 0;
1949 }
1950
1951 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1952                              struct ib_udata *udata)
1953 {
1954         struct c4iw_dev *rhp;
1955         struct c4iw_qp *qhp;
1956         struct c4iw_pd *php;
1957         struct c4iw_cq *schp;
1958         struct c4iw_cq *rchp;
1959         struct c4iw_create_qp_resp uresp;
1960         unsigned int sqsize, rqsize = 0;
1961         struct c4iw_ucontext *ucontext;
1962         int ret;
1963         struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm;
1964         struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL;
1965
1966         pr_debug("ib_pd %p\n", pd);
1967
1968         if (attrs->qp_type != IB_QPT_RC)
1969                 return ERR_PTR(-EINVAL);
1970
1971         php = to_c4iw_pd(pd);
1972         rhp = php->rhp;
1973         schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1974         rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1975         if (!schp || !rchp)
1976                 return ERR_PTR(-EINVAL);
1977
1978         if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1979                 return ERR_PTR(-EINVAL);
1980
1981         if (!attrs->srq) {
1982                 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size)
1983                         return ERR_PTR(-E2BIG);
1984                 rqsize = attrs->cap.max_recv_wr + 1;
1985                 if (rqsize < 8)
1986                         rqsize = 8;
1987         }
1988
1989         if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size)
1990                 return ERR_PTR(-E2BIG);
1991         sqsize = attrs->cap.max_send_wr + 1;
1992         if (sqsize < 8)
1993                 sqsize = 8;
1994
1995         ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1996
1997         qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1998         if (!qhp)
1999                 return ERR_PTR(-ENOMEM);
2000
2001         qhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
2002         if (!qhp->wr_waitp) {
2003                 ret = -ENOMEM;
2004                 goto err_free_qhp;
2005         }
2006
2007         qhp->wq.sq.size = sqsize;
2008         qhp->wq.sq.memsize =
2009                 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
2010                 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64);
2011         qhp->wq.sq.flush_cidx = -1;
2012         if (!attrs->srq) {
2013                 qhp->wq.rq.size = rqsize;
2014                 qhp->wq.rq.memsize =
2015                         (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
2016                         sizeof(*qhp->wq.rq.queue);
2017         }
2018
2019         if (ucontext) {
2020                 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
2021                 if (!attrs->srq)
2022                         qhp->wq.rq.memsize =
2023                                 roundup(qhp->wq.rq.memsize, PAGE_SIZE);
2024         }
2025
2026         ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
2027                         ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
2028                         qhp->wr_waitp, !attrs->srq);
2029         if (ret)
2030                 goto err_free_wr_wait;
2031
2032         attrs->cap.max_recv_wr = rqsize - 1;
2033         attrs->cap.max_send_wr = sqsize - 1;
2034         attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
2035
2036         qhp->rhp = rhp;
2037         qhp->attr.pd = php->pdid;
2038         qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
2039         qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
2040         qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
2041         qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
2042         qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
2043         if (!attrs->srq) {
2044                 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
2045                 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
2046         }
2047         qhp->attr.state = C4IW_QP_STATE_IDLE;
2048         qhp->attr.next_state = C4IW_QP_STATE_IDLE;
2049         qhp->attr.enable_rdma_read = 1;
2050         qhp->attr.enable_rdma_write = 1;
2051         qhp->attr.enable_bind = 1;
2052         qhp->attr.max_ord = 0;
2053         qhp->attr.max_ird = 0;
2054         qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
2055         spin_lock_init(&qhp->lock);
2056         mutex_init(&qhp->mutex);
2057         init_waitqueue_head(&qhp->wait);
2058         kref_init(&qhp->kref);
2059         INIT_WORK(&qhp->free_work, free_qp_work);
2060
2061         ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
2062         if (ret)
2063                 goto err_destroy_qp;
2064
2065         if (udata && ucontext) {
2066                 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL);
2067                 if (!sq_key_mm) {
2068                         ret = -ENOMEM;
2069                         goto err_remove_handle;
2070                 }
2071                 if (!attrs->srq) {
2072                         rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL);
2073                         if (!rq_key_mm) {
2074                                 ret = -ENOMEM;
2075                                 goto err_free_sq_key;
2076                         }
2077                 }
2078                 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL);
2079                 if (!sq_db_key_mm) {
2080                         ret = -ENOMEM;
2081                         goto err_free_rq_key;
2082                 }
2083                 if (!attrs->srq) {
2084                         rq_db_key_mm =
2085                                 kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL);
2086                         if (!rq_db_key_mm) {
2087                                 ret = -ENOMEM;
2088                                 goto err_free_sq_db_key;
2089                         }
2090                 }
2091                 if (t4_sq_onchip(&qhp->wq.sq)) {
2092                         ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm),
2093                                                  GFP_KERNEL);
2094                         if (!ma_sync_key_mm) {
2095                                 ret = -ENOMEM;
2096                                 goto err_free_rq_db_key;
2097                         }
2098                         uresp.flags = C4IW_QPF_ONCHIP;
2099                 } else
2100                         uresp.flags = 0;
2101                 uresp.qid_mask = rhp->rdev.qpmask;
2102                 uresp.sqid = qhp->wq.sq.qid;
2103                 uresp.sq_size = qhp->wq.sq.size;
2104                 uresp.sq_memsize = qhp->wq.sq.memsize;
2105                 if (!attrs->srq) {
2106                         uresp.rqid = qhp->wq.rq.qid;
2107                         uresp.rq_size = qhp->wq.rq.size;
2108                         uresp.rq_memsize = qhp->wq.rq.memsize;
2109                 }
2110                 spin_lock(&ucontext->mmap_lock);
2111                 if (ma_sync_key_mm) {
2112                         uresp.ma_sync_key = ucontext->key;
2113                         ucontext->key += PAGE_SIZE;
2114                 } else {
2115                         uresp.ma_sync_key =  0;
2116                 }
2117                 uresp.sq_key = ucontext->key;
2118                 ucontext->key += PAGE_SIZE;
2119                 if (!attrs->srq) {
2120                         uresp.rq_key = ucontext->key;
2121                         ucontext->key += PAGE_SIZE;
2122                 }
2123                 uresp.sq_db_gts_key = ucontext->key;
2124                 ucontext->key += PAGE_SIZE;
2125                 if (!attrs->srq) {
2126                         uresp.rq_db_gts_key = ucontext->key;
2127                         ucontext->key += PAGE_SIZE;
2128                 }
2129                 spin_unlock(&ucontext->mmap_lock);
2130                 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
2131                 if (ret)
2132                         goto err_free_ma_sync_key;
2133                 sq_key_mm->key = uresp.sq_key;
2134                 sq_key_mm->addr = qhp->wq.sq.phys_addr;
2135                 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize);
2136                 insert_mmap(ucontext, sq_key_mm);
2137                 if (!attrs->srq) {
2138                         rq_key_mm->key = uresp.rq_key;
2139                         rq_key_mm->addr = virt_to_phys(qhp->wq.rq.queue);
2140                         rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize);
2141                         insert_mmap(ucontext, rq_key_mm);
2142                 }
2143                 sq_db_key_mm->key = uresp.sq_db_gts_key;
2144                 sq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.sq.bar2_pa;
2145                 sq_db_key_mm->len = PAGE_SIZE;
2146                 insert_mmap(ucontext, sq_db_key_mm);
2147                 if (!attrs->srq) {
2148                         rq_db_key_mm->key = uresp.rq_db_gts_key;
2149                         rq_db_key_mm->addr =
2150                                 (u64)(unsigned long)qhp->wq.rq.bar2_pa;
2151                         rq_db_key_mm->len = PAGE_SIZE;
2152                         insert_mmap(ucontext, rq_db_key_mm);
2153                 }
2154                 if (ma_sync_key_mm) {
2155                         ma_sync_key_mm->key = uresp.ma_sync_key;
2156                         ma_sync_key_mm->addr =
2157                                 (pci_resource_start(rhp->rdev.lldi.pdev, 0) +
2158                                 PCIE_MA_SYNC_A) & PAGE_MASK;
2159                         ma_sync_key_mm->len = PAGE_SIZE;
2160                         insert_mmap(ucontext, ma_sync_key_mm);
2161                 }
2162
2163                 c4iw_get_ucontext(ucontext);
2164                 qhp->ucontext = ucontext;
2165         }
2166         if (!attrs->srq) {
2167                 qhp->wq.qp_errp =
2168                         &qhp->wq.rq.queue[qhp->wq.rq.size].status.qp_err;
2169         } else {
2170                 qhp->wq.qp_errp =
2171                         &qhp->wq.sq.queue[qhp->wq.sq.size].status.qp_err;
2172                 qhp->wq.srqidxp =
2173                         &qhp->wq.sq.queue[qhp->wq.sq.size].status.srqidx;
2174         }
2175
2176         qhp->ibqp.qp_num = qhp->wq.sq.qid;
2177         if (attrs->srq)
2178                 qhp->srq = to_c4iw_srq(attrs->srq);
2179         INIT_LIST_HEAD(&qhp->db_fc_entry);
2180         pr_debug("sq id %u size %u memsize %zu num_entries %u rq id %u size %u memsize %zu num_entries %u\n",
2181                  qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize,
2182                  attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size,
2183                  qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
2184         return &qhp->ibqp;
2185 err_free_ma_sync_key:
2186         kfree(ma_sync_key_mm);
2187 err_free_rq_db_key:
2188         if (!attrs->srq)
2189                 kfree(rq_db_key_mm);
2190 err_free_sq_db_key:
2191         kfree(sq_db_key_mm);
2192 err_free_rq_key:
2193         if (!attrs->srq)
2194                 kfree(rq_key_mm);
2195 err_free_sq_key:
2196         kfree(sq_key_mm);
2197 err_remove_handle:
2198         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
2199 err_destroy_qp:
2200         destroy_qp(&rhp->rdev, &qhp->wq,
2201                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx, !attrs->srq);
2202 err_free_wr_wait:
2203         c4iw_put_wr_wait(qhp->wr_waitp);
2204 err_free_qhp:
2205         kfree(qhp);
2206         return ERR_PTR(ret);
2207 }
2208
2209 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2210                       int attr_mask, struct ib_udata *udata)
2211 {
2212         struct c4iw_dev *rhp;
2213         struct c4iw_qp *qhp;
2214         enum c4iw_qp_attr_mask mask = 0;
2215         struct c4iw_qp_attributes attrs;
2216
2217         pr_debug("ib_qp %p\n", ibqp);
2218
2219         /* iwarp does not support the RTR state */
2220         if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
2221                 attr_mask &= ~IB_QP_STATE;
2222
2223         /* Make sure we still have something left to do */
2224         if (!attr_mask)
2225                 return 0;
2226
2227         memset(&attrs, 0, sizeof attrs);
2228         qhp = to_c4iw_qp(ibqp);
2229         rhp = qhp->rhp;
2230
2231         attrs.next_state = c4iw_convert_state(attr->qp_state);
2232         attrs.enable_rdma_read = (attr->qp_access_flags &
2233                                IB_ACCESS_REMOTE_READ) ?  1 : 0;
2234         attrs.enable_rdma_write = (attr->qp_access_flags &
2235                                 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
2236         attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
2237
2238
2239         mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
2240         mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
2241                         (C4IW_QP_ATTR_ENABLE_RDMA_READ |
2242                          C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
2243                          C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
2244
2245         /*
2246          * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
2247          * ringing the queue db when we're in DB_FULL mode.
2248          * Only allow this on T4 devices.
2249          */
2250         attrs.sq_db_inc = attr->sq_psn;
2251         attrs.rq_db_inc = attr->rq_psn;
2252         mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
2253         mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
2254         if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
2255             (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
2256                 return -EINVAL;
2257
2258         return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
2259 }
2260
2261 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
2262 {
2263         pr_debug("ib_dev %p qpn 0x%x\n", dev, qpn);
2264         return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
2265 }
2266
2267 void c4iw_dispatch_srq_limit_reached_event(struct c4iw_srq *srq)
2268 {
2269         struct ib_event event = {0};
2270
2271         event.device = &srq->rhp->ibdev;
2272         event.element.srq = &srq->ibsrq;
2273         event.event = IB_EVENT_SRQ_LIMIT_REACHED;
2274         ib_dispatch_event(&event);
2275 }
2276
2277 int c4iw_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *attr,
2278                     enum ib_srq_attr_mask srq_attr_mask,
2279                     struct ib_udata *udata)
2280 {
2281         struct c4iw_srq *srq = to_c4iw_srq(ib_srq);
2282         int ret = 0;
2283
2284         /*
2285          * XXX 0 mask == a SW interrupt for srq_limit reached...
2286          */
2287         if (udata && !srq_attr_mask) {
2288                 c4iw_dispatch_srq_limit_reached_event(srq);
2289                 goto out;
2290         }
2291
2292         /* no support for this yet */
2293         if (srq_attr_mask & IB_SRQ_MAX_WR) {
2294                 ret = -EINVAL;
2295                 goto out;
2296         }
2297
2298         if (!udata && (srq_attr_mask & IB_SRQ_LIMIT)) {
2299                 srq->armed = true;
2300                 srq->srq_limit = attr->srq_limit;
2301         }
2302 out:
2303         return ret;
2304 }
2305
2306 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2307                      int attr_mask, struct ib_qp_init_attr *init_attr)
2308 {
2309         struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
2310
2311         memset(attr, 0, sizeof *attr);
2312         memset(init_attr, 0, sizeof *init_attr);
2313         attr->qp_state = to_ib_qp_state(qhp->attr.state);
2314         init_attr->cap.max_send_wr = qhp->attr.sq_num_entries;
2315         init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries;
2316         init_attr->cap.max_send_sge = qhp->attr.sq_max_sges;
2317         init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges;
2318         init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE;
2319         init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0;
2320         return 0;
2321 }
2322
2323 static void free_srq_queue(struct c4iw_srq *srq, struct c4iw_dev_ucontext *uctx,
2324                            struct c4iw_wr_wait *wr_waitp)
2325 {
2326         struct c4iw_rdev *rdev = &srq->rhp->rdev;
2327         struct sk_buff *skb = srq->destroy_skb;
2328         struct t4_srq *wq = &srq->wq;
2329         struct fw_ri_res_wr *res_wr;
2330         struct fw_ri_res *res;
2331         int wr_len;
2332
2333         wr_len = sizeof(*res_wr) + sizeof(*res);
2334         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
2335
2336         res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
2337         memset(res_wr, 0, wr_len);
2338         res_wr->op_nres = cpu_to_be32(FW_WR_OP_V(FW_RI_RES_WR) |
2339                         FW_RI_RES_WR_NRES_V(1) |
2340                         FW_WR_COMPL_F);
2341         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
2342         res_wr->cookie = (uintptr_t)wr_waitp;
2343         res = res_wr->res;
2344         res->u.srq.restype = FW_RI_RES_TYPE_SRQ;
2345         res->u.srq.op = FW_RI_RES_OP_RESET;
2346         res->u.srq.srqid = cpu_to_be32(srq->idx);
2347         res->u.srq.eqid = cpu_to_be32(wq->qid);
2348
2349         c4iw_init_wr_wait(wr_waitp);
2350         c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, __func__);
2351
2352         dma_free_coherent(&rdev->lldi.pdev->dev,
2353                           wq->memsize, wq->queue,
2354                         pci_unmap_addr(wq, mapping));
2355         c4iw_rqtpool_free(rdev, wq->rqt_hwaddr, wq->rqt_size);
2356         kfree(wq->sw_rq);
2357         c4iw_put_qpid(rdev, wq->qid, uctx);
2358 }
2359
2360 static int alloc_srq_queue(struct c4iw_srq *srq, struct c4iw_dev_ucontext *uctx,
2361                            struct c4iw_wr_wait *wr_waitp)
2362 {
2363         struct c4iw_rdev *rdev = &srq->rhp->rdev;
2364         int user = (uctx != &rdev->uctx);
2365         struct t4_srq *wq = &srq->wq;
2366         struct fw_ri_res_wr *res_wr;
2367         struct fw_ri_res *res;
2368         struct sk_buff *skb;
2369         int wr_len;
2370         int eqsize;
2371         int ret = -ENOMEM;
2372
2373         wq->qid = c4iw_get_qpid(rdev, uctx);
2374         if (!wq->qid)
2375                 goto err;
2376
2377         if (!user) {
2378                 wq->sw_rq = kcalloc(wq->size, sizeof(*wq->sw_rq),
2379                                     GFP_KERNEL);
2380                 if (!wq->sw_rq)
2381                         goto err_put_qpid;
2382                 wq->pending_wrs = kcalloc(srq->wq.size,
2383                                           sizeof(*srq->wq.pending_wrs),
2384                                           GFP_KERNEL);
2385                 if (!wq->pending_wrs)
2386                         goto err_free_sw_rq;
2387         }
2388
2389         wq->rqt_size = wq->size;
2390         wq->rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rqt_size);
2391         if (!wq->rqt_hwaddr)
2392                 goto err_free_pending_wrs;
2393         wq->rqt_abs_idx = (wq->rqt_hwaddr - rdev->lldi.vr->rq.start) >>
2394                 T4_RQT_ENTRY_SHIFT;
2395
2396         wq->queue = dma_alloc_coherent(&rdev->lldi.pdev->dev,
2397                                        wq->memsize, &wq->dma_addr,
2398                         GFP_KERNEL);
2399         if (!wq->queue)
2400                 goto err_free_rqtpool;
2401
2402         memset(wq->queue, 0, wq->memsize);
2403         pci_unmap_addr_set(wq, mapping, wq->dma_addr);
2404
2405         wq->bar2_va = c4iw_bar2_addrs(rdev, wq->qid, T4_BAR2_QTYPE_EGRESS,
2406                                       &wq->bar2_qid,
2407                         user ? &wq->bar2_pa : NULL);
2408
2409         /*
2410          * User mode must have bar2 access.
2411          */
2412
2413         if (user && !wq->bar2_va) {
2414                 pr_warn(MOD "%s: srqid %u not in BAR2 range.\n",
2415                         pci_name(rdev->lldi.pdev), wq->qid);
2416                 ret = -EINVAL;
2417                 goto err_free_queue;
2418         }
2419
2420         /* build fw_ri_res_wr */
2421         wr_len = sizeof(*res_wr) + sizeof(*res);
2422
2423         skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL);
2424         if (!skb)
2425                 goto err_free_queue;
2426         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
2427
2428         res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
2429         memset(res_wr, 0, wr_len);
2430         res_wr->op_nres = cpu_to_be32(FW_WR_OP_V(FW_RI_RES_WR) |
2431                         FW_RI_RES_WR_NRES_V(1) |
2432                         FW_WR_COMPL_F);
2433         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
2434         res_wr->cookie = (uintptr_t)wr_waitp;
2435         res = res_wr->res;
2436         res->u.srq.restype = FW_RI_RES_TYPE_SRQ;
2437         res->u.srq.op = FW_RI_RES_OP_WRITE;
2438
2439         /*
2440          * eqsize is the number of 64B entries plus the status page size.
2441          */
2442         eqsize = wq->size * T4_RQ_NUM_SLOTS +
2443                 rdev->hw_queue.t4_eq_status_entries;
2444         res->u.srq.eqid = cpu_to_be32(wq->qid);
2445         res->u.srq.fetchszm_to_iqid =
2446                                                 /* no host cidx updates */
2447                 cpu_to_be32(FW_RI_RES_WR_HOSTFCMODE_V(0) |
2448                 FW_RI_RES_WR_CPRIO_V(0) |       /* don't keep in chip cache */
2449                 FW_RI_RES_WR_PCIECHN_V(0) |     /* set by uP at ri_init time */
2450                 FW_RI_RES_WR_FETCHRO_V(0));     /* relaxed_ordering */
2451         res->u.srq.dcaen_to_eqsize =
2452                 cpu_to_be32(FW_RI_RES_WR_DCAEN_V(0) |
2453                 FW_RI_RES_WR_DCACPU_V(0) |
2454                 FW_RI_RES_WR_FBMIN_V(2) |
2455                 FW_RI_RES_WR_FBMAX_V(3) |
2456                 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
2457                 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
2458                 FW_RI_RES_WR_EQSIZE_V(eqsize));
2459         res->u.srq.eqaddr = cpu_to_be64(wq->dma_addr);
2460         res->u.srq.srqid = cpu_to_be32(srq->idx);
2461         res->u.srq.pdid = cpu_to_be32(srq->pdid);
2462         res->u.srq.hwsrqsize = cpu_to_be32(wq->rqt_size);
2463         res->u.srq.hwsrqaddr = cpu_to_be32(wq->rqt_hwaddr -
2464                         rdev->lldi.vr->rq.start);
2465
2466         c4iw_init_wr_wait(wr_waitp);
2467
2468         ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, wq->qid, __func__);
2469         if (ret)
2470                 goto err_free_queue;
2471
2472         pr_debug("%s srq %u eqid %u pdid %u queue va %p pa 0x%llx\n"
2473                         " bar2_addr %p rqt addr 0x%x size %d\n",
2474                         __func__, srq->idx, wq->qid, srq->pdid, wq->queue,
2475                         (u64)virt_to_phys(wq->queue), wq->bar2_va,
2476                         wq->rqt_hwaddr, wq->rqt_size);
2477
2478         return 0;
2479 err_free_queue:
2480         dma_free_coherent(&rdev->lldi.pdev->dev,
2481                           wq->memsize, wq->queue,
2482                         pci_unmap_addr(wq, mapping));
2483 err_free_rqtpool:
2484         c4iw_rqtpool_free(rdev, wq->rqt_hwaddr, wq->rqt_size);
2485 err_free_pending_wrs:
2486         if (!user)
2487                 kfree(wq->pending_wrs);
2488 err_free_sw_rq:
2489         if (!user)
2490                 kfree(wq->sw_rq);
2491 err_put_qpid:
2492         c4iw_put_qpid(rdev, wq->qid, uctx);
2493 err:
2494         return ret;
2495 }
2496
2497 void c4iw_copy_wr_to_srq(struct t4_srq *srq, union t4_recv_wr *wqe, u8 len16)
2498 {
2499         u64 *src, *dst;
2500
2501         src = (u64 *)wqe;
2502         dst = (u64 *)((u8 *)srq->queue + srq->wq_pidx * T4_EQ_ENTRY_SIZE);
2503         while (len16) {
2504                 *dst++ = *src++;
2505                 if (dst >= (u64 *)&srq->queue[srq->size])
2506                         dst = (u64 *)srq->queue;
2507                 *dst++ = *src++;
2508                 if (dst >= (u64 *)&srq->queue[srq->size])
2509                         dst = (u64 *)srq->queue;
2510                 len16--;
2511         }
2512 }
2513
2514 struct ib_srq *c4iw_create_srq(struct ib_pd *pd, struct ib_srq_init_attr *attrs,
2515                                struct ib_udata *udata)
2516 {
2517         struct c4iw_dev *rhp;
2518         struct c4iw_srq *srq;
2519         struct c4iw_pd *php;
2520         struct c4iw_create_srq_resp uresp;
2521         struct c4iw_ucontext *ucontext;
2522         struct c4iw_mm_entry *srq_key_mm, *srq_db_key_mm;
2523         int rqsize;
2524         int ret;
2525         int wr_len;
2526
2527         pr_debug("%s ib_pd %p\n", __func__, pd);
2528
2529         php = to_c4iw_pd(pd);
2530         rhp = php->rhp;
2531
2532         if (!rhp->rdev.lldi.vr->srq.size)
2533                 return ERR_PTR(-EINVAL);
2534         if (attrs->attr.max_wr > rhp->rdev.hw_queue.t4_max_rq_size)
2535                 return ERR_PTR(-E2BIG);
2536         if (attrs->attr.max_sge > T4_MAX_RECV_SGE)
2537                 return ERR_PTR(-E2BIG);
2538
2539         /*
2540          * SRQ RQT and RQ must be a power of 2 and at least 16 deep.
2541          */
2542         rqsize = attrs->attr.max_wr + 1;
2543         rqsize = roundup_pow_of_two(max_t(u16, rqsize, 16));
2544
2545         ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
2546
2547         srq = kzalloc(sizeof(*srq), GFP_KERNEL);
2548         if (!srq)
2549                 return ERR_PTR(-ENOMEM);
2550
2551         srq->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
2552         if (!srq->wr_waitp) {
2553                 ret = -ENOMEM;
2554                 goto err_free_srq;
2555         }
2556
2557         srq->idx = c4iw_alloc_srq_idx(&rhp->rdev);
2558         if (srq->idx < 0) {
2559                 ret = -ENOMEM;
2560                 goto err_free_wr_wait;
2561         }
2562
2563         wr_len = sizeof(struct fw_ri_res_wr) + sizeof(struct fw_ri_res);
2564         srq->destroy_skb = alloc_skb(wr_len, GFP_KERNEL);
2565         if (!srq->destroy_skb) {
2566                 ret = -ENOMEM;
2567                 goto err_free_srq_idx;
2568         }
2569
2570         srq->rhp = rhp;
2571         srq->pdid = php->pdid;
2572
2573         srq->wq.size = rqsize;
2574         srq->wq.memsize =
2575                 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
2576                 sizeof(*srq->wq.queue);
2577         if (ucontext)
2578                 srq->wq.memsize = roundup(srq->wq.memsize, PAGE_SIZE);
2579
2580         ret = alloc_srq_queue(srq, ucontext ? &ucontext->uctx :
2581                         &rhp->rdev.uctx, srq->wr_waitp);
2582         if (ret)
2583                 goto err_free_skb;
2584         attrs->attr.max_wr = rqsize - 1;
2585
2586         if (CHELSIO_CHIP_VERSION(rhp->rdev.lldi.adapter_type) > CHELSIO_T6)
2587                 srq->flags = T4_SRQ_LIMIT_SUPPORT;
2588
2589         ret = insert_handle(rhp, &rhp->qpidr, srq, srq->wq.qid);
2590         if (ret)
2591                 goto err_free_queue;
2592
2593         if (udata) {
2594                 srq_key_mm = kmalloc(sizeof(*srq_key_mm), GFP_KERNEL);
2595                 if (!srq_key_mm) {
2596                         ret = -ENOMEM;
2597                         goto err_remove_handle;
2598                 }
2599                 srq_db_key_mm = kmalloc(sizeof(*srq_db_key_mm), GFP_KERNEL);
2600                 if (!srq_db_key_mm) {
2601                         ret = -ENOMEM;
2602                         goto err_free_srq_key_mm;
2603                 }
2604                 uresp.flags = srq->flags;
2605                 uresp.qid_mask = rhp->rdev.qpmask;
2606                 uresp.srqid = srq->wq.qid;
2607                 uresp.srq_size = srq->wq.size;
2608                 uresp.srq_memsize = srq->wq.memsize;
2609                 uresp.rqt_abs_idx = srq->wq.rqt_abs_idx;
2610                 spin_lock(&ucontext->mmap_lock);
2611                 uresp.srq_key = ucontext->key;
2612                 ucontext->key += PAGE_SIZE;
2613                 uresp.srq_db_gts_key = ucontext->key;
2614                 ucontext->key += PAGE_SIZE;
2615                 spin_unlock(&ucontext->mmap_lock);
2616                 ret = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
2617                 if (ret)
2618                         goto err_free_srq_db_key_mm;
2619                 srq_key_mm->key = uresp.srq_key;
2620                 srq_key_mm->addr = virt_to_phys(srq->wq.queue);
2621                 srq_key_mm->len = PAGE_ALIGN(srq->wq.memsize);
2622                 insert_mmap(ucontext, srq_key_mm);
2623                 srq_db_key_mm->key = uresp.srq_db_gts_key;
2624                 srq_db_key_mm->addr = (u64)(unsigned long)srq->wq.bar2_pa;
2625                 srq_db_key_mm->len = PAGE_SIZE;
2626                 insert_mmap(ucontext, srq_db_key_mm);
2627         }
2628
2629         pr_debug("%s srq qid %u idx %u size %u memsize %lu num_entries %u\n",
2630                  __func__, srq->wq.qid, srq->idx, srq->wq.size,
2631                         (unsigned long)srq->wq.memsize, attrs->attr.max_wr);
2632
2633         spin_lock_init(&srq->lock);
2634         return &srq->ibsrq;
2635 err_free_srq_db_key_mm:
2636         kfree(srq_db_key_mm);
2637 err_free_srq_key_mm:
2638         kfree(srq_key_mm);
2639 err_remove_handle:
2640         remove_handle(rhp, &rhp->qpidr, srq->wq.qid);
2641 err_free_queue:
2642         free_srq_queue(srq, ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
2643                        srq->wr_waitp);
2644 err_free_skb:
2645         if (srq->destroy_skb)
2646                 kfree_skb(srq->destroy_skb);
2647 err_free_srq_idx:
2648         c4iw_free_srq_idx(&rhp->rdev, srq->idx);
2649 err_free_wr_wait:
2650         c4iw_put_wr_wait(srq->wr_waitp);
2651 err_free_srq:
2652         kfree(srq);
2653         return ERR_PTR(ret);
2654 }
2655
2656 int c4iw_destroy_srq(struct ib_srq *ibsrq)
2657 {
2658         struct c4iw_dev *rhp;
2659         struct c4iw_srq *srq;
2660         struct c4iw_ucontext *ucontext;
2661
2662         srq = to_c4iw_srq(ibsrq);
2663         rhp = srq->rhp;
2664
2665         pr_debug("%s id %d\n", __func__, srq->wq.qid);
2666
2667         remove_handle(rhp, &rhp->qpidr, srq->wq.qid);
2668         ucontext = ibsrq->uobject ?
2669                 to_c4iw_ucontext(ibsrq->uobject->context) : NULL;
2670         free_srq_queue(srq, ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
2671                        srq->wr_waitp);
2672         c4iw_free_srq_idx(&rhp->rdev, srq->idx);
2673         c4iw_put_wr_wait(srq->wr_waitp);
2674         kfree(srq);
2675         return 0;
2676 }