2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
37 static int db_delay_usecs = 1;
38 module_param(db_delay_usecs, int, 0644);
39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
41 static int ocqp_support = 1;
42 module_param(ocqp_support, int, 0644);
43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
45 int db_fc_threshold = 1000;
46 module_param(db_fc_threshold, int, 0644);
47 MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
51 int db_coalescing_threshold;
52 module_param(db_coalescing_threshold, int, 0644);
53 MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
57 static int max_fr_immd = T4_MAX_FR_IMMD;
58 module_param(max_fr_immd, int, 0644);
59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
61 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
64 spin_lock_irqsave(&qhp->lock, flag);
65 qhp->attr.state = state;
66 spin_unlock_irqrestore(&qhp->lock, flag);
69 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
71 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
74 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
76 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
77 pci_unmap_addr(sq, mapping));
80 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
83 dealloc_oc_sq(rdev, sq);
85 dealloc_host_sq(rdev, sq);
88 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
90 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
92 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
95 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
96 rdev->lldi.vr->ocq.start;
97 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
98 rdev->lldi.vr->ocq.start);
99 sq->flags |= T4_SQ_ONCHIP;
103 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
105 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
106 &(sq->dma_addr), GFP_KERNEL);
109 sq->phys_addr = virt_to_phys(sq->queue);
110 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
114 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
118 ret = alloc_oc_sq(rdev, sq);
120 ret = alloc_host_sq(rdev, sq);
124 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
125 struct c4iw_dev_ucontext *uctx)
128 * uP clears EQ contexts when the connection exits rdma mode,
129 * so no need to post a RESET WR for these EQs.
131 dma_free_coherent(&(rdev->lldi.pdev->dev),
132 wq->rq.memsize, wq->rq.queue,
133 dma_unmap_addr(&wq->rq, mapping));
134 dealloc_sq(rdev, &wq->sq);
135 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
138 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
139 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
143 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
144 struct t4_cq *rcq, struct t4_cq *scq,
145 struct c4iw_dev_ucontext *uctx)
147 int user = (uctx != &rdev->uctx);
148 struct fw_ri_res_wr *res_wr;
149 struct fw_ri_res *res;
151 struct c4iw_wr_wait wr_wait;
156 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
160 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
167 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
174 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
183 * RQT must be a power of 2.
185 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
186 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
187 if (!wq->rq.rqt_hwaddr) {
192 ret = alloc_sq(rdev, &wq->sq, user);
195 memset(wq->sq.queue, 0, wq->sq.memsize);
196 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
198 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
199 wq->rq.memsize, &(wq->rq.dma_addr),
205 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
206 __func__, wq->sq.queue,
207 (unsigned long long)virt_to_phys(wq->sq.queue),
209 (unsigned long long)virt_to_phys(wq->rq.queue));
210 memset(wq->rq.queue, 0, wq->rq.memsize);
211 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
213 wq->db = rdev->lldi.db_reg;
214 wq->gts = rdev->lldi.gts_reg;
215 if (user || is_t5(rdev->lldi.adapter_type)) {
218 off = (wq->sq.qid << rdev->qpshift) & PAGE_MASK;
220 wq->sq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
222 off += 128 * (wq->sq.qid & rdev->qpmask) + 8;
223 wq->sq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
225 off = (wq->rq.qid << rdev->qpshift) & PAGE_MASK;
227 wq->rq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
229 off += 128 * (wq->rq.qid & rdev->qpmask) + 8;
230 wq->rq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
236 /* build fw_ri_res_wr */
237 wr_len = sizeof *res_wr + 2 * sizeof *res;
239 skb = alloc_skb(wr_len, GFP_KERNEL);
244 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
246 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
247 memset(res_wr, 0, wr_len);
248 res_wr->op_nres = cpu_to_be32(
249 FW_WR_OP(FW_RI_RES_WR) |
250 V_FW_RI_RES_WR_NRES(2) |
252 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
253 res_wr->cookie = (unsigned long) &wr_wait;
255 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
256 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
259 * eqsize is the number of 64B entries plus the status page size.
261 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
263 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
264 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
265 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
266 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
267 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
268 V_FW_RI_RES_WR_IQID(scq->cqid));
269 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
270 V_FW_RI_RES_WR_DCAEN(0) |
271 V_FW_RI_RES_WR_DCACPU(0) |
272 V_FW_RI_RES_WR_FBMIN(2) |
273 V_FW_RI_RES_WR_FBMAX(2) |
274 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
275 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
276 V_FW_RI_RES_WR_EQSIZE(eqsize));
277 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
278 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
280 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
281 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
284 * eqsize is the number of 64B entries plus the status page size.
286 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
287 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
288 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
289 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
290 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
291 V_FW_RI_RES_WR_IQID(rcq->cqid));
292 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
293 V_FW_RI_RES_WR_DCAEN(0) |
294 V_FW_RI_RES_WR_DCACPU(0) |
295 V_FW_RI_RES_WR_FBMIN(2) |
296 V_FW_RI_RES_WR_FBMAX(2) |
297 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
298 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
299 V_FW_RI_RES_WR_EQSIZE(eqsize));
300 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
301 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
303 c4iw_init_wr_wait(&wr_wait);
305 ret = c4iw_ofld_send(rdev, skb);
308 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
312 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%lx rqudb 0x%lx\n",
313 __func__, wq->sq.qid, wq->rq.qid, wq->db,
314 (__force unsigned long) wq->sq.udb,
315 (__force unsigned long) wq->rq.udb);
319 dma_free_coherent(&(rdev->lldi.pdev->dev),
320 wq->rq.memsize, wq->rq.queue,
321 dma_unmap_addr(&wq->rq, mapping));
323 dealloc_sq(rdev, &wq->sq);
325 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
331 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
333 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
337 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
338 struct ib_send_wr *wr, int max, u32 *plenp)
345 dstp = (u8 *)immdp->data;
346 for (i = 0; i < wr->num_sge; i++) {
347 if ((plen + wr->sg_list[i].length) > max)
349 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
350 plen += wr->sg_list[i].length;
351 rem = wr->sg_list[i].length;
353 if (dstp == (u8 *)&sq->queue[sq->size])
354 dstp = (u8 *)sq->queue;
355 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
358 len = (u8 *)&sq->queue[sq->size] - dstp;
359 memcpy(dstp, srcp, len);
365 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
367 memset(dstp, 0, len);
368 immdp->op = FW_RI_DATA_IMMD;
371 immdp->immdlen = cpu_to_be32(plen);
376 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
377 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
378 int num_sge, u32 *plenp)
383 __be64 *flitp = (__be64 *)isglp->sge;
385 for (i = 0; i < num_sge; i++) {
386 if ((plen + sg_list[i].length) < plen)
388 plen += sg_list[i].length;
389 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
391 if (++flitp == queue_end)
393 *flitp = cpu_to_be64(sg_list[i].addr);
394 if (++flitp == queue_end)
397 *flitp = (__force __be64)0;
398 isglp->op = FW_RI_DATA_ISGL;
400 isglp->nsge = cpu_to_be16(num_sge);
407 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
408 struct ib_send_wr *wr, u8 *len16)
414 if (wr->num_sge > T4_MAX_SEND_SGE)
416 switch (wr->opcode) {
418 if (wr->send_flags & IB_SEND_SOLICITED)
419 wqe->send.sendop_pkd = cpu_to_be32(
420 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
422 wqe->send.sendop_pkd = cpu_to_be32(
423 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
424 wqe->send.stag_inv = 0;
426 case IB_WR_SEND_WITH_INV:
427 if (wr->send_flags & IB_SEND_SOLICITED)
428 wqe->send.sendop_pkd = cpu_to_be32(
429 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
431 wqe->send.sendop_pkd = cpu_to_be32(
432 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
433 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
442 if (wr->send_flags & IB_SEND_INLINE) {
443 ret = build_immd(sq, wqe->send.u.immd_src, wr,
444 T4_MAX_SEND_INLINE, &plen);
447 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
450 ret = build_isgl((__be64 *)sq->queue,
451 (__be64 *)&sq->queue[sq->size],
452 wqe->send.u.isgl_src,
453 wr->sg_list, wr->num_sge, &plen);
456 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
457 wr->num_sge * sizeof(struct fw_ri_sge);
460 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
461 wqe->send.u.immd_src[0].r1 = 0;
462 wqe->send.u.immd_src[0].r2 = 0;
463 wqe->send.u.immd_src[0].immdlen = 0;
464 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
467 *len16 = DIV_ROUND_UP(size, 16);
468 wqe->send.plen = cpu_to_be32(plen);
472 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
473 struct ib_send_wr *wr, u8 *len16)
479 if (wr->num_sge > T4_MAX_SEND_SGE)
482 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
483 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
485 if (wr->send_flags & IB_SEND_INLINE) {
486 ret = build_immd(sq, wqe->write.u.immd_src, wr,
487 T4_MAX_WRITE_INLINE, &plen);
490 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
493 ret = build_isgl((__be64 *)sq->queue,
494 (__be64 *)&sq->queue[sq->size],
495 wqe->write.u.isgl_src,
496 wr->sg_list, wr->num_sge, &plen);
499 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
500 wr->num_sge * sizeof(struct fw_ri_sge);
503 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
504 wqe->write.u.immd_src[0].r1 = 0;
505 wqe->write.u.immd_src[0].r2 = 0;
506 wqe->write.u.immd_src[0].immdlen = 0;
507 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
510 *len16 = DIV_ROUND_UP(size, 16);
511 wqe->write.plen = cpu_to_be32(plen);
515 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
520 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
521 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
523 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
524 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
525 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
526 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
528 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
530 wqe->read.stag_src = cpu_to_be32(2);
531 wqe->read.to_src_hi = 0;
532 wqe->read.to_src_lo = 0;
533 wqe->read.stag_sink = cpu_to_be32(2);
535 wqe->read.to_sink_hi = 0;
536 wqe->read.to_sink_lo = 0;
540 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
544 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
545 struct ib_recv_wr *wr, u8 *len16)
549 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
550 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
551 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
554 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
555 wr->num_sge * sizeof(struct fw_ri_sge), 16);
559 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
560 struct ib_send_wr *wr, u8 *len16, u8 t5dev)
563 struct fw_ri_immd *imdp;
566 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
569 if (wr->wr.fast_reg.page_list_len >
570 t4_max_fr_depth(use_dsgl))
573 wqe->fr.qpbinde_to_dcacpu = 0;
574 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
575 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
576 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
578 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
579 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
580 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
581 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
584 if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
585 struct c4iw_fr_page_list *c4pl =
586 to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
587 struct fw_ri_dsgl *sglp;
589 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
590 wr->wr.fast_reg.page_list->page_list[i] = (__force u64)
592 wr->wr.fast_reg.page_list->page_list[i]);
595 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
596 sglp->op = FW_RI_DATA_DSGL;
598 sglp->nsge = cpu_to_be16(1);
599 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
600 sglp->len0 = cpu_to_be32(pbllen);
602 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
604 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
605 imdp->op = FW_RI_DATA_IMMD;
608 imdp->immdlen = cpu_to_be32(pbllen);
609 p = (__be64 *)(imdp + 1);
611 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
613 (u64)wr->wr.fast_reg.page_list->page_list[i]);
615 if (++p == (__be64 *)&sq->queue[sq->size])
616 p = (__be64 *)sq->queue;
622 if (++p == (__be64 *)&sq->queue[sq->size])
623 p = (__be64 *)sq->queue;
625 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
631 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
634 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
636 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
640 void c4iw_qp_add_ref(struct ib_qp *qp)
642 PDBG("%s ib_qp %p\n", __func__, qp);
643 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
646 void c4iw_qp_rem_ref(struct ib_qp *qp)
648 PDBG("%s ib_qp %p\n", __func__, qp);
649 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
650 wake_up(&(to_c4iw_qp(qp)->wait));
653 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
655 if (list_empty(entry))
656 list_add_tail(entry, head);
659 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
663 spin_lock_irqsave(&qhp->rhp->lock, flags);
664 spin_lock(&qhp->lock);
665 if (qhp->rhp->db_state == NORMAL)
666 t4_ring_sq_db(&qhp->wq, inc,
667 is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
669 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
670 qhp->wq.sq.wq_pidx_inc += inc;
672 spin_unlock(&qhp->lock);
673 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
677 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
681 spin_lock_irqsave(&qhp->rhp->lock, flags);
682 spin_lock(&qhp->lock);
683 if (qhp->rhp->db_state == NORMAL)
684 t4_ring_rq_db(&qhp->wq, inc,
685 is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
687 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
688 qhp->wq.rq.wq_pidx_inc += inc;
690 spin_unlock(&qhp->lock);
691 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
695 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
696 struct ib_send_wr **bad_wr)
700 enum fw_wr_opcodes fw_opcode = 0;
701 enum fw_ri_wr_flags fw_flags;
703 union t4_wr *wqe = NULL;
705 struct t4_swsqe *swsqe;
709 qhp = to_c4iw_qp(ibqp);
710 spin_lock_irqsave(&qhp->lock, flag);
711 if (t4_wq_in_error(&qhp->wq)) {
712 spin_unlock_irqrestore(&qhp->lock, flag);
715 num_wrs = t4_sq_avail(&qhp->wq);
717 spin_unlock_irqrestore(&qhp->lock, flag);
726 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
727 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
730 if (wr->send_flags & IB_SEND_SOLICITED)
731 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
732 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
733 fw_flags |= FW_RI_COMPLETION_FLAG;
734 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
735 switch (wr->opcode) {
736 case IB_WR_SEND_WITH_INV:
738 if (wr->send_flags & IB_SEND_FENCE)
739 fw_flags |= FW_RI_READ_FENCE_FLAG;
740 fw_opcode = FW_RI_SEND_WR;
741 if (wr->opcode == IB_WR_SEND)
742 swsqe->opcode = FW_RI_SEND;
744 swsqe->opcode = FW_RI_SEND_WITH_INV;
745 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
747 case IB_WR_RDMA_WRITE:
748 fw_opcode = FW_RI_RDMA_WRITE_WR;
749 swsqe->opcode = FW_RI_RDMA_WRITE;
750 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
752 case IB_WR_RDMA_READ:
753 case IB_WR_RDMA_READ_WITH_INV:
754 fw_opcode = FW_RI_RDMA_READ_WR;
755 swsqe->opcode = FW_RI_READ_REQ;
756 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
757 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
760 err = build_rdma_read(wqe, wr, &len16);
763 swsqe->read_len = wr->sg_list[0].length;
764 if (!qhp->wq.sq.oldest_read)
765 qhp->wq.sq.oldest_read = swsqe;
767 case IB_WR_FAST_REG_MR:
768 fw_opcode = FW_RI_FR_NSMR_WR;
769 swsqe->opcode = FW_RI_FAST_REGISTER;
770 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16,
772 qhp->rhp->rdev.lldi.adapter_type) ?
775 case IB_WR_LOCAL_INV:
776 if (wr->send_flags & IB_SEND_FENCE)
777 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
778 fw_opcode = FW_RI_INV_LSTAG_WR;
779 swsqe->opcode = FW_RI_LOCAL_INV;
780 err = build_inv_stag(wqe, wr, &len16);
783 PDBG("%s post of type=%d TBD!\n", __func__,
791 swsqe->idx = qhp->wq.sq.pidx;
793 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
796 swsqe->wr_id = wr->wr_id;
798 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
800 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
801 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
802 swsqe->opcode, swsqe->read_len);
805 t4_sq_produce(&qhp->wq, len16);
806 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
808 if (!qhp->rhp->rdev.status_page->db_off) {
809 t4_ring_sq_db(&qhp->wq, idx,
810 is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
811 spin_unlock_irqrestore(&qhp->lock, flag);
813 spin_unlock_irqrestore(&qhp->lock, flag);
814 ring_kernel_sq_db(qhp, idx);
819 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
820 struct ib_recv_wr **bad_wr)
824 union t4_recv_wr *wqe = NULL;
830 qhp = to_c4iw_qp(ibqp);
831 spin_lock_irqsave(&qhp->lock, flag);
832 if (t4_wq_in_error(&qhp->wq)) {
833 spin_unlock_irqrestore(&qhp->lock, flag);
836 num_wrs = t4_rq_avail(&qhp->wq);
838 spin_unlock_irqrestore(&qhp->lock, flag);
842 if (wr->num_sge > T4_MAX_RECV_SGE) {
847 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
851 err = build_rdma_recv(qhp, wqe, wr, &len16);
859 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
861 wqe->recv.opcode = FW_RI_RECV_WR;
863 wqe->recv.wrid = qhp->wq.rq.pidx;
867 wqe->recv.len16 = len16;
868 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
869 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
870 t4_rq_produce(&qhp->wq, len16);
871 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
875 if (!qhp->rhp->rdev.status_page->db_off) {
876 t4_ring_rq_db(&qhp->wq, idx,
877 is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
878 spin_unlock_irqrestore(&qhp->lock, flag);
880 spin_unlock_irqrestore(&qhp->lock, flag);
881 ring_kernel_rq_db(qhp, idx);
886 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
891 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
901 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
906 status = CQE_STATUS(err_cqe);
907 opcode = CQE_OPCODE(err_cqe);
908 rqtype = RQ_TYPE(err_cqe);
909 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
910 (opcode == FW_RI_SEND_WITH_SE_INV);
911 tagged = (opcode == FW_RI_RDMA_WRITE) ||
912 (rqtype && (opcode == FW_RI_READ_RESP));
917 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
918 *ecode = RDMAP_CANT_INV_STAG;
920 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
921 *ecode = RDMAP_INV_STAG;
925 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
926 if ((opcode == FW_RI_SEND_WITH_INV) ||
927 (opcode == FW_RI_SEND_WITH_SE_INV))
928 *ecode = RDMAP_CANT_INV_STAG;
930 *ecode = RDMAP_STAG_NOT_ASSOC;
933 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
934 *ecode = RDMAP_STAG_NOT_ASSOC;
937 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
938 *ecode = RDMAP_ACC_VIOL;
941 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
942 *ecode = RDMAP_TO_WRAP;
946 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
947 *ecode = DDPT_BASE_BOUNDS;
949 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
950 *ecode = RDMAP_BASE_BOUNDS;
953 case T4_ERR_INVALIDATE_SHARED_MR:
954 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
955 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
956 *ecode = RDMAP_CANT_INV_STAG;
959 case T4_ERR_ECC_PSTAG:
960 case T4_ERR_INTERNAL_ERR:
961 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
964 case T4_ERR_OUT_OF_RQE:
965 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
966 *ecode = DDPU_INV_MSN_NOBUF;
968 case T4_ERR_PBL_ADDR_BOUND:
969 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
970 *ecode = DDPT_BASE_BOUNDS;
973 *layer_type = LAYER_MPA|DDP_LLP;
974 *ecode = MPA_CRC_ERR;
977 *layer_type = LAYER_MPA|DDP_LLP;
978 *ecode = MPA_MARKER_ERR;
980 case T4_ERR_PDU_LEN_ERR:
981 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
982 *ecode = DDPU_MSG_TOOBIG;
984 case T4_ERR_DDP_VERSION:
986 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
987 *ecode = DDPT_INV_VERS;
989 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
990 *ecode = DDPU_INV_VERS;
993 case T4_ERR_RDMA_VERSION:
994 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
995 *ecode = RDMAP_INV_VERS;
998 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
999 *ecode = RDMAP_INV_OPCODE;
1001 case T4_ERR_DDP_QUEUE_NUM:
1002 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1003 *ecode = DDPU_INV_QN;
1006 case T4_ERR_MSN_GAP:
1007 case T4_ERR_MSN_RANGE:
1008 case T4_ERR_IRD_OVERFLOW:
1009 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1010 *ecode = DDPU_INV_MSN_RANGE;
1013 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1017 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1018 *ecode = DDPU_INV_MO;
1021 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1027 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1030 struct fw_ri_wr *wqe;
1031 struct sk_buff *skb;
1032 struct terminate_message *term;
1034 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1037 skb = alloc_skb(sizeof *wqe, gfp);
1040 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1042 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1043 memset(wqe, 0, sizeof *wqe);
1044 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
1045 wqe->flowid_len16 = cpu_to_be32(
1046 FW_WR_FLOWID(qhp->ep->hwtid) |
1047 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1049 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1050 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1051 term = (struct terminate_message *)wqe->u.terminate.termmsg;
1052 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1053 term->layer_etype = qhp->attr.layer_etype;
1054 term->ecode = qhp->attr.ecode;
1056 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1057 c4iw_ofld_send(&qhp->rhp->rdev, skb);
1061 * Assumes qhp lock is held.
1063 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1064 struct c4iw_cq *schp)
1070 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
1072 /* locking hierarchy: cq lock first, then qp lock. */
1073 spin_lock_irqsave(&rchp->lock, flag);
1074 spin_lock(&qhp->lock);
1076 if (qhp->wq.flushed) {
1077 spin_unlock(&qhp->lock);
1078 spin_unlock_irqrestore(&rchp->lock, flag);
1081 qhp->wq.flushed = 1;
1083 c4iw_flush_hw_cq(rchp);
1084 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1085 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1086 spin_unlock(&qhp->lock);
1087 spin_unlock_irqrestore(&rchp->lock, flag);
1089 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1090 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1091 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1094 /* locking hierarchy: cq lock first, then qp lock. */
1095 spin_lock_irqsave(&schp->lock, flag);
1096 spin_lock(&qhp->lock);
1098 c4iw_flush_hw_cq(schp);
1099 flushed = c4iw_flush_sq(qhp);
1100 spin_unlock(&qhp->lock);
1101 spin_unlock_irqrestore(&schp->lock, flag);
1103 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1104 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
1105 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1109 static void flush_qp(struct c4iw_qp *qhp)
1111 struct c4iw_cq *rchp, *schp;
1114 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1115 schp = to_c4iw_cq(qhp->ibqp.send_cq);
1117 t4_set_wq_in_error(&qhp->wq);
1118 if (qhp->ibqp.uobject) {
1119 t4_set_cq_in_error(&rchp->cq);
1120 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1121 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1122 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1124 t4_set_cq_in_error(&schp->cq);
1125 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1126 (*schp->ibcq.comp_handler)(&schp->ibcq,
1127 schp->ibcq.cq_context);
1128 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1132 __flush_qp(qhp, rchp, schp);
1135 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1138 struct fw_ri_wr *wqe;
1140 struct sk_buff *skb;
1142 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1145 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1148 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1150 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1151 memset(wqe, 0, sizeof *wqe);
1152 wqe->op_compl = cpu_to_be32(
1153 FW_WR_OP(FW_RI_INIT_WR) |
1155 wqe->flowid_len16 = cpu_to_be32(
1156 FW_WR_FLOWID(ep->hwtid) |
1157 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1158 wqe->cookie = (unsigned long) &ep->com.wr_wait;
1160 wqe->u.fini.type = FW_RI_TYPE_FINI;
1161 ret = c4iw_ofld_send(&rhp->rdev, skb);
1165 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1166 qhp->wq.sq.qid, __func__);
1168 PDBG("%s ret %d\n", __func__, ret);
1172 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1174 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1175 memset(&init->u, 0, sizeof init->u);
1177 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1178 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1179 init->u.write.stag_sink = cpu_to_be32(1);
1180 init->u.write.to_sink = cpu_to_be64(1);
1181 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1182 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1183 sizeof(struct fw_ri_immd),
1186 case FW_RI_INIT_P2PTYPE_READ_REQ:
1187 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1188 init->u.read.stag_src = cpu_to_be32(1);
1189 init->u.read.to_src_lo = cpu_to_be32(1);
1190 init->u.read.stag_sink = cpu_to_be32(1);
1191 init->u.read.to_sink_lo = cpu_to_be32(1);
1192 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1197 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1199 struct fw_ri_wr *wqe;
1201 struct sk_buff *skb;
1203 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1206 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1209 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1211 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1212 memset(wqe, 0, sizeof *wqe);
1213 wqe->op_compl = cpu_to_be32(
1214 FW_WR_OP(FW_RI_INIT_WR) |
1216 wqe->flowid_len16 = cpu_to_be32(
1217 FW_WR_FLOWID(qhp->ep->hwtid) |
1218 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1220 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
1222 wqe->u.init.type = FW_RI_TYPE_INIT;
1223 wqe->u.init.mpareqbit_p2ptype =
1224 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1225 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1226 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1227 if (qhp->attr.mpa_attr.recv_marker_enabled)
1228 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1229 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1230 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1231 if (qhp->attr.mpa_attr.crc_enabled)
1232 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1234 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1235 FW_RI_QP_RDMA_WRITE_ENABLE |
1236 FW_RI_QP_BIND_ENABLE;
1237 if (!qhp->ibqp.uobject)
1238 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1239 FW_RI_QP_STAG0_ENABLE;
1240 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1241 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1242 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1243 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1244 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1245 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1246 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1247 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1248 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1249 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1250 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1251 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1252 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1253 rhp->rdev.lldi.vr->rq.start);
1254 if (qhp->attr.mpa_attr.initiator)
1255 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1257 ret = c4iw_ofld_send(&rhp->rdev, skb);
1261 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1262 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1264 PDBG("%s ret %d\n", __func__, ret);
1268 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1269 enum c4iw_qp_attr_mask mask,
1270 struct c4iw_qp_attributes *attrs,
1274 struct c4iw_qp_attributes newattr = qhp->attr;
1279 struct c4iw_ep *ep = NULL;
1281 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1282 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1283 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1285 mutex_lock(&qhp->mutex);
1287 /* Process attr changes if in IDLE */
1288 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1289 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1293 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1294 newattr.enable_rdma_read = attrs->enable_rdma_read;
1295 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1296 newattr.enable_rdma_write = attrs->enable_rdma_write;
1297 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1298 newattr.enable_bind = attrs->enable_bind;
1299 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1300 if (attrs->max_ord > c4iw_max_read_depth) {
1304 newattr.max_ord = attrs->max_ord;
1306 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1307 if (attrs->max_ird > c4iw_max_read_depth) {
1311 newattr.max_ird = attrs->max_ird;
1313 qhp->attr = newattr;
1316 if (mask & C4IW_QP_ATTR_SQ_DB) {
1317 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1320 if (mask & C4IW_QP_ATTR_RQ_DB) {
1321 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1325 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1327 if (qhp->attr.state == attrs->next_state)
1330 switch (qhp->attr.state) {
1331 case C4IW_QP_STATE_IDLE:
1332 switch (attrs->next_state) {
1333 case C4IW_QP_STATE_RTS:
1334 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1338 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1342 qhp->attr.mpa_attr = attrs->mpa_attr;
1343 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1344 qhp->ep = qhp->attr.llp_stream_handle;
1345 set_state(qhp, C4IW_QP_STATE_RTS);
1348 * Ref the endpoint here and deref when we
1349 * disassociate the endpoint from the QP. This
1350 * happens in CLOSING->IDLE transition or *->ERROR
1353 c4iw_get_ep(&qhp->ep->com);
1354 ret = rdma_init(rhp, qhp);
1358 case C4IW_QP_STATE_ERROR:
1359 set_state(qhp, C4IW_QP_STATE_ERROR);
1367 case C4IW_QP_STATE_RTS:
1368 switch (attrs->next_state) {
1369 case C4IW_QP_STATE_CLOSING:
1370 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1371 t4_set_wq_in_error(&qhp->wq);
1372 set_state(qhp, C4IW_QP_STATE_CLOSING);
1377 c4iw_get_ep(&qhp->ep->com);
1379 ret = rdma_fini(rhp, qhp, ep);
1383 case C4IW_QP_STATE_TERMINATE:
1384 t4_set_wq_in_error(&qhp->wq);
1385 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1386 qhp->attr.layer_etype = attrs->layer_etype;
1387 qhp->attr.ecode = attrs->ecode;
1393 ret = rdma_fini(rhp, qhp, ep);
1397 c4iw_get_ep(&qhp->ep->com);
1399 case C4IW_QP_STATE_ERROR:
1400 t4_set_wq_in_error(&qhp->wq);
1401 set_state(qhp, C4IW_QP_STATE_ERROR);
1406 c4iw_get_ep(&qhp->ep->com);
1415 case C4IW_QP_STATE_CLOSING:
1420 switch (attrs->next_state) {
1421 case C4IW_QP_STATE_IDLE:
1423 set_state(qhp, C4IW_QP_STATE_IDLE);
1424 qhp->attr.llp_stream_handle = NULL;
1425 c4iw_put_ep(&qhp->ep->com);
1427 wake_up(&qhp->wait);
1429 case C4IW_QP_STATE_ERROR:
1436 case C4IW_QP_STATE_ERROR:
1437 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1441 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1445 set_state(qhp, C4IW_QP_STATE_IDLE);
1447 case C4IW_QP_STATE_TERMINATE:
1455 printk(KERN_ERR "%s in a bad state %d\n",
1456 __func__, qhp->attr.state);
1463 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1466 /* disassociate the LLP connection */
1467 qhp->attr.llp_stream_handle = NULL;
1471 set_state(qhp, C4IW_QP_STATE_ERROR);
1474 wake_up(&qhp->wait);
1478 mutex_unlock(&qhp->mutex);
1481 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1484 * If disconnect is 1, then we need to initiate a disconnect
1485 * on the EP. This can be a normal close (RTS->CLOSING) or
1486 * an abnormal close (RTS/CLOSING->ERROR).
1489 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1491 c4iw_put_ep(&ep->com);
1495 * If free is 1, then we've disassociated the EP from the QP
1496 * and we need to dereference the EP.
1499 c4iw_put_ep(&ep->com);
1500 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1504 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1506 struct c4iw_dev *rhp;
1507 struct c4iw_qp *qhp;
1508 struct c4iw_qp_attributes attrs;
1509 struct c4iw_ucontext *ucontext;
1511 qhp = to_c4iw_qp(ib_qp);
1514 attrs.next_state = C4IW_QP_STATE_ERROR;
1515 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1516 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1518 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1519 wait_event(qhp->wait, !qhp->ep);
1521 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1522 atomic_dec(&qhp->refcnt);
1523 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1525 spin_lock_irq(&rhp->lock);
1526 if (!list_empty(&qhp->db_fc_entry))
1527 list_del_init(&qhp->db_fc_entry);
1528 spin_unlock_irq(&rhp->lock);
1530 ucontext = ib_qp->uobject ?
1531 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1532 destroy_qp(&rhp->rdev, &qhp->wq,
1533 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1535 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1540 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1541 struct ib_udata *udata)
1543 struct c4iw_dev *rhp;
1544 struct c4iw_qp *qhp;
1545 struct c4iw_pd *php;
1546 struct c4iw_cq *schp;
1547 struct c4iw_cq *rchp;
1548 struct c4iw_create_qp_resp uresp;
1549 unsigned int sqsize, rqsize;
1550 struct c4iw_ucontext *ucontext;
1552 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1554 PDBG("%s ib_pd %p\n", __func__, pd);
1556 if (attrs->qp_type != IB_QPT_RC)
1557 return ERR_PTR(-EINVAL);
1559 php = to_c4iw_pd(pd);
1561 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1562 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1564 return ERR_PTR(-EINVAL);
1566 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1567 return ERR_PTR(-EINVAL);
1569 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1570 if (rqsize > T4_MAX_RQ_SIZE)
1571 return ERR_PTR(-E2BIG);
1573 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1574 if (sqsize > T4_MAX_SQ_SIZE)
1575 return ERR_PTR(-E2BIG);
1577 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1579 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1581 return ERR_PTR(-ENOMEM);
1582 qhp->wq.sq.size = sqsize;
1583 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1584 qhp->wq.sq.flush_cidx = -1;
1585 qhp->wq.rq.size = rqsize;
1586 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1589 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1590 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1593 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1594 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1596 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1597 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1601 attrs->cap.max_recv_wr = rqsize - 1;
1602 attrs->cap.max_send_wr = sqsize - 1;
1603 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1606 qhp->attr.pd = php->pdid;
1607 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1608 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1609 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1610 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1611 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1612 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1613 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1614 qhp->attr.state = C4IW_QP_STATE_IDLE;
1615 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1616 qhp->attr.enable_rdma_read = 1;
1617 qhp->attr.enable_rdma_write = 1;
1618 qhp->attr.enable_bind = 1;
1619 qhp->attr.max_ord = 1;
1620 qhp->attr.max_ird = 1;
1621 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1622 spin_lock_init(&qhp->lock);
1623 mutex_init(&qhp->mutex);
1624 init_waitqueue_head(&qhp->wait);
1625 atomic_set(&qhp->refcnt, 1);
1627 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1632 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1637 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1642 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1647 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1652 if (t4_sq_onchip(&qhp->wq.sq)) {
1653 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1658 uresp.flags = C4IW_QPF_ONCHIP;
1661 uresp.qid_mask = rhp->rdev.qpmask;
1662 uresp.sqid = qhp->wq.sq.qid;
1663 uresp.sq_size = qhp->wq.sq.size;
1664 uresp.sq_memsize = qhp->wq.sq.memsize;
1665 uresp.rqid = qhp->wq.rq.qid;
1666 uresp.rq_size = qhp->wq.rq.size;
1667 uresp.rq_memsize = qhp->wq.rq.memsize;
1668 spin_lock(&ucontext->mmap_lock);
1670 uresp.ma_sync_key = ucontext->key;
1671 ucontext->key += PAGE_SIZE;
1673 uresp.ma_sync_key = 0;
1675 uresp.sq_key = ucontext->key;
1676 ucontext->key += PAGE_SIZE;
1677 uresp.rq_key = ucontext->key;
1678 ucontext->key += PAGE_SIZE;
1679 uresp.sq_db_gts_key = ucontext->key;
1680 ucontext->key += PAGE_SIZE;
1681 uresp.rq_db_gts_key = ucontext->key;
1682 ucontext->key += PAGE_SIZE;
1683 spin_unlock(&ucontext->mmap_lock);
1684 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1687 mm1->key = uresp.sq_key;
1688 mm1->addr = qhp->wq.sq.phys_addr;
1689 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1690 insert_mmap(ucontext, mm1);
1691 mm2->key = uresp.rq_key;
1692 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1693 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1694 insert_mmap(ucontext, mm2);
1695 mm3->key = uresp.sq_db_gts_key;
1696 mm3->addr = (__force unsigned long) qhp->wq.sq.udb;
1697 mm3->len = PAGE_SIZE;
1698 insert_mmap(ucontext, mm3);
1699 mm4->key = uresp.rq_db_gts_key;
1700 mm4->addr = (__force unsigned long) qhp->wq.rq.udb;
1701 mm4->len = PAGE_SIZE;
1702 insert_mmap(ucontext, mm4);
1704 mm5->key = uresp.ma_sync_key;
1705 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1706 + A_PCIE_MA_SYNC) & PAGE_MASK;
1707 mm5->len = PAGE_SIZE;
1708 insert_mmap(ucontext, mm5);
1711 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1712 init_timer(&(qhp->timer));
1713 INIT_LIST_HEAD(&qhp->db_fc_entry);
1714 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1715 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1729 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1731 destroy_qp(&rhp->rdev, &qhp->wq,
1732 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1735 return ERR_PTR(ret);
1738 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1739 int attr_mask, struct ib_udata *udata)
1741 struct c4iw_dev *rhp;
1742 struct c4iw_qp *qhp;
1743 enum c4iw_qp_attr_mask mask = 0;
1744 struct c4iw_qp_attributes attrs;
1746 PDBG("%s ib_qp %p\n", __func__, ibqp);
1748 /* iwarp does not support the RTR state */
1749 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1750 attr_mask &= ~IB_QP_STATE;
1752 /* Make sure we still have something left to do */
1756 memset(&attrs, 0, sizeof attrs);
1757 qhp = to_c4iw_qp(ibqp);
1760 attrs.next_state = c4iw_convert_state(attr->qp_state);
1761 attrs.enable_rdma_read = (attr->qp_access_flags &
1762 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1763 attrs.enable_rdma_write = (attr->qp_access_flags &
1764 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1765 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1768 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1769 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1770 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1771 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1772 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1775 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1776 * ringing the queue db when we're in DB_FULL mode.
1778 attrs.sq_db_inc = attr->sq_psn;
1779 attrs.rq_db_inc = attr->rq_psn;
1780 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1781 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1783 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1786 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1788 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1789 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1792 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1793 int attr_mask, struct ib_qp_init_attr *init_attr)
1795 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1797 memset(attr, 0, sizeof *attr);
1798 memset(init_attr, 0, sizeof *init_attr);
1799 attr->qp_state = to_ib_qp_state(qhp->attr.state);