2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6 * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #include <linux/delay.h>
39 #include <linux/gfp.h>
43 #include "c2_status.h"
45 #define C2_MAX_ORD_PER_QP 128
46 #define C2_MAX_IRD_PER_QP 128
48 #define C2_HINT_MAKE(q_index, hint_count) (((q_index) << 16) | hint_count)
49 #define C2_HINT_GET_INDEX(hint) (((hint) & 0x7FFF0000) >> 16)
50 #define C2_HINT_GET_COUNT(hint) ((hint) & 0x0000FFFF)
53 static const u8 c2_opcode[] = {
54 [IB_WR_SEND] = C2_WR_TYPE_SEND,
55 [IB_WR_SEND_WITH_IMM] = NO_SUPPORT,
56 [IB_WR_RDMA_WRITE] = C2_WR_TYPE_RDMA_WRITE,
57 [IB_WR_RDMA_WRITE_WITH_IMM] = NO_SUPPORT,
58 [IB_WR_RDMA_READ] = C2_WR_TYPE_RDMA_READ,
59 [IB_WR_ATOMIC_CMP_AND_SWP] = NO_SUPPORT,
60 [IB_WR_ATOMIC_FETCH_AND_ADD] = NO_SUPPORT,
63 static int to_c2_state(enum ib_qp_state ib_state)
67 return C2_QP_STATE_IDLE;
69 return C2_QP_STATE_RTS;
71 return C2_QP_STATE_CLOSING;
73 return C2_QP_STATE_CLOSING;
75 return C2_QP_STATE_ERROR;
81 static int to_ib_state(enum c2_qp_state c2_state)
84 case C2_QP_STATE_IDLE:
86 case C2_QP_STATE_CONNECTING:
90 case C2_QP_STATE_CLOSING:
92 case C2_QP_STATE_ERROR:
94 case C2_QP_STATE_TERMINATE:
101 static const char *to_ib_state_str(int ib_state)
103 static const char *state_str[] = {
112 if (ib_state < IB_QPS_RESET ||
113 ib_state > IB_QPS_ERR)
114 return "<invalid IB QP state>";
116 ib_state -= IB_QPS_RESET;
117 return state_str[ib_state];
120 void c2_set_qp_state(struct c2_qp *qp, int c2_state)
122 int new_state = to_ib_state(c2_state);
124 pr_debug("%s: qp[%p] state modify %s --> %s\n",
127 to_ib_state_str(qp->state),
128 to_ib_state_str(new_state));
129 qp->state = new_state;
132 #define C2_QP_NO_ATTR_CHANGE 0xFFFFFFFF
134 int c2_qp_modify(struct c2_dev *c2dev, struct c2_qp *qp,
135 struct ib_qp_attr *attr, int attr_mask)
137 struct c2wr_qp_modify_req wr;
138 struct c2wr_qp_modify_rep *reply;
139 struct c2_vq_req *vq_req;
144 pr_debug("%s:%d qp=%p, %s --> %s\n",
147 to_ib_state_str(qp->state),
148 to_ib_state_str(attr->qp_state));
150 vq_req = vq_req_alloc(c2dev);
154 c2_wr_set_id(&wr, CCWR_QP_MODIFY);
155 wr.hdr.context = (unsigned long) vq_req;
156 wr.rnic_handle = c2dev->adapter_handle;
157 wr.qp_handle = qp->adapter_handle;
158 wr.ord = cpu_to_be32(C2_QP_NO_ATTR_CHANGE);
159 wr.ird = cpu_to_be32(C2_QP_NO_ATTR_CHANGE);
160 wr.sq_depth = cpu_to_be32(C2_QP_NO_ATTR_CHANGE);
161 wr.rq_depth = cpu_to_be32(C2_QP_NO_ATTR_CHANGE);
163 if (attr_mask & IB_QP_STATE) {
164 /* Ensure the state is valid */
165 if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR) {
170 wr.next_qp_state = cpu_to_be32(to_c2_state(attr->qp_state));
172 if (attr->qp_state == IB_QPS_ERR) {
173 spin_lock_irqsave(&qp->lock, flags);
174 if (qp->cm_id && qp->state == IB_QPS_RTS) {
175 pr_debug("Generating CLOSE event for QP-->ERR, "
176 "qp=%p, cm_id=%p\n",qp,qp->cm_id);
177 /* Generate an CLOSE event */
178 vq_req->cm_id = qp->cm_id;
179 vq_req->event = IW_CM_EVENT_CLOSE;
181 spin_unlock_irqrestore(&qp->lock, flags);
183 next_state = attr->qp_state;
185 } else if (attr_mask & IB_QP_CUR_STATE) {
187 if (attr->cur_qp_state != IB_QPS_RTR &&
188 attr->cur_qp_state != IB_QPS_RTS &&
189 attr->cur_qp_state != IB_QPS_SQD &&
190 attr->cur_qp_state != IB_QPS_SQE) {
195 cpu_to_be32(to_c2_state(attr->cur_qp_state));
197 next_state = attr->cur_qp_state;
204 /* reference the request struct */
205 vq_req_get(c2dev, vq_req);
207 err = vq_send_wr(c2dev, (union c2wr *) & wr);
209 vq_req_put(c2dev, vq_req);
213 err = vq_wait_for_reply(c2dev, vq_req);
217 reply = (struct c2wr_qp_modify_rep *) (unsigned long) vq_req->reply_msg;
223 err = c2_errno(reply);
225 qp->state = next_state;
228 pr_debug("%s: c2_errno=%d\n", __func__, err);
231 * If we're going to error and generating the event here, then
232 * we need to remove the reference because there will be no
233 * close event generated by the adapter
235 spin_lock_irqsave(&qp->lock, flags);
236 if (vq_req->event==IW_CM_EVENT_CLOSE && qp->cm_id) {
237 qp->cm_id->rem_ref(qp->cm_id);
240 spin_unlock_irqrestore(&qp->lock, flags);
242 vq_repbuf_free(c2dev, reply);
244 vq_req_free(c2dev, vq_req);
246 pr_debug("%s:%d qp=%p, cur_state=%s\n",
249 to_ib_state_str(qp->state));
253 int c2_qp_set_read_limits(struct c2_dev *c2dev, struct c2_qp *qp,
256 struct c2wr_qp_modify_req wr;
257 struct c2wr_qp_modify_rep *reply;
258 struct c2_vq_req *vq_req;
261 vq_req = vq_req_alloc(c2dev);
265 c2_wr_set_id(&wr, CCWR_QP_MODIFY);
266 wr.hdr.context = (unsigned long) vq_req;
267 wr.rnic_handle = c2dev->adapter_handle;
268 wr.qp_handle = qp->adapter_handle;
269 wr.ord = cpu_to_be32(ord);
270 wr.ird = cpu_to_be32(ird);
271 wr.sq_depth = cpu_to_be32(C2_QP_NO_ATTR_CHANGE);
272 wr.rq_depth = cpu_to_be32(C2_QP_NO_ATTR_CHANGE);
273 wr.next_qp_state = cpu_to_be32(C2_QP_NO_ATTR_CHANGE);
275 /* reference the request struct */
276 vq_req_get(c2dev, vq_req);
278 err = vq_send_wr(c2dev, (union c2wr *) & wr);
280 vq_req_put(c2dev, vq_req);
284 err = vq_wait_for_reply(c2dev, vq_req);
288 reply = (struct c2wr_qp_modify_rep *) (unsigned long)
295 err = c2_errno(reply);
296 vq_repbuf_free(c2dev, reply);
298 vq_req_free(c2dev, vq_req);
302 static int destroy_qp(struct c2_dev *c2dev, struct c2_qp *qp)
304 struct c2_vq_req *vq_req;
305 struct c2wr_qp_destroy_req wr;
306 struct c2wr_qp_destroy_rep *reply;
311 * Allocate a verb request message
313 vq_req = vq_req_alloc(c2dev);
321 c2_wr_set_id(&wr, CCWR_QP_DESTROY);
322 wr.hdr.context = (unsigned long) vq_req;
323 wr.rnic_handle = c2dev->adapter_handle;
324 wr.qp_handle = qp->adapter_handle;
327 * reference the request struct. dereferenced in the int handler.
329 vq_req_get(c2dev, vq_req);
331 spin_lock_irqsave(&qp->lock, flags);
332 if (qp->cm_id && qp->state == IB_QPS_RTS) {
333 pr_debug("destroy_qp: generating CLOSE event for QP-->ERR, "
334 "qp=%p, cm_id=%p\n",qp,qp->cm_id);
335 /* Generate an CLOSE event */
337 vq_req->cm_id = qp->cm_id;
338 vq_req->event = IW_CM_EVENT_CLOSE;
340 spin_unlock_irqrestore(&qp->lock, flags);
345 err = vq_send_wr(c2dev, (union c2wr *) & wr);
347 vq_req_put(c2dev, vq_req);
352 * Wait for reply from adapter
354 err = vq_wait_for_reply(c2dev, vq_req);
362 reply = (struct c2wr_qp_destroy_rep *) (unsigned long) (vq_req->reply_msg);
368 spin_lock_irqsave(&qp->lock, flags);
370 qp->cm_id->rem_ref(qp->cm_id);
373 spin_unlock_irqrestore(&qp->lock, flags);
375 vq_repbuf_free(c2dev, reply);
377 vq_req_free(c2dev, vq_req);
381 static int c2_alloc_qpn(struct c2_dev *c2dev, struct c2_qp *qp)
386 spin_lock_irq(&c2dev->qp_table.lock);
387 ret = idr_get_new_above(&c2dev->qp_table.idr, qp,
388 c2dev->qp_table.last++, &qp->qpn);
389 spin_unlock_irq(&c2dev->qp_table.lock);
390 } while ((ret == -EAGAIN) &&
391 idr_pre_get(&c2dev->qp_table.idr, GFP_KERNEL));
395 static void c2_free_qpn(struct c2_dev *c2dev, int qpn)
397 spin_lock_irq(&c2dev->qp_table.lock);
398 idr_remove(&c2dev->qp_table.idr, qpn);
399 spin_unlock_irq(&c2dev->qp_table.lock);
402 struct c2_qp *c2_find_qpn(struct c2_dev *c2dev, int qpn)
407 spin_lock_irqsave(&c2dev->qp_table.lock, flags);
408 qp = idr_find(&c2dev->qp_table.idr, qpn);
409 spin_unlock_irqrestore(&c2dev->qp_table.lock, flags);
413 int c2_alloc_qp(struct c2_dev *c2dev,
415 struct ib_qp_init_attr *qp_attrs, struct c2_qp *qp)
417 struct c2wr_qp_create_req wr;
418 struct c2wr_qp_create_rep *reply;
419 struct c2_vq_req *vq_req;
420 struct c2_cq *send_cq = to_c2cq(qp_attrs->send_cq);
421 struct c2_cq *recv_cq = to_c2cq(qp_attrs->recv_cq);
422 unsigned long peer_pa;
423 u32 q_size, msg_size, mmap_size;
427 err = c2_alloc_qpn(c2dev, qp);
430 qp->ibqp.qp_num = qp->qpn;
431 qp->ibqp.qp_type = IB_QPT_RC;
433 /* Allocate the SQ and RQ shared pointers */
434 qp->sq_mq.shared = c2_alloc_mqsp(c2dev, c2dev->kern_mqsp_pool,
435 &qp->sq_mq.shared_dma, GFP_KERNEL);
436 if (!qp->sq_mq.shared) {
441 qp->rq_mq.shared = c2_alloc_mqsp(c2dev, c2dev->kern_mqsp_pool,
442 &qp->rq_mq.shared_dma, GFP_KERNEL);
443 if (!qp->rq_mq.shared) {
448 /* Allocate the verbs request */
449 vq_req = vq_req_alloc(c2dev);
450 if (vq_req == NULL) {
455 /* Initialize the work request */
456 memset(&wr, 0, sizeof(wr));
457 c2_wr_set_id(&wr, CCWR_QP_CREATE);
458 wr.hdr.context = (unsigned long) vq_req;
459 wr.rnic_handle = c2dev->adapter_handle;
460 wr.sq_cq_handle = send_cq->adapter_handle;
461 wr.rq_cq_handle = recv_cq->adapter_handle;
462 wr.sq_depth = cpu_to_be32(qp_attrs->cap.max_send_wr + 1);
463 wr.rq_depth = cpu_to_be32(qp_attrs->cap.max_recv_wr + 1);
465 wr.flags = cpu_to_be32(QP_RDMA_READ | QP_RDMA_WRITE | QP_MW_BIND |
466 QP_ZERO_STAG | QP_RDMA_READ_RESPONSE);
467 wr.send_sgl_depth = cpu_to_be32(qp_attrs->cap.max_send_sge);
468 wr.recv_sgl_depth = cpu_to_be32(qp_attrs->cap.max_recv_sge);
469 wr.rdma_write_sgl_depth = cpu_to_be32(qp_attrs->cap.max_send_sge);
470 wr.shared_sq_ht = cpu_to_be64(qp->sq_mq.shared_dma);
471 wr.shared_rq_ht = cpu_to_be64(qp->rq_mq.shared_dma);
472 wr.ord = cpu_to_be32(C2_MAX_ORD_PER_QP);
473 wr.ird = cpu_to_be32(C2_MAX_IRD_PER_QP);
474 wr.pd_id = pd->pd_id;
475 wr.user_context = (unsigned long) qp;
477 vq_req_get(c2dev, vq_req);
479 /* Send the WR to the adapter */
480 err = vq_send_wr(c2dev, (union c2wr *) & wr);
482 vq_req_put(c2dev, vq_req);
486 /* Wait for the verb reply */
487 err = vq_wait_for_reply(c2dev, vq_req);
492 /* Process the reply */
493 reply = (struct c2wr_qp_create_rep *) (unsigned long) (vq_req->reply_msg);
499 if ((err = c2_wr_get_result(reply)) != 0) {
503 /* Fill in the kernel QP struct */
504 atomic_set(&qp->refcount, 1);
505 qp->adapter_handle = reply->qp_handle;
506 qp->state = IB_QPS_RESET;
507 qp->send_sgl_depth = qp_attrs->cap.max_send_sge;
508 qp->rdma_write_sgl_depth = qp_attrs->cap.max_send_sge;
509 qp->recv_sgl_depth = qp_attrs->cap.max_recv_sge;
510 init_waitqueue_head(&qp->wait);
512 /* Initialize the SQ MQ */
513 q_size = be32_to_cpu(reply->sq_depth);
514 msg_size = be32_to_cpu(reply->sq_msg_size);
515 peer_pa = c2dev->pa + be32_to_cpu(reply->sq_mq_start);
516 mmap_size = PAGE_ALIGN(sizeof(struct c2_mq_shared) + msg_size * q_size);
517 mmap = ioremap_nocache(peer_pa, mmap_size);
523 c2_mq_req_init(&qp->sq_mq,
524 be32_to_cpu(reply->sq_mq_index),
527 mmap + sizeof(struct c2_mq_shared), /* pool start */
529 C2_MQ_ADAPTER_TARGET);
531 /* Initialize the RQ mq */
532 q_size = be32_to_cpu(reply->rq_depth);
533 msg_size = be32_to_cpu(reply->rq_msg_size);
534 peer_pa = c2dev->pa + be32_to_cpu(reply->rq_mq_start);
535 mmap_size = PAGE_ALIGN(sizeof(struct c2_mq_shared) + msg_size * q_size);
536 mmap = ioremap_nocache(peer_pa, mmap_size);
542 c2_mq_req_init(&qp->rq_mq,
543 be32_to_cpu(reply->rq_mq_index),
546 mmap + sizeof(struct c2_mq_shared), /* pool start */
548 C2_MQ_ADAPTER_TARGET);
550 vq_repbuf_free(c2dev, reply);
551 vq_req_free(c2dev, vq_req);
556 iounmap(qp->sq_mq.peer);
558 destroy_qp(c2dev, qp);
560 vq_repbuf_free(c2dev, reply);
562 vq_req_free(c2dev, vq_req);
564 c2_free_mqsp(qp->rq_mq.shared);
566 c2_free_mqsp(qp->sq_mq.shared);
568 c2_free_qpn(c2dev, qp->qpn);
572 static inline void c2_lock_cqs(struct c2_cq *send_cq, struct c2_cq *recv_cq)
574 if (send_cq == recv_cq)
575 spin_lock_irq(&send_cq->lock);
576 else if (send_cq > recv_cq) {
577 spin_lock_irq(&send_cq->lock);
578 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
580 spin_lock_irq(&recv_cq->lock);
581 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
585 static inline void c2_unlock_cqs(struct c2_cq *send_cq, struct c2_cq *recv_cq)
587 if (send_cq == recv_cq)
588 spin_unlock_irq(&send_cq->lock);
589 else if (send_cq > recv_cq) {
590 spin_unlock(&recv_cq->lock);
591 spin_unlock_irq(&send_cq->lock);
593 spin_unlock(&send_cq->lock);
594 spin_unlock_irq(&recv_cq->lock);
598 void c2_free_qp(struct c2_dev *c2dev, struct c2_qp *qp)
600 struct c2_cq *send_cq;
601 struct c2_cq *recv_cq;
603 send_cq = to_c2cq(qp->ibqp.send_cq);
604 recv_cq = to_c2cq(qp->ibqp.recv_cq);
607 * Lock CQs here, so that CQ polling code can do QP lookup
608 * without taking a lock.
610 c2_lock_cqs(send_cq, recv_cq);
611 c2_free_qpn(c2dev, qp->qpn);
612 c2_unlock_cqs(send_cq, recv_cq);
615 * Destroy qp in the rnic...
617 destroy_qp(c2dev, qp);
620 * Mark any unreaped CQEs as null and void.
622 c2_cq_clean(c2dev, qp, send_cq->cqn);
623 if (send_cq != recv_cq)
624 c2_cq_clean(c2dev, qp, recv_cq->cqn);
626 * Unmap the MQs and return the shared pointers
627 * to the message pool.
629 iounmap(qp->sq_mq.peer);
630 iounmap(qp->rq_mq.peer);
631 c2_free_mqsp(qp->sq_mq.shared);
632 c2_free_mqsp(qp->rq_mq.shared);
634 atomic_dec(&qp->refcount);
635 wait_event(qp->wait, !atomic_read(&qp->refcount));
642 * Move an SGL from the user's work request struct into a CCIL Work Request
643 * message, swapping to WR byte order and ensure the total length doesn't
647 * dst - ptr to CCIL Work Request message SGL memory.
648 * src - ptr to the consumers SGL memory.
656 move_sgl(struct c2_data_addr * dst, struct ib_sge *src, int count, u32 * p_len,
659 u32 tot = 0; /* running total */
660 u8 acount = 0; /* running total non-0 len sge's */
664 * If the addition of this SGE causes the
665 * total SGL length to exceed 2^32-1, then
668 * If the current total plus the next element length
669 * wraps, then it will go negative and be less than the
672 if ((tot + src->length) < tot) {
676 * Bug: 1456 (as well as 1498 & 1643)
677 * Skip over any sge's supplied with len=0
681 dst->stag = cpu_to_be32(src->lkey);
682 dst->to = cpu_to_be64(src->addr);
683 dst->length = cpu_to_be32(src->length);
693 * Bug: 1476 (as well as 1498, 1456 and 1643)
694 * Setup the SGL in the WR to make it easier for the RNIC.
695 * This way, the FW doesn't have to deal with special cases.
696 * Setting length=0 should be sufficient.
704 *actual_count = acount;
709 * Function: c2_activity (private function)
712 * Post an mq index to the host->adapter activity fifo.
715 * c2dev - ptr to c2dev structure
716 * mq_index - mq index to post
717 * shared - value most recently written to shared
724 static inline void c2_activity(struct c2_dev *c2dev, u32 mq_index, u16 shared)
727 * First read the register to see if the FIFO is full, and if so,
728 * spin until it's not. This isn't perfect -- there is no
729 * synchronization among the clients of the register, but in
730 * practice it prevents multiple CPU from hammering the bus
731 * with PCI RETRY. Note that when this does happen, the card
732 * cannot get on the bus and the card and system hang in a
733 * deadlock -- thus the need for this code. [TOT]
735 while (readl(c2dev->regs + PCI_BAR0_ADAPTER_HINT) & 0x80000000)
738 __raw_writel(C2_HINT_MAKE(mq_index, shared),
739 c2dev->regs + PCI_BAR0_ADAPTER_HINT);
743 * Function: qp_wr_post
746 * This in-line function allocates a MQ msg, then moves the host-copy of
747 * the completed WR into msg. Then it posts the message.
750 * q - ptr to user MQ.
751 * wr - ptr to host-copy of the WR.
752 * qp - ptr to user qp
753 * size - Number of bytes to post. Assumed to be divisible by 4.
760 static int qp_wr_post(struct c2_mq *q, union c2wr * wr, struct c2_qp *qp, u32 size)
764 msg = c2_mq_alloc(q);
769 ((c2wr_hdr_t *) wr)->magic = cpu_to_be32(CCWR_MAGIC);
773 * Since all header fields in the WR are the same as the
774 * CQE, set the following so the adapter need not.
776 c2_wr_set_result(wr, CCERR_PENDING);
779 * Copy the wr down to the adapter
781 memcpy((void *) msg, (void *) wr, size);
788 int c2_post_send(struct ib_qp *ibqp, struct ib_send_wr *ib_wr,
789 struct ib_send_wr **bad_wr)
791 struct c2_dev *c2dev = to_c2dev(ibqp->device);
792 struct c2_qp *qp = to_c2qp(ibqp);
794 unsigned long lock_flags;
802 if (qp->state > IB_QPS_RTS) {
810 wr.sqwr.sq_hdr.user_hdr.hdr.context = ib_wr->wr_id;
811 if (ib_wr->send_flags & IB_SEND_SIGNALED) {
812 flags |= SQ_SIGNALED;
815 switch (ib_wr->opcode) {
817 case IB_WR_SEND_WITH_INV:
818 if (ib_wr->opcode == IB_WR_SEND) {
819 if (ib_wr->send_flags & IB_SEND_SOLICITED)
820 c2_wr_set_id(&wr, C2_WR_TYPE_SEND_SE);
822 c2_wr_set_id(&wr, C2_WR_TYPE_SEND);
823 wr.sqwr.send.remote_stag = 0;
825 if (ib_wr->send_flags & IB_SEND_SOLICITED)
826 c2_wr_set_id(&wr, C2_WR_TYPE_SEND_SE_INV);
828 c2_wr_set_id(&wr, C2_WR_TYPE_SEND_INV);
829 wr.sqwr.send.remote_stag =
830 cpu_to_be32(ib_wr->ex.invalidate_rkey);
833 msg_size = sizeof(struct c2wr_send_req) +
834 sizeof(struct c2_data_addr) * ib_wr->num_sge;
835 if (ib_wr->num_sge > qp->send_sgl_depth) {
839 if (ib_wr->send_flags & IB_SEND_FENCE) {
840 flags |= SQ_READ_FENCE;
842 err = move_sgl((struct c2_data_addr *) & (wr.sqwr.send.data),
845 &tot_len, &actual_sge_count);
846 wr.sqwr.send.sge_len = cpu_to_be32(tot_len);
847 c2_wr_set_sge_count(&wr, actual_sge_count);
849 case IB_WR_RDMA_WRITE:
850 c2_wr_set_id(&wr, C2_WR_TYPE_RDMA_WRITE);
851 msg_size = sizeof(struct c2wr_rdma_write_req) +
852 (sizeof(struct c2_data_addr) * ib_wr->num_sge);
853 if (ib_wr->num_sge > qp->rdma_write_sgl_depth) {
857 if (ib_wr->send_flags & IB_SEND_FENCE) {
858 flags |= SQ_READ_FENCE;
860 wr.sqwr.rdma_write.remote_stag =
861 cpu_to_be32(ib_wr->wr.rdma.rkey);
862 wr.sqwr.rdma_write.remote_to =
863 cpu_to_be64(ib_wr->wr.rdma.remote_addr);
864 err = move_sgl((struct c2_data_addr *)
865 & (wr.sqwr.rdma_write.data),
868 &tot_len, &actual_sge_count);
869 wr.sqwr.rdma_write.sge_len = cpu_to_be32(tot_len);
870 c2_wr_set_sge_count(&wr, actual_sge_count);
872 case IB_WR_RDMA_READ:
873 c2_wr_set_id(&wr, C2_WR_TYPE_RDMA_READ);
874 msg_size = sizeof(struct c2wr_rdma_read_req);
876 /* IWarp only suppots 1 sge for RDMA reads */
877 if (ib_wr->num_sge > 1) {
883 * Move the local and remote stag/to/len into the WR.
885 wr.sqwr.rdma_read.local_stag =
886 cpu_to_be32(ib_wr->sg_list->lkey);
887 wr.sqwr.rdma_read.local_to =
888 cpu_to_be64(ib_wr->sg_list->addr);
889 wr.sqwr.rdma_read.remote_stag =
890 cpu_to_be32(ib_wr->wr.rdma.rkey);
891 wr.sqwr.rdma_read.remote_to =
892 cpu_to_be64(ib_wr->wr.rdma.remote_addr);
893 wr.sqwr.rdma_read.length =
894 cpu_to_be32(ib_wr->sg_list->length);
904 * If we had an error on the last wr build, then
905 * break out. Possible errors include bogus WR
906 * type, and a bogus SGL length...
915 c2_wr_set_flags(&wr, flags);
920 spin_lock_irqsave(&qp->lock, lock_flags);
921 err = qp_wr_post(&qp->sq_mq, &wr, qp, msg_size);
923 spin_unlock_irqrestore(&qp->lock, lock_flags);
928 * Enqueue mq index to activity FIFO.
930 c2_activity(c2dev, qp->sq_mq.index, qp->sq_mq.hint_count);
931 spin_unlock_irqrestore(&qp->lock, lock_flags);
942 int c2_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *ib_wr,
943 struct ib_recv_wr **bad_wr)
945 struct c2_dev *c2dev = to_c2dev(ibqp->device);
946 struct c2_qp *qp = to_c2qp(ibqp);
948 unsigned long lock_flags;
951 if (qp->state > IB_QPS_RTS) {
957 * Try and post each work request
963 if (ib_wr->num_sge > qp->recv_sgl_depth) {
969 * Create local host-copy of the WR
971 wr.rqwr.rq_hdr.user_hdr.hdr.context = ib_wr->wr_id;
972 c2_wr_set_id(&wr, CCWR_RECV);
973 c2_wr_set_flags(&wr, 0);
975 /* sge_count is limited to eight bits. */
976 BUG_ON(ib_wr->num_sge >= 256);
977 err = move_sgl((struct c2_data_addr *) & (wr.rqwr.data),
979 ib_wr->num_sge, &tot_len, &actual_sge_count);
980 c2_wr_set_sge_count(&wr, actual_sge_count);
983 * If we had an error on the last wr build, then
984 * break out. Possible errors include bogus WR
985 * type, and a bogus SGL length...
991 spin_lock_irqsave(&qp->lock, lock_flags);
992 err = qp_wr_post(&qp->rq_mq, &wr, qp, qp->rq_mq.msg_size);
994 spin_unlock_irqrestore(&qp->lock, lock_flags);
999 * Enqueue mq index to activity FIFO
1001 c2_activity(c2dev, qp->rq_mq.index, qp->rq_mq.hint_count);
1002 spin_unlock_irqrestore(&qp->lock, lock_flags);
1004 ib_wr = ib_wr->next;
1013 void __devinit c2_init_qp_table(struct c2_dev *c2dev)
1015 spin_lock_init(&c2dev->qp_table.lock);
1016 idr_init(&c2dev->qp_table.idr);
1019 void __devexit c2_cleanup_qp_table(struct c2_dev *c2dev)
1021 idr_destroy(&c2dev->qp_table.idr);