drivers/iio/proximity/sx9324.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2021 Google LLC.
   4  *
   5  * Driver for Semtech's SX9324 capacitive proximity/button solution.
   6  * Based on SX9324 driver and copy of datasheet at:
   7  * https://edit.wpgdadawant.com/uploads/news_file/program/2019/30184/tech_files/program_30184_suggest_other_file.pdf
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/bits.h>
  12 #include <linux/bitfield.h>
  13 #include <linux/delay.h>
  14 #include <linux/i2c.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/kernel.h>
  17 #include <linux/log2.h>
  18 #include <linux/mod_devicetable.h>
  19 #include <linux/module.h>
  20 #include <linux/pm.h>
  21 #include <linux/property.h>
  22 #include <linux/regmap.h>
  23
  24 #include <linux/iio/iio.h>
  25
  26 #include "sx_common.h"
  27
  28 /* Register definitions. */
  29 #define SX9324_REG_IRQ_SRC              SX_COMMON_REG_IRQ_SRC
  30 #define SX9324_REG_STAT0                0x01
  31 #define SX9324_REG_STAT1                0x02
  32 #define SX9324_REG_STAT2                0x03
  33 #define SX9324_REG_STAT2_COMPSTAT_MASK  GENMASK(3, 0)
  34 #define SX9324_REG_STAT3                0x04
  35 #define SX9324_REG_IRQ_MSK              0x05
  36 #define SX9324_CONVDONE_IRQ             BIT(3)
  37 #define SX9324_FAR_IRQ                  BIT(5)
  38 #define SX9324_CLOSE_IRQ                BIT(6)
  39 #define SX9324_REG_IRQ_CFG0             0x06
  40 #define SX9324_REG_IRQ_CFG1             0x07
  41 #define SX9324_REG_IRQ_CFG1_FAILCOND    0x80
  42 #define SX9324_REG_IRQ_CFG2             0x08
  43
  44 #define SX9324_REG_GNRL_CTRL0           0x10
  45 #define SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK GENMASK(4, 0)
  46 #define SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS 0x16
  47 #define SX9324_REG_GNRL_CTRL1           0x11
  48 #define SX9324_REG_GNRL_CTRL1_PHEN_MASK GENMASK(3, 0)
  49 #define SX9324_REG_GNRL_CTRL1_PAUSECTRL 0x20
  50
  51 #define SX9324_REG_I2C_ADDR             0x14
  52 #define SX9324_REG_CLK_SPRD             0x15
  53
  54 #define SX9324_REG_AFE_CTRL0            0x20
  55 #define SX9324_REG_AFE_CTRL1            0x21
  56 #define SX9324_REG_AFE_CTRL2            0x22
  57 #define SX9324_REG_AFE_CTRL3            0x23
  58 #define SX9324_REG_AFE_CTRL4            0x24
  59 #define SX9324_REG_AFE_CTRL4_FREQ_83_33HZ 0x40
  60 #define SX9324_REG_AFE_CTRL4_RESOLUTION_MASK GENMASK(2, 0)
  61 #define SX9324_REG_AFE_CTRL4_RES_100    0x04
  62 #define SX9324_REG_AFE_CTRL5            0x25
  63 #define SX9324_REG_AFE_CTRL6            0x26
  64 #define SX9324_REG_AFE_CTRL7            0x27
  65 #define SX9324_REG_AFE_PH0              0x28
  66 #define SX9324_REG_AFE_PH0_PIN_MASK(_pin) \
  67         GENMASK(2 * (_pin) + 1, 2 * (_pin))
  68
  69 #define SX9324_REG_AFE_PH1              0x29
  70 #define SX9324_REG_AFE_PH2              0x2a
  71 #define SX9324_REG_AFE_PH3              0x2b
  72 #define SX9324_REG_AFE_CTRL8            0x2c
  73 #define SX9324_REG_AFE_CTRL8_RESFILTN_4KOHM 0x02
  74 #define SX9324_REG_AFE_CTRL9            0x2d
  75 #define SX9324_REG_AFE_CTRL9_AGAIN_1    0x08
  76
  77 #define SX9324_REG_PROX_CTRL0           0x30
  78 #define SX9324_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3)
  79 #define SX9324_REG_PROX_CTRL0_GAIN_1            0x80
  80 #define SX9324_REG_PROX_CTRL0_RAWFILT_MASK      GENMASK(2, 0)
  81 #define SX9324_REG_PROX_CTRL0_RAWFILT_1P50      0x01
  82 #define SX9324_REG_PROX_CTRL1           0x31
  83 #define SX9324_REG_PROX_CTRL2           0x32
  84 #define SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K 0x20
  85 #define SX9324_REG_PROX_CTRL3           0x33
  86 #define SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES   0x40
  87 #define SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K 0x20
  88 #define SX9324_REG_PROX_CTRL4           0x34
  89 #define SX9324_REG_PROX_CTRL4_AVGNEGFILT_MASK   GENMASK(5, 3)
  90 #define SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 0x08
  91 #define SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK   GENMASK(2, 0)
  92 #define SX9324_REG_PROX_CTRL3_AVGPOS_FILT_256 0x04
  93 #define SX9324_REG_PROX_CTRL5           0x35
  94 #define SX9324_REG_PROX_CTRL5_HYST_MASK                 GENMASK(5, 4)
  95 #define SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK       GENMASK(3, 2)
  96 #define SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK         GENMASK(1, 0)
  97 #define SX9324_REG_PROX_CTRL6           0x36
  98 #define SX9324_REG_PROX_CTRL6_PROXTHRESH_32     0x08
  99 #define SX9324_REG_PROX_CTRL7           0x37
 100
 101 #define SX9324_REG_ADV_CTRL0            0x40
 102 #define SX9324_REG_ADV_CTRL1            0x41
 103 #define SX9324_REG_ADV_CTRL2            0x42
 104 #define SX9324_REG_ADV_CTRL3            0x43
 105 #define SX9324_REG_ADV_CTRL4            0x44
 106 #define SX9324_REG_ADV_CTRL5            0x45
 107 #define SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK GENMASK(3, 2)
 108 #define SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1   0x04
 109 #define SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1   0x01
 110 #define SX9324_REG_ADV_CTRL6            0x46
 111 #define SX9324_REG_ADV_CTRL7            0x47
 112 #define SX9324_REG_ADV_CTRL8            0x48
 113 #define SX9324_REG_ADV_CTRL9            0x49
 114 #define SX9324_REG_ADV_CTRL10           0x4a
 115 #define SX9324_REG_ADV_CTRL11           0x4b
 116 #define SX9324_REG_ADV_CTRL12           0x4c
 117 #define SX9324_REG_ADV_CTRL13           0x4d
 118 #define SX9324_REG_ADV_CTRL14           0x4e
 119 #define SX9324_REG_ADV_CTRL15           0x4f
 120 #define SX9324_REG_ADV_CTRL16           0x50
 121 #define SX9324_REG_ADV_CTRL17           0x51
 122 #define SX9324_REG_ADV_CTRL18           0x52
 123 #define SX9324_REG_ADV_CTRL19           0x53
 124 #define SX9324_REG_ADV_CTRL20           0x54
 125 #define SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION 0xf0
 126
 127 #define SX9324_REG_PHASE_SEL            0x60
 128
 129 #define SX9324_REG_USEFUL_MSB           0x61
 130 #define SX9324_REG_USEFUL_LSB           0x62
 131
 132 #define SX9324_REG_AVG_MSB              0x63
 133 #define SX9324_REG_AVG_LSB              0x64
 134
 135 #define SX9324_REG_DIFF_MSB             0x65
 136 #define SX9324_REG_DIFF_LSB             0x66
 137
 138 #define SX9324_REG_OFFSET_MSB           0x67
 139 #define SX9324_REG_OFFSET_LSB           0x68
 140
 141 #define SX9324_REG_SAR_MSB              0x69
 142 #define SX9324_REG_SAR_LSB              0x6a
 143
 144 #define SX9324_REG_RESET                0x9f
 145 /* Write this to REG_RESET to do a soft reset. */
 146 #define SX9324_SOFT_RESET               0xde
 147
 148 #define SX9324_REG_WHOAMI               0xfa
 149 #define   SX9324_WHOAMI_VALUE           0x23
 150
 151 #define SX9324_REG_REVISION             0xfe
 152
 153 /* 4 channels, as defined in STAT0: PH0, PH1, PH2 and PH3. */
 154 #define SX9324_NUM_CHANNELS             4
 155 /* 3 CS pins: CS0, CS1, CS2. */
 156 #define SX9324_NUM_PINS                 3
 157
 158 static const char * const sx9324_cs_pin_usage[] = { "HZ", "MI", "DS", "GD" };
 159
 160 static ssize_t sx9324_phase_configuration_show(struct iio_dev *indio_dev,
 161                                                uintptr_t private,
 162                                                const struct iio_chan_spec *chan,
 163                                                char *buf)
 164 {
 165         struct sx_common_data *data = iio_priv(indio_dev);
 166         unsigned int val;
 167         int i, ret, pin_idx;
 168         size_t len = 0;
 169
 170         ret = regmap_read(data->regmap, SX9324_REG_AFE_PH0 + chan->channel, &val);
 171         if (ret < 0)
 172                 return ret;
 173
 174         for (i = 0; i < SX9324_NUM_PINS; i++) {
 175                 pin_idx = (val & SX9324_REG_AFE_PH0_PIN_MASK(i)) >> (2 * i);
 176                 len += sysfs_emit_at(buf, len, "%s,",
 177                                      sx9324_cs_pin_usage[pin_idx]);
 178         }
 179         buf[len - 1] = '\n';
 180         return len;
 181 }
 182
 183 static const struct iio_chan_spec_ext_info sx9324_channel_ext_info[] = {
 184         {
 185                 .name = "setup",
 186                 .shared = IIO_SEPARATE,
 187                 .read = sx9324_phase_configuration_show,
 188         },
 189         {}
 190 };
 191
 192 #define SX9324_CHANNEL(idx)                                      \
 193 {                                                                \
 194         .type = IIO_PROXIMITY,                                   \
 195         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |           \
 196                               BIT(IIO_CHAN_INFO_HARDWAREGAIN),   \
 197         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
 198         .info_mask_separate_available =                          \
 199                 BIT(IIO_CHAN_INFO_HARDWAREGAIN),                 \
 200         .info_mask_shared_by_all_available =                     \
 201                 BIT(IIO_CHAN_INFO_SAMP_FREQ),                    \
 202         .indexed = 1,                                            \
 203         .channel = idx,                                          \
 204         .address = SX9324_REG_DIFF_MSB,                          \
 205         .event_spec = sx_common_events,                          \
 206         .num_event_specs = ARRAY_SIZE(sx_common_events),         \
 207         .scan_index = idx,                                       \
 208         .scan_type = {                                           \
 209                 .sign = 's',                                     \
 210                 .realbits = 12,                                  \
 211                 .storagebits = 16,                               \
 212                 .endianness = IIO_BE,                            \
 213         },                                                       \
 214         .ext_info = sx9324_channel_ext_info,                     \
 215 }
 216
 217 static const struct iio_chan_spec sx9324_channels[] = {
 218         SX9324_CHANNEL(0),                      /* Phase 0 */
 219         SX9324_CHANNEL(1),                      /* Phase 1 */
 220         SX9324_CHANNEL(2),                      /* Phase 2 */
 221         SX9324_CHANNEL(3),                      /* Phase 3 */
 222         IIO_CHAN_SOFT_TIMESTAMP(4),
 223 };
 224
 225 /*
 226  * Each entry contains the integer part (val) and the fractional part, in micro
 227  * seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO.
 228  */
 229 static const struct {
 230         int val;
 231         int val2;
 232 } sx9324_samp_freq_table[] = {
 233         { 1000, 0 },  /* 00000: Min (no idle time) */
 234         { 500, 0 },  /* 00001: 2 ms */
 235         { 250, 0 },  /* 00010: 4 ms */
 236         { 166, 666666 },  /* 00011: 6 ms */
 237         { 125, 0 },  /* 00100: 8 ms */
 238         { 100, 0 },  /* 00101: 10 ms */
 239         { 71, 428571 },  /* 00110: 14 ms */
 240         { 55, 555556 },  /* 00111: 18 ms */
 241         { 45, 454545 },  /* 01000: 22 ms */
 242         { 38, 461538 },  /* 01001: 26 ms */
 243         { 33, 333333 },  /* 01010: 30 ms */
 244         { 29, 411765 },  /* 01011: 34 ms */
 245         { 26, 315789 },  /* 01100: 38 ms */
 246         { 23, 809524 },  /* 01101: 42 ms */
 247         { 21, 739130 },  /* 01110: 46 ms */
 248         { 20, 0 },  /* 01111: 50 ms */
 249         { 17, 857143 },  /* 10000: 56 ms */
 250         { 16, 129032 },  /* 10001: 62 ms */
 251         { 14, 705882 },  /* 10010: 68 ms */
 252         { 13, 513514 },  /* 10011: 74 ms */
 253         { 12, 500000 },  /* 10100: 80 ms */
 254         { 11, 111111 },  /* 10101: 90 ms */
 255         { 10, 0 },  /* 10110: 100 ms (Typ.) */
 256         { 5, 0 },  /* 10111: 200 ms */
 257         { 3, 333333 },  /* 11000: 300 ms */
 258         { 2, 500000 },  /* 11001: 400 ms */
 259         { 1, 666667 },  /* 11010: 600 ms */
 260         { 1, 250000 },  /* 11011: 800 ms */
 261         { 1, 0 },  /* 11100: 1 s */
 262         { 0, 500000 },  /* 11101: 2 s */
 263         { 0, 333333 },  /* 11110: 3 s */
 264         { 0, 250000 },  /* 11111: 4 s */
 265 };
 266
 267 static const unsigned int sx9324_scan_period_table[] = {
 268         2,   15,  30,  45,   60,   90,   120,  200,
 269         400, 600, 800, 1000, 2000, 3000, 4000, 5000,
 270 };
 271
 272 static const struct regmap_range sx9324_writable_reg_ranges[] = {
 273         /*
 274          * To set COMPSTAT for compensation, even if datasheet says register is
 275          * RO.
 276          */
 277         regmap_reg_range(SX9324_REG_STAT2, SX9324_REG_STAT2),
 278         regmap_reg_range(SX9324_REG_IRQ_MSK, SX9324_REG_IRQ_CFG2),
 279         regmap_reg_range(SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL1),
 280         /* Leave i2c and clock spreading as unavailable */
 281         regmap_reg_range(SX9324_REG_AFE_CTRL0, SX9324_REG_AFE_CTRL9),
 282         regmap_reg_range(SX9324_REG_PROX_CTRL0, SX9324_REG_PROX_CTRL7),
 283         regmap_reg_range(SX9324_REG_ADV_CTRL0, SX9324_REG_ADV_CTRL20),
 284         regmap_reg_range(SX9324_REG_PHASE_SEL, SX9324_REG_PHASE_SEL),
 285         regmap_reg_range(SX9324_REG_OFFSET_MSB, SX9324_REG_OFFSET_LSB),
 286         regmap_reg_range(SX9324_REG_RESET, SX9324_REG_RESET),
 287 };
 288
 289 static const struct regmap_access_table sx9324_writeable_regs = {
 290         .yes_ranges = sx9324_writable_reg_ranges,
 291         .n_yes_ranges = ARRAY_SIZE(sx9324_writable_reg_ranges),
 292 };
 293
 294 /*
 295  * All allocated registers are readable, so we just list unallocated
 296  * ones.
 297  */
 298 static const struct regmap_range sx9324_non_readable_reg_ranges[] = {
 299         regmap_reg_range(SX9324_REG_IRQ_CFG2 + 1, SX9324_REG_GNRL_CTRL0 - 1),
 300         regmap_reg_range(SX9324_REG_GNRL_CTRL1 + 1, SX9324_REG_AFE_CTRL0 - 1),
 301         regmap_reg_range(SX9324_REG_AFE_CTRL9 + 1, SX9324_REG_PROX_CTRL0 - 1),
 302         regmap_reg_range(SX9324_REG_PROX_CTRL7 + 1, SX9324_REG_ADV_CTRL0 - 1),
 303         regmap_reg_range(SX9324_REG_ADV_CTRL20 + 1, SX9324_REG_PHASE_SEL - 1),
 304         regmap_reg_range(SX9324_REG_SAR_LSB + 1, SX9324_REG_RESET - 1),
 305         regmap_reg_range(SX9324_REG_RESET + 1, SX9324_REG_WHOAMI - 1),
 306         regmap_reg_range(SX9324_REG_WHOAMI + 1, SX9324_REG_REVISION - 1),
 307 };
 308
 309 static const struct regmap_access_table sx9324_readable_regs = {
 310         .no_ranges = sx9324_non_readable_reg_ranges,
 311         .n_no_ranges = ARRAY_SIZE(sx9324_non_readable_reg_ranges),
 312 };
 313
 314 static const struct regmap_range sx9324_volatile_reg_ranges[] = {
 315         regmap_reg_range(SX9324_REG_IRQ_SRC, SX9324_REG_STAT3),
 316         regmap_reg_range(SX9324_REG_USEFUL_MSB, SX9324_REG_DIFF_LSB),
 317         regmap_reg_range(SX9324_REG_SAR_MSB, SX9324_REG_SAR_LSB),
 318         regmap_reg_range(SX9324_REG_WHOAMI, SX9324_REG_WHOAMI),
 319         regmap_reg_range(SX9324_REG_REVISION, SX9324_REG_REVISION),
 320 };
 321
 322 static const struct regmap_access_table sx9324_volatile_regs = {
 323         .yes_ranges = sx9324_volatile_reg_ranges,
 324         .n_yes_ranges = ARRAY_SIZE(sx9324_volatile_reg_ranges),
 325 };
 326
 327 static const struct regmap_config sx9324_regmap_config = {
 328         .reg_bits = 8,
 329         .val_bits = 8,
 330
 331         .max_register = SX9324_REG_REVISION,
 332         .cache_type = REGCACHE_RBTREE,
 333
 334         .wr_table = &sx9324_writeable_regs,
 335         .rd_table = &sx9324_readable_regs,
 336         .volatile_table = &sx9324_volatile_regs,
 337 };
 338
 339 static int sx9324_read_prox_data(struct sx_common_data *data,
 340                                  const struct iio_chan_spec *chan,
 341                                  __be16 *val)
 342 {
 343         int ret;
 344
 345         ret = regmap_write(data->regmap, SX9324_REG_PHASE_SEL, chan->channel);
 346         if (ret < 0)
 347                 return ret;
 348
 349         return regmap_bulk_read(data->regmap, chan->address, val, sizeof(*val));
 350 }
 351
 352 /*
 353  * If we have no interrupt support, we have to wait for a scan period
 354  * after enabling a channel to get a result.
 355  */
 356 static int sx9324_wait_for_sample(struct sx_common_data *data)
 357 {
 358         int ret;
 359         unsigned int val;
 360
 361         ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL0, &val);
 362         if (ret < 0)
 363                 return ret;
 364         val = FIELD_GET(SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, val);
 365
 366         msleep(sx9324_scan_period_table[val]);
 367
 368         return 0;
 369 }
 370
 371 static int sx9324_read_gain(struct sx_common_data *data,
 372                             const struct iio_chan_spec *chan, int *val)
 373 {
 374         unsigned int reg, regval;
 375         int ret;
 376
 377         reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2;
 378         ret = regmap_read(data->regmap, reg, &regval);
 379         if (ret)
 380                 return ret;
 381
 382         *val = 1 << FIELD_GET(SX9324_REG_PROX_CTRL0_GAIN_MASK, regval);
 383
 384         return IIO_VAL_INT;
 385 }
 386
 387 static int sx9324_read_samp_freq(struct sx_common_data *data,
 388                                  int *val, int *val2)
 389 {
 390         int ret;
 391         unsigned int regval;
 392
 393         ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL0, &regval);
 394         if (ret)
 395                 return ret;
 396
 397         regval = FIELD_GET(SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, regval);
 398         *val = sx9324_samp_freq_table[regval].val;
 399         *val2 = sx9324_samp_freq_table[regval].val2;
 400
 401         return IIO_VAL_INT_PLUS_MICRO;
 402 }
 403
 404 static int sx9324_read_raw(struct iio_dev *indio_dev,
 405                            const struct iio_chan_spec *chan,
 406                            int *val, int *val2, long mask)
 407 {
 408         struct sx_common_data *data = iio_priv(indio_dev);
 409         int ret;
 410
 411         switch (mask) {
 412         case IIO_CHAN_INFO_RAW:
 413                 ret = iio_device_claim_direct_mode(indio_dev);
 414                 if (ret)
 415                         return ret;
 416
 417                 ret = sx_common_read_proximity(data, chan, val);
 418                 iio_device_release_direct_mode(indio_dev);
 419                 return ret;
 420         case IIO_CHAN_INFO_HARDWAREGAIN:
 421                 ret = iio_device_claim_direct_mode(indio_dev);
 422                 if (ret)
 423                         return ret;
 424
 425                 ret = sx9324_read_gain(data, chan, val);
 426                 iio_device_release_direct_mode(indio_dev);
 427                 return ret;
 428         case IIO_CHAN_INFO_SAMP_FREQ:
 429                 return sx9324_read_samp_freq(data, val, val2);
 430         default:
 431                 return -EINVAL;
 432         }
 433 }
 434
 435 static const int sx9324_gain_vals[] = { 1, 2, 4, 8 };
 436
 437 static int sx9324_read_avail(struct iio_dev *indio_dev,
 438                              struct iio_chan_spec const *chan,
 439                              const int **vals, int *type, int *length,
 440                              long mask)
 441 {
 442         if (chan->type != IIO_PROXIMITY)
 443                 return -EINVAL;
 444
 445         switch (mask) {
 446         case IIO_CHAN_INFO_HARDWAREGAIN:
 447                 *type = IIO_VAL_INT;
 448                 *length = ARRAY_SIZE(sx9324_gain_vals);
 449                 *vals = sx9324_gain_vals;
 450                 return IIO_AVAIL_LIST;
 451         case IIO_CHAN_INFO_SAMP_FREQ:
 452                 *type = IIO_VAL_INT_PLUS_MICRO;
 453                 *length = ARRAY_SIZE(sx9324_samp_freq_table) * 2;
 454                 *vals = (int *)sx9324_samp_freq_table;
 455                 return IIO_AVAIL_LIST;
 456         default:
 457                 return -EINVAL;
 458         }
 459 }
 460
 461 static int sx9324_set_samp_freq(struct sx_common_data *data,
 462                                 int val, int val2)
 463 {
 464         int i, ret;
 465
 466         for (i = 0; i < ARRAY_SIZE(sx9324_samp_freq_table); i++)
 467                 if (val == sx9324_samp_freq_table[i].val &&
 468                     val2 == sx9324_samp_freq_table[i].val2)
 469                         break;
 470
 471         if (i == ARRAY_SIZE(sx9324_samp_freq_table))
 472                 return -EINVAL;
 473
 474         mutex_lock(&data->mutex);
 475
 476         ret = regmap_update_bits(data->regmap,
 477                                  SX9324_REG_GNRL_CTRL0,
 478                                  SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, i);
 479
 480         mutex_unlock(&data->mutex);
 481
 482         return ret;
 483 }
 484
 485 static int sx9324_read_thresh(struct sx_common_data *data,
 486                               const struct iio_chan_spec *chan, int *val)
 487 {
 488         unsigned int regval;
 489         unsigned int reg;
 490         int ret;
 491
 492         /*
 493          * TODO(gwendal): Depending on the phase function
 494          * (proximity/table/body), retrieve the right threshold.
 495          * For now, return the proximity threshold.
 496          */
 497         reg = SX9324_REG_PROX_CTRL6 + chan->channel / 2;
 498         ret = regmap_read(data->regmap, reg, &regval);
 499         if (ret)
 500                 return ret;
 501
 502         if (regval <= 1)
 503                 *val = regval;
 504         else
 505                 *val = (regval * regval) / 2;
 506
 507         return IIO_VAL_INT;
 508 }
 509
 510 static int sx9324_read_hysteresis(struct sx_common_data *data,
 511                                   const struct iio_chan_spec *chan, int *val)
 512 {
 513         unsigned int regval, pthresh;
 514         int ret;
 515
 516         ret = sx9324_read_thresh(data, chan, &pthresh);
 517         if (ret < 0)
 518                 return ret;
 519
 520         ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, &regval);
 521         if (ret)
 522                 return ret;
 523
 524         regval = FIELD_GET(SX9324_REG_PROX_CTRL5_HYST_MASK, regval);
 525         if (!regval)
 526                 *val = 0;
 527         else
 528                 *val = pthresh >> (5 - regval);
 529
 530         return IIO_VAL_INT;
 531 }
 532
 533 static int sx9324_read_far_debounce(struct sx_common_data *data, int *val)
 534 {
 535         unsigned int regval;
 536         int ret;
 537
 538         ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, &regval);
 539         if (ret)
 540                 return ret;
 541
 542         regval = FIELD_GET(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, regval);
 543         if (regval)
 544                 *val = 1 << regval;
 545         else
 546                 *val = 0;
 547
 548         return IIO_VAL_INT;
 549 }
 550
 551 static int sx9324_read_close_debounce(struct sx_common_data *data, int *val)
 552 {
 553         unsigned int regval;
 554         int ret;
 555
 556         ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, &regval);
 557         if (ret)
 558                 return ret;
 559
 560         regval = FIELD_GET(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, regval);
 561         if (regval)
 562                 *val = 1 << regval;
 563         else
 564                 *val = 0;
 565
 566         return IIO_VAL_INT;
 567 }
 568
 569 static int sx9324_read_event_val(struct iio_dev *indio_dev,
 570                                  const struct iio_chan_spec *chan,
 571                                  enum iio_event_type type,
 572                                  enum iio_event_direction dir,
 573                                  enum iio_event_info info, int *val, int *val2)
 574 {
 575         struct sx_common_data *data = iio_priv(indio_dev);
 576
 577         if (chan->type != IIO_PROXIMITY)
 578                 return -EINVAL;
 579
 580         switch (info) {
 581         case IIO_EV_INFO_VALUE:
 582                 return sx9324_read_thresh(data, chan, val);
 583         case IIO_EV_INFO_PERIOD:
 584                 switch (dir) {
 585                 case IIO_EV_DIR_RISING:
 586                         return sx9324_read_far_debounce(data, val);
 587                 case IIO_EV_DIR_FALLING:
 588                         return sx9324_read_close_debounce(data, val);
 589                 default:
 590                         return -EINVAL;
 591                 }
 592         case IIO_EV_INFO_HYSTERESIS:
 593                 return sx9324_read_hysteresis(data, chan, val);
 594         default:
 595                 return -EINVAL;
 596         }
 597 }
 598
 599 static int sx9324_write_thresh(struct sx_common_data *data,
 600                                const struct iio_chan_spec *chan, int _val)
 601 {
 602         unsigned int reg, val = _val;
 603         int ret;
 604
 605         reg = SX9324_REG_PROX_CTRL6 + chan->channel / 2;
 606
 607         if (val >= 1)
 608                 val = int_sqrt(2 * val);
 609
 610         if (val > 0xff)
 611                 return -EINVAL;
 612
 613         mutex_lock(&data->mutex);
 614         ret = regmap_write(data->regmap, reg, val);
 615         mutex_unlock(&data->mutex);
 616
 617         return ret;
 618 }
 619
 620 static int sx9324_write_hysteresis(struct sx_common_data *data,
 621                                    const struct iio_chan_spec *chan, int _val)
 622 {
 623         unsigned int hyst, val = _val;
 624         int ret, pthresh;
 625
 626         ret = sx9324_read_thresh(data, chan, &pthresh);
 627         if (ret < 0)
 628                 return ret;
 629
 630         if (val == 0)
 631                 hyst = 0;
 632         else if (val >= pthresh >> 2)
 633                 hyst = 3;
 634         else if (val >= pthresh >> 3)
 635                 hyst = 2;
 636         else if (val >= pthresh >> 4)
 637                 hyst = 1;
 638         else
 639                 return -EINVAL;
 640
 641         hyst = FIELD_PREP(SX9324_REG_PROX_CTRL5_HYST_MASK, hyst);
 642         mutex_lock(&data->mutex);
 643         ret = regmap_update_bits(data->regmap, SX9324_REG_PROX_CTRL5,
 644                                  SX9324_REG_PROX_CTRL5_HYST_MASK, hyst);
 645         mutex_unlock(&data->mutex);
 646
 647         return ret;
 648 }
 649
 650 static int sx9324_write_far_debounce(struct sx_common_data *data, int _val)
 651 {
 652         unsigned int regval, val = _val;
 653         int ret;
 654
 655         if (val > 0)
 656                 val = ilog2(val);
 657         if (!FIELD_FIT(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, val))
 658                 return -EINVAL;
 659
 660         regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, val);
 661
 662         mutex_lock(&data->mutex);
 663         ret = regmap_update_bits(data->regmap, SX9324_REG_PROX_CTRL5,
 664                                  SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK,
 665                                  regval);
 666         mutex_unlock(&data->mutex);
 667
 668         return ret;
 669 }
 670
 671 static int sx9324_write_close_debounce(struct sx_common_data *data, int _val)
 672 {
 673         unsigned int regval, val = _val;
 674         int ret;
 675
 676         if (val > 0)
 677                 val = ilog2(val);
 678         if (!FIELD_FIT(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, val))
 679                 return -EINVAL;
 680
 681         regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, val);
 682
 683         mutex_lock(&data->mutex);
 684         ret = regmap_update_bits(data->regmap, SX9324_REG_PROX_CTRL5,
 685                                  SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK,
 686                                  regval);
 687         mutex_unlock(&data->mutex);
 688
 689         return ret;
 690 }
 691
 692 static int sx9324_write_event_val(struct iio_dev *indio_dev,
 693                                   const struct iio_chan_spec *chan,
 694                                   enum iio_event_type type,
 695                                   enum iio_event_direction dir,
 696                                   enum iio_event_info info, int val, int val2)
 697 {
 698         struct sx_common_data *data = iio_priv(indio_dev);
 699
 700         if (chan->type != IIO_PROXIMITY)
 701                 return -EINVAL;
 702
 703         switch (info) {
 704         case IIO_EV_INFO_VALUE:
 705                 return sx9324_write_thresh(data, chan, val);
 706         case IIO_EV_INFO_PERIOD:
 707                 switch (dir) {
 708                 case IIO_EV_DIR_RISING:
 709                         return sx9324_write_far_debounce(data, val);
 710                 case IIO_EV_DIR_FALLING:
 711                         return sx9324_write_close_debounce(data, val);
 712                 default:
 713                         return -EINVAL;
 714                 }
 715         case IIO_EV_INFO_HYSTERESIS:
 716                 return sx9324_write_hysteresis(data, chan, val);
 717         default:
 718                 return -EINVAL;
 719         }
 720 }
 721
 722 static int sx9324_write_gain(struct sx_common_data *data,
 723                              const struct iio_chan_spec *chan, int val)
 724 {
 725         unsigned int gain, reg;
 726         int ret;
 727
 728         gain = ilog2(val);
 729         reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2;
 730         gain = FIELD_PREP(SX9324_REG_PROX_CTRL0_GAIN_MASK, gain);
 731
 732         mutex_lock(&data->mutex);
 733         ret = regmap_update_bits(data->regmap, reg,
 734                                  SX9324_REG_PROX_CTRL0_GAIN_MASK,
 735                                  gain);
 736         mutex_unlock(&data->mutex);
 737
 738         return ret;
 739 }
 740
 741 static int sx9324_write_raw(struct iio_dev *indio_dev,
 742                             const struct iio_chan_spec *chan, int val, int val2,
 743                             long mask)
 744 {
 745         struct sx_common_data *data = iio_priv(indio_dev);
 746
 747         switch (mask) {
 748         case IIO_CHAN_INFO_SAMP_FREQ:
 749                 return sx9324_set_samp_freq(data, val, val2);
 750         case IIO_CHAN_INFO_HARDWAREGAIN:
 751                 return sx9324_write_gain(data, chan, val);
 752         default:
 753                 return -EINVAL;
 754         }
 755 }
 756
 757 static const struct sx_common_reg_default sx9324_default_regs[] = {
 758         { SX9324_REG_IRQ_MSK, 0x00 },
 759         { SX9324_REG_IRQ_CFG0, 0x00 },
 760         { SX9324_REG_IRQ_CFG1, SX9324_REG_IRQ_CFG1_FAILCOND },
 761         { SX9324_REG_IRQ_CFG2, 0x00 },
 762         { SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS },
 763         /*
 764          * The lower 4 bits should not be set as it enable sensors measurements.
 765          * Turning the detection on before the configuration values are set to
 766          * good values can cause the device to return erroneous readings.
 767          */
 768         { SX9324_REG_GNRL_CTRL1, SX9324_REG_GNRL_CTRL1_PAUSECTRL },
 769
 770         { SX9324_REG_AFE_CTRL0, 0x00 },
 771         { SX9324_REG_AFE_CTRL3, 0x00 },
 772         { SX9324_REG_AFE_CTRL4, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ |
 773                 SX9324_REG_AFE_CTRL4_RES_100 },
 774         { SX9324_REG_AFE_CTRL6, 0x00 },
 775         { SX9324_REG_AFE_CTRL7, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ |
 776                 SX9324_REG_AFE_CTRL4_RES_100 },
 777
 778         /* TODO(gwendal): PHx use chip default or all grounded? */
 779         { SX9324_REG_AFE_PH0, 0x29 },
 780         { SX9324_REG_AFE_PH1, 0x26 },
 781         { SX9324_REG_AFE_PH2, 0x1a },
 782         { SX9324_REG_AFE_PH3, 0x16 },
 783
 784         { SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESFILTN_4KOHM },
 785         { SX9324_REG_AFE_CTRL9, SX9324_REG_AFE_CTRL9_AGAIN_1 },
 786
 787         { SX9324_REG_PROX_CTRL0, SX9324_REG_PROX_CTRL0_GAIN_1 |
 788                 SX9324_REG_PROX_CTRL0_RAWFILT_1P50 },
 789         { SX9324_REG_PROX_CTRL1, SX9324_REG_PROX_CTRL0_GAIN_1 |
 790                 SX9324_REG_PROX_CTRL0_RAWFILT_1P50 },
 791         { SX9324_REG_PROX_CTRL2, SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K },
 792         { SX9324_REG_PROX_CTRL3, SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES |
 793                 SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K },
 794         { SX9324_REG_PROX_CTRL4, SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 |
 795                 SX9324_REG_PROX_CTRL3_AVGPOS_FILT_256 },
 796         { SX9324_REG_PROX_CTRL5, 0x00 },
 797         { SX9324_REG_PROX_CTRL6, SX9324_REG_PROX_CTRL6_PROXTHRESH_32 },
 798         { SX9324_REG_PROX_CTRL7, SX9324_REG_PROX_CTRL6_PROXTHRESH_32 },
 799         { SX9324_REG_ADV_CTRL0, 0x00 },
 800         { SX9324_REG_ADV_CTRL1, 0x00 },
 801         { SX9324_REG_ADV_CTRL2, 0x00 },
 802         { SX9324_REG_ADV_CTRL3, 0x00 },
 803         { SX9324_REG_ADV_CTRL4, 0x00 },
 804         { SX9324_REG_ADV_CTRL5, SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1 |
 805                 SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1 },
 806         { SX9324_REG_ADV_CTRL6, 0x00 },
 807         { SX9324_REG_ADV_CTRL7, 0x00 },
 808         { SX9324_REG_ADV_CTRL8, 0x00 },
 809         { SX9324_REG_ADV_CTRL9, 0x00 },
 810         /* Body/Table threshold */
 811         { SX9324_REG_ADV_CTRL10, 0x00 },
 812         { SX9324_REG_ADV_CTRL11, 0x00 },
 813         { SX9324_REG_ADV_CTRL12, 0x00 },
 814         /* TODO(gwendal): SAR currenly disabled */
 815         { SX9324_REG_ADV_CTRL13, 0x00 },
 816         { SX9324_REG_ADV_CTRL14, 0x00 },
 817         { SX9324_REG_ADV_CTRL15, 0x00 },
 818         { SX9324_REG_ADV_CTRL16, 0x00 },
 819         { SX9324_REG_ADV_CTRL17, 0x00 },
 820         { SX9324_REG_ADV_CTRL18, 0x00 },
 821         { SX9324_REG_ADV_CTRL19, SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION },
 822         { SX9324_REG_ADV_CTRL20, SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION },
 823 };
 824
 825 /* Activate all channels and perform an initial compensation. */
 826 static int sx9324_init_compensation(struct iio_dev *indio_dev)
 827 {
 828         struct sx_common_data *data = iio_priv(indio_dev);
 829         unsigned int val;
 830         int ret;
 831
 832         /* run the compensation phase on all channels */
 833         ret = regmap_update_bits(data->regmap, SX9324_REG_STAT2,
 834                                  SX9324_REG_STAT2_COMPSTAT_MASK,
 835                                  SX9324_REG_STAT2_COMPSTAT_MASK);
 836         if (ret)
 837                 return ret;
 838
 839         return regmap_read_poll_timeout(data->regmap, SX9324_REG_STAT2, val,
 840                                         !(val & SX9324_REG_STAT2_COMPSTAT_MASK),
 841                                         20000, 2000000);
 842 }
 843
 844 static const struct sx_common_reg_default *
 845 sx9324_get_default_reg(struct device *dev, int idx,
 846                        struct sx_common_reg_default *reg_def)
 847 {
 848 #define SX9324_PIN_DEF "semtech,ph0-pin"
 849 #define SX9324_RESOLUTION_DEF "semtech,ph01-resolution"
 850 #define SX9324_PROXRAW_DEF "semtech,ph01-proxraw-strength"
 851         unsigned int pin_defs[SX9324_NUM_PINS];
 852         char prop[] = SX9324_PROXRAW_DEF;
 853         u32 start = 0, raw = 0, pos = 0;
 854         int ret, count, ph, pin;
 855
 856         memcpy(reg_def, &sx9324_default_regs[idx], sizeof(*reg_def));
 857         switch (reg_def->reg) {
 858         case SX9324_REG_AFE_PH0:
 859         case SX9324_REG_AFE_PH1:
 860         case SX9324_REG_AFE_PH2:
 861         case SX9324_REG_AFE_PH3:
 862                 ph = reg_def->reg - SX9324_REG_AFE_PH0;
 863                 scnprintf(prop, ARRAY_SIZE(prop), "semtech,ph%d-pin", ph);
 864
 865                 count = device_property_count_u32(dev, prop);
 866                 if (count != ARRAY_SIZE(pin_defs))
 867                         break;
 868                 ret = device_property_read_u32_array(dev, prop, pin_defs,
 869                                                      ARRAY_SIZE(pin_defs));
 870                 for (pin = 0; pin < SX9324_NUM_PINS; pin++)
 871                         raw |= (pin_defs[pin] << (2 * pin)) &
 872                                SX9324_REG_AFE_PH0_PIN_MASK(pin);
 873                 reg_def->def = raw;
 874                 break;
 875         case SX9324_REG_AFE_CTRL4:
 876         case SX9324_REG_AFE_CTRL7:
 877                 if (reg_def->reg == SX9324_REG_AFE_CTRL4)
 878                         strncpy(prop, "semtech,ph01-resolution",
 879                                 ARRAY_SIZE(prop));
 880                 else
 881                         strncpy(prop, "semtech,ph23-resolution",
 882                                 ARRAY_SIZE(prop));
 883
 884                 ret = device_property_read_u32(dev, prop, &raw);
 885                 if (ret)
 886                         break;
 887
 888                 raw = ilog2(raw) - 3;
 889
 890                 reg_def->def &= ~SX9324_REG_AFE_CTRL4_RESOLUTION_MASK;
 891                 reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL4_RESOLUTION_MASK,
 892                                            raw);
 893                 break;
 894         case SX9324_REG_ADV_CTRL5:
 895                 ret = device_property_read_u32(dev, "semtech,startup-sensor",
 896                                                &start);
 897                 if (ret)
 898                         break;
 899
 900                 reg_def->def &= ~SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK;
 901                 reg_def->def |= FIELD_PREP(SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK,
 902                                            start);
 903                 break;
 904         case SX9324_REG_PROX_CTRL4:
 905                 ret = device_property_read_u32(dev, "semtech,avg-pos-strength",
 906                                                &pos);
 907                 if (ret)
 908                         break;
 909
 910                 /* Powers of 2, except for a gap between 16 and 64 */
 911                 raw = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3);
 912
 913                 reg_def->def &= ~SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK;
 914                 reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK,
 915                                            raw);
 916                 break;
 917         case SX9324_REG_PROX_CTRL0:
 918         case SX9324_REG_PROX_CTRL1:
 919                 if (reg_def->reg == SX9324_REG_PROX_CTRL0)
 920                         strncpy(prop, "semtech,ph01-proxraw-strength",
 921                                 ARRAY_SIZE(prop));
 922                 else
 923                         strncpy(prop, "semtech,ph23-proxraw-strength",
 924                                 ARRAY_SIZE(prop));
 925                 ret = device_property_read_u32(dev, prop, &raw);
 926                 if (ret)
 927                         break;
 928
 929                 reg_def->def &= ~SX9324_REG_PROX_CTRL0_RAWFILT_MASK;
 930                 reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL0_RAWFILT_MASK,
 931                                            raw);
 932                 break;
 933         }
 934         return reg_def;
 935 }
 936
 937 static int sx9324_check_whoami(struct device *dev,
 938                                struct iio_dev *indio_dev)
 939 {
 940         /*
 941          * Only one sensor for this driver. Assuming the device tree
 942          * is correct, just set the sensor name.
 943          */
 944         indio_dev->name = "sx9324";
 945         return 0;
 946 }
 947
 948 static const struct sx_common_chip_info sx9324_chip_info = {
 949         .reg_stat = SX9324_REG_STAT0,
 950         .reg_irq_msk = SX9324_REG_IRQ_MSK,
 951         .reg_enable_chan = SX9324_REG_GNRL_CTRL1,
 952         .reg_reset = SX9324_REG_RESET,
 953
 954         .mask_enable_chan = SX9324_REG_GNRL_CTRL1_PHEN_MASK,
 955         .irq_msk_offset = 3,
 956         .num_channels = SX9324_NUM_CHANNELS,
 957         .num_default_regs = ARRAY_SIZE(sx9324_default_regs),
 958
 959         .ops = {
 960                 .read_prox_data = sx9324_read_prox_data,
 961                 .check_whoami = sx9324_check_whoami,
 962                 .init_compensation = sx9324_init_compensation,
 963                 .wait_for_sample = sx9324_wait_for_sample,
 964                 .get_default_reg = sx9324_get_default_reg,
 965         },
 966
 967         .iio_channels = sx9324_channels,
 968         .num_iio_channels = ARRAY_SIZE(sx9324_channels),
 969         .iio_info =  {
 970                 .read_raw = sx9324_read_raw,
 971                 .read_avail = sx9324_read_avail,
 972                 .read_event_value = sx9324_read_event_val,
 973                 .write_event_value = sx9324_write_event_val,
 974                 .write_raw = sx9324_write_raw,
 975                 .read_event_config = sx_common_read_event_config,
 976                 .write_event_config = sx_common_write_event_config,
 977         },
 978 };
 979
 980 static int sx9324_probe(struct i2c_client *client)
 981 {
 982         return sx_common_probe(client, &sx9324_chip_info, &sx9324_regmap_config);
 983 }
 984
 985 static int __maybe_unused sx9324_suspend(struct device *dev)
 986 {
 987         struct sx_common_data *data = iio_priv(dev_get_drvdata(dev));
 988         unsigned int regval;
 989         int ret;
 990
 991         disable_irq_nosync(data->client->irq);
 992
 993         mutex_lock(&data->mutex);
 994         ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL1, &regval);
 995
 996         data->suspend_ctrl =
 997                 FIELD_GET(SX9324_REG_GNRL_CTRL1_PHEN_MASK, regval);
 998
 999         if (ret < 0)
1000                 goto out;
1001
1002         /* Disable all phases, send the device to sleep. */
1003         ret = regmap_write(data->regmap, SX9324_REG_GNRL_CTRL1, 0);
1004
1005 out:
1006         mutex_unlock(&data->mutex);
1007         return ret;
1008 }
1009
1010 static int __maybe_unused sx9324_resume(struct device *dev)
1011 {
1012         struct sx_common_data *data = iio_priv(dev_get_drvdata(dev));
1013         int ret;
1014
1015         mutex_lock(&data->mutex);
1016         ret = regmap_write(data->regmap, SX9324_REG_GNRL_CTRL1,
1017                            data->suspend_ctrl | SX9324_REG_GNRL_CTRL1_PAUSECTRL);
1018         mutex_unlock(&data->mutex);
1019         if (ret)
1020                 return ret;
1021
1022         enable_irq(data->client->irq);
1023         return 0;
1024 }
1025
1026 static SIMPLE_DEV_PM_OPS(sx9324_pm_ops, sx9324_suspend, sx9324_resume);
1027
1028 static const struct acpi_device_id sx9324_acpi_match[] = {
1029         { "STH9324", SX9324_WHOAMI_VALUE },
1030         { }
1031 };
1032 MODULE_DEVICE_TABLE(acpi, sx9324_acpi_match);
1033
1034 static const struct of_device_id sx9324_of_match[] = {
1035         { .compatible = "semtech,sx9324", (void *)SX9324_WHOAMI_VALUE },
1036         { }
1037 };
1038 MODULE_DEVICE_TABLE(of, sx9324_of_match);
1039
1040 static const struct i2c_device_id sx9324_id[] = {
1041         { "sx9324", SX9324_WHOAMI_VALUE },
1042         { }
1043 };
1044 MODULE_DEVICE_TABLE(i2c, sx9324_id);
1045
1046 static struct i2c_driver sx9324_driver = {
1047         .driver = {
1048                 .name   = "sx9324",
1049                 .acpi_match_table = sx9324_acpi_match,
1050                 .of_match_table = sx9324_of_match,
1051                 .pm = &sx9324_pm_ops,
1052
1053                 /*
1054                  * Lots of i2c transfers in probe + over 200 ms waiting in
1055                  * sx9324_init_compensation() mean a slow probe; prefer async
1056                  * so we don't delay boot if we're builtin to the kernel.
1057                  */
1058                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1059         },
1060         .probe_new      = sx9324_probe,
1061         .id_table       = sx9324_id,
1062 };
1063 module_i2c_driver(sx9324_driver);
1064
1065 MODULE_AUTHOR("Gwendal Grignou <gwendal@chromium.org>");
1066 MODULE_DESCRIPTION("Driver for Semtech SX9324 proximity sensor");
1067 MODULE_LICENSE("GPL v2");
1068 MODULE_IMPORT_NS(SEMTECH_PROX);