1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2019 Analog Devices Inc.
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
10 #include <linux/debugfs.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/kernel.h>
14 #include <linux/iio/buffer.h>
15 #include <linux/iio/iio.h>
16 #include <linux/iio/imu/adis.h>
17 #include <linux/iio/trigger_consumer.h>
18 #include <linux/irq.h>
19 #include <linux/lcm.h>
20 #include <linux/math.h>
21 #include <linux/module.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/property.h>
24 #include <linux/spi/spi.h>
26 #define ADIS16475_REG_DIAG_STAT 0x02
27 #define ADIS16475_REG_X_GYRO_L 0x04
28 #define ADIS16475_REG_Y_GYRO_L 0x08
29 #define ADIS16475_REG_Z_GYRO_L 0x0C
30 #define ADIS16475_REG_X_ACCEL_L 0x10
31 #define ADIS16475_REG_Y_ACCEL_L 0x14
32 #define ADIS16475_REG_Z_ACCEL_L 0x18
33 #define ADIS16475_REG_TEMP_OUT 0x1c
34 #define ADIS16475_REG_X_GYRO_BIAS_L 0x40
35 #define ADIS16475_REG_Y_GYRO_BIAS_L 0x44
36 #define ADIS16475_REG_Z_GYRO_BIAS_L 0x48
37 #define ADIS16475_REG_X_ACCEL_BIAS_L 0x4c
38 #define ADIS16475_REG_Y_ACCEL_BIAS_L 0x50
39 #define ADIS16475_REG_Z_ACCEL_BIAS_L 0x54
40 #define ADIS16475_REG_FILT_CTRL 0x5c
41 #define ADIS16475_FILT_CTRL_MASK GENMASK(2, 0)
42 #define ADIS16475_FILT_CTRL(x) FIELD_PREP(ADIS16475_FILT_CTRL_MASK, x)
43 #define ADIS16475_REG_MSG_CTRL 0x60
44 #define ADIS16475_MSG_CTRL_DR_POL_MASK BIT(0)
45 #define ADIS16475_MSG_CTRL_DR_POL(x) \
46 FIELD_PREP(ADIS16475_MSG_CTRL_DR_POL_MASK, x)
47 #define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2)
48 #define ADIS16475_SYNC_MODE(x) FIELD_PREP(ADIS16475_SYNC_MODE_MASK, x)
49 #define ADIS16475_REG_UP_SCALE 0x62
50 #define ADIS16475_REG_DEC_RATE 0x64
51 #define ADIS16475_REG_GLOB_CMD 0x68
52 #define ADIS16475_REG_FIRM_REV 0x6c
53 #define ADIS16475_REG_FIRM_DM 0x6e
54 #define ADIS16475_REG_FIRM_Y 0x70
55 #define ADIS16475_REG_PROD_ID 0x72
56 #define ADIS16475_REG_SERIAL_NUM 0x74
57 #define ADIS16475_REG_FLASH_CNT 0x7c
58 #define ADIS16500_BURST32_MASK BIT(9)
59 #define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x)
60 /* number of data elements in burst mode */
61 #define ADIS16475_BURST32_MAX_DATA 32
62 #define ADIS16475_BURST_MAX_DATA 20
63 #define ADIS16475_MAX_SCAN_DATA 20
64 /* spi max speed in brust mode */
65 #define ADIS16475_BURST_MAX_SPEED 1000000
66 #define ADIS16475_LSB_DEC_MASK BIT(0)
67 #define ADIS16475_LSB_FIR_MASK BIT(1)
70 ADIS16475_SYNC_DIRECT = 1,
71 ADIS16475_SYNC_SCALED,
72 ADIS16475_SYNC_OUTPUT,
73 ADIS16475_SYNC_PULSE = 5,
76 struct adis16475_sync {
82 struct adis16475_chip_info {
83 const struct iio_chan_spec *channels;
84 const struct adis16475_sync *sync;
85 const struct adis_data adis_data;
100 const struct adis16475_chip_info *info;
104 unsigned long lsb_flag;
106 /* Alignment needed for the timestamp */
107 __be16 data[ADIS16475_MAX_SCAN_DATA] __aligned(8);
111 ADIS16475_SCAN_GYRO_X,
112 ADIS16475_SCAN_GYRO_Y,
113 ADIS16475_SCAN_GYRO_Z,
114 ADIS16475_SCAN_ACCEL_X,
115 ADIS16475_SCAN_ACCEL_Y,
116 ADIS16475_SCAN_ACCEL_Z,
118 ADIS16475_SCAN_DIAG_S_FLAGS,
119 ADIS16475_SCAN_CRC_FAILURE,
122 static bool low_rate_allow;
123 module_param(low_rate_allow, bool, 0444);
124 MODULE_PARM_DESC(low_rate_allow,
125 "Allow IMU rates below the minimum advisable when external clk is used in SCALED mode (default: N)");
127 #ifdef CONFIG_DEBUG_FS
128 static ssize_t adis16475_show_firmware_revision(struct file *file,
129 char __user *userbuf,
130 size_t count, loff_t *ppos)
132 struct adis16475 *st = file->private_data;
138 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_REV, &rev);
142 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff);
144 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
147 static const struct file_operations adis16475_firmware_revision_fops = {
149 .read = adis16475_show_firmware_revision,
150 .llseek = default_llseek,
151 .owner = THIS_MODULE,
154 static ssize_t adis16475_show_firmware_date(struct file *file,
155 char __user *userbuf,
156 size_t count, loff_t *ppos)
158 struct adis16475 *st = file->private_data;
164 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_Y, &year);
168 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_DM, &md);
172 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", md >> 8, md & 0xff,
175 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
178 static const struct file_operations adis16475_firmware_date_fops = {
180 .read = adis16475_show_firmware_date,
181 .llseek = default_llseek,
182 .owner = THIS_MODULE,
185 static int adis16475_show_serial_number(void *arg, u64 *val)
187 struct adis16475 *st = arg;
191 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_SERIAL_NUM, &serial);
199 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_serial_number_fops,
200 adis16475_show_serial_number, NULL, "0x%.4llx\n");
202 static int adis16475_show_product_id(void *arg, u64 *val)
204 struct adis16475 *st = arg;
208 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_PROD_ID, &prod_id);
216 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_product_id_fops,
217 adis16475_show_product_id, NULL, "%llu\n");
219 static int adis16475_show_flash_count(void *arg, u64 *val)
221 struct adis16475 *st = arg;
225 ret = adis_read_reg_32(&st->adis, ADIS16475_REG_FLASH_CNT,
234 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_flash_count_fops,
235 adis16475_show_flash_count, NULL, "%lld\n");
237 static void adis16475_debugfs_init(struct iio_dev *indio_dev)
239 struct adis16475 *st = iio_priv(indio_dev);
240 struct dentry *d = iio_get_debugfs_dentry(indio_dev);
242 debugfs_create_file_unsafe("serial_number", 0400,
243 d, st, &adis16475_serial_number_fops);
244 debugfs_create_file_unsafe("product_id", 0400,
245 d, st, &adis16475_product_id_fops);
246 debugfs_create_file_unsafe("flash_count", 0400,
247 d, st, &adis16475_flash_count_fops);
248 debugfs_create_file("firmware_revision", 0400,
249 d, st, &adis16475_firmware_revision_fops);
250 debugfs_create_file("firmware_date", 0400, d,
251 st, &adis16475_firmware_date_fops);
254 static void adis16475_debugfs_init(struct iio_dev *indio_dev)
259 static int adis16475_get_freq(struct adis16475 *st, u32 *freq)
263 u32 sample_rate = st->clk_freq;
265 adis_dev_lock(&st->adis);
267 if (st->sync_mode == ADIS16475_SYNC_SCALED) {
270 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, &sync_scale);
274 sample_rate = st->clk_freq * sync_scale;
277 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, &dec);
281 adis_dev_unlock(&st->adis);
283 *freq = DIV_ROUND_CLOSEST(sample_rate, dec + 1);
287 adis_dev_unlock(&st->adis);
291 static int adis16475_set_freq(struct adis16475 *st, const u32 freq)
295 u32 sample_rate = st->clk_freq;
300 adis_dev_lock(&st->adis);
302 * When using sync scaled mode, the input clock needs to be scaled so that we have
303 * an IMU sample rate between (optimally) 1900 and 2100. After this, we can use the
304 * decimation filter to lower the sampling rate in order to get what the user wants.
305 * Optimally, the user sample rate is a multiple of both the IMU sample rate and
306 * the input clock. Hence, calculating the sync_scale dynamically gives us better
307 * chances of achieving a perfect/integer value for DEC_RATE. The math here is:
308 * 1. lcm of the input clock and the desired output rate.
309 * 2. get the highest multiple of the previous result lower than the adis max rate.
310 * 3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE
311 * and DEC_RATE (to get the user output rate)
313 if (st->sync_mode == ADIS16475_SYNC_SCALED) {
314 unsigned long scaled_rate = lcm(st->clk_freq, freq);
318 * If lcm is bigger than the IMU maximum sampling rate there's no perfect
319 * solution. In this case, we get the highest multiple of the input clock
320 * lower than the IMU max sample rate.
322 if (scaled_rate > 2100000)
323 scaled_rate = 2100000 / st->clk_freq * st->clk_freq;
325 scaled_rate = 2100000 / scaled_rate * scaled_rate;
328 * This is not an hard requirement but it's not advised to run the IMU
329 * with a sample rate lower than 1900Hz due to possible undersampling
330 * issues. However, there are users that might really want to take the risk.
331 * Hence, we provide a module parameter for them. If set, we allow sample
332 * rates lower than 1.9KHz. By default, we won't allow this and we just roundup
333 * the rate to the next multiple of the input clock bigger than 1.9KHz. This
334 * is done like this as in some cases (when DEC_RATE is 0) might give
335 * us the closest value to the one desired by the user...
337 if (scaled_rate < 1900000 && !low_rate_allow)
338 scaled_rate = roundup(1900000, st->clk_freq);
340 sync_scale = scaled_rate / st->clk_freq;
341 ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, sync_scale);
345 sample_rate = scaled_rate;
348 dec = DIV_ROUND_CLOSEST(sample_rate, freq);
353 if (dec > st->info->max_dec)
354 dec = st->info->max_dec;
356 ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, dec);
360 adis_dev_unlock(&st->adis);
362 * If decimation is used, then gyro and accel data will have meaningful
363 * bits on the LSB registers. This info is used on the trigger handler.
365 assign_bit(ADIS16475_LSB_DEC_MASK, &st->lsb_flag, dec);
369 adis_dev_unlock(&st->adis);
373 /* The values are approximated. */
374 static const u32 adis16475_3db_freqs[] = {
375 [0] = 720, /* Filter disabled, full BW (~720Hz) */
384 static int adis16475_get_filter(struct adis16475 *st, u32 *filter)
388 const int mask = ADIS16475_FILT_CTRL_MASK;
390 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, &filter_sz);
394 *filter = adis16475_3db_freqs[filter_sz & mask];
399 static int adis16475_set_filter(struct adis16475 *st, const u32 filter)
401 int i = ARRAY_SIZE(adis16475_3db_freqs);
405 if (adis16475_3db_freqs[i] >= filter)
409 ret = adis_write_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL,
410 ADIS16475_FILT_CTRL(i));
415 * If FIR is used, then gyro and accel data will have meaningful
416 * bits on the LSB registers. This info is used on the trigger handler.
418 assign_bit(ADIS16475_LSB_FIR_MASK, &st->lsb_flag, i);
423 static const u32 adis16475_calib_regs[] = {
424 [ADIS16475_SCAN_GYRO_X] = ADIS16475_REG_X_GYRO_BIAS_L,
425 [ADIS16475_SCAN_GYRO_Y] = ADIS16475_REG_Y_GYRO_BIAS_L,
426 [ADIS16475_SCAN_GYRO_Z] = ADIS16475_REG_Z_GYRO_BIAS_L,
427 [ADIS16475_SCAN_ACCEL_X] = ADIS16475_REG_X_ACCEL_BIAS_L,
428 [ADIS16475_SCAN_ACCEL_Y] = ADIS16475_REG_Y_ACCEL_BIAS_L,
429 [ADIS16475_SCAN_ACCEL_Z] = ADIS16475_REG_Z_ACCEL_BIAS_L,
432 static int adis16475_read_raw(struct iio_dev *indio_dev,
433 const struct iio_chan_spec *chan,
434 int *val, int *val2, long info)
436 struct adis16475 *st = iio_priv(indio_dev);
441 case IIO_CHAN_INFO_RAW:
442 return adis_single_conversion(indio_dev, chan, 0, val);
443 case IIO_CHAN_INFO_SCALE:
444 switch (chan->type) {
446 *val = st->info->gyro_max_val;
447 *val2 = st->info->gyro_max_scale;
448 return IIO_VAL_FRACTIONAL;
450 *val = st->info->accel_max_val;
451 *val2 = st->info->accel_max_scale;
452 return IIO_VAL_FRACTIONAL;
454 *val = st->info->temp_scale;
459 case IIO_CHAN_INFO_CALIBBIAS:
460 ret = adis_read_reg_32(&st->adis,
461 adis16475_calib_regs[chan->scan_index],
467 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
468 ret = adis16475_get_filter(st, val);
473 case IIO_CHAN_INFO_SAMP_FREQ:
474 ret = adis16475_get_freq(st, &tmp);
479 *val2 = (tmp % 1000) * 1000;
480 return IIO_VAL_INT_PLUS_MICRO;
486 static int adis16475_write_raw(struct iio_dev *indio_dev,
487 const struct iio_chan_spec *chan,
488 int val, int val2, long info)
490 struct adis16475 *st = iio_priv(indio_dev);
494 case IIO_CHAN_INFO_SAMP_FREQ:
495 tmp = val * 1000 + val2 / 1000;
496 return adis16475_set_freq(st, tmp);
497 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
498 return adis16475_set_filter(st, val);
499 case IIO_CHAN_INFO_CALIBBIAS:
500 return adis_write_reg_32(&st->adis,
501 adis16475_calib_regs[chan->scan_index],
508 #define ADIS16475_MOD_CHAN(_type, _mod, _address, _si, _r_bits, _s_bits) \
512 .channel2 = (_mod), \
513 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
514 BIT(IIO_CHAN_INFO_CALIBBIAS), \
515 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
516 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
517 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
518 .address = (_address), \
519 .scan_index = (_si), \
522 .realbits = (_r_bits), \
523 .storagebits = (_s_bits), \
524 .endianness = IIO_BE, \
528 #define ADIS16475_GYRO_CHANNEL(_mod) \
529 ADIS16475_MOD_CHAN(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
530 ADIS16475_REG_ ## _mod ## _GYRO_L, \
531 ADIS16475_SCAN_GYRO_ ## _mod, 32, 32)
533 #define ADIS16475_ACCEL_CHANNEL(_mod) \
534 ADIS16475_MOD_CHAN(IIO_ACCEL, IIO_MOD_ ## _mod, \
535 ADIS16475_REG_ ## _mod ## _ACCEL_L, \
536 ADIS16475_SCAN_ACCEL_ ## _mod, 32, 32)
538 #define ADIS16475_TEMP_CHANNEL() { \
542 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
543 BIT(IIO_CHAN_INFO_SCALE), \
544 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
545 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
546 .address = ADIS16475_REG_TEMP_OUT, \
547 .scan_index = ADIS16475_SCAN_TEMP, \
552 .endianness = IIO_BE, \
556 static const struct iio_chan_spec adis16475_channels[] = {
557 ADIS16475_GYRO_CHANNEL(X),
558 ADIS16475_GYRO_CHANNEL(Y),
559 ADIS16475_GYRO_CHANNEL(Z),
560 ADIS16475_ACCEL_CHANNEL(X),
561 ADIS16475_ACCEL_CHANNEL(Y),
562 ADIS16475_ACCEL_CHANNEL(Z),
563 ADIS16475_TEMP_CHANNEL(),
564 IIO_CHAN_SOFT_TIMESTAMP(7)
567 enum adis16475_variant {
591 ADIS16475_DIAG_STAT_DATA_PATH = 1,
592 ADIS16475_DIAG_STAT_FLASH_MEM,
593 ADIS16475_DIAG_STAT_SPI,
594 ADIS16475_DIAG_STAT_STANDBY,
595 ADIS16475_DIAG_STAT_SENSOR,
596 ADIS16475_DIAG_STAT_MEMORY,
597 ADIS16475_DIAG_STAT_CLK,
600 static const char * const adis16475_status_error_msgs[] = {
601 [ADIS16475_DIAG_STAT_DATA_PATH] = "Data Path Overrun",
602 [ADIS16475_DIAG_STAT_FLASH_MEM] = "Flash memory update failure",
603 [ADIS16475_DIAG_STAT_SPI] = "SPI communication error",
604 [ADIS16475_DIAG_STAT_STANDBY] = "Standby mode",
605 [ADIS16475_DIAG_STAT_SENSOR] = "Sensor failure",
606 [ADIS16475_DIAG_STAT_MEMORY] = "Memory failure",
607 [ADIS16475_DIAG_STAT_CLK] = "Clock error",
610 #define ADIS16475_DATA(_prod_id, _timeouts) \
612 .msc_ctrl_reg = ADIS16475_REG_MSG_CTRL, \
613 .glob_cmd_reg = ADIS16475_REG_GLOB_CMD, \
614 .diag_stat_reg = ADIS16475_REG_DIAG_STAT, \
615 .prod_id_reg = ADIS16475_REG_PROD_ID, \
616 .prod_id = (_prod_id), \
617 .self_test_mask = BIT(2), \
618 .self_test_reg = ADIS16475_REG_GLOB_CMD, \
619 .cs_change_delay = 16, \
622 .status_error_msgs = adis16475_status_error_msgs, \
623 .status_error_mask = BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \
624 BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \
625 BIT(ADIS16475_DIAG_STAT_SPI) | \
626 BIT(ADIS16475_DIAG_STAT_STANDBY) | \
627 BIT(ADIS16475_DIAG_STAT_SENSOR) | \
628 BIT(ADIS16475_DIAG_STAT_MEMORY) | \
629 BIT(ADIS16475_DIAG_STAT_CLK), \
630 .unmasked_drdy = true, \
631 .timeouts = (_timeouts), \
632 .burst_reg_cmd = ADIS16475_REG_GLOB_CMD, \
633 .burst_len = ADIS16475_BURST_MAX_DATA, \
634 .burst_max_len = ADIS16475_BURST32_MAX_DATA, \
635 .burst_max_speed_hz = ADIS16475_BURST_MAX_SPEED \
638 static const struct adis16475_sync adis16475_sync_mode[] = {
639 { ADIS16475_SYNC_OUTPUT },
640 { ADIS16475_SYNC_DIRECT, 1900, 2100 },
641 { ADIS16475_SYNC_SCALED, 1, 128 },
642 { ADIS16475_SYNC_PULSE, 1000, 2100 },
645 static const struct adis_timeout adis16475_timeouts = {
651 static const struct adis_timeout adis1650x_timeouts = {
657 static const struct adis16475_chip_info adis16475_chip_info[] = {
660 .num_channels = ARRAY_SIZE(adis16475_channels),
661 .channels = adis16475_channels,
663 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
665 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
669 .sync = adis16475_sync_mode,
670 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
671 .adis_data = ADIS16475_DATA(16470, &adis16475_timeouts),
674 .name = "adis16475-1",
675 .num_channels = ARRAY_SIZE(adis16475_channels),
676 .channels = adis16475_channels,
678 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
680 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
684 .sync = adis16475_sync_mode,
685 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
686 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts),
689 .name = "adis16475-2",
690 .num_channels = ARRAY_SIZE(adis16475_channels),
691 .channels = adis16475_channels,
693 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
695 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
699 .sync = adis16475_sync_mode,
700 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
701 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts),
704 .name = "adis16475-3",
705 .num_channels = ARRAY_SIZE(adis16475_channels),
706 .channels = adis16475_channels,
708 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
710 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
714 .sync = adis16475_sync_mode,
715 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
716 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts),
719 .name = "adis16477-1",
720 .num_channels = ARRAY_SIZE(adis16475_channels),
721 .channels = adis16475_channels,
723 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
725 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
729 .sync = adis16475_sync_mode,
730 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
731 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts),
734 .name = "adis16477-2",
735 .num_channels = ARRAY_SIZE(adis16475_channels),
736 .channels = adis16475_channels,
738 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
740 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
744 .sync = adis16475_sync_mode,
745 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
746 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts),
749 .name = "adis16477-3",
750 .num_channels = ARRAY_SIZE(adis16475_channels),
751 .channels = adis16475_channels,
753 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
755 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
759 .sync = adis16475_sync_mode,
760 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
761 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts),
764 .name = "adis16465-1",
765 .num_channels = ARRAY_SIZE(adis16475_channels),
766 .channels = adis16475_channels,
768 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
770 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
774 .sync = adis16475_sync_mode,
775 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
776 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts),
779 .name = "adis16465-2",
780 .num_channels = ARRAY_SIZE(adis16475_channels),
781 .channels = adis16475_channels,
783 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
785 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
789 .sync = adis16475_sync_mode,
790 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
791 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts),
794 .name = "adis16465-3",
795 .num_channels = ARRAY_SIZE(adis16475_channels),
796 .channels = adis16475_channels,
798 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
800 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
804 .sync = adis16475_sync_mode,
805 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
806 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts),
809 .name = "adis16467-1",
810 .num_channels = ARRAY_SIZE(adis16475_channels),
811 .channels = adis16475_channels,
813 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
815 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
819 .sync = adis16475_sync_mode,
820 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
821 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts),
824 .name = "adis16467-2",
825 .num_channels = ARRAY_SIZE(adis16475_channels),
826 .channels = adis16475_channels,
828 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
830 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
834 .sync = adis16475_sync_mode,
835 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
836 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts),
839 .name = "adis16467-3",
840 .num_channels = ARRAY_SIZE(adis16475_channels),
841 .channels = adis16475_channels,
843 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
845 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
849 .sync = adis16475_sync_mode,
850 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
851 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts),
855 .num_channels = ARRAY_SIZE(adis16475_channels),
856 .channels = adis16475_channels,
858 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
859 .accel_max_val = 392,
860 .accel_max_scale = 32000 << 16,
864 .sync = adis16475_sync_mode,
865 /* pulse sync not supported */
866 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
868 .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts),
871 .name = "adis16505-1",
872 .num_channels = ARRAY_SIZE(adis16475_channels),
873 .channels = adis16475_channels,
875 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
877 .accel_max_scale = 32000 << 16,
881 .sync = adis16475_sync_mode,
882 /* pulse sync not supported */
883 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
885 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts),
888 .name = "adis16505-2",
889 .num_channels = ARRAY_SIZE(adis16475_channels),
890 .channels = adis16475_channels,
892 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
894 .accel_max_scale = 32000 << 16,
898 .sync = adis16475_sync_mode,
899 /* pulse sync not supported */
900 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
902 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts),
905 .name = "adis16505-3",
906 .num_channels = ARRAY_SIZE(adis16475_channels),
907 .channels = adis16475_channels,
909 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
911 .accel_max_scale = 32000 << 16,
915 .sync = adis16475_sync_mode,
916 /* pulse sync not supported */
917 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
919 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts),
922 .name = "adis16507-1",
923 .num_channels = ARRAY_SIZE(adis16475_channels),
924 .channels = adis16475_channels,
926 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
927 .accel_max_val = 392,
928 .accel_max_scale = 32000 << 16,
932 .sync = adis16475_sync_mode,
933 /* pulse sync not supported */
934 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
936 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts),
939 .name = "adis16507-2",
940 .num_channels = ARRAY_SIZE(adis16475_channels),
941 .channels = adis16475_channels,
943 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
944 .accel_max_val = 392,
945 .accel_max_scale = 32000 << 16,
949 .sync = adis16475_sync_mode,
950 /* pulse sync not supported */
951 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
953 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts),
956 .name = "adis16507-3",
957 .num_channels = ARRAY_SIZE(adis16475_channels),
958 .channels = adis16475_channels,
960 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
961 .accel_max_val = 392,
962 .accel_max_scale = 32000 << 16,
966 .sync = adis16475_sync_mode,
967 /* pulse sync not supported */
968 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
970 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts),
974 static const struct iio_info adis16475_info = {
975 .read_raw = &adis16475_read_raw,
976 .write_raw = &adis16475_write_raw,
977 .update_scan_mode = adis_update_scan_mode,
978 .debugfs_reg_access = adis_debugfs_reg_access,
981 static bool adis16475_validate_crc(const u8 *buffer, u16 crc,
985 /* extra 6 elements for low gyro and accel */
986 const u16 sz = burst32 ? ADIS16475_BURST32_MAX_DATA :
987 ADIS16475_BURST_MAX_DATA;
989 for (i = 0; i < sz - 2; i++)
995 static void adis16475_burst32_check(struct adis16475 *st)
998 struct adis *adis = &st->adis;
1000 if (!st->info->has_burst32)
1003 if (st->lsb_flag && !st->burst32) {
1004 const u16 en = ADIS16500_BURST32(1);
1006 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1007 ADIS16500_BURST32_MASK, en);
1014 * In 32-bit mode we need extra 2 bytes for all gyro
1015 * and accel channels.
1017 adis->burst_extra_len = 6 * sizeof(u16);
1018 adis->xfer[1].len += 6 * sizeof(u16);
1019 dev_dbg(&adis->spi->dev, "Enable burst32 mode, xfer:%d",
1022 } else if (!st->lsb_flag && st->burst32) {
1023 const u16 en = ADIS16500_BURST32(0);
1025 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1026 ADIS16500_BURST32_MASK, en);
1030 st->burst32 = false;
1032 /* Remove the extra bits */
1033 adis->burst_extra_len = 0;
1034 adis->xfer[1].len -= 6 * sizeof(u16);
1035 dev_dbg(&adis->spi->dev, "Disable burst32 mode, xfer:%d\n",
1040 static irqreturn_t adis16475_trigger_handler(int irq, void *p)
1042 struct iio_poll_func *pf = p;
1043 struct iio_dev *indio_dev = pf->indio_dev;
1044 struct adis16475 *st = iio_priv(indio_dev);
1045 struct adis *adis = &st->adis;
1046 int ret, bit, i = 0;
1050 /* offset until the first element after gyro and accel */
1051 const u8 offset = st->burst32 ? 13 : 7;
1053 ret = spi_sync(adis->spi, &adis->msg);
1057 buffer = adis->buffer;
1059 crc = be16_to_cpu(buffer[offset + 2]);
1060 valid = adis16475_validate_crc(adis->buffer, crc, st->burst32);
1062 dev_err(&adis->spi->dev, "Invalid crc\n");
1066 for_each_set_bit(bit, indio_dev->active_scan_mask,
1067 indio_dev->masklength) {
1069 * When burst mode is used, system flags is the first data
1070 * channel in the sequence, but the scan index is 7.
1073 case ADIS16475_SCAN_TEMP:
1074 st->data[i++] = buffer[offset];
1076 case ADIS16475_SCAN_GYRO_X ... ADIS16475_SCAN_ACCEL_Z:
1078 * The first 2 bytes on the received data are the
1079 * DIAG_STAT reg, hence the +1 offset here...
1083 st->data[i++] = buffer[bit * 2 + 2];
1085 st->data[i++] = buffer[bit * 2 + 1];
1087 st->data[i++] = buffer[bit + 1];
1089 * Don't bother in doing the manual read if the
1090 * device supports burst32. burst32 will be
1091 * enabled in the next call to
1092 * adis16475_burst32_check()...
1094 if (st->lsb_flag && !st->info->has_burst32) {
1096 const u32 reg = ADIS16475_REG_X_GYRO_L +
1099 adis_read_reg_16(adis, reg, &val);
1100 st->data[i++] = cpu_to_be16(val);
1102 /* lower not used */
1110 iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp);
1113 * We only check the burst mode at the end of the current capture since
1114 * it takes a full data ready cycle for the device to update the burst
1117 adis16475_burst32_check(st);
1118 iio_trigger_notify_done(indio_dev->trig);
1123 static int adis16475_config_sync_mode(struct adis16475 *st)
1126 struct device *dev = &st->adis.spi->dev;
1127 const struct adis16475_sync *sync;
1130 /* default to internal clk */
1131 st->clk_freq = st->info->int_clk * 1000;
1133 ret = device_property_read_u32(dev, "adi,sync-mode", &sync_mode);
1137 if (sync_mode >= st->info->num_sync) {
1138 dev_err(dev, "Invalid sync mode: %u for %s\n", sync_mode,
1143 sync = &st->info->sync[sync_mode];
1144 st->sync_mode = sync->sync_mode;
1146 /* All the other modes require external input signal */
1147 if (sync->sync_mode != ADIS16475_SYNC_OUTPUT) {
1148 struct clk *clk = devm_clk_get_enabled(dev, NULL);
1151 return PTR_ERR(clk);
1153 st->clk_freq = clk_get_rate(clk);
1154 if (st->clk_freq < sync->min_rate ||
1155 st->clk_freq > sync->max_rate) {
1157 "Clk rate:%u not in a valid range:[%u %u]\n",
1158 st->clk_freq, sync->min_rate, sync->max_rate);
1162 if (sync->sync_mode == ADIS16475_SYNC_SCALED) {
1166 * In sync scaled mode, the IMU sample rate is the clk_freq * sync_scale.
1167 * Hence, default the IMU sample rate to the highest multiple of the input
1168 * clock lower than the IMU max sample rate. The optimal range is
1171 up_scale = 2100 / st->clk_freq;
1173 ret = __adis_write_reg_16(&st->adis,
1174 ADIS16475_REG_UP_SCALE,
1180 st->clk_freq *= 1000;
1183 * Keep in mind that the mask for the clk modes in adis1650*
1184 * chips is different (1100 instead of 11100). However, we
1185 * are not configuring BIT(4) in these chips and the default
1186 * value is 0, so we are fine in doing the below operations.
1187 * I'm keeping this for simplicity and avoiding extra variables
1190 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1191 ADIS16475_SYNC_MODE_MASK, sync->sync_mode);
1195 usleep_range(250, 260);
1200 static int adis16475_config_irq_pin(struct adis16475 *st)
1203 struct irq_data *desc;
1207 struct spi_device *spi = st->adis.spi;
1209 desc = irq_get_irq_data(spi->irq);
1211 dev_err(&spi->dev, "Could not find IRQ %d\n", spi->irq);
1215 * It is possible to configure the data ready polarity. Furthermore, we
1216 * need to update the adis struct if we want data ready as active low.
1218 irq_type = irqd_get_trigger_type(desc);
1219 if (irq_type == IRQ_TYPE_EDGE_RISING) {
1221 st->adis.irq_flag = IRQF_TRIGGER_RISING;
1222 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) {
1224 st->adis.irq_flag = IRQF_TRIGGER_FALLING;
1226 dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n",
1231 val = ADIS16475_MSG_CTRL_DR_POL(polarity);
1232 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1233 ADIS16475_MSG_CTRL_DR_POL_MASK, val);
1237 * There is a delay writing to any bits written to the MSC_CTRL
1238 * register. It should not be bigger than 200us, so 250 should be more
1241 usleep_range(250, 260);
1246 static const struct of_device_id adis16475_of_match[] = {
1247 { .compatible = "adi,adis16470",
1248 .data = &adis16475_chip_info[ADIS16470] },
1249 { .compatible = "adi,adis16475-1",
1250 .data = &adis16475_chip_info[ADIS16475_1] },
1251 { .compatible = "adi,adis16475-2",
1252 .data = &adis16475_chip_info[ADIS16475_2] },
1253 { .compatible = "adi,adis16475-3",
1254 .data = &adis16475_chip_info[ADIS16475_3] },
1255 { .compatible = "adi,adis16477-1",
1256 .data = &adis16475_chip_info[ADIS16477_1] },
1257 { .compatible = "adi,adis16477-2",
1258 .data = &adis16475_chip_info[ADIS16477_2] },
1259 { .compatible = "adi,adis16477-3",
1260 .data = &adis16475_chip_info[ADIS16477_3] },
1261 { .compatible = "adi,adis16465-1",
1262 .data = &adis16475_chip_info[ADIS16465_1] },
1263 { .compatible = "adi,adis16465-2",
1264 .data = &adis16475_chip_info[ADIS16465_2] },
1265 { .compatible = "adi,adis16465-3",
1266 .data = &adis16475_chip_info[ADIS16465_3] },
1267 { .compatible = "adi,adis16467-1",
1268 .data = &adis16475_chip_info[ADIS16467_1] },
1269 { .compatible = "adi,adis16467-2",
1270 .data = &adis16475_chip_info[ADIS16467_2] },
1271 { .compatible = "adi,adis16467-3",
1272 .data = &adis16475_chip_info[ADIS16467_3] },
1273 { .compatible = "adi,adis16500",
1274 .data = &adis16475_chip_info[ADIS16500] },
1275 { .compatible = "adi,adis16505-1",
1276 .data = &adis16475_chip_info[ADIS16505_1] },
1277 { .compatible = "adi,adis16505-2",
1278 .data = &adis16475_chip_info[ADIS16505_2] },
1279 { .compatible = "adi,adis16505-3",
1280 .data = &adis16475_chip_info[ADIS16505_3] },
1281 { .compatible = "adi,adis16507-1",
1282 .data = &adis16475_chip_info[ADIS16507_1] },
1283 { .compatible = "adi,adis16507-2",
1284 .data = &adis16475_chip_info[ADIS16507_2] },
1285 { .compatible = "adi,adis16507-3",
1286 .data = &adis16475_chip_info[ADIS16507_3] },
1289 MODULE_DEVICE_TABLE(of, adis16475_of_match);
1291 static int adis16475_probe(struct spi_device *spi)
1293 struct iio_dev *indio_dev;
1294 struct adis16475 *st;
1297 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1301 st = iio_priv(indio_dev);
1303 st->info = device_get_match_data(&spi->dev);
1307 ret = adis_init(&st->adis, indio_dev, spi, &st->info->adis_data);
1311 indio_dev->name = st->info->name;
1312 indio_dev->channels = st->info->channels;
1313 indio_dev->num_channels = st->info->num_channels;
1314 indio_dev->info = &adis16475_info;
1315 indio_dev->modes = INDIO_DIRECT_MODE;
1317 ret = __adis_initial_startup(&st->adis);
1321 ret = adis16475_config_irq_pin(st);
1325 ret = adis16475_config_sync_mode(st);
1329 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev,
1330 adis16475_trigger_handler);
1334 ret = devm_iio_device_register(&spi->dev, indio_dev);
1338 adis16475_debugfs_init(indio_dev);
1343 static struct spi_driver adis16475_driver = {
1345 .name = "adis16475",
1346 .of_match_table = adis16475_of_match,
1348 .probe = adis16475_probe,
1350 module_spi_driver(adis16475_driver);
1352 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
1353 MODULE_DESCRIPTION("Analog Devices ADIS16475 IMU driver");
1354 MODULE_LICENSE("GPL");
1355 MODULE_IMPORT_NS(IIO_ADISLIB);