1 // SPDX-License-Identifier: GPL-2.0-only
3 * AD5592R Digital <-> Analog converters driver
5 * Copyright 2014-2016 Analog Devices Inc.
6 * Author: Paul Cercueil <paul.cercueil@analog.com>
9 #include <linux/bitops.h>
10 #include <linux/delay.h>
11 #include <linux/iio/iio.h>
12 #include <linux/module.h>
13 #include <linux/mutex.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/property.h>
20 #include <dt-bindings/iio/adi,ad5592r.h>
22 #include "ad5592r-base.h"
24 static int ad5592r_gpio_get(struct gpio_chip *chip, unsigned offset)
26 struct ad5592r_state *st = gpiochip_get_data(chip);
30 mutex_lock(&st->gpio_lock);
32 if (st->gpio_out & BIT(offset))
35 ret = st->ops->gpio_read(st, &val);
37 mutex_unlock(&st->gpio_lock);
42 return !!(val & BIT(offset));
45 static void ad5592r_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
47 struct ad5592r_state *st = gpiochip_get_data(chip);
49 mutex_lock(&st->gpio_lock);
52 st->gpio_val |= BIT(offset);
54 st->gpio_val &= ~BIT(offset);
56 st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
58 mutex_unlock(&st->gpio_lock);
61 static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
63 struct ad5592r_state *st = gpiochip_get_data(chip);
66 mutex_lock(&st->gpio_lock);
68 st->gpio_out &= ~BIT(offset);
69 st->gpio_in |= BIT(offset);
71 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
75 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
78 mutex_unlock(&st->gpio_lock);
83 static int ad5592r_gpio_direction_output(struct gpio_chip *chip,
84 unsigned offset, int value)
86 struct ad5592r_state *st = gpiochip_get_data(chip);
89 mutex_lock(&st->gpio_lock);
92 st->gpio_val |= BIT(offset);
94 st->gpio_val &= ~BIT(offset);
96 st->gpio_in &= ~BIT(offset);
97 st->gpio_out |= BIT(offset);
99 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
103 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
107 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
110 mutex_unlock(&st->gpio_lock);
115 static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset)
117 struct ad5592r_state *st = gpiochip_get_data(chip);
119 if (!(st->gpio_map & BIT(offset))) {
120 dev_err(st->dev, "GPIO %d is reserved by alternate function\n",
128 static int ad5592r_gpio_init(struct ad5592r_state *st)
133 st->gpiochip.label = dev_name(st->dev);
134 st->gpiochip.base = -1;
135 st->gpiochip.ngpio = 8;
136 st->gpiochip.parent = st->dev;
137 st->gpiochip.can_sleep = true;
138 st->gpiochip.direction_input = ad5592r_gpio_direction_input;
139 st->gpiochip.direction_output = ad5592r_gpio_direction_output;
140 st->gpiochip.get = ad5592r_gpio_get;
141 st->gpiochip.set = ad5592r_gpio_set;
142 st->gpiochip.request = ad5592r_gpio_request;
143 st->gpiochip.owner = THIS_MODULE;
145 mutex_init(&st->gpio_lock);
147 return gpiochip_add_data(&st->gpiochip, st);
150 static void ad5592r_gpio_cleanup(struct ad5592r_state *st)
153 gpiochip_remove(&st->gpiochip);
156 static int ad5592r_reset(struct ad5592r_state *st)
158 struct gpio_desc *gpio;
160 gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW);
162 return PTR_ERR(gpio);
166 gpiod_set_value(gpio, 1);
168 mutex_lock(&st->lock);
169 /* Writing this magic value resets the device */
170 st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac);
171 mutex_unlock(&st->lock);
179 static int ad5592r_get_vref(struct ad5592r_state *st)
184 ret = regulator_get_voltage(st->reg);
194 static int ad5592r_set_channel_modes(struct ad5592r_state *st)
196 const struct ad5592r_rw_ops *ops = st->ops;
199 u8 pulldown = 0, tristate = 0, dac = 0, adc = 0;
202 for (i = 0; i < st->num_channels; i++) {
203 switch (st->channel_modes[i]) {
212 case CH_MODE_DAC_AND_ADC:
218 st->gpio_map |= BIT(i);
219 st->gpio_in |= BIT(i); /* Default to input */
224 switch (st->channel_offstate[i]) {
225 case CH_OFFSTATE_OUT_TRISTATE:
229 case CH_OFFSTATE_OUT_LOW:
230 st->gpio_out |= BIT(i);
233 case CH_OFFSTATE_OUT_HIGH:
234 st->gpio_out |= BIT(i);
235 st->gpio_val |= BIT(i);
238 case CH_OFFSTATE_PULLDOWN:
246 mutex_lock(&st->lock);
248 /* Pull down unused pins to GND */
249 ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown);
253 ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate);
257 /* Configure pins that we use */
258 ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac);
262 ret = ops->reg_write(st, AD5592R_REG_ADC_EN, adc);
266 ret = ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
270 ret = ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
274 ret = ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
278 /* Verify that we can read back at least one register */
279 ret = ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back);
280 if (!ret && (read_back & 0xff) != adc)
284 mutex_unlock(&st->lock);
288 static int ad5592r_reset_channel_modes(struct ad5592r_state *st)
292 for (i = 0; i < ARRAY_SIZE(st->channel_modes); i++)
293 st->channel_modes[i] = CH_MODE_UNUSED;
295 return ad5592r_set_channel_modes(st);
298 static int ad5592r_write_raw(struct iio_dev *iio_dev,
299 struct iio_chan_spec const *chan, int val, int val2, long mask)
301 struct ad5592r_state *st = iio_priv(iio_dev);
305 case IIO_CHAN_INFO_RAW:
307 if (val >= (1 << chan->scan_type.realbits) || val < 0)
313 mutex_lock(&st->lock);
314 ret = st->ops->write_dac(st, chan->channel, val);
316 st->cached_dac[chan->channel] = val;
317 mutex_unlock(&st->lock);
319 case IIO_CHAN_INFO_SCALE:
320 if (chan->type == IIO_VOLTAGE) {
323 if (val == st->scale_avail[0][0] &&
324 val2 == st->scale_avail[0][1])
326 else if (val == st->scale_avail[1][0] &&
327 val2 == st->scale_avail[1][1])
332 mutex_lock(&st->lock);
334 ret = st->ops->reg_read(st, AD5592R_REG_CTRL,
335 &st->cached_gp_ctrl);
337 mutex_unlock(&st->lock);
343 st->cached_gp_ctrl |=
344 AD5592R_REG_CTRL_DAC_RANGE;
346 st->cached_gp_ctrl &=
347 ~AD5592R_REG_CTRL_DAC_RANGE;
350 st->cached_gp_ctrl |=
351 AD5592R_REG_CTRL_ADC_RANGE;
353 st->cached_gp_ctrl &=
354 ~AD5592R_REG_CTRL_ADC_RANGE;
357 ret = st->ops->reg_write(st, AD5592R_REG_CTRL,
359 mutex_unlock(&st->lock);
371 static int ad5592r_read_raw(struct iio_dev *iio_dev,
372 struct iio_chan_spec const *chan,
373 int *val, int *val2, long m)
375 struct ad5592r_state *st = iio_priv(iio_dev);
380 case IIO_CHAN_INFO_RAW:
381 mutex_lock(&st->lock);
384 ret = st->ops->read_adc(st, chan->channel, &read_val);
388 if ((read_val >> 12 & 0x7) != (chan->channel & 0x7)) {
389 dev_err(st->dev, "Error while reading channel %u\n",
395 read_val &= GENMASK(11, 0);
398 read_val = st->cached_dac[chan->channel];
401 dev_dbg(st->dev, "Channel %u read: 0x%04hX\n",
402 chan->channel, read_val);
404 *val = (int) read_val;
407 case IIO_CHAN_INFO_SCALE:
408 *val = ad5592r_get_vref(st);
410 if (chan->type == IIO_TEMP) {
411 s64 tmp = *val * (3767897513LL / 25LL);
412 *val = div_s64_rem(tmp, 1000000000LL, val2);
414 return IIO_VAL_INT_PLUS_MICRO;
418 mutex_lock(&st->lock);
421 mult = !!(st->cached_gp_ctrl &
422 AD5592R_REG_CTRL_DAC_RANGE);
424 mult = !!(st->cached_gp_ctrl &
425 AD5592R_REG_CTRL_ADC_RANGE);
429 *val2 = chan->scan_type.realbits;
430 ret = IIO_VAL_FRACTIONAL_LOG2;
433 case IIO_CHAN_INFO_OFFSET:
434 ret = ad5592r_get_vref(st);
436 mutex_lock(&st->lock);
438 if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE)
439 *val = (-34365 * 25) / ret;
441 *val = (-75365 * 25) / ret;
449 mutex_unlock(&st->lock);
453 static int ad5592r_write_raw_get_fmt(struct iio_dev *indio_dev,
454 struct iio_chan_spec const *chan, long mask)
457 case IIO_CHAN_INFO_SCALE:
458 return IIO_VAL_INT_PLUS_NANO;
461 return IIO_VAL_INT_PLUS_MICRO;
467 static const struct iio_info ad5592r_info = {
468 .read_raw = ad5592r_read_raw,
469 .write_raw = ad5592r_write_raw,
470 .write_raw_get_fmt = ad5592r_write_raw_get_fmt,
473 static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev,
475 const struct iio_chan_spec *chan,
478 struct ad5592r_state *st = iio_priv(iio_dev);
480 return sprintf(buf, "%d.%09u %d.%09u\n",
481 st->scale_avail[0][0], st->scale_avail[0][1],
482 st->scale_avail[1][0], st->scale_avail[1][1]);
485 static const struct iio_chan_spec_ext_info ad5592r_ext_info[] = {
487 .name = "scale_available",
488 .read = ad5592r_show_scale_available,
494 static void ad5592r_setup_channel(struct iio_dev *iio_dev,
495 struct iio_chan_spec *chan, bool output, unsigned id)
497 chan->type = IIO_VOLTAGE;
499 chan->output = output;
501 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
502 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
503 chan->scan_type.sign = 'u';
504 chan->scan_type.realbits = 12;
505 chan->scan_type.storagebits = 16;
506 chan->ext_info = ad5592r_ext_info;
509 static int ad5592r_alloc_channels(struct iio_dev *iio_dev)
511 struct ad5592r_state *st = iio_priv(iio_dev);
512 unsigned i, curr_channel = 0,
513 num_channels = st->num_channels;
514 struct iio_chan_spec *channels;
515 struct fwnode_handle *child;
519 device_for_each_child_node(st->dev, child) {
520 ret = fwnode_property_read_u32(child, "reg", ®);
521 if (ret || reg >= ARRAY_SIZE(st->channel_modes))
524 ret = fwnode_property_read_u32(child, "adi,mode", &tmp);
526 st->channel_modes[reg] = tmp;
528 fwnode_property_read_u32(child, "adi,off-state", &tmp);
530 st->channel_offstate[reg] = tmp;
533 channels = devm_kcalloc(st->dev,
534 1 + 2 * num_channels, sizeof(*channels),
539 for (i = 0; i < num_channels; i++) {
540 switch (st->channel_modes[i]) {
542 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
548 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
553 case CH_MODE_DAC_AND_ADC:
554 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
557 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
567 channels[curr_channel].type = IIO_TEMP;
568 channels[curr_channel].channel = 8;
569 channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
570 BIT(IIO_CHAN_INFO_SCALE) |
571 BIT(IIO_CHAN_INFO_OFFSET);
574 iio_dev->num_channels = curr_channel;
575 iio_dev->channels = channels;
580 static void ad5592r_init_scales(struct ad5592r_state *st, int vref_mV)
582 s64 tmp = (s64)vref_mV * 1000000000LL >> 12;
584 st->scale_avail[0][0] =
585 div_s64_rem(tmp, 1000000000LL, &st->scale_avail[0][1]);
586 st->scale_avail[1][0] =
587 div_s64_rem(tmp * 2, 1000000000LL, &st->scale_avail[1][1]);
590 int ad5592r_probe(struct device *dev, const char *name,
591 const struct ad5592r_rw_ops *ops)
593 struct iio_dev *iio_dev;
594 struct ad5592r_state *st;
597 iio_dev = devm_iio_device_alloc(dev, sizeof(*st));
601 st = iio_priv(iio_dev);
604 st->num_channels = 8;
605 dev_set_drvdata(dev, iio_dev);
607 st->reg = devm_regulator_get_optional(dev, "vref");
608 if (IS_ERR(st->reg)) {
609 if ((PTR_ERR(st->reg) != -ENODEV) && dev->of_node)
610 return PTR_ERR(st->reg);
614 ret = regulator_enable(st->reg);
619 iio_dev->name = name;
620 iio_dev->info = &ad5592r_info;
621 iio_dev->modes = INDIO_DIRECT_MODE;
623 mutex_init(&st->lock);
625 ad5592r_init_scales(st, ad5592r_get_vref(st));
627 ret = ad5592r_reset(st);
629 goto error_disable_reg;
631 ret = ops->reg_write(st, AD5592R_REG_PD,
632 (st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0);
634 goto error_disable_reg;
636 ret = ad5592r_alloc_channels(iio_dev);
638 goto error_disable_reg;
640 ret = ad5592r_set_channel_modes(st);
642 goto error_reset_ch_modes;
644 ret = iio_device_register(iio_dev);
646 goto error_reset_ch_modes;
648 ret = ad5592r_gpio_init(st);
650 goto error_dev_unregister;
654 error_dev_unregister:
655 iio_device_unregister(iio_dev);
657 error_reset_ch_modes:
658 ad5592r_reset_channel_modes(st);
662 regulator_disable(st->reg);
666 EXPORT_SYMBOL_GPL(ad5592r_probe);
668 int ad5592r_remove(struct device *dev)
670 struct iio_dev *iio_dev = dev_get_drvdata(dev);
671 struct ad5592r_state *st = iio_priv(iio_dev);
673 iio_device_unregister(iio_dev);
674 ad5592r_reset_channel_modes(st);
675 ad5592r_gpio_cleanup(st);
678 regulator_disable(st->reg);
682 EXPORT_SYMBOL_GPL(ad5592r_remove);
684 MODULE_AUTHOR("Paul Cercueil <paul.cercueil@analog.com>");
685 MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters");
686 MODULE_LICENSE("GPL v2");