1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale Vybrid vf610 ADC driver
5 * Copyright 2013 Freescale Semiconductor, Inc.
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/interrupt.h>
11 #include <linux/delay.h>
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
15 #include <linux/clk.h>
16 #include <linux/completion.h>
18 #include <linux/of_irq.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/of_platform.h>
21 #include <linux/err.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/sysfs.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
30 /* This will be the driver name the kernel reports */
31 #define DRIVER_NAME "vf610-adc"
33 /* Vybrid/IMX ADC registers */
34 #define VF610_REG_ADC_HC0 0x00
35 #define VF610_REG_ADC_HC1 0x04
36 #define VF610_REG_ADC_HS 0x08
37 #define VF610_REG_ADC_R0 0x0c
38 #define VF610_REG_ADC_R1 0x10
39 #define VF610_REG_ADC_CFG 0x14
40 #define VF610_REG_ADC_GC 0x18
41 #define VF610_REG_ADC_GS 0x1c
42 #define VF610_REG_ADC_CV 0x20
43 #define VF610_REG_ADC_OFS 0x24
44 #define VF610_REG_ADC_CAL 0x28
45 #define VF610_REG_ADC_PCTL 0x30
47 /* Configuration register field define */
48 #define VF610_ADC_MODE_BIT8 0x00
49 #define VF610_ADC_MODE_BIT10 0x04
50 #define VF610_ADC_MODE_BIT12 0x08
51 #define VF610_ADC_MODE_MASK 0x0c
52 #define VF610_ADC_BUSCLK2_SEL 0x01
53 #define VF610_ADC_ALTCLK_SEL 0x02
54 #define VF610_ADC_ADACK_SEL 0x03
55 #define VF610_ADC_ADCCLK_MASK 0x03
56 #define VF610_ADC_CLK_DIV2 0x20
57 #define VF610_ADC_CLK_DIV4 0x40
58 #define VF610_ADC_CLK_DIV8 0x60
59 #define VF610_ADC_CLK_MASK 0x60
60 #define VF610_ADC_ADLSMP_LONG 0x10
61 #define VF610_ADC_ADSTS_SHORT 0x100
62 #define VF610_ADC_ADSTS_NORMAL 0x200
63 #define VF610_ADC_ADSTS_LONG 0x300
64 #define VF610_ADC_ADSTS_MASK 0x300
65 #define VF610_ADC_ADLPC_EN 0x80
66 #define VF610_ADC_ADHSC_EN 0x400
67 #define VF610_ADC_REFSEL_VALT 0x800
68 #define VF610_ADC_REFSEL_VBG 0x1000
69 #define VF610_ADC_ADTRG_HARD 0x2000
70 #define VF610_ADC_AVGS_8 0x4000
71 #define VF610_ADC_AVGS_16 0x8000
72 #define VF610_ADC_AVGS_32 0xC000
73 #define VF610_ADC_AVGS_MASK 0xC000
74 #define VF610_ADC_OVWREN 0x10000
76 /* General control register field define */
77 #define VF610_ADC_ADACKEN 0x1
78 #define VF610_ADC_DMAEN 0x2
79 #define VF610_ADC_ACREN 0x4
80 #define VF610_ADC_ACFGT 0x8
81 #define VF610_ADC_ACFE 0x10
82 #define VF610_ADC_AVGEN 0x20
83 #define VF610_ADC_ADCON 0x40
84 #define VF610_ADC_CAL 0x80
86 /* Other field define */
87 #define VF610_ADC_ADCHC(x) ((x) & 0x1F)
88 #define VF610_ADC_AIEN (0x1 << 7)
89 #define VF610_ADC_CONV_DISABLE 0x1F
90 #define VF610_ADC_HS_COCO0 0x1
91 #define VF610_ADC_CALF 0x2
92 #define VF610_ADC_TIMEOUT msecs_to_jiffies(100)
94 #define DEFAULT_SAMPLE_TIME 1000
96 /* V at 25°C of 696 mV */
97 #define VF610_VTEMP25_3V0 950
98 /* V at 25°C of 699 mV */
99 #define VF610_VTEMP25_3V3 867
100 /* Typical sensor slope coefficient at all temperatures */
101 #define VF610_TEMP_SLOPE_COEFF 1840
104 VF610_ADCIOC_BUSCLK_SET,
105 VF610_ADCIOC_ALTCLK_SET,
106 VF610_ADCIOC_ADACK_SET,
110 VF610_ADCIOC_VR_VREF_SET,
111 VF610_ADCIOC_VR_VALT_SET,
112 VF610_ADCIOC_VR_VBG_SET,
123 enum conversion_mode_sel {
124 VF610_ADC_CONV_NORMAL,
125 VF610_ADC_CONV_HIGH_SPEED,
126 VF610_ADC_CONV_LOW_POWER,
134 VF610_ADCK_CYCLES_13,
135 VF610_ADCK_CYCLES_17,
136 VF610_ADCK_CYCLES_21,
137 VF610_ADCK_CYCLES_25,
140 struct vf610_adc_feature {
141 enum clk_sel clk_sel;
142 enum vol_ref vol_ref;
143 enum conversion_mode_sel conv_mode;
149 u32 default_sample_time;
162 struct regulator *vref;
164 u32 max_adck_rate[3];
165 struct vf610_adc_feature adc_feature;
167 u32 sample_freq_avail[5];
169 struct completion completion;
173 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
174 static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 };
176 static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
178 struct vf610_adc_feature *adc_feature = &info->adc_feature;
179 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
180 u32 adck_period, lst_addr_min;
183 adck_rate = info->max_adck_rate[adc_feature->conv_mode];
186 /* calculate clk divider which is within specification */
187 divisor = ipg_rate / adck_rate;
188 adc_feature->clk_div = 1 << fls(divisor + 1);
190 /* fall-back value using a safe divisor */
191 adc_feature->clk_div = 8;
194 adck_rate = ipg_rate / adc_feature->clk_div;
197 * Determine the long sample time adder value to be used based
198 * on the default minimum sample time provided.
200 adck_period = NSEC_PER_SEC / adck_rate;
201 lst_addr_min = adc_feature->default_sample_time / adck_period;
202 for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) {
203 if (vf610_lst_adder[i] > lst_addr_min) {
204 adc_feature->lst_adder_index = i;
210 * Calculate ADC sample frequencies
211 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
212 * which is the same as bus clock.
214 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
215 * SFCAdder: fixed to 6 ADCK cycles
216 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
217 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
218 * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles
220 for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
221 info->sample_freq_avail[i] =
222 adck_rate / (6 + vf610_hw_avgs[i] *
223 (25 + vf610_lst_adder[adc_feature->lst_adder_index]));
226 static inline void vf610_adc_cfg_init(struct vf610_adc *info)
228 struct vf610_adc_feature *adc_feature = &info->adc_feature;
230 /* set default Configuration for ADC controller */
231 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
232 adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
234 adc_feature->calibration = true;
235 adc_feature->ovwren = true;
237 adc_feature->res_mode = 12;
238 adc_feature->sample_rate = 1;
240 adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
242 vf610_adc_calculate_rates(info);
245 static void vf610_adc_cfg_post_set(struct vf610_adc *info)
247 struct vf610_adc_feature *adc_feature = &info->adc_feature;
251 switch (adc_feature->clk_sel) {
252 case VF610_ADCIOC_ALTCLK_SET:
253 cfg_data |= VF610_ADC_ALTCLK_SEL;
255 case VF610_ADCIOC_ADACK_SET:
256 cfg_data |= VF610_ADC_ADACK_SEL;
262 /* low power set for calibration */
263 cfg_data |= VF610_ADC_ADLPC_EN;
265 /* enable high speed for calibration */
266 cfg_data |= VF610_ADC_ADHSC_EN;
268 /* voltage reference */
269 switch (adc_feature->vol_ref) {
270 case VF610_ADCIOC_VR_VREF_SET:
272 case VF610_ADCIOC_VR_VALT_SET:
273 cfg_data |= VF610_ADC_REFSEL_VALT;
275 case VF610_ADCIOC_VR_VBG_SET:
276 cfg_data |= VF610_ADC_REFSEL_VBG;
279 dev_err(info->dev, "error voltage reference\n");
282 /* data overwrite enable */
283 if (adc_feature->ovwren)
284 cfg_data |= VF610_ADC_OVWREN;
286 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
287 writel(gc_data, info->regs + VF610_REG_ADC_GC);
290 static void vf610_adc_calibration(struct vf610_adc *info)
294 if (!info->adc_feature.calibration)
297 /* enable calibration interrupt */
298 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
299 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
301 adc_gc = readl(info->regs + VF610_REG_ADC_GC);
302 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
304 if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
305 dev_err(info->dev, "Timeout for adc calibration\n");
307 adc_gc = readl(info->regs + VF610_REG_ADC_GS);
308 if (adc_gc & VF610_ADC_CALF)
309 dev_err(info->dev, "ADC calibration failed\n");
311 info->adc_feature.calibration = false;
314 static void vf610_adc_cfg_set(struct vf610_adc *info)
316 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
319 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
321 cfg_data &= ~VF610_ADC_ADLPC_EN;
322 if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
323 cfg_data |= VF610_ADC_ADLPC_EN;
325 cfg_data &= ~VF610_ADC_ADHSC_EN;
326 if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
327 cfg_data |= VF610_ADC_ADHSC_EN;
329 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
332 static void vf610_adc_sample_set(struct vf610_adc *info)
334 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
335 int cfg_data, gc_data;
337 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
338 gc_data = readl(info->regs + VF610_REG_ADC_GC);
340 /* resolution mode */
341 cfg_data &= ~VF610_ADC_MODE_MASK;
342 switch (adc_feature->res_mode) {
344 cfg_data |= VF610_ADC_MODE_BIT8;
347 cfg_data |= VF610_ADC_MODE_BIT10;
350 cfg_data |= VF610_ADC_MODE_BIT12;
353 dev_err(info->dev, "error resolution mode\n");
357 /* clock select and clock divider */
358 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
359 switch (adc_feature->clk_div) {
363 cfg_data |= VF610_ADC_CLK_DIV2;
366 cfg_data |= VF610_ADC_CLK_DIV4;
369 cfg_data |= VF610_ADC_CLK_DIV8;
372 switch (adc_feature->clk_sel) {
373 case VF610_ADCIOC_BUSCLK_SET:
374 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
377 dev_err(info->dev, "error clk divider\n");
384 * Set ADLSMP and ADSTS based on the Long Sample Time Adder value
387 switch (adc_feature->lst_adder_index) {
388 case VF610_ADCK_CYCLES_3:
390 case VF610_ADCK_CYCLES_5:
391 cfg_data |= VF610_ADC_ADSTS_SHORT;
393 case VF610_ADCK_CYCLES_7:
394 cfg_data |= VF610_ADC_ADSTS_NORMAL;
396 case VF610_ADCK_CYCLES_9:
397 cfg_data |= VF610_ADC_ADSTS_LONG;
399 case VF610_ADCK_CYCLES_13:
400 cfg_data |= VF610_ADC_ADLSMP_LONG;
402 case VF610_ADCK_CYCLES_17:
403 cfg_data |= VF610_ADC_ADLSMP_LONG;
404 cfg_data |= VF610_ADC_ADSTS_SHORT;
406 case VF610_ADCK_CYCLES_21:
407 cfg_data |= VF610_ADC_ADLSMP_LONG;
408 cfg_data |= VF610_ADC_ADSTS_NORMAL;
410 case VF610_ADCK_CYCLES_25:
411 cfg_data |= VF610_ADC_ADLSMP_LONG;
412 cfg_data |= VF610_ADC_ADSTS_NORMAL;
415 dev_err(info->dev, "error in sample time select\n");
418 /* update hardware average selection */
419 cfg_data &= ~VF610_ADC_AVGS_MASK;
420 gc_data &= ~VF610_ADC_AVGEN;
421 switch (adc_feature->sample_rate) {
422 case VF610_ADC_SAMPLE_1:
424 case VF610_ADC_SAMPLE_4:
425 gc_data |= VF610_ADC_AVGEN;
427 case VF610_ADC_SAMPLE_8:
428 gc_data |= VF610_ADC_AVGEN;
429 cfg_data |= VF610_ADC_AVGS_8;
431 case VF610_ADC_SAMPLE_16:
432 gc_data |= VF610_ADC_AVGEN;
433 cfg_data |= VF610_ADC_AVGS_16;
435 case VF610_ADC_SAMPLE_32:
436 gc_data |= VF610_ADC_AVGEN;
437 cfg_data |= VF610_ADC_AVGS_32;
441 "error hardware sample average select\n");
444 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
445 writel(gc_data, info->regs + VF610_REG_ADC_GC);
448 static void vf610_adc_hw_init(struct vf610_adc *info)
450 /* CFG: Feature set */
451 vf610_adc_cfg_post_set(info);
452 vf610_adc_sample_set(info);
454 /* adc calibration */
455 vf610_adc_calibration(info);
457 /* CFG: power and speed set */
458 vf610_adc_cfg_set(info);
461 static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
462 const struct iio_chan_spec *chan,
465 struct vf610_adc *info = iio_priv(indio_dev);
467 mutex_lock(&indio_dev->mlock);
468 info->adc_feature.conv_mode = mode;
469 vf610_adc_calculate_rates(info);
470 vf610_adc_hw_init(info);
471 mutex_unlock(&indio_dev->mlock);
476 static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
477 const struct iio_chan_spec *chan)
479 struct vf610_adc *info = iio_priv(indio_dev);
481 return info->adc_feature.conv_mode;
484 static const char * const vf610_conv_modes[] = { "normal", "high-speed",
487 static const struct iio_enum vf610_conversion_mode = {
488 .items = vf610_conv_modes,
489 .num_items = ARRAY_SIZE(vf610_conv_modes),
490 .get = vf610_get_conversion_mode,
491 .set = vf610_set_conversion_mode,
494 static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
495 IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
499 #define VF610_ADC_CHAN(_idx, _chan_type) { \
500 .type = (_chan_type), \
503 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
504 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
505 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
506 .ext_info = vf610_ext_info, \
507 .scan_index = (_idx), \
515 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \
516 .type = (_chan_type), \
518 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
519 .scan_index = (_idx), \
527 static const struct iio_chan_spec vf610_adc_iio_channels[] = {
528 VF610_ADC_CHAN(0, IIO_VOLTAGE),
529 VF610_ADC_CHAN(1, IIO_VOLTAGE),
530 VF610_ADC_CHAN(2, IIO_VOLTAGE),
531 VF610_ADC_CHAN(3, IIO_VOLTAGE),
532 VF610_ADC_CHAN(4, IIO_VOLTAGE),
533 VF610_ADC_CHAN(5, IIO_VOLTAGE),
534 VF610_ADC_CHAN(6, IIO_VOLTAGE),
535 VF610_ADC_CHAN(7, IIO_VOLTAGE),
536 VF610_ADC_CHAN(8, IIO_VOLTAGE),
537 VF610_ADC_CHAN(9, IIO_VOLTAGE),
538 VF610_ADC_CHAN(10, IIO_VOLTAGE),
539 VF610_ADC_CHAN(11, IIO_VOLTAGE),
540 VF610_ADC_CHAN(12, IIO_VOLTAGE),
541 VF610_ADC_CHAN(13, IIO_VOLTAGE),
542 VF610_ADC_CHAN(14, IIO_VOLTAGE),
543 VF610_ADC_CHAN(15, IIO_VOLTAGE),
544 VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
545 IIO_CHAN_SOFT_TIMESTAMP(32),
549 static int vf610_adc_read_data(struct vf610_adc *info)
553 result = readl(info->regs + VF610_REG_ADC_R0);
555 switch (info->adc_feature.res_mode) {
572 static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
574 struct iio_dev *indio_dev = dev_id;
575 struct vf610_adc *info = iio_priv(indio_dev);
578 coco = readl(info->regs + VF610_REG_ADC_HS);
579 if (coco & VF610_ADC_HS_COCO0) {
580 info->value = vf610_adc_read_data(info);
581 if (iio_buffer_enabled(indio_dev)) {
582 info->buffer[0] = info->value;
583 iio_push_to_buffers_with_timestamp(indio_dev,
585 iio_get_time_ns(indio_dev));
586 iio_trigger_notify_done(indio_dev->trig);
588 complete(&info->completion);
594 static ssize_t vf610_show_samp_freq_avail(struct device *dev,
595 struct device_attribute *attr, char *buf)
597 struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
601 for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
602 len += scnprintf(buf + len, PAGE_SIZE - len,
603 "%u ", info->sample_freq_avail[i]);
605 /* replace trailing space by newline */
611 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
613 static struct attribute *vf610_attributes[] = {
614 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
618 static const struct attribute_group vf610_attribute_group = {
619 .attrs = vf610_attributes,
622 static int vf610_read_raw(struct iio_dev *indio_dev,
623 struct iio_chan_spec const *chan,
628 struct vf610_adc *info = iio_priv(indio_dev);
633 case IIO_CHAN_INFO_RAW:
634 case IIO_CHAN_INFO_PROCESSED:
635 mutex_lock(&indio_dev->mlock);
636 if (iio_buffer_enabled(indio_dev)) {
637 mutex_unlock(&indio_dev->mlock);
641 reinit_completion(&info->completion);
642 hc_cfg = VF610_ADC_ADCHC(chan->channel);
643 hc_cfg |= VF610_ADC_AIEN;
644 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
645 ret = wait_for_completion_interruptible_timeout
646 (&info->completion, VF610_ADC_TIMEOUT);
648 mutex_unlock(&indio_dev->mlock);
652 mutex_unlock(&indio_dev->mlock);
656 switch (chan->type) {
662 * Calculate in degree Celsius times 1000
663 * Using the typical sensor slope of 1.84 mV/°C
664 * and VREFH_ADC at 3.3V, V at 25°C of 699 mV
666 *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) *
667 1000000 / VF610_TEMP_SLOPE_COEFF;
671 mutex_unlock(&indio_dev->mlock);
675 mutex_unlock(&indio_dev->mlock);
678 case IIO_CHAN_INFO_SCALE:
679 *val = info->vref_uv / 1000;
680 *val2 = info->adc_feature.res_mode;
681 return IIO_VAL_FRACTIONAL_LOG2;
683 case IIO_CHAN_INFO_SAMP_FREQ:
684 *val = info->sample_freq_avail[info->adc_feature.sample_rate];
695 static int vf610_write_raw(struct iio_dev *indio_dev,
696 struct iio_chan_spec const *chan,
701 struct vf610_adc *info = iio_priv(indio_dev);
705 case IIO_CHAN_INFO_SAMP_FREQ:
707 i < ARRAY_SIZE(info->sample_freq_avail);
709 if (val == info->sample_freq_avail[i]) {
710 info->adc_feature.sample_rate = i;
711 vf610_adc_sample_set(info);
723 static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev)
725 struct vf610_adc *info = iio_priv(indio_dev);
726 unsigned int channel;
730 ret = iio_triggered_buffer_postenable(indio_dev);
734 val = readl(info->regs + VF610_REG_ADC_GC);
735 val |= VF610_ADC_ADCON;
736 writel(val, info->regs + VF610_REG_ADC_GC);
738 channel = find_first_bit(indio_dev->active_scan_mask,
739 indio_dev->masklength);
741 val = VF610_ADC_ADCHC(channel);
742 val |= VF610_ADC_AIEN;
744 writel(val, info->regs + VF610_REG_ADC_HC0);
749 static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev)
751 struct vf610_adc *info = iio_priv(indio_dev);
752 unsigned int hc_cfg = 0;
755 val = readl(info->regs + VF610_REG_ADC_GC);
756 val &= ~VF610_ADC_ADCON;
757 writel(val, info->regs + VF610_REG_ADC_GC);
759 hc_cfg |= VF610_ADC_CONV_DISABLE;
760 hc_cfg &= ~VF610_ADC_AIEN;
762 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
764 return iio_triggered_buffer_predisable(indio_dev);
767 static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
768 .postenable = &vf610_adc_buffer_postenable,
769 .predisable = &vf610_adc_buffer_predisable,
770 .validate_scan_mask = &iio_validate_scan_mask_onehot,
773 static int vf610_adc_reg_access(struct iio_dev *indio_dev,
774 unsigned reg, unsigned writeval,
777 struct vf610_adc *info = iio_priv(indio_dev);
779 if ((readval == NULL) ||
780 ((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
783 *readval = readl(info->regs + reg);
788 static const struct iio_info vf610_adc_iio_info = {
789 .read_raw = &vf610_read_raw,
790 .write_raw = &vf610_write_raw,
791 .debugfs_reg_access = &vf610_adc_reg_access,
792 .attrs = &vf610_attribute_group,
795 static const struct of_device_id vf610_adc_match[] = {
796 { .compatible = "fsl,vf610-adc", },
799 MODULE_DEVICE_TABLE(of, vf610_adc_match);
801 static int vf610_adc_probe(struct platform_device *pdev)
803 struct vf610_adc *info;
804 struct iio_dev *indio_dev;
808 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
810 dev_err(&pdev->dev, "Failed allocating iio device\n");
814 info = iio_priv(indio_dev);
815 info->dev = &pdev->dev;
817 info->regs = devm_platform_ioremap_resource(pdev, 0);
818 if (IS_ERR(info->regs))
819 return PTR_ERR(info->regs);
821 irq = platform_get_irq(pdev, 0);
825 ret = devm_request_irq(info->dev, irq,
827 dev_name(&pdev->dev), indio_dev);
829 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
833 info->clk = devm_clk_get(&pdev->dev, "adc");
834 if (IS_ERR(info->clk)) {
835 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
837 return PTR_ERR(info->clk);
840 info->vref = devm_regulator_get(&pdev->dev, "vref");
841 if (IS_ERR(info->vref))
842 return PTR_ERR(info->vref);
844 ret = regulator_enable(info->vref);
848 info->vref_uv = regulator_get_voltage(info->vref);
850 of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency",
851 info->max_adck_rate, 3);
853 ret = of_property_read_u32(pdev->dev.of_node, "min-sample-time",
854 &info->adc_feature.default_sample_time);
856 info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME;
858 platform_set_drvdata(pdev, indio_dev);
860 init_completion(&info->completion);
862 indio_dev->name = dev_name(&pdev->dev);
863 indio_dev->dev.parent = &pdev->dev;
864 indio_dev->dev.of_node = pdev->dev.of_node;
865 indio_dev->info = &vf610_adc_iio_info;
866 indio_dev->modes = INDIO_DIRECT_MODE;
867 indio_dev->channels = vf610_adc_iio_channels;
868 indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
870 ret = clk_prepare_enable(info->clk);
873 "Could not prepare or enable the clock.\n");
874 goto error_adc_clk_enable;
877 vf610_adc_cfg_init(info);
878 vf610_adc_hw_init(info);
880 ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
881 NULL, &iio_triggered_buffer_setup_ops);
883 dev_err(&pdev->dev, "Couldn't initialise the buffer\n");
884 goto error_iio_device_register;
887 ret = iio_device_register(indio_dev);
889 dev_err(&pdev->dev, "Couldn't register the device.\n");
890 goto error_adc_buffer_init;
895 error_adc_buffer_init:
896 iio_triggered_buffer_cleanup(indio_dev);
897 error_iio_device_register:
898 clk_disable_unprepare(info->clk);
899 error_adc_clk_enable:
900 regulator_disable(info->vref);
905 static int vf610_adc_remove(struct platform_device *pdev)
907 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
908 struct vf610_adc *info = iio_priv(indio_dev);
910 iio_device_unregister(indio_dev);
911 iio_triggered_buffer_cleanup(indio_dev);
912 regulator_disable(info->vref);
913 clk_disable_unprepare(info->clk);
918 #ifdef CONFIG_PM_SLEEP
919 static int vf610_adc_suspend(struct device *dev)
921 struct iio_dev *indio_dev = dev_get_drvdata(dev);
922 struct vf610_adc *info = iio_priv(indio_dev);
925 /* ADC controller enters to stop mode */
926 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
927 hc_cfg |= VF610_ADC_CONV_DISABLE;
928 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
930 clk_disable_unprepare(info->clk);
931 regulator_disable(info->vref);
936 static int vf610_adc_resume(struct device *dev)
938 struct iio_dev *indio_dev = dev_get_drvdata(dev);
939 struct vf610_adc *info = iio_priv(indio_dev);
942 ret = regulator_enable(info->vref);
946 ret = clk_prepare_enable(info->clk);
950 vf610_adc_hw_init(info);
955 regulator_disable(info->vref);
960 static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);
962 static struct platform_driver vf610_adc_driver = {
963 .probe = vf610_adc_probe,
964 .remove = vf610_adc_remove,
967 .of_match_table = vf610_adc_match,
968 .pm = &vf610_adc_pm_ops,
972 module_platform_driver(vf610_adc_driver);
974 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
975 MODULE_DESCRIPTION("Freescale VF610 ADC driver");
976 MODULE_LICENSE("GPL v2");