1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
8 #include <linux/delay.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/mod_devicetable.h>
13 #include <linux/platform_device.h>
14 #include <linux/property.h>
15 #include <linux/iopoll.h>
17 #include <linux/iio/iio.h>
19 /* Register definitions */
20 #define MT6577_AUXADC_CON0 0x00
21 #define MT6577_AUXADC_CON1 0x04
22 #define MT6577_AUXADC_CON2 0x10
23 #define MT6577_AUXADC_STA BIT(0)
25 #define MT6577_AUXADC_DAT0 0x14
26 #define MT6577_AUXADC_RDY0 BIT(12)
28 #define MT6577_AUXADC_MISC 0x94
29 #define MT6577_AUXADC_PDN_EN BIT(14)
31 #define MT6577_AUXADC_DAT_MASK 0xfff
32 #define MT6577_AUXADC_SLEEP_US 1000
33 #define MT6577_AUXADC_TIMEOUT_US 10000
34 #define MT6577_AUXADC_POWER_READY_MS 1
35 #define MT6577_AUXADC_SAMPLE_READY_US 25
37 struct mtk_auxadc_compatible {
38 bool sample_data_cali;
39 bool check_global_idle;
42 struct mt6577_auxadc_device {
43 void __iomem *reg_base;
46 const struct mtk_auxadc_compatible *dev_comp;
49 static const struct mtk_auxadc_compatible mt8186_compat = {
50 .sample_data_cali = false,
51 .check_global_idle = false,
54 static const struct mtk_auxadc_compatible mt8173_compat = {
55 .sample_data_cali = false,
56 .check_global_idle = true,
59 static const struct mtk_auxadc_compatible mt6765_compat = {
60 .sample_data_cali = true,
61 .check_global_idle = false,
64 #define MT6577_AUXADC_CHANNEL(idx) { \
65 .type = IIO_VOLTAGE, \
68 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
71 static const struct iio_chan_spec mt6577_auxadc_iio_channels[] = {
72 MT6577_AUXADC_CHANNEL(0),
73 MT6577_AUXADC_CHANNEL(1),
74 MT6577_AUXADC_CHANNEL(2),
75 MT6577_AUXADC_CHANNEL(3),
76 MT6577_AUXADC_CHANNEL(4),
77 MT6577_AUXADC_CHANNEL(5),
78 MT6577_AUXADC_CHANNEL(6),
79 MT6577_AUXADC_CHANNEL(7),
80 MT6577_AUXADC_CHANNEL(8),
81 MT6577_AUXADC_CHANNEL(9),
82 MT6577_AUXADC_CHANNEL(10),
83 MT6577_AUXADC_CHANNEL(11),
84 MT6577_AUXADC_CHANNEL(12),
85 MT6577_AUXADC_CHANNEL(13),
86 MT6577_AUXADC_CHANNEL(14),
87 MT6577_AUXADC_CHANNEL(15),
90 /* For Voltage calculation */
91 #define VOLTAGE_FULL_RANGE 1500 /* VA voltage */
92 #define AUXADC_PRECISE 4096 /* 12 bits */
94 static int mt_auxadc_get_cali_data(int rawdata, bool enable_cali)
99 static inline void mt6577_auxadc_mod_reg(void __iomem *reg,
100 u32 or_mask, u32 and_mask)
110 static int mt6577_auxadc_read(struct iio_dev *indio_dev,
111 struct iio_chan_spec const *chan)
114 void __iomem *reg_channel;
116 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
118 reg_channel = adc_dev->reg_base + MT6577_AUXADC_DAT0 +
119 chan->channel * 0x04;
121 mutex_lock(&adc_dev->lock);
123 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1,
124 0, 1 << chan->channel);
126 /* read channel and make sure old ready bit == 0 */
127 ret = readl_poll_timeout(reg_channel, val,
128 ((val & MT6577_AUXADC_RDY0) == 0),
129 MT6577_AUXADC_SLEEP_US,
130 MT6577_AUXADC_TIMEOUT_US);
132 dev_err(indio_dev->dev.parent,
133 "wait for channel[%d] ready bit clear time out\n",
138 /* set bit to trigger sample */
139 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1,
140 1 << chan->channel, 0);
142 /* we must delay here for hardware sample channel data */
143 udelay(MT6577_AUXADC_SAMPLE_READY_US);
145 if (adc_dev->dev_comp->check_global_idle) {
146 /* check MTK_AUXADC_CON2 if auxadc is idle */
147 ret = readl_poll_timeout(adc_dev->reg_base + MT6577_AUXADC_CON2,
148 val, ((val & MT6577_AUXADC_STA) == 0),
149 MT6577_AUXADC_SLEEP_US,
150 MT6577_AUXADC_TIMEOUT_US);
152 dev_err(indio_dev->dev.parent,
153 "wait for auxadc idle time out\n");
158 /* read channel and make sure ready bit == 1 */
159 ret = readl_poll_timeout(reg_channel, val,
160 ((val & MT6577_AUXADC_RDY0) != 0),
161 MT6577_AUXADC_SLEEP_US,
162 MT6577_AUXADC_TIMEOUT_US);
164 dev_err(indio_dev->dev.parent,
165 "wait for channel[%d] data ready time out\n",
171 val = readl(reg_channel) & MT6577_AUXADC_DAT_MASK;
173 mutex_unlock(&adc_dev->lock);
179 mutex_unlock(&adc_dev->lock);
184 static int mt6577_auxadc_read_raw(struct iio_dev *indio_dev,
185 struct iio_chan_spec const *chan,
190 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
193 case IIO_CHAN_INFO_PROCESSED:
194 *val = mt6577_auxadc_read(indio_dev, chan);
196 dev_err(indio_dev->dev.parent,
197 "failed to sample data on channel[%d]\n",
201 if (adc_dev->dev_comp->sample_data_cali)
202 *val = mt_auxadc_get_cali_data(*val, true);
204 /* Convert adc raw data to voltage: 0 - 1500 mV */
205 *val = *val * VOLTAGE_FULL_RANGE / AUXADC_PRECISE;
214 static const struct iio_info mt6577_auxadc_info = {
215 .read_raw = &mt6577_auxadc_read_raw,
218 static int mt6577_auxadc_resume(struct device *dev)
220 struct iio_dev *indio_dev = dev_get_drvdata(dev);
221 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
224 ret = clk_prepare_enable(adc_dev->adc_clk);
226 pr_err("failed to enable auxadc clock\n");
230 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
231 MT6577_AUXADC_PDN_EN, 0);
232 mdelay(MT6577_AUXADC_POWER_READY_MS);
237 static int mt6577_auxadc_suspend(struct device *dev)
239 struct iio_dev *indio_dev = dev_get_drvdata(dev);
240 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
242 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
243 0, MT6577_AUXADC_PDN_EN);
244 clk_disable_unprepare(adc_dev->adc_clk);
249 static int mt6577_auxadc_probe(struct platform_device *pdev)
251 struct mt6577_auxadc_device *adc_dev;
252 unsigned long adc_clk_rate;
253 struct iio_dev *indio_dev;
256 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
260 adc_dev = iio_priv(indio_dev);
261 indio_dev->name = dev_name(&pdev->dev);
262 indio_dev->info = &mt6577_auxadc_info;
263 indio_dev->modes = INDIO_DIRECT_MODE;
264 indio_dev->channels = mt6577_auxadc_iio_channels;
265 indio_dev->num_channels = ARRAY_SIZE(mt6577_auxadc_iio_channels);
267 adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
268 if (IS_ERR(adc_dev->reg_base)) {
269 dev_err(&pdev->dev, "failed to get auxadc base address\n");
270 return PTR_ERR(adc_dev->reg_base);
273 adc_dev->adc_clk = devm_clk_get(&pdev->dev, "main");
274 if (IS_ERR(adc_dev->adc_clk)) {
275 dev_err(&pdev->dev, "failed to get auxadc clock\n");
276 return PTR_ERR(adc_dev->adc_clk);
279 ret = clk_prepare_enable(adc_dev->adc_clk);
281 dev_err(&pdev->dev, "failed to enable auxadc clock\n");
285 adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
288 dev_err(&pdev->dev, "null clock rate\n");
289 goto err_disable_clk;
292 adc_dev->dev_comp = device_get_match_data(&pdev->dev);
294 mutex_init(&adc_dev->lock);
296 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
297 MT6577_AUXADC_PDN_EN, 0);
298 mdelay(MT6577_AUXADC_POWER_READY_MS);
300 platform_set_drvdata(pdev, indio_dev);
302 ret = iio_device_register(indio_dev);
304 dev_err(&pdev->dev, "failed to register iio device\n");
311 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
312 0, MT6577_AUXADC_PDN_EN);
314 clk_disable_unprepare(adc_dev->adc_clk);
318 static int mt6577_auxadc_remove(struct platform_device *pdev)
320 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
321 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
323 iio_device_unregister(indio_dev);
325 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
326 0, MT6577_AUXADC_PDN_EN);
328 clk_disable_unprepare(adc_dev->adc_clk);
333 static DEFINE_SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops,
334 mt6577_auxadc_suspend,
335 mt6577_auxadc_resume);
337 static const struct of_device_id mt6577_auxadc_of_match[] = {
338 { .compatible = "mediatek,mt2701-auxadc", .data = &mt8173_compat },
339 { .compatible = "mediatek,mt2712-auxadc", .data = &mt8173_compat },
340 { .compatible = "mediatek,mt7622-auxadc", .data = &mt8173_compat },
341 { .compatible = "mediatek,mt8173-auxadc", .data = &mt8173_compat },
342 { .compatible = "mediatek,mt8186-auxadc", .data = &mt8186_compat },
343 { .compatible = "mediatek,mt6765-auxadc", .data = &mt6765_compat },
346 MODULE_DEVICE_TABLE(of, mt6577_auxadc_of_match);
348 static struct platform_driver mt6577_auxadc_driver = {
350 .name = "mt6577-auxadc",
351 .of_match_table = mt6577_auxadc_of_match,
352 .pm = pm_sleep_ptr(&mt6577_auxadc_pm_ops),
354 .probe = mt6577_auxadc_probe,
355 .remove = mt6577_auxadc_remove,
357 module_platform_driver(mt6577_auxadc_driver);
359 MODULE_AUTHOR("Zhiyong Tao <zhiyong.tao@mediatek.com>");
360 MODULE_DESCRIPTION("MTK AUXADC Device Driver");
361 MODULE_LICENSE("GPL v2");