drivers/iio/adc/meson_saradc.c

   1 /*
   2  * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
   3  *
   4  * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * You should have received a copy of the GNU General Public License
  11  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  12  */
  13
  14 #include <linux/bitfield.h>
  15 #include <linux/clk.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/iio/iio.h>
  20 #include <linux/module.h>
  21 #include <linux/nvmem-consumer.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/of.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/regmap.h>
  28 #include <linux/regulator/consumer.h>
  29
  30 #define MESON_SAR_ADC_REG0                                      0x00
  31         #define MESON_SAR_ADC_REG0_PANEL_DETECT                 BIT(31)
  32         #define MESON_SAR_ADC_REG0_BUSY_MASK                    GENMASK(30, 28)
  33         #define MESON_SAR_ADC_REG0_DELTA_BUSY                   BIT(30)
  34         #define MESON_SAR_ADC_REG0_AVG_BUSY                     BIT(29)
  35         #define MESON_SAR_ADC_REG0_SAMPLE_BUSY                  BIT(28)
  36         #define MESON_SAR_ADC_REG0_FIFO_FULL                    BIT(27)
  37         #define MESON_SAR_ADC_REG0_FIFO_EMPTY                   BIT(26)
  38         #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK              GENMASK(25, 21)
  39         #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK           GENMASK(20, 19)
  40         #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK            GENMASK(18, 16)
  41         #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL             BIT(15)
  42         #define MESON_SAR_ADC_REG0_SAMPLING_STOP                BIT(14)
  43         #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK           GENMASK(13, 12)
  44         #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL               BIT(10)
  45         #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN                BIT(9)
  46         #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK            GENMASK(8, 4)
  47         #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN                  BIT(3)
  48         #define MESON_SAR_ADC_REG0_SAMPLING_START               BIT(2)
  49         #define MESON_SAR_ADC_REG0_CONTINUOUS_EN                BIT(1)
  50         #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE         BIT(0)
  51
  52 #define MESON_SAR_ADC_CHAN_LIST                                 0x04
  53         #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK          GENMASK(26, 24)
  54         #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan)       \
  55                                         (GENMASK(2, 0) << ((_chan) * 3))
  56
  57 #define MESON_SAR_ADC_AVG_CNTL                                  0x08
  58         #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan)    \
  59                                         (16 + ((_chan) * 2))
  60         #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan)     \
  61                                         (GENMASK(17, 16) << ((_chan) * 2))
  62         #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
  63                                         (0 + ((_chan) * 2))
  64         #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan)  \
  65                                         (GENMASK(1, 0) << ((_chan) * 2))
  66
  67 #define MESON_SAR_ADC_REG3                                      0x0c
  68         #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY              BIT(31)
  69         #define MESON_SAR_ADC_REG3_CLK_EN                       BIT(30)
  70         #define MESON_SAR_ADC_REG3_BL30_INITIALIZED             BIT(28)
  71         #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN    BIT(27)
  72         #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE    BIT(26)
  73         #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK      GENMASK(25, 23)
  74         #define MESON_SAR_ADC_REG3_DETECT_EN                    BIT(22)
  75         #define MESON_SAR_ADC_REG3_ADC_EN                       BIT(21)
  76         #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK      GENMASK(20, 18)
  77         #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK  GENMASK(17, 16)
  78         #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT            10
  79         #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH            5
  80         #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK           GENMASK(9, 8)
  81         #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK               GENMASK(7, 0)
  82
  83 #define MESON_SAR_ADC_DELAY                                     0x10
  84         #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK          GENMASK(25, 24)
  85         #define MESON_SAR_ADC_DELAY_BL30_BUSY                   BIT(15)
  86         #define MESON_SAR_ADC_DELAY_KERNEL_BUSY                 BIT(14)
  87         #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK          GENMASK(23, 16)
  88         #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK         GENMASK(9, 8)
  89         #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK         GENMASK(7, 0)
  90
  91 #define MESON_SAR_ADC_LAST_RD                                   0x14
  92         #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK        GENMASK(23, 16)
  93         #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK        GENMASK(9, 0)
  94
  95 #define MESON_SAR_ADC_FIFO_RD                                   0x18
  96         #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK              GENMASK(14, 12)
  97         #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK         GENMASK(11, 0)
  98
  99 #define MESON_SAR_ADC_AUX_SW                                    0x1c
 100         #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan)  \
 101                                         (8 + (((_chan) - 2) * 3))
 102         #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX                 BIT(6)
 103         #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX                 BIT(5)
 104         #define MESON_SAR_ADC_AUX_SW_MODE_SEL                   BIT(4)
 105         #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW                BIT(3)
 106         #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW                BIT(2)
 107         #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW                BIT(1)
 108         #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW                BIT(0)
 109
 110 #define MESON_SAR_ADC_CHAN_10_SW                                0x20
 111         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK     GENMASK(25, 23)
 112         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX       BIT(22)
 113         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX       BIT(21)
 114         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL         BIT(20)
 115         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW      BIT(19)
 116         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW      BIT(18)
 117         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW      BIT(17)
 118         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW      BIT(16)
 119         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK     GENMASK(9, 7)
 120         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX       BIT(6)
 121         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX       BIT(5)
 122         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL         BIT(4)
 123         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW      BIT(3)
 124         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW      BIT(2)
 125         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW      BIT(1)
 126         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW      BIT(0)
 127
 128 #define MESON_SAR_ADC_DETECT_IDLE_SW                            0x24
 129         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN       BIT(26)
 130         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK    GENMASK(25, 23)
 131         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX  BIT(22)
 132         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX  BIT(21)
 133         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL    BIT(20)
 134         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
 135         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
 136         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
 137         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
 138         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK  GENMASK(9, 7)
 139         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX    BIT(6)
 140         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX    BIT(5)
 141         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL      BIT(4)
 142         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW   BIT(3)
 143         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW   BIT(2)
 144         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW   BIT(1)
 145         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW   BIT(0)
 146
 147 #define MESON_SAR_ADC_DELTA_10                                  0x28
 148         #define MESON_SAR_ADC_DELTA_10_TEMP_SEL                 BIT(27)
 149         #define MESON_SAR_ADC_DELTA_10_TS_REVE1                 BIT(26)
 150         #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK   GENMASK(25, 16)
 151         #define MESON_SAR_ADC_DELTA_10_TS_REVE0                 BIT(15)
 152         #define MESON_SAR_ADC_DELTA_10_TS_C_MASK                GENMASK(14, 11)
 153         #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN                BIT(10)
 154         #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK   GENMASK(9, 0)
 155
 156 /*
 157  * NOTE: registers from here are undocumented (the vendor Linux kernel driver
 158  * and u-boot source served as reference). These only seem to be relevant on
 159  * GXBB and newer.
 160  */
 161 #define MESON_SAR_ADC_REG11                                     0x2c
 162         #define MESON_SAR_ADC_REG11_BANDGAP_EN                  BIT(13)
 163
 164 #define MESON_SAR_ADC_REG13                                     0x34
 165         #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK      GENMASK(13, 8)
 166
 167 #define MESON_SAR_ADC_MAX_FIFO_SIZE                             32
 168 #define MESON_SAR_ADC_TIMEOUT                                   100 /* ms */
 169 #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL                  6
 170 #define MESON_SAR_ADC_TEMP_OFFSET                               27
 171
 172 /* temperature sensor calibration information in eFuse */
 173 #define MESON_SAR_ADC_EFUSE_BYTES                               4
 174 #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL                 GENMASK(6, 0)
 175 #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED                 BIT(7)
 176
 177 /* for use with IIO_VAL_INT_PLUS_MICRO */
 178 #define MILLION                                                 1000000
 179
 180 #define MESON_SAR_ADC_CHAN(_chan) {                                     \
 181         .type = IIO_VOLTAGE,                                            \
 182         .indexed = 1,                                                   \
 183         .channel = _chan,                                               \
 184         .address = _chan,                                               \
 185         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 186                                 BIT(IIO_CHAN_INFO_AVERAGE_RAW),         \
 187         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),           \
 188         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) |       \
 189                                 BIT(IIO_CHAN_INFO_CALIBSCALE),          \
 190         .datasheet_name = "SAR_ADC_CH"#_chan,                           \
 191 }
 192
 193 #define MESON_SAR_ADC_TEMP_CHAN(_chan) {                                \
 194         .type = IIO_TEMP,                                               \
 195         .channel = _chan,                                               \
 196         .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL,              \
 197         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 198                                 BIT(IIO_CHAN_INFO_AVERAGE_RAW),         \
 199         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |         \
 200                                         BIT(IIO_CHAN_INFO_SCALE),       \
 201         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) |       \
 202                                 BIT(IIO_CHAN_INFO_CALIBSCALE),          \
 203         .datasheet_name = "TEMP_SENSOR",                                \
 204 }
 205
 206 static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
 207         MESON_SAR_ADC_CHAN(0),
 208         MESON_SAR_ADC_CHAN(1),
 209         MESON_SAR_ADC_CHAN(2),
 210         MESON_SAR_ADC_CHAN(3),
 211         MESON_SAR_ADC_CHAN(4),
 212         MESON_SAR_ADC_CHAN(5),
 213         MESON_SAR_ADC_CHAN(6),
 214         MESON_SAR_ADC_CHAN(7),
 215         IIO_CHAN_SOFT_TIMESTAMP(8),
 216 };
 217
 218 static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {
 219         MESON_SAR_ADC_CHAN(0),
 220         MESON_SAR_ADC_CHAN(1),
 221         MESON_SAR_ADC_CHAN(2),
 222         MESON_SAR_ADC_CHAN(3),
 223         MESON_SAR_ADC_CHAN(4),
 224         MESON_SAR_ADC_CHAN(5),
 225         MESON_SAR_ADC_CHAN(6),
 226         MESON_SAR_ADC_CHAN(7),
 227         MESON_SAR_ADC_TEMP_CHAN(8),
 228         IIO_CHAN_SOFT_TIMESTAMP(9),
 229 };
 230
 231 enum meson_sar_adc_avg_mode {
 232         NO_AVERAGING = 0x0,
 233         MEAN_AVERAGING = 0x1,
 234         MEDIAN_AVERAGING = 0x2,
 235 };
 236
 237 enum meson_sar_adc_num_samples {
 238         ONE_SAMPLE = 0x0,
 239         TWO_SAMPLES = 0x1,
 240         FOUR_SAMPLES = 0x2,
 241         EIGHT_SAMPLES = 0x3,
 242 };
 243
 244 enum meson_sar_adc_chan7_mux_sel {
 245         CHAN7_MUX_VSS = 0x0,
 246         CHAN7_MUX_VDD_DIV4 = 0x1,
 247         CHAN7_MUX_VDD_DIV2 = 0x2,
 248         CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
 249         CHAN7_MUX_VDD = 0x4,
 250         CHAN7_MUX_CH7_INPUT = 0x7,
 251 };
 252
 253 struct meson_sar_adc_param {
 254         bool                                    has_bl30_integration;
 255         unsigned long                           clock_rate;
 256         u32                                     bandgap_reg;
 257         unsigned int                            resolution;
 258         const struct regmap_config              *regmap_config;
 259         u8                                      temperature_trimming_bits;
 260         unsigned int                            temperature_multiplier;
 261         unsigned int                            temperature_divider;
 262 };
 263
 264 struct meson_sar_adc_data {
 265         const struct meson_sar_adc_param        *param;
 266         const char                              *name;
 267 };
 268
 269 struct meson_sar_adc_priv {
 270         struct regmap                           *regmap;
 271         struct regulator                        *vref;
 272         const struct meson_sar_adc_param        *param;
 273         struct clk                              *clkin;
 274         struct clk                              *core_clk;
 275         struct clk                              *adc_sel_clk;
 276         struct clk                              *adc_clk;
 277         struct clk_gate                         clk_gate;
 278         struct clk                              *adc_div_clk;
 279         struct clk_divider                      clk_div;
 280         struct completion                       done;
 281         int                                     calibbias;
 282         int                                     calibscale;
 283         bool                                    temperature_sensor_calibrated;
 284         u8                                      temperature_sensor_coefficient;
 285         u16                                     temperature_sensor_adc_val;
 286 };
 287
 288 static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {
 289         .reg_bits = 8,
 290         .val_bits = 32,
 291         .reg_stride = 4,
 292         .max_register = MESON_SAR_ADC_REG13,
 293 };
 294
 295 static const struct regmap_config meson_sar_adc_regmap_config_meson8 = {
 296         .reg_bits = 8,
 297         .val_bits = 32,
 298         .reg_stride = 4,
 299         .max_register = MESON_SAR_ADC_DELTA_10,
 300 };
 301
 302 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
 303 {
 304         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 305         u32 regval;
 306
 307         regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
 308
 309         return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
 310 }
 311
 312 static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val)
 313 {
 314         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 315         int tmp;
 316
 317         /* use val_calib = scale * val_raw + offset calibration function */
 318         tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
 319
 320         return clamp(tmp, 0, (1 << priv->param->resolution) - 1);
 321 }
 322
 323 static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
 324 {
 325         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 326         int regval, timeout = 10000;
 327
 328         /*
 329          * NOTE: we need a small delay before reading the status, otherwise
 330          * the sample engine may not have started internally (which would
 331          * seem to us that sampling is already finished).
 332          */
 333         do {
 334                 udelay(1);
 335                 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
 336         } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
 337
 338         if (timeout < 0)
 339                 return -ETIMEDOUT;
 340
 341         return 0;
 342 }
 343
 344 static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
 345                                          const struct iio_chan_spec *chan,
 346                                          int *val)
 347 {
 348         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 349         int regval, fifo_chan, fifo_val, count;
 350
 351         if(!wait_for_completion_timeout(&priv->done,
 352                                 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT)))
 353                 return -ETIMEDOUT;
 354
 355         count = meson_sar_adc_get_fifo_count(indio_dev);
 356         if (count != 1) {
 357                 dev_err(&indio_dev->dev,
 358                         "ADC FIFO has %d element(s) instead of one\n", count);
 359                 return -EINVAL;
 360         }
 361
 362         regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);
 363         fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
 364         if (fifo_chan != chan->address) {
 365                 dev_err(&indio_dev->dev,
 366                         "ADC FIFO entry belongs to channel %d instead of %lu\n",
 367                         fifo_chan, chan->address);
 368                 return -EINVAL;
 369         }
 370
 371         fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
 372         fifo_val &= GENMASK(priv->param->resolution - 1, 0);
 373         *val = meson_sar_adc_calib_val(indio_dev, fifo_val);
 374
 375         return 0;
 376 }
 377
 378 static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
 379                                         const struct iio_chan_spec *chan,
 380                                         enum meson_sar_adc_avg_mode mode,
 381                                         enum meson_sar_adc_num_samples samples)
 382 {
 383         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 384         int val, address = chan->address;
 385
 386         val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address);
 387         regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
 388                            MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address),
 389                            val);
 390
 391         val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address);
 392         regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
 393                            MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val);
 394 }
 395
 396 static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
 397                                         const struct iio_chan_spec *chan)
 398 {
 399         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 400         u32 regval;
 401
 402         /*
 403          * the SAR ADC engine allows sampling multiple channels at the same
 404          * time. to keep it simple we're only working with one *internal*
 405          * channel, which starts counting at index 0 (which means: count = 1).
 406          */
 407         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
 408         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
 409                            MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
 410
 411         /* map channel index 0 to the channel which we want to read */
 412         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
 413                             chan->address);
 414         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
 415                            MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
 416
 417         regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
 418                             chan->address);
 419         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
 420                            MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
 421                            regval);
 422
 423         regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
 424                             chan->address);
 425         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
 426                            MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
 427                            regval);
 428
 429         if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) {
 430                 if (chan->type == IIO_TEMP)
 431                         regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL;
 432                 else
 433                         regval = 0;
 434
 435                 regmap_update_bits(priv->regmap,
 436                                    MESON_SAR_ADC_DELTA_10,
 437                                    MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval);
 438         }
 439 }
 440
 441 static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
 442                                         enum meson_sar_adc_chan7_mux_sel sel)
 443 {
 444         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 445         u32 regval;
 446
 447         regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
 448         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 449                            MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
 450
 451         usleep_range(10, 20);
 452 }
 453
 454 static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
 455 {
 456         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 457
 458         reinit_completion(&priv->done);
 459
 460         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 461                            MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
 462                            MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
 463
 464         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 465                            MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
 466                            MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
 467
 468         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 469                            MESON_SAR_ADC_REG0_SAMPLING_START,
 470                            MESON_SAR_ADC_REG0_SAMPLING_START);
 471 }
 472
 473 static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
 474 {
 475         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 476
 477         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 478                            MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
 479
 480         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 481                            MESON_SAR_ADC_REG0_SAMPLING_STOP,
 482                            MESON_SAR_ADC_REG0_SAMPLING_STOP);
 483
 484         /* wait until all modules are stopped */
 485         meson_sar_adc_wait_busy_clear(indio_dev);
 486
 487         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 488                            MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
 489 }
 490
 491 static int meson_sar_adc_lock(struct iio_dev *indio_dev)
 492 {
 493         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 494         int val, timeout = 10000;
 495
 496         mutex_lock(&indio_dev->mlock);
 497
 498         if (priv->param->has_bl30_integration) {
 499                 /* prevent BL30 from using the SAR ADC while we are using it */
 500                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 501                                 MESON_SAR_ADC_DELAY_KERNEL_BUSY,
 502                                 MESON_SAR_ADC_DELAY_KERNEL_BUSY);
 503
 504                 /*
 505                  * wait until BL30 releases it's lock (so we can use the SAR
 506                  * ADC)
 507                  */
 508                 do {
 509                         udelay(1);
 510                         regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
 511                 } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
 512
 513                 if (timeout < 0) {
 514                         mutex_unlock(&indio_dev->mlock);
 515                         return -ETIMEDOUT;
 516                 }
 517         }
 518
 519         return 0;
 520 }
 521
 522 static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
 523 {
 524         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 525
 526         if (priv->param->has_bl30_integration)
 527                 /* allow BL30 to use the SAR ADC again */
 528                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 529                                 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
 530
 531         mutex_unlock(&indio_dev->mlock);
 532 }
 533
 534 static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
 535 {
 536         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 537         unsigned int count, tmp;
 538
 539         for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
 540                 if (!meson_sar_adc_get_fifo_count(indio_dev))
 541                         break;
 542
 543                 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
 544         }
 545 }
 546
 547 static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
 548                                     const struct iio_chan_spec *chan,
 549                                     enum meson_sar_adc_avg_mode avg_mode,
 550                                     enum meson_sar_adc_num_samples avg_samples,
 551                                     int *val)
 552 {
 553         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 554         int ret;
 555
 556         if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)
 557                 return -ENOTSUPP;
 558
 559         ret = meson_sar_adc_lock(indio_dev);
 560         if (ret)
 561                 return ret;
 562
 563         /* clear the FIFO to make sure we're not reading old values */
 564         meson_sar_adc_clear_fifo(indio_dev);
 565
 566         meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
 567
 568         meson_sar_adc_enable_channel(indio_dev, chan);
 569
 570         meson_sar_adc_start_sample_engine(indio_dev);
 571         ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
 572         meson_sar_adc_stop_sample_engine(indio_dev);
 573
 574         meson_sar_adc_unlock(indio_dev);
 575
 576         if (ret) {
 577                 dev_warn(indio_dev->dev.parent,
 578                          "failed to read sample for channel %lu: %d\n",
 579                          chan->address, ret);
 580                 return ret;
 581         }
 582
 583         return IIO_VAL_INT;
 584 }
 585
 586 static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
 587                                            const struct iio_chan_spec *chan,
 588                                            int *val, int *val2, long mask)
 589 {
 590         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 591         int ret;
 592
 593         switch (mask) {
 594         case IIO_CHAN_INFO_RAW:
 595                 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
 596                                                 ONE_SAMPLE, val);
 597                 break;
 598
 599         case IIO_CHAN_INFO_AVERAGE_RAW:
 600                 return meson_sar_adc_get_sample(indio_dev, chan,
 601                                                 MEAN_AVERAGING, EIGHT_SAMPLES,
 602                                                 val);
 603                 break;
 604
 605         case IIO_CHAN_INFO_SCALE:
 606                 if (chan->type == IIO_VOLTAGE) {
 607                         ret = regulator_get_voltage(priv->vref);
 608                         if (ret < 0) {
 609                                 dev_err(indio_dev->dev.parent,
 610                                         "failed to get vref voltage: %d\n",
 611                                         ret);
 612                                 return ret;
 613                         }
 614
 615                         *val = ret / 1000;
 616                         *val2 = priv->param->resolution;
 617                         return IIO_VAL_FRACTIONAL_LOG2;
 618                 } else if (chan->type == IIO_TEMP) {
 619                         /* SoC specific multiplier and divider */
 620                         *val = priv->param->temperature_multiplier;
 621                         *val2 = priv->param->temperature_divider;
 622
 623                         /* celsius to millicelsius */
 624                         *val *= 1000;
 625
 626                         return IIO_VAL_FRACTIONAL;
 627                 } else {
 628                         return -EINVAL;
 629                 }
 630
 631         case IIO_CHAN_INFO_CALIBBIAS:
 632                 *val = priv->calibbias;
 633                 return IIO_VAL_INT;
 634
 635         case IIO_CHAN_INFO_CALIBSCALE:
 636                 *val = priv->calibscale / MILLION;
 637                 *val2 = priv->calibscale % MILLION;
 638                 return IIO_VAL_INT_PLUS_MICRO;
 639
 640         case IIO_CHAN_INFO_OFFSET:
 641                 *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET *
 642                                          priv->param->temperature_divider,
 643                                          priv->param->temperature_multiplier);
 644                 *val -= priv->temperature_sensor_adc_val;
 645                 return IIO_VAL_INT;
 646
 647         default:
 648                 return -EINVAL;
 649         }
 650 }
 651
 652 static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
 653                                   void __iomem *base)
 654 {
 655         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 656         struct clk_init_data init;
 657         const char *clk_parents[1];
 658
 659         init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
 660                                    dev_name(indio_dev->dev.parent));
 661         if (!init.name)
 662                 return -ENOMEM;
 663
 664         init.flags = 0;
 665         init.ops = &clk_divider_ops;
 666         clk_parents[0] = __clk_get_name(priv->clkin);
 667         init.parent_names = clk_parents;
 668         init.num_parents = 1;
 669
 670         priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
 671         priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
 672         priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
 673         priv->clk_div.hw.init = &init;
 674         priv->clk_div.flags = 0;
 675
 676         priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
 677                                               &priv->clk_div.hw);
 678         if (WARN_ON(IS_ERR(priv->adc_div_clk)))
 679                 return PTR_ERR(priv->adc_div_clk);
 680
 681         init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
 682                                    dev_name(indio_dev->dev.parent));
 683         if (!init.name)
 684                 return -ENOMEM;
 685
 686         init.flags = CLK_SET_RATE_PARENT;
 687         init.ops = &clk_gate_ops;
 688         clk_parents[0] = __clk_get_name(priv->adc_div_clk);
 689         init.parent_names = clk_parents;
 690         init.num_parents = 1;
 691
 692         priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
 693         priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
 694         priv->clk_gate.hw.init = &init;
 695
 696         priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
 697         if (WARN_ON(IS_ERR(priv->adc_clk)))
 698                 return PTR_ERR(priv->adc_clk);
 699
 700         return 0;
 701 }
 702
 703 static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev)
 704 {
 705         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 706         u8 *buf, trimming_bits, trimming_mask, upper_adc_val;
 707         struct nvmem_cell *temperature_calib;
 708         size_t read_len;
 709         int ret;
 710
 711         temperature_calib = devm_nvmem_cell_get(&indio_dev->dev,
 712                                                 "temperature_calib");
 713         if (IS_ERR(temperature_calib)) {
 714                 ret = PTR_ERR(temperature_calib);
 715
 716                 /*
 717                  * leave the temperature sensor disabled if no calibration data
 718                  * was passed via nvmem-cells.
 719                  */
 720                 if (ret == -ENODEV)
 721                         return 0;
 722
 723                 if (ret != -EPROBE_DEFER)
 724                         dev_err(indio_dev->dev.parent,
 725                                 "failed to get temperature_calib cell\n");
 726
 727                 return ret;
 728         }
 729
 730         read_len = MESON_SAR_ADC_EFUSE_BYTES;
 731         buf = nvmem_cell_read(temperature_calib, &read_len);
 732         if (IS_ERR(buf)) {
 733                 dev_err(indio_dev->dev.parent,
 734                         "failed to read temperature_calib cell\n");
 735                 return PTR_ERR(buf);
 736         } else if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {
 737                 kfree(buf);
 738                 dev_err(indio_dev->dev.parent,
 739                         "invalid read size of temperature_calib cell\n");
 740                 return -EINVAL;
 741         }
 742
 743         trimming_bits = priv->param->temperature_trimming_bits;
 744         trimming_mask = BIT(trimming_bits) - 1;
 745
 746         priv->temperature_sensor_calibrated =
 747                 buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED;
 748         priv->temperature_sensor_coefficient = buf[2] & trimming_mask;
 749
 750         upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL,
 751                                   buf[3]);
 752
 753         priv->temperature_sensor_adc_val = buf[2];
 754         priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE;
 755         priv->temperature_sensor_adc_val >>= trimming_bits;
 756
 757         kfree(buf);
 758
 759         return 0;
 760 }
 761
 762 static int meson_sar_adc_init(struct iio_dev *indio_dev)
 763 {
 764         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 765         int regval, i, ret;
 766
 767         /*
 768          * make sure we start at CH7 input since the other muxes are only used
 769          * for internal calibration.
 770          */
 771         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
 772
 773         if (priv->param->has_bl30_integration) {
 774                 /*
 775                  * leave sampling delay and the input clocks as configured by
 776                  * BL30 to make sure BL30 gets the values it expects when
 777                  * reading the temperature sensor.
 778                  */
 779                 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
 780                 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
 781                         return 0;
 782         }
 783
 784         meson_sar_adc_stop_sample_engine(indio_dev);
 785
 786         /*
 787          * disable this bit as seems to be only relevant for Meson6 (based
 788          * on the vendor driver), which we don't support at the moment.
 789          */
 790         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 791                         MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, 0);
 792
 793         /* disable all channels by default */
 794         regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
 795
 796         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 797                            MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
 798         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 799                            MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
 800                            MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
 801
 802         /* delay between two samples = (10+1) * 1uS */
 803         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 804                            MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
 805                            FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
 806                                       10));
 807         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 808                            MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
 809                            FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
 810                                       0));
 811
 812         /* delay between two samples = (10+1) * 1uS */
 813         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 814                            MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
 815                            FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
 816                                       10));
 817         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 818                            MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
 819                            FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
 820                                       1));
 821
 822         /*
 823          * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
 824          * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
 825          */
 826         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
 827         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
 828                            MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
 829                            regval);
 830         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
 831         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
 832                            MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
 833                            regval);
 834
 835         /*
 836          * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
 837          * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
 838          * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
 839          * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
 840          */
 841         regval = 0;
 842         for (i = 2; i <= 7; i++)
 843                 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
 844         regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
 845         regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
 846         regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
 847
 848         if (priv->temperature_sensor_calibrated) {
 849                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 850                                    MESON_SAR_ADC_DELTA_10_TS_REVE1,
 851                                    MESON_SAR_ADC_DELTA_10_TS_REVE1);
 852                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 853                                    MESON_SAR_ADC_DELTA_10_TS_REVE0,
 854                                    MESON_SAR_ADC_DELTA_10_TS_REVE0);
 855
 856                 /*
 857                  * set bits [3:0] of the TSC (temperature sensor coefficient)
 858                  * to get the correct values when reading the temperature.
 859                  */
 860                 regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK,
 861                                     priv->temperature_sensor_coefficient);
 862                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 863                                    MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval);
 864         } else {
 865                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 866                                    MESON_SAR_ADC_DELTA_10_TS_REVE1, 0);
 867                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 868                                    MESON_SAR_ADC_DELTA_10_TS_REVE0, 0);
 869         }
 870
 871         ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
 872         if (ret) {
 873                 dev_err(indio_dev->dev.parent,
 874                         "failed to set adc parent to clkin\n");
 875                 return ret;
 876         }
 877
 878         ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate);
 879         if (ret) {
 880                 dev_err(indio_dev->dev.parent,
 881                         "failed to set adc clock rate\n");
 882                 return ret;
 883         }
 884
 885         return 0;
 886 }
 887
 888 static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
 889 {
 890         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 891         const struct meson_sar_adc_param *param = priv->param;
 892         u32 enable_mask;
 893
 894         if (param->bandgap_reg == MESON_SAR_ADC_REG11)
 895                 enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;
 896         else
 897                 enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;
 898
 899         regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask,
 900                            on_off ? enable_mask : 0);
 901 }
 902
 903 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
 904 {
 905         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 906         int ret;
 907         u32 regval;
 908
 909         ret = meson_sar_adc_lock(indio_dev);
 910         if (ret)
 911                 goto err_lock;
 912
 913         ret = regulator_enable(priv->vref);
 914         if (ret < 0) {
 915                 dev_err(indio_dev->dev.parent,
 916                         "failed to enable vref regulator\n");
 917                 goto err_vref;
 918         }
 919
 920         ret = clk_prepare_enable(priv->core_clk);
 921         if (ret) {
 922                 dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
 923                 goto err_core_clk;
 924         }
 925
 926         regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
 927         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 928                            MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
 929
 930         meson_sar_adc_set_bandgap(indio_dev, true);
 931
 932         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 933                            MESON_SAR_ADC_REG3_ADC_EN,
 934                            MESON_SAR_ADC_REG3_ADC_EN);
 935
 936         udelay(5);
 937
 938         ret = clk_prepare_enable(priv->adc_clk);
 939         if (ret) {
 940                 dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
 941                 goto err_adc_clk;
 942         }
 943
 944         meson_sar_adc_unlock(indio_dev);
 945
 946         return 0;
 947
 948 err_adc_clk:
 949         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 950                            MESON_SAR_ADC_REG3_ADC_EN, 0);
 951         meson_sar_adc_set_bandgap(indio_dev, false);
 952         clk_disable_unprepare(priv->core_clk);
 953 err_core_clk:
 954         regulator_disable(priv->vref);
 955 err_vref:
 956         meson_sar_adc_unlock(indio_dev);
 957 err_lock:
 958         return ret;
 959 }
 960
 961 static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
 962 {
 963         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 964         int ret;
 965
 966         ret = meson_sar_adc_lock(indio_dev);
 967         if (ret)
 968                 return ret;
 969
 970         clk_disable_unprepare(priv->adc_clk);
 971
 972         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 973                            MESON_SAR_ADC_REG3_ADC_EN, 0);
 974
 975         meson_sar_adc_set_bandgap(indio_dev, false);
 976
 977         clk_disable_unprepare(priv->core_clk);
 978
 979         regulator_disable(priv->vref);
 980
 981         meson_sar_adc_unlock(indio_dev);
 982
 983         return 0;
 984 }
 985
 986 static irqreturn_t meson_sar_adc_irq(int irq, void *data)
 987 {
 988         struct iio_dev *indio_dev = data;
 989         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 990         unsigned int cnt, threshold;
 991         u32 regval;
 992
 993         regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
 994         cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
 995         threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
 996
 997         if (cnt < threshold)
 998                 return IRQ_NONE;
 999
1000         complete(&priv->done);
1001
1002         return IRQ_HANDLED;
1003 }
1004
1005 static int meson_sar_adc_calib(struct iio_dev *indio_dev)
1006 {
1007         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1008         int ret, nominal0, nominal1, value0, value1;
1009
1010         /* use points 25% and 75% for calibration */
1011         nominal0 = (1 << priv->param->resolution) / 4;
1012         nominal1 = (1 << priv->param->resolution) * 3 / 4;
1013
1014         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4);
1015         usleep_range(10, 20);
1016         ret = meson_sar_adc_get_sample(indio_dev,
1017                                        &indio_dev->channels[7],
1018                                        MEAN_AVERAGING, EIGHT_SAMPLES, &value0);
1019         if (ret < 0)
1020                 goto out;
1021
1022         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4);
1023         usleep_range(10, 20);
1024         ret = meson_sar_adc_get_sample(indio_dev,
1025                                        &indio_dev->channels[7],
1026                                        MEAN_AVERAGING, EIGHT_SAMPLES, &value1);
1027         if (ret < 0)
1028                 goto out;
1029
1030         if (value1 <= value0) {
1031                 ret = -EINVAL;
1032                 goto out;
1033         }
1034
1035         priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
1036                                    value1 - value0);
1037         priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
1038                                              MILLION);
1039         ret = 0;
1040 out:
1041         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
1042
1043         return ret;
1044 }
1045
1046 static const struct iio_info meson_sar_adc_iio_info = {
1047         .read_raw = meson_sar_adc_iio_info_read_raw,
1048 };
1049
1050 static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
1051         .has_bl30_integration = false,
1052         .clock_rate = 1150000,
1053         .bandgap_reg = MESON_SAR_ADC_DELTA_10,
1054         .regmap_config = &meson_sar_adc_regmap_config_meson8,
1055         .resolution = 10,
1056         .temperature_trimming_bits = 4,
1057         .temperature_multiplier = 18 * 10000,
1058         .temperature_divider = 1024 * 10 * 85,
1059 };
1060
1061 static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
1062         .has_bl30_integration = false,
1063         .clock_rate = 1150000,
1064         .bandgap_reg = MESON_SAR_ADC_DELTA_10,
1065         .regmap_config = &meson_sar_adc_regmap_config_meson8,
1066         .resolution = 10,
1067 };
1068
1069 static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
1070         .has_bl30_integration = true,
1071         .clock_rate = 1200000,
1072         .bandgap_reg = MESON_SAR_ADC_REG11,
1073         .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1074         .resolution = 10,
1075 };
1076
1077 static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
1078         .has_bl30_integration = true,
1079         .clock_rate = 1200000,
1080         .bandgap_reg = MESON_SAR_ADC_REG11,
1081         .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1082         .resolution = 12,
1083 };
1084
1085 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
1086         .param = &meson_sar_adc_meson8_param,
1087         .name = "meson-meson8-saradc",
1088 };
1089
1090 static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
1091         .param = &meson_sar_adc_meson8b_param,
1092         .name = "meson-meson8b-saradc",
1093 };
1094
1095 static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = {
1096         .param = &meson_sar_adc_meson8b_param,
1097         .name = "meson-meson8m2-saradc",
1098 };
1099
1100 static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
1101         .param = &meson_sar_adc_gxbb_param,
1102         .name = "meson-gxbb-saradc",
1103 };
1104
1105 static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
1106         .param = &meson_sar_adc_gxl_param,
1107         .name = "meson-gxl-saradc",
1108 };
1109
1110 static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
1111         .param = &meson_sar_adc_gxl_param,
1112         .name = "meson-gxm-saradc",
1113 };
1114
1115 static const struct meson_sar_adc_data meson_sar_adc_axg_data = {
1116         .param = &meson_sar_adc_gxl_param,
1117         .name = "meson-axg-saradc",
1118 };
1119
1120 static const struct of_device_id meson_sar_adc_of_match[] = {
1121         {
1122                 .compatible = "amlogic,meson8-saradc",
1123                 .data = &meson_sar_adc_meson8_data,
1124         },
1125         {
1126                 .compatible = "amlogic,meson8b-saradc",
1127                 .data = &meson_sar_adc_meson8b_data,
1128         },
1129         {
1130                 .compatible = "amlogic,meson8m2-saradc",
1131                 .data = &meson_sar_adc_meson8m2_data,
1132         },
1133         {
1134                 .compatible = "amlogic,meson-gxbb-saradc",
1135                 .data = &meson_sar_adc_gxbb_data,
1136         }, {
1137                 .compatible = "amlogic,meson-gxl-saradc",
1138                 .data = &meson_sar_adc_gxl_data,
1139         }, {
1140                 .compatible = "amlogic,meson-gxm-saradc",
1141                 .data = &meson_sar_adc_gxm_data,
1142         }, {
1143                 .compatible = "amlogic,meson-axg-saradc",
1144                 .data = &meson_sar_adc_axg_data,
1145         },
1146         {},
1147 };
1148 MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
1149
1150 static int meson_sar_adc_probe(struct platform_device *pdev)
1151 {
1152         const struct meson_sar_adc_data *match_data;
1153         struct meson_sar_adc_priv *priv;
1154         struct iio_dev *indio_dev;
1155         struct resource *res;
1156         void __iomem *base;
1157         int irq, ret;
1158
1159         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
1160         if (!indio_dev) {
1161                 dev_err(&pdev->dev, "failed allocating iio device\n");
1162                 return -ENOMEM;
1163         }
1164
1165         priv = iio_priv(indio_dev);
1166         init_completion(&priv->done);
1167
1168         match_data = of_device_get_match_data(&pdev->dev);
1169         if (!match_data) {
1170                 dev_err(&pdev->dev, "failed to get match data\n");
1171                 return -ENODEV;
1172         }
1173
1174         priv->param = match_data->param;
1175
1176         indio_dev->name = match_data->name;
1177         indio_dev->dev.parent = &pdev->dev;
1178         indio_dev->dev.of_node = pdev->dev.of_node;
1179         indio_dev->modes = INDIO_DIRECT_MODE;
1180         indio_dev->info = &meson_sar_adc_iio_info;
1181
1182         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1183         base = devm_ioremap_resource(&pdev->dev, res);
1184         if (IS_ERR(base))
1185                 return PTR_ERR(base);
1186
1187         irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1188         if (!irq)
1189                 return -EINVAL;
1190
1191         ret = devm_request_irq(&pdev->dev, irq, meson_sar_adc_irq, IRQF_SHARED,
1192                                dev_name(&pdev->dev), indio_dev);
1193         if (ret)
1194                 return ret;
1195
1196         priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
1197                                              priv->param->regmap_config);
1198         if (IS_ERR(priv->regmap))
1199                 return PTR_ERR(priv->regmap);
1200
1201         priv->clkin = devm_clk_get(&pdev->dev, "clkin");
1202         if (IS_ERR(priv->clkin)) {
1203                 dev_err(&pdev->dev, "failed to get clkin\n");
1204                 return PTR_ERR(priv->clkin);
1205         }
1206
1207         priv->core_clk = devm_clk_get(&pdev->dev, "core");
1208         if (IS_ERR(priv->core_clk)) {
1209                 dev_err(&pdev->dev, "failed to get core clk\n");
1210                 return PTR_ERR(priv->core_clk);
1211         }
1212
1213         priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
1214         if (IS_ERR(priv->adc_clk)) {
1215                 if (PTR_ERR(priv->adc_clk) == -ENOENT) {
1216                         priv->adc_clk = NULL;
1217                 } else {
1218                         dev_err(&pdev->dev, "failed to get adc clk\n");
1219                         return PTR_ERR(priv->adc_clk);
1220                 }
1221         }
1222
1223         priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
1224         if (IS_ERR(priv->adc_sel_clk)) {
1225                 if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
1226                         priv->adc_sel_clk = NULL;
1227                 } else {
1228                         dev_err(&pdev->dev, "failed to get adc_sel clk\n");
1229                         return PTR_ERR(priv->adc_sel_clk);
1230                 }
1231         }
1232
1233         /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
1234         if (!priv->adc_clk) {
1235                 ret = meson_sar_adc_clk_init(indio_dev, base);
1236                 if (ret)
1237                         return ret;
1238         }
1239
1240         priv->vref = devm_regulator_get(&pdev->dev, "vref");
1241         if (IS_ERR(priv->vref)) {
1242                 dev_err(&pdev->dev, "failed to get vref regulator\n");
1243                 return PTR_ERR(priv->vref);
1244         }
1245
1246         priv->calibscale = MILLION;
1247
1248         if (priv->param->temperature_trimming_bits) {
1249                 ret = meson_sar_adc_temp_sensor_init(indio_dev);
1250                 if (ret)
1251                         return ret;
1252         }
1253
1254         if (priv->temperature_sensor_calibrated) {
1255                 indio_dev->channels = meson_sar_adc_and_temp_iio_channels;
1256                 indio_dev->num_channels =
1257                         ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels);
1258         } else {
1259                 indio_dev->channels = meson_sar_adc_iio_channels;
1260                 indio_dev->num_channels =
1261                         ARRAY_SIZE(meson_sar_adc_iio_channels);
1262         }
1263
1264         ret = meson_sar_adc_init(indio_dev);
1265         if (ret)
1266                 goto err;
1267
1268         ret = meson_sar_adc_hw_enable(indio_dev);
1269         if (ret)
1270                 goto err;
1271
1272         ret = meson_sar_adc_calib(indio_dev);
1273         if (ret)
1274                 dev_warn(&pdev->dev, "calibration failed\n");
1275
1276         platform_set_drvdata(pdev, indio_dev);
1277
1278         ret = iio_device_register(indio_dev);
1279         if (ret)
1280                 goto err_hw;
1281
1282         return 0;
1283
1284 err_hw:
1285         meson_sar_adc_hw_disable(indio_dev);
1286 err:
1287         return ret;
1288 }
1289
1290 static int meson_sar_adc_remove(struct platform_device *pdev)
1291 {
1292         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1293
1294         iio_device_unregister(indio_dev);
1295
1296         return meson_sar_adc_hw_disable(indio_dev);
1297 }
1298
1299 static int __maybe_unused meson_sar_adc_suspend(struct device *dev)
1300 {
1301         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1302
1303         return meson_sar_adc_hw_disable(indio_dev);
1304 }
1305
1306 static int __maybe_unused meson_sar_adc_resume(struct device *dev)
1307 {
1308         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1309
1310         return meson_sar_adc_hw_enable(indio_dev);
1311 }
1312
1313 static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
1314                          meson_sar_adc_suspend, meson_sar_adc_resume);
1315
1316 static struct platform_driver meson_sar_adc_driver = {
1317         .probe          = meson_sar_adc_probe,
1318         .remove         = meson_sar_adc_remove,
1319         .driver         = {
1320                 .name   = "meson-saradc",
1321                 .of_match_table = meson_sar_adc_of_match,
1322                 .pm = &meson_sar_adc_pm_ops,
1323         },
1324 };
1325
1326 module_platform_driver(meson_sar_adc_driver);
1327
1328 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
1329 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
1330 MODULE_LICENSE("GPL v2");