1 // SPDX-License-Identifier: GPL-2.0+
3 * NXP i.MX93 ADC driver
8 #include <linux/bitfield.h>
10 #include <linux/completion.h>
11 #include <linux/err.h>
12 #include <linux/iio/iio.h>
13 #include <linux/interrupt.h>
15 #include <linux/iopoll.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regulator/consumer.h>
22 #define IMX93_ADC_DRIVER_NAME "imx93-adc"
24 /* Register map definition */
25 #define IMX93_ADC_MCR 0x00
26 #define IMX93_ADC_MSR 0x04
27 #define IMX93_ADC_ISR 0x10
28 #define IMX93_ADC_IMR 0x20
29 #define IMX93_ADC_CIMR0 0x24
30 #define IMX93_ADC_CTR0 0x94
31 #define IMX93_ADC_NCMR0 0xA4
32 #define IMX93_ADC_PCDR0 0x100
33 #define IMX93_ADC_PCDR1 0x104
34 #define IMX93_ADC_PCDR2 0x108
35 #define IMX93_ADC_PCDR3 0x10c
36 #define IMX93_ADC_PCDR4 0x110
37 #define IMX93_ADC_PCDR5 0x114
38 #define IMX93_ADC_PCDR6 0x118
39 #define IMX93_ADC_PCDR7 0x11c
40 #define IMX93_ADC_CALSTAT 0x39C
43 #define IMX93_ADC_MCR_MODE_MASK BIT(29)
44 #define IMX93_ADC_MCR_NSTART_MASK BIT(24)
45 #define IMX93_ADC_MCR_CALSTART_MASK BIT(14)
46 #define IMX93_ADC_MCR_ADCLKSE_MASK BIT(8)
47 #define IMX93_ADC_MCR_PWDN_MASK BIT(0)
48 #define IMX93_ADC_MSR_CALFAIL_MASK BIT(30)
49 #define IMX93_ADC_MSR_CALBUSY_MASK BIT(29)
50 #define IMX93_ADC_MSR_ADCSTATUS_MASK GENMASK(2, 0)
51 #define IMX93_ADC_ISR_ECH_MASK BIT(0)
52 #define IMX93_ADC_ISR_EOC_MASK BIT(1)
53 #define IMX93_ADC_ISR_EOC_ECH_MASK (IMX93_ADC_ISR_EOC_MASK | \
54 IMX93_ADC_ISR_ECH_MASK)
55 #define IMX93_ADC_IMR_JEOC_MASK BIT(3)
56 #define IMX93_ADC_IMR_JECH_MASK BIT(2)
57 #define IMX93_ADC_IMR_EOC_MASK BIT(1)
58 #define IMX93_ADC_IMR_ECH_MASK BIT(0)
59 #define IMX93_ADC_PCDR_CDATA_MASK GENMASK(11, 0)
62 #define IMX93_ADC_MSR_ADCSTATUS_IDLE 0
63 #define IMX93_ADC_MSR_ADCSTATUS_POWER_DOWN 1
64 #define IMX93_ADC_MSR_ADCSTATUS_WAIT_STATE 2
65 #define IMX93_ADC_MSR_ADCSTATUS_BUSY_IN_CALIBRATION 3
66 #define IMX93_ADC_MSR_ADCSTATUS_SAMPLE 4
67 #define IMX93_ADC_MSR_ADCSTATUS_CONVERSION 6
69 #define IMX93_ADC_TIMEOUT msecs_to_jiffies(100)
76 struct regulator *vref;
77 /* lock to protect against multiple access to the device */
79 struct completion completion;
82 #define IMX93_ADC_CHAN(_idx) { \
83 .type = IIO_VOLTAGE, \
86 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
87 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
88 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
91 static const struct iio_chan_spec imx93_adc_iio_channels[] = {
98 static void imx93_adc_power_down(struct imx93_adc *adc)
103 mcr = readl(adc->regs + IMX93_ADC_MCR);
104 mcr |= FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1);
105 writel(mcr, adc->regs + IMX93_ADC_MCR);
107 ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr,
108 ((msr & IMX93_ADC_MSR_ADCSTATUS_MASK) ==
109 IMX93_ADC_MSR_ADCSTATUS_POWER_DOWN),
111 if (ret == -ETIMEDOUT)
113 "ADC do not in power down mode, current MSR is %x\n",
117 static void imx93_adc_power_up(struct imx93_adc *adc)
121 /* bring ADC out of power down state, in idle state */
122 mcr = readl(adc->regs + IMX93_ADC_MCR);
123 mcr &= ~FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1);
124 writel(mcr, adc->regs + IMX93_ADC_MCR);
127 static void imx93_adc_config_ad_clk(struct imx93_adc *adc)
131 /* put adc in power down mode */
132 imx93_adc_power_down(adc);
134 /* config the AD_CLK equal to bus clock */
135 mcr = readl(adc->regs + IMX93_ADC_MCR);
136 mcr |= FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1);
137 writel(mcr, adc->regs + IMX93_ADC_MCR);
139 imx93_adc_power_up(adc);
142 static int imx93_adc_calibration(struct imx93_adc *adc)
147 /* make sure ADC in power down mode */
148 imx93_adc_power_down(adc);
150 /* config SAR controller operating clock */
151 mcr = readl(adc->regs + IMX93_ADC_MCR);
152 mcr &= ~FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1);
153 writel(mcr, adc->regs + IMX93_ADC_MCR);
155 imx93_adc_power_up(adc);
158 * TODO: we use the default TSAMP/NRSMPL/AVGEN in MCR,
159 * can add the setting of these bit if need in future.
162 /* run calibration */
163 mcr = readl(adc->regs + IMX93_ADC_MCR);
164 mcr |= FIELD_PREP(IMX93_ADC_MCR_CALSTART_MASK, 1);
165 writel(mcr, adc->regs + IMX93_ADC_MCR);
167 /* wait calibration to be finished */
168 ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr,
169 !(msr & IMX93_ADC_MSR_CALBUSY_MASK), 1000, 2000000);
170 if (ret == -ETIMEDOUT) {
171 dev_warn(adc->dev, "ADC do not finish calibration in 2 min!\n");
172 imx93_adc_power_down(adc);
176 /* check whether calbration is success or not */
177 msr = readl(adc->regs + IMX93_ADC_MSR);
178 if (msr & IMX93_ADC_MSR_CALFAIL_MASK) {
179 dev_warn(adc->dev, "ADC calibration failed!\n");
180 imx93_adc_power_down(adc);
187 static int imx93_adc_read_channel_conversion(struct imx93_adc *adc,
195 reinit_completion(&adc->completion);
197 /* config channel mask register */
198 channel = 1 << channel_number;
199 writel(channel, adc->regs + IMX93_ADC_NCMR0);
201 /* TODO: can config desired sample time in CTRn if need */
203 /* config interrupt mask */
204 imr = FIELD_PREP(IMX93_ADC_IMR_EOC_MASK, 1);
205 writel(imr, adc->regs + IMX93_ADC_IMR);
206 writel(channel, adc->regs + IMX93_ADC_CIMR0);
208 /* config one-shot mode */
209 mcr = readl(adc->regs + IMX93_ADC_MCR);
210 mcr &= ~FIELD_PREP(IMX93_ADC_MCR_MODE_MASK, 1);
211 writel(mcr, adc->regs + IMX93_ADC_MCR);
213 /* start normal conversion */
214 mcr = readl(adc->regs + IMX93_ADC_MCR);
215 mcr |= FIELD_PREP(IMX93_ADC_MCR_NSTART_MASK, 1);
216 writel(mcr, adc->regs + IMX93_ADC_MCR);
218 ret = wait_for_completion_interruptible_timeout(&adc->completion,
226 pcda = readl(adc->regs + IMX93_ADC_PCDR0 + channel_number * 4);
228 *result = FIELD_GET(IMX93_ADC_PCDR_CDATA_MASK, pcda);
233 static int imx93_adc_read_raw(struct iio_dev *indio_dev,
234 struct iio_chan_spec const *chan,
235 int *val, int *val2, long mask)
237 struct imx93_adc *adc = iio_priv(indio_dev);
238 struct device *dev = adc->dev;
243 case IIO_CHAN_INFO_RAW:
244 pm_runtime_get_sync(dev);
245 mutex_lock(&adc->lock);
246 ret = imx93_adc_read_channel_conversion(adc, chan->channel, val);
247 mutex_unlock(&adc->lock);
248 pm_runtime_mark_last_busy(dev);
249 pm_runtime_put_sync_autosuspend(dev);
255 case IIO_CHAN_INFO_SCALE:
256 ret = vref_uv = regulator_get_voltage(adc->vref);
259 *val = vref_uv / 1000;
261 return IIO_VAL_FRACTIONAL_LOG2;
263 case IIO_CHAN_INFO_SAMP_FREQ:
264 *val = clk_get_rate(adc->ipg_clk);
272 static irqreturn_t imx93_adc_isr(int irq, void *dev_id)
274 struct imx93_adc *adc = dev_id;
275 u32 isr, eoc, unexpected;
277 isr = readl(adc->regs + IMX93_ADC_ISR);
279 if (FIELD_GET(IMX93_ADC_ISR_EOC_ECH_MASK, isr)) {
280 eoc = isr & IMX93_ADC_ISR_EOC_ECH_MASK;
281 writel(eoc, adc->regs + IMX93_ADC_ISR);
282 complete(&adc->completion);
285 unexpected = isr & ~IMX93_ADC_ISR_EOC_ECH_MASK;
287 writel(unexpected, adc->regs + IMX93_ADC_ISR);
288 dev_err(adc->dev, "Unexpected interrupt 0x%08x.\n", unexpected);
295 static const struct iio_info imx93_adc_iio_info = {
296 .read_raw = &imx93_adc_read_raw,
299 static int imx93_adc_probe(struct platform_device *pdev)
301 struct imx93_adc *adc;
302 struct iio_dev *indio_dev;
303 struct device *dev = &pdev->dev;
306 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
308 return dev_err_probe(dev, -ENOMEM,
309 "Failed allocating iio device\n");
311 adc = iio_priv(indio_dev);
314 mutex_init(&adc->lock);
315 adc->regs = devm_platform_ioremap_resource(pdev, 0);
316 if (IS_ERR(adc->regs))
317 return dev_err_probe(dev, PTR_ERR(adc->regs),
318 "Failed getting ioremap resource\n");
320 /* The third irq is for ADC conversion usage */
321 adc->irq = platform_get_irq(pdev, 2);
325 adc->ipg_clk = devm_clk_get(dev, "ipg");
326 if (IS_ERR(adc->ipg_clk))
327 return dev_err_probe(dev, PTR_ERR(adc->ipg_clk),
328 "Failed getting clock.\n");
330 adc->vref = devm_regulator_get(dev, "vref");
331 if (IS_ERR(adc->vref))
332 return dev_err_probe(dev, PTR_ERR(adc->vref),
333 "Failed getting reference voltage.\n");
335 ret = regulator_enable(adc->vref);
337 return dev_err_probe(dev, ret,
338 "Failed to enable reference voltage.\n");
340 platform_set_drvdata(pdev, indio_dev);
342 init_completion(&adc->completion);
344 indio_dev->name = "imx93-adc";
345 indio_dev->info = &imx93_adc_iio_info;
346 indio_dev->modes = INDIO_DIRECT_MODE;
347 indio_dev->channels = imx93_adc_iio_channels;
348 indio_dev->num_channels = ARRAY_SIZE(imx93_adc_iio_channels);
350 ret = clk_prepare_enable(adc->ipg_clk);
352 dev_err_probe(dev, ret,
353 "Failed to enable ipg clock.\n");
354 goto error_regulator_disable;
357 ret = request_irq(adc->irq, imx93_adc_isr, 0, IMX93_ADC_DRIVER_NAME, adc);
359 dev_err_probe(dev, ret,
360 "Failed requesting irq, irq = %d\n", adc->irq);
361 goto error_ipg_clk_disable;
364 ret = imx93_adc_calibration(adc);
366 goto error_free_adc_irq;
368 imx93_adc_config_ad_clk(adc);
370 ret = iio_device_register(indio_dev);
372 dev_err_probe(dev, ret,
373 "Failed to register this iio device.\n");
374 goto error_adc_power_down;
377 pm_runtime_set_active(dev);
378 pm_runtime_set_autosuspend_delay(dev, 50);
379 pm_runtime_use_autosuspend(dev);
380 pm_runtime_enable(dev);
384 error_adc_power_down:
385 imx93_adc_power_down(adc);
387 free_irq(adc->irq, adc);
388 error_ipg_clk_disable:
389 clk_disable_unprepare(adc->ipg_clk);
390 error_regulator_disable:
391 regulator_disable(adc->vref);
396 static int imx93_adc_remove(struct platform_device *pdev)
398 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
399 struct imx93_adc *adc = iio_priv(indio_dev);
400 struct device *dev = adc->dev;
402 /* adc power down need clock on */
403 pm_runtime_get_sync(dev);
405 pm_runtime_disable(dev);
406 pm_runtime_dont_use_autosuspend(dev);
407 pm_runtime_put_noidle(dev);
409 iio_device_unregister(indio_dev);
410 imx93_adc_power_down(adc);
411 free_irq(adc->irq, adc);
412 clk_disable_unprepare(adc->ipg_clk);
413 regulator_disable(adc->vref);
418 static int imx93_adc_runtime_suspend(struct device *dev)
420 struct iio_dev *indio_dev = dev_get_drvdata(dev);
421 struct imx93_adc *adc = iio_priv(indio_dev);
423 imx93_adc_power_down(adc);
424 clk_disable_unprepare(adc->ipg_clk);
425 regulator_disable(adc->vref);
430 static int imx93_adc_runtime_resume(struct device *dev)
432 struct iio_dev *indio_dev = dev_get_drvdata(dev);
433 struct imx93_adc *adc = iio_priv(indio_dev);
436 ret = regulator_enable(adc->vref);
439 "Can't enable adc reference top voltage, err = %d\n",
444 ret = clk_prepare_enable(adc->ipg_clk);
446 dev_err(dev, "Could not prepare or enable clock.\n");
447 goto err_disable_reg;
450 imx93_adc_power_up(adc);
455 regulator_disable(adc->vref);
460 static DEFINE_RUNTIME_DEV_PM_OPS(imx93_adc_pm_ops,
461 imx93_adc_runtime_suspend,
462 imx93_adc_runtime_resume, NULL);
464 static const struct of_device_id imx93_adc_match[] = {
465 { .compatible = "nxp,imx93-adc", },
468 MODULE_DEVICE_TABLE(of, imx93_adc_match);
470 static struct platform_driver imx93_adc_driver = {
471 .probe = imx93_adc_probe,
472 .remove = imx93_adc_remove,
474 .name = IMX93_ADC_DRIVER_NAME,
475 .of_match_table = imx93_adc_match,
476 .pm = pm_ptr(&imx93_adc_pm_ops),
480 module_platform_driver(imx93_adc_driver);
482 MODULE_DESCRIPTION("NXP i.MX93 ADC driver");
483 MODULE_AUTHOR("Haibo Chen <haibo.chen@nxp.com>");
484 MODULE_LICENSE("GPL");