2 * Driver for the Diolan DLN-2 USB-ADC adapter
4 * Copyright (c) 2017 Jack Andersen
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation, version 2.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/types.h>
14 #include <linux/platform_device.h>
15 #include <linux/mfd/dln2.h>
17 #include <linux/iio/iio.h>
18 #include <linux/iio/sysfs.h>
19 #include <linux/iio/trigger.h>
20 #include <linux/iio/trigger_consumer.h>
21 #include <linux/iio/triggered_buffer.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/kfifo_buf.h>
25 #define DLN2_ADC_MOD_NAME "dln2-adc"
27 #define DLN2_ADC_ID 0x06
29 #define DLN2_ADC_GET_CHANNEL_COUNT DLN2_CMD(0x01, DLN2_ADC_ID)
30 #define DLN2_ADC_ENABLE DLN2_CMD(0x02, DLN2_ADC_ID)
31 #define DLN2_ADC_DISABLE DLN2_CMD(0x03, DLN2_ADC_ID)
32 #define DLN2_ADC_CHANNEL_ENABLE DLN2_CMD(0x05, DLN2_ADC_ID)
33 #define DLN2_ADC_CHANNEL_DISABLE DLN2_CMD(0x06, DLN2_ADC_ID)
34 #define DLN2_ADC_SET_RESOLUTION DLN2_CMD(0x08, DLN2_ADC_ID)
35 #define DLN2_ADC_CHANNEL_GET_VAL DLN2_CMD(0x0A, DLN2_ADC_ID)
36 #define DLN2_ADC_CHANNEL_GET_ALL_VAL DLN2_CMD(0x0B, DLN2_ADC_ID)
37 #define DLN2_ADC_CHANNEL_SET_CFG DLN2_CMD(0x0C, DLN2_ADC_ID)
38 #define DLN2_ADC_CHANNEL_GET_CFG DLN2_CMD(0x0D, DLN2_ADC_ID)
39 #define DLN2_ADC_CONDITION_MET_EV DLN2_CMD(0x10, DLN2_ADC_ID)
41 #define DLN2_ADC_EVENT_NONE 0
42 #define DLN2_ADC_EVENT_BELOW 1
43 #define DLN2_ADC_EVENT_LEVEL_ABOVE 2
44 #define DLN2_ADC_EVENT_OUTSIDE 3
45 #define DLN2_ADC_EVENT_INSIDE 4
46 #define DLN2_ADC_EVENT_ALWAYS 5
48 #define DLN2_ADC_MAX_CHANNELS 8
49 #define DLN2_ADC_DATA_BITS 10
52 * Plays similar role to iio_demux_table in subsystem core; except allocated
53 * in a fixed 8-element array.
55 struct dln2_adc_demux_table {
62 struct platform_device *pdev;
63 struct iio_chan_spec iio_channels[DLN2_ADC_MAX_CHANNELS + 1];
64 int port, trigger_chan;
65 struct iio_trigger *trig;
67 /* Cached sample period in milliseconds */
68 unsigned int sample_period;
70 unsigned int demux_count;
71 struct dln2_adc_demux_table demux[DLN2_ADC_MAX_CHANNELS];
72 /* Precomputed timestamp padding offset and length */
73 unsigned int ts_pad_offset, ts_pad_length;
76 struct dln2_adc_port_chan {
81 struct dln2_adc_get_all_vals {
83 __le16 values[DLN2_ADC_MAX_CHANNELS];
86 static void dln2_adc_add_demux(struct dln2_adc *dln2,
87 unsigned int in_loc, unsigned int out_loc,
90 struct dln2_adc_demux_table *p = dln2->demux_count ?
91 &dln2->demux[dln2->demux_count - 1] : NULL;
93 if (p && p->from + p->length == in_loc &&
94 p->to + p->length == out_loc) {
96 } else if (dln2->demux_count < DLN2_ADC_MAX_CHANNELS) {
97 p = &dln2->demux[dln2->demux_count++];
104 static void dln2_adc_update_demux(struct dln2_adc *dln2)
106 int in_ind = -1, out_ind;
107 unsigned int in_loc = 0, out_loc = 0;
108 struct iio_dev *indio_dev = platform_get_drvdata(dln2->pdev);
110 /* Clear out any old demux */
111 dln2->demux_count = 0;
113 /* Optimize all 8-channels case */
114 if (indio_dev->masklength &&
115 (*indio_dev->active_scan_mask & 0xff) == 0xff) {
116 dln2_adc_add_demux(dln2, 0, 0, 16);
117 dln2->ts_pad_offset = 0;
118 dln2->ts_pad_length = 0;
122 /* Build demux table from fixed 8-channels to active_scan_mask */
123 for_each_set_bit(out_ind,
124 indio_dev->active_scan_mask,
125 indio_dev->masklength) {
126 /* Handle timestamp separately */
127 if (out_ind == DLN2_ADC_MAX_CHANNELS)
129 for (++in_ind; in_ind != out_ind; ++in_ind)
131 dln2_adc_add_demux(dln2, in_loc, out_loc, 2);
136 if (indio_dev->scan_timestamp) {
137 size_t ts_offset = indio_dev->scan_bytes / sizeof(int64_t) - 1;
139 dln2->ts_pad_offset = out_loc;
140 dln2->ts_pad_length = ts_offset * sizeof(int64_t) - out_loc;
142 dln2->ts_pad_offset = 0;
143 dln2->ts_pad_length = 0;
147 static int dln2_adc_get_chan_count(struct dln2_adc *dln2)
150 u8 port = dln2->port;
152 int olen = sizeof(count);
154 ret = dln2_transfer(dln2->pdev, DLN2_ADC_GET_CHANNEL_COUNT,
155 &port, sizeof(port), &count, &olen);
157 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
160 if (olen < sizeof(count))
166 static int dln2_adc_set_port_resolution(struct dln2_adc *dln2)
169 struct dln2_adc_port_chan port_chan = {
171 .chan = DLN2_ADC_DATA_BITS,
174 ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_SET_RESOLUTION,
175 &port_chan, sizeof(port_chan));
177 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
182 static int dln2_adc_set_chan_enabled(struct dln2_adc *dln2,
183 int channel, bool enable)
186 struct dln2_adc_port_chan port_chan = {
190 u16 cmd = enable ? DLN2_ADC_CHANNEL_ENABLE : DLN2_ADC_CHANNEL_DISABLE;
192 ret = dln2_transfer_tx(dln2->pdev, cmd, &port_chan, sizeof(port_chan));
194 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
199 static int dln2_adc_set_port_enabled(struct dln2_adc *dln2, bool enable,
203 u8 port = dln2->port;
205 int olen = sizeof(conflict);
206 u16 cmd = enable ? DLN2_ADC_ENABLE : DLN2_ADC_DISABLE;
211 ret = dln2_transfer(dln2->pdev, cmd, &port, sizeof(port),
214 dev_dbg(&dln2->pdev->dev, "Problem in %s(%d)\n",
215 __func__, (int)enable);
216 if (conflict_out && enable && olen >= sizeof(conflict))
217 *conflict_out = le16_to_cpu(conflict);
220 if (enable && olen < sizeof(conflict))
226 static int dln2_adc_set_chan_period(struct dln2_adc *dln2,
227 unsigned int channel, unsigned int period)
231 struct dln2_adc_port_chan port_chan;
236 } __packed set_cfg = {
237 .port_chan.port = dln2->port,
238 .port_chan.chan = channel,
239 .type = period ? DLN2_ADC_EVENT_ALWAYS : DLN2_ADC_EVENT_NONE,
240 .period = cpu_to_le16(period)
243 ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_CHANNEL_SET_CFG,
244 &set_cfg, sizeof(set_cfg));
246 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
251 static int dln2_adc_read(struct dln2_adc *dln2, unsigned int channel)
254 struct iio_dev *indio_dev = platform_get_drvdata(dln2->pdev);
257 int olen = sizeof(value);
258 struct dln2_adc_port_chan port_chan = {
263 ret = iio_device_claim_direct_mode(indio_dev);
267 ret = dln2_adc_set_chan_enabled(dln2, channel, true);
271 ret = dln2_adc_set_port_enabled(dln2, true, &conflict);
274 dev_err(&dln2->pdev->dev,
275 "ADC pins conflict with mask %04X\n",
283 * Call GET_VAL twice due to initial zero-return immediately after
286 for (i = 0; i < 2; ++i) {
287 ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_VAL,
288 &port_chan, sizeof(port_chan),
291 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
294 if (olen < sizeof(value)) {
300 ret = le16_to_cpu(value);
303 dln2_adc_set_port_enabled(dln2, false, NULL);
305 dln2_adc_set_chan_enabled(dln2, channel, false);
307 iio_device_release_direct_mode(indio_dev);
312 static int dln2_adc_read_all(struct dln2_adc *dln2,
313 struct dln2_adc_get_all_vals *get_all_vals)
316 __u8 port = dln2->port;
317 int olen = sizeof(*get_all_vals);
319 ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_ALL_VAL,
320 &port, sizeof(port), get_all_vals, &olen);
322 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
325 if (olen < sizeof(*get_all_vals))
331 static int dln2_adc_read_raw(struct iio_dev *indio_dev,
332 struct iio_chan_spec const *chan,
338 unsigned int microhertz;
339 struct dln2_adc *dln2 = iio_priv(indio_dev);
342 case IIO_CHAN_INFO_RAW:
343 mutex_lock(&dln2->mutex);
344 ret = dln2_adc_read(dln2, chan->channel);
345 mutex_unlock(&dln2->mutex);
353 case IIO_CHAN_INFO_SCALE:
355 * Voltage reference is fixed at 3.3v
356 * 3.3 / (1 << 10) * 1000000000
360 return IIO_VAL_INT_PLUS_NANO;
362 case IIO_CHAN_INFO_SAMP_FREQ:
363 if (dln2->sample_period) {
364 microhertz = 1000000000 / dln2->sample_period;
365 *val = microhertz / 1000000;
366 *val2 = microhertz % 1000000;
372 return IIO_VAL_INT_PLUS_MICRO;
379 static int dln2_adc_write_raw(struct iio_dev *indio_dev,
380 struct iio_chan_spec const *chan,
386 unsigned int microhertz;
387 struct dln2_adc *dln2 = iio_priv(indio_dev);
390 case IIO_CHAN_INFO_SAMP_FREQ:
391 microhertz = 1000000 * val + val2;
393 mutex_lock(&dln2->mutex);
395 dln2->sample_period =
396 microhertz ? 1000000000 / microhertz : UINT_MAX;
397 if (dln2->sample_period > 65535) {
398 dln2->sample_period = 65535;
399 dev_warn(&dln2->pdev->dev,
400 "clamping period to 65535ms\n");
404 * The first requested channel is arbitrated as a shared
405 * trigger source, so only one event is registered with the
406 * DLN. The event handler will then read all enabled channel
407 * values using DLN2_ADC_CHANNEL_GET_ALL_VAL to maintain
408 * synchronization between ADC readings.
410 if (dln2->trigger_chan != -1)
411 ret = dln2_adc_set_chan_period(dln2,
412 dln2->trigger_chan, dln2->sample_period);
416 mutex_unlock(&dln2->mutex);
425 static int dln2_update_scan_mode(struct iio_dev *indio_dev,
426 const unsigned long *scan_mask)
428 struct dln2_adc *dln2 = iio_priv(indio_dev);
429 int chan_count = indio_dev->num_channels - 1;
432 mutex_lock(&dln2->mutex);
434 for (i = 0; i < chan_count; ++i) {
435 ret = dln2_adc_set_chan_enabled(dln2, i,
436 test_bit(i, scan_mask));
438 for (j = 0; j < i; ++j)
439 dln2_adc_set_chan_enabled(dln2, j, false);
440 mutex_unlock(&dln2->mutex);
441 dev_err(&dln2->pdev->dev,
442 "Unable to enable ADC channel %d\n", i);
447 dln2_adc_update_demux(dln2);
449 mutex_unlock(&dln2->mutex);
454 #define DLN2_ADC_CHAN(lval, idx) { \
455 lval.type = IIO_VOLTAGE; \
456 lval.channel = idx; \
458 lval.info_mask_separate = BIT(IIO_CHAN_INFO_RAW); \
459 lval.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \
460 BIT(IIO_CHAN_INFO_SAMP_FREQ); \
461 lval.scan_index = idx; \
462 lval.scan_type.sign = 'u'; \
463 lval.scan_type.realbits = DLN2_ADC_DATA_BITS; \
464 lval.scan_type.storagebits = 16; \
465 lval.scan_type.endianness = IIO_LE; \
468 /* Assignment version of IIO_CHAN_SOFT_TIMESTAMP */
469 #define IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(lval, _si) { \
470 lval.type = IIO_TIMESTAMP; \
472 lval.scan_index = _si; \
473 lval.scan_type.sign = 's'; \
474 lval.scan_type.realbits = 64; \
475 lval.scan_type.storagebits = 64; \
478 static const struct iio_info dln2_adc_info = {
479 .read_raw = dln2_adc_read_raw,
480 .write_raw = dln2_adc_write_raw,
481 .update_scan_mode = dln2_update_scan_mode,
482 .driver_module = THIS_MODULE,
485 static irqreturn_t dln2_adc_trigger_h(int irq, void *p)
487 struct iio_poll_func *pf = p;
488 struct iio_dev *indio_dev = pf->indio_dev;
490 __le16 values[DLN2_ADC_MAX_CHANNELS];
491 int64_t timestamp_space;
493 struct dln2_adc_get_all_vals dev_data;
494 struct dln2_adc *dln2 = iio_priv(indio_dev);
495 const struct dln2_adc_demux_table *t;
498 mutex_lock(&dln2->mutex);
499 ret = dln2_adc_read_all(dln2, &dev_data);
500 mutex_unlock(&dln2->mutex);
504 /* Demux operation */
505 for (i = 0; i < dln2->demux_count; ++i) {
507 memcpy((void *)data.values + t->to,
508 (void *)dev_data.values + t->from, t->length);
511 /* Zero padding space between values and timestamp */
512 if (dln2->ts_pad_length)
513 memset((void *)data.values + dln2->ts_pad_offset,
514 0, dln2->ts_pad_length);
516 iio_push_to_buffers_with_timestamp(indio_dev, &data,
517 iio_get_time_ns(indio_dev));
520 iio_trigger_notify_done(indio_dev->trig);
524 static int dln2_adc_triggered_buffer_postenable(struct iio_dev *indio_dev)
527 struct dln2_adc *dln2 = iio_priv(indio_dev);
529 unsigned int trigger_chan;
531 mutex_lock(&dln2->mutex);
534 ret = dln2_adc_set_port_enabled(dln2, true, &conflict);
536 mutex_unlock(&dln2->mutex);
537 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
539 dev_err(&dln2->pdev->dev,
540 "ADC pins conflict with mask %04X\n",
547 /* Assign trigger channel based on first enabled channel */
548 trigger_chan = find_first_bit(indio_dev->active_scan_mask,
549 indio_dev->masklength);
550 if (trigger_chan < DLN2_ADC_MAX_CHANNELS) {
551 dln2->trigger_chan = trigger_chan;
552 ret = dln2_adc_set_chan_period(dln2, dln2->trigger_chan,
553 dln2->sample_period);
554 mutex_unlock(&dln2->mutex);
556 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
560 dln2->trigger_chan = -1;
561 mutex_unlock(&dln2->mutex);
564 return iio_triggered_buffer_postenable(indio_dev);
567 static int dln2_adc_triggered_buffer_predisable(struct iio_dev *indio_dev)
570 struct dln2_adc *dln2 = iio_priv(indio_dev);
572 mutex_lock(&dln2->mutex);
574 /* Disable trigger channel */
575 if (dln2->trigger_chan != -1) {
576 dln2_adc_set_chan_period(dln2, dln2->trigger_chan, 0);
577 dln2->trigger_chan = -1;
581 ret = dln2_adc_set_port_enabled(dln2, false, NULL);
583 mutex_unlock(&dln2->mutex);
585 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
589 return iio_triggered_buffer_predisable(indio_dev);
592 static const struct iio_buffer_setup_ops dln2_adc_buffer_setup_ops = {
593 .postenable = dln2_adc_triggered_buffer_postenable,
594 .predisable = dln2_adc_triggered_buffer_predisable,
597 static void dln2_adc_event(struct platform_device *pdev, u16 echo,
598 const void *data, int len)
600 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
601 struct dln2_adc *dln2 = iio_priv(indio_dev);
603 /* Called via URB completion handler */
604 iio_trigger_poll(dln2->trig);
607 static const struct iio_trigger_ops dln2_adc_trigger_ops = {
608 .owner = THIS_MODULE,
611 static int dln2_adc_probe(struct platform_device *pdev)
613 struct device *dev = &pdev->dev;
614 struct dln2_adc *dln2;
615 struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
616 struct iio_dev *indio_dev;
619 indio_dev = devm_iio_device_alloc(dev, sizeof(*dln2));
621 dev_err(dev, "failed allocating iio device\n");
625 dln2 = iio_priv(indio_dev);
627 dln2->port = pdata->port;
628 dln2->trigger_chan = -1;
629 mutex_init(&dln2->mutex);
631 platform_set_drvdata(pdev, indio_dev);
633 ret = dln2_adc_set_port_resolution(dln2);
635 dev_err(dev, "failed to set ADC resolution to 10 bits\n");
639 chans = dln2_adc_get_chan_count(dln2);
641 dev_err(dev, "failed to get channel count: %d\n", chans);
644 if (chans > DLN2_ADC_MAX_CHANNELS) {
645 chans = DLN2_ADC_MAX_CHANNELS;
646 dev_warn(dev, "clamping channels to %d\n",
647 DLN2_ADC_MAX_CHANNELS);
650 for (i = 0; i < chans; ++i)
651 DLN2_ADC_CHAN(dln2->iio_channels[i], i)
652 IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(dln2->iio_channels[i], i);
654 indio_dev->name = DLN2_ADC_MOD_NAME;
655 indio_dev->dev.parent = dev;
656 indio_dev->info = &dln2_adc_info;
657 indio_dev->modes = INDIO_DIRECT_MODE;
658 indio_dev->channels = dln2->iio_channels;
659 indio_dev->num_channels = chans + 1;
660 indio_dev->setup_ops = &dln2_adc_buffer_setup_ops;
662 dln2->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
663 indio_dev->name, indio_dev->id);
665 dev_err(dev, "failed to allocate trigger\n");
668 dln2->trig->ops = &dln2_adc_trigger_ops;
669 iio_trigger_set_drvdata(dln2->trig, dln2);
670 devm_iio_trigger_register(dev, dln2->trig);
671 iio_trigger_set_immutable(indio_dev, dln2->trig);
673 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
675 &dln2_adc_buffer_setup_ops);
677 dev_err(dev, "failed to allocate triggered buffer: %d\n", ret);
681 ret = dln2_register_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV,
684 dev_err(dev, "failed to setup DLN2 periodic event: %d\n", ret);
688 ret = iio_device_register(indio_dev);
690 dev_err(dev, "failed to register iio device: %d\n", ret);
691 goto unregister_event;
697 dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV);
702 static int dln2_adc_remove(struct platform_device *pdev)
704 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
706 iio_device_unregister(indio_dev);
707 dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV);
711 static struct platform_driver dln2_adc_driver = {
712 .driver.name = DLN2_ADC_MOD_NAME,
713 .probe = dln2_adc_probe,
714 .remove = dln2_adc_remove,
717 module_platform_driver(dln2_adc_driver);
719 MODULE_AUTHOR("Jack Andersen <jackoalan@gmail.com");
720 MODULE_DESCRIPTION("Driver for the Diolan DLN2 ADC interface");
721 MODULE_LICENSE("GPL v2");
722 MODULE_ALIAS("platform:dln2-adc");