2 * mma8452.c - Support for following Freescale 3-axis accelerometers:
11 * Copyright 2015 Martin Kepplinger <martin.kepplinger@theobroma-systems.com>
12 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
14 * This file is subject to the terms and conditions of version 2 of
15 * the GNU General Public License. See the file COPYING in the main
16 * directory of this archive for more details.
18 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
20 * TODO: orientation events
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/iio/iio.h>
26 #include <linux/iio/sysfs.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/trigger.h>
29 #include <linux/iio/trigger_consumer.h>
30 #include <linux/iio/triggered_buffer.h>
31 #include <linux/iio/events.h>
32 #include <linux/delay.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/pm_runtime.h>
37 #define MMA8452_STATUS 0x00
38 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
39 #define MMA8452_OUT_X 0x01 /* MSB first */
40 #define MMA8452_OUT_Y 0x03
41 #define MMA8452_OUT_Z 0x05
42 #define MMA8452_INT_SRC 0x0c
43 #define MMA8452_WHO_AM_I 0x0d
44 #define MMA8452_DATA_CFG 0x0e
45 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
46 #define MMA8452_DATA_CFG_FS_2G 0
47 #define MMA8452_DATA_CFG_FS_4G 1
48 #define MMA8452_DATA_CFG_FS_8G 2
49 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
50 #define MMA8452_HP_FILTER_CUTOFF 0x0f
51 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
52 #define MMA8452_FF_MT_CFG 0x15
53 #define MMA8452_FF_MT_CFG_OAE BIT(6)
54 #define MMA8452_FF_MT_CFG_ELE BIT(7)
55 #define MMA8452_FF_MT_SRC 0x16
56 #define MMA8452_FF_MT_SRC_XHE BIT(1)
57 #define MMA8452_FF_MT_SRC_YHE BIT(3)
58 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
59 #define MMA8452_FF_MT_THS 0x17
60 #define MMA8452_FF_MT_THS_MASK 0x7f
61 #define MMA8452_FF_MT_COUNT 0x18
62 #define MMA8452_TRANSIENT_CFG 0x1d
63 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
64 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
65 #define MMA8452_TRANSIENT_SRC 0x1e
66 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
67 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
68 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
69 #define MMA8452_TRANSIENT_THS 0x1f
70 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
71 #define MMA8452_TRANSIENT_COUNT 0x20
72 #define MMA8452_CTRL_REG1 0x2a
73 #define MMA8452_CTRL_ACTIVE BIT(0)
74 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
75 #define MMA8452_CTRL_DR_SHIFT 3
76 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
77 #define MMA8452_CTRL_REG2 0x2b
78 #define MMA8452_CTRL_REG2_RST BIT(6)
79 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
80 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
81 #define MMA8452_CTRL_REG4 0x2d
82 #define MMA8452_CTRL_REG5 0x2e
83 #define MMA8452_OFF_X 0x2f
84 #define MMA8452_OFF_Y 0x30
85 #define MMA8452_OFF_Z 0x31
87 #define MMA8452_MAX_REG 0x31
89 #define MMA8452_INT_DRDY BIT(0)
90 #define MMA8452_INT_FF_MT BIT(2)
91 #define MMA8452_INT_TRANS BIT(5)
93 #define MMA8451_DEVICE_ID 0x1a
94 #define MMA8452_DEVICE_ID 0x2a
95 #define MMA8453_DEVICE_ID 0x3a
96 #define MMA8652_DEVICE_ID 0x4a
97 #define MMA8653_DEVICE_ID 0x5a
98 #define FXLS8471_DEVICE_ID 0x6a
100 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
102 struct mma8452_data {
103 struct i2c_client *client;
107 const struct mma_chip_info *chip_info;
111 * struct mma_chip_info - chip specific data for Freescale's accelerometers
112 * @chip_id: WHO_AM_I register's value
113 * @channels: struct iio_chan_spec matching the device's
115 * @num_channels: number of channels
116 * @mma_scales: scale factors for converting register values
117 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
118 * per mode: m/s^2 and micro m/s^2
119 * @ev_cfg: event config register address
120 * @ev_cfg_ele: latch bit in event config register
121 * @ev_cfg_chan_shift: number of the bit to enable events in X
122 * direction; in event config register
123 * @ev_src: event source register address
124 * @ev_src_xe: bit in event source register that indicates
125 * an event in X direction
126 * @ev_src_ye: bit in event source register that indicates
127 * an event in Y direction
128 * @ev_src_ze: bit in event source register that indicates
129 * an event in Z direction
130 * @ev_ths: event threshold register address
131 * @ev_ths_mask: mask for the threshold value
132 * @ev_count: event count (period) register address
134 * Since not all chips supported by the driver support comparing high pass
135 * filtered data for events (interrupts), different interrupt sources are
136 * used for different chips and the relevant registers are included here.
138 struct mma_chip_info {
140 const struct iio_chan_spec *channels;
142 const int mma_scales[3][2];
145 u8 ev_cfg_chan_shift;
162 static int mma8452_drdy(struct mma8452_data *data)
166 while (tries-- > 0) {
167 int ret = i2c_smbus_read_byte_data(data->client,
171 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
177 dev_err(&data->client->dev, "data not ready\n");
182 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
188 ret = pm_runtime_get_sync(&client->dev);
190 pm_runtime_mark_last_busy(&client->dev);
191 ret = pm_runtime_put_autosuspend(&client->dev);
195 dev_err(&client->dev,
196 "failed to change power state to %d\n", on);
198 pm_runtime_put_noidle(&client->dev);
207 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
209 int ret = mma8452_drdy(data);
214 ret = mma8452_set_runtime_pm_state(data->client, true);
218 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
219 3 * sizeof(__be16), (u8 *)buf);
221 ret = mma8452_set_runtime_pm_state(data->client, false);
226 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
232 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
233 vals[n][0], vals[n][1]);
235 /* replace trailing space by newline */
241 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
245 if (val == vals[n][0] && val2 == vals[n][1])
251 static int mma8452_get_odr_index(struct mma8452_data *data)
253 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
254 MMA8452_CTRL_DR_SHIFT;
257 static const int mma8452_samp_freq[8][2] = {
258 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
259 {6, 250000}, {1, 560000}
262 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
263 static const int mma8452_transient_time_step_us[4][8] = {
264 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
265 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
266 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
267 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
270 /* Datasheet table "High-Pass Filter Cutoff Options" */
271 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
273 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
274 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
275 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
276 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
277 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
278 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
279 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
280 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
282 { /* low noise low power */
283 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
284 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
285 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
286 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
287 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
288 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
289 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
290 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
292 { /* high resolution */
293 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
294 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
295 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
296 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
297 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
298 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
299 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
300 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
303 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
304 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
305 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
306 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
307 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
308 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
309 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
310 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
314 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
315 static const u16 mma8452_os_ratio[4][8] = {
316 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
317 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
318 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
319 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
320 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
323 static int mma8452_get_power_mode(struct mma8452_data *data)
327 reg = i2c_smbus_read_byte_data(data->client,
332 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
333 MMA8452_CTRL_REG2_MODS_SHIFT);
336 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
337 struct device_attribute *attr,
340 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
341 ARRAY_SIZE(mma8452_samp_freq));
344 static ssize_t mma8452_show_scale_avail(struct device *dev,
345 struct device_attribute *attr,
348 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
349 to_i2c_client(dev)));
351 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
352 ARRAY_SIZE(data->chip_info->mma_scales));
355 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
356 struct device_attribute *attr,
359 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
360 struct mma8452_data *data = iio_priv(indio_dev);
363 i = mma8452_get_odr_index(data);
364 j = mma8452_get_power_mode(data);
368 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
369 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
372 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
373 struct device_attribute *attr,
376 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
377 struct mma8452_data *data = iio_priv(indio_dev);
378 int i = mma8452_get_odr_index(data);
383 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
384 if (val == mma8452_os_ratio[j][i])
387 val = mma8452_os_ratio[j][i];
389 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
396 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
397 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
398 mma8452_show_scale_avail, NULL, 0);
399 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
400 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
401 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, S_IRUGO,
402 mma8452_show_os_ratio_avail, NULL, 0);
404 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
407 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
408 ARRAY_SIZE(mma8452_samp_freq),
412 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
414 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
415 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
418 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
423 i = mma8452_get_odr_index(data);
424 j = mma8452_get_power_mode(data);
428 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
429 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
432 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
436 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
440 i = mma8452_get_odr_index(data);
441 j = mma8452_get_power_mode(data);
445 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
446 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
447 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
452 static int mma8452_read_raw(struct iio_dev *indio_dev,
453 struct iio_chan_spec const *chan,
454 int *val, int *val2, long mask)
456 struct mma8452_data *data = iio_priv(indio_dev);
461 case IIO_CHAN_INFO_RAW:
462 if (iio_buffer_enabled(indio_dev))
465 mutex_lock(&data->lock);
466 ret = mma8452_read(data, buffer);
467 mutex_unlock(&data->lock);
471 *val = sign_extend32(be16_to_cpu(
472 buffer[chan->scan_index]) >> chan->scan_type.shift,
473 chan->scan_type.realbits - 1);
476 case IIO_CHAN_INFO_SCALE:
477 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
478 *val = data->chip_info->mma_scales[i][0];
479 *val2 = data->chip_info->mma_scales[i][1];
481 return IIO_VAL_INT_PLUS_MICRO;
482 case IIO_CHAN_INFO_SAMP_FREQ:
483 i = mma8452_get_odr_index(data);
484 *val = mma8452_samp_freq[i][0];
485 *val2 = mma8452_samp_freq[i][1];
487 return IIO_VAL_INT_PLUS_MICRO;
488 case IIO_CHAN_INFO_CALIBBIAS:
489 ret = i2c_smbus_read_byte_data(data->client,
495 *val = sign_extend32(ret, 7);
498 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
499 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
500 ret = mma8452_read_hp_filter(data, val, val2);
508 return IIO_VAL_INT_PLUS_MICRO;
509 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
510 ret = mma8452_get_power_mode(data);
514 i = mma8452_get_odr_index(data);
516 *val = mma8452_os_ratio[ret][i];
523 static int mma8452_standby(struct mma8452_data *data)
525 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
526 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
529 static int mma8452_active(struct mma8452_data *data)
531 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
535 /* returns >0 if active, 0 if in standby and <0 on error */
536 static int mma8452_is_active(struct mma8452_data *data)
540 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
544 return reg & MMA8452_CTRL_ACTIVE;
547 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
552 mutex_lock(&data->lock);
554 is_active = mma8452_is_active(data);
560 /* config can only be changed when in standby */
562 ret = mma8452_standby(data);
567 ret = i2c_smbus_write_byte_data(data->client, reg, val);
572 ret = mma8452_active(data);
579 mutex_unlock(&data->lock);
584 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
588 reg = i2c_smbus_read_byte_data(data->client,
593 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
594 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
596 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
599 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
600 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
603 const struct mma_chip_info *chip = data->chip_info;
605 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
609 return !(val & MMA8452_FF_MT_CFG_OAE);
612 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
615 const struct mma_chip_info *chip = data->chip_info;
617 if ((state && mma8452_freefall_mode_enabled(data)) ||
618 (!state && !(mma8452_freefall_mode_enabled(data))))
621 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
626 val |= BIT(idx_x + chip->ev_cfg_chan_shift);
627 val |= BIT(idx_y + chip->ev_cfg_chan_shift);
628 val |= BIT(idx_z + chip->ev_cfg_chan_shift);
629 val &= ~MMA8452_FF_MT_CFG_OAE;
631 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
632 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
633 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
634 val |= MMA8452_FF_MT_CFG_OAE;
637 val = mma8452_change_config(data, chip->ev_cfg, val);
644 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
649 i = mma8452_get_hp_filter_index(data, val, val2);
653 reg = i2c_smbus_read_byte_data(data->client,
654 MMA8452_HP_FILTER_CUTOFF);
658 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
661 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
664 static int mma8452_write_raw(struct iio_dev *indio_dev,
665 struct iio_chan_spec const *chan,
666 int val, int val2, long mask)
668 struct mma8452_data *data = iio_priv(indio_dev);
671 if (iio_buffer_enabled(indio_dev))
675 case IIO_CHAN_INFO_SAMP_FREQ:
676 i = mma8452_get_samp_freq_index(data, val, val2);
680 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
681 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
683 return mma8452_change_config(data, MMA8452_CTRL_REG1,
685 case IIO_CHAN_INFO_SCALE:
686 i = mma8452_get_scale_index(data, val, val2);
690 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
693 return mma8452_change_config(data, MMA8452_DATA_CFG,
695 case IIO_CHAN_INFO_CALIBBIAS:
696 if (val < -128 || val > 127)
699 return mma8452_change_config(data,
700 MMA8452_OFF_X + chan->scan_index,
703 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
704 if (val == 0 && val2 == 0) {
705 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
707 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
708 ret = mma8452_set_hp_filter_frequency(data, val, val2);
713 return mma8452_change_config(data, MMA8452_DATA_CFG,
716 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
717 ret = mma8452_get_odr_index(data);
719 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
720 if (mma8452_os_ratio[i][ret] == val)
721 return mma8452_set_power_mode(data, i);
729 static int mma8452_read_thresh(struct iio_dev *indio_dev,
730 const struct iio_chan_spec *chan,
731 enum iio_event_type type,
732 enum iio_event_direction dir,
733 enum iio_event_info info,
736 struct mma8452_data *data = iio_priv(indio_dev);
737 int ret, us, power_mode;
740 case IIO_EV_INFO_VALUE:
741 ret = i2c_smbus_read_byte_data(data->client,
742 data->chip_info->ev_ths);
746 *val = ret & data->chip_info->ev_ths_mask;
750 case IIO_EV_INFO_PERIOD:
751 ret = i2c_smbus_read_byte_data(data->client,
752 data->chip_info->ev_count);
756 power_mode = mma8452_get_power_mode(data);
760 us = ret * mma8452_transient_time_step_us[power_mode][
761 mma8452_get_odr_index(data)];
762 *val = us / USEC_PER_SEC;
763 *val2 = us % USEC_PER_SEC;
765 return IIO_VAL_INT_PLUS_MICRO;
767 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
768 ret = i2c_smbus_read_byte_data(data->client,
769 MMA8452_TRANSIENT_CFG);
773 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
777 ret = mma8452_read_hp_filter(data, val, val2);
782 return IIO_VAL_INT_PLUS_MICRO;
789 static int mma8452_write_thresh(struct iio_dev *indio_dev,
790 const struct iio_chan_spec *chan,
791 enum iio_event_type type,
792 enum iio_event_direction dir,
793 enum iio_event_info info,
796 struct mma8452_data *data = iio_priv(indio_dev);
800 case IIO_EV_INFO_VALUE:
801 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
804 return mma8452_change_config(data, data->chip_info->ev_ths,
807 case IIO_EV_INFO_PERIOD:
808 ret = mma8452_get_power_mode(data);
812 steps = (val * USEC_PER_SEC + val2) /
813 mma8452_transient_time_step_us[ret][
814 mma8452_get_odr_index(data)];
816 if (steps < 0 || steps > 0xff)
819 return mma8452_change_config(data, data->chip_info->ev_count,
822 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
823 reg = i2c_smbus_read_byte_data(data->client,
824 MMA8452_TRANSIENT_CFG);
828 if (val == 0 && val2 == 0) {
829 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
831 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
832 ret = mma8452_set_hp_filter_frequency(data, val, val2);
837 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
844 static int mma8452_read_event_config(struct iio_dev *indio_dev,
845 const struct iio_chan_spec *chan,
846 enum iio_event_type type,
847 enum iio_event_direction dir)
849 struct mma8452_data *data = iio_priv(indio_dev);
850 const struct mma_chip_info *chip = data->chip_info;
854 case IIO_EV_DIR_FALLING:
855 return mma8452_freefall_mode_enabled(data);
856 case IIO_EV_DIR_RISING:
857 if (mma8452_freefall_mode_enabled(data))
860 ret = i2c_smbus_read_byte_data(data->client,
861 data->chip_info->ev_cfg);
865 return !!(ret & BIT(chan->scan_index +
866 chip->ev_cfg_chan_shift));
872 static int mma8452_write_event_config(struct iio_dev *indio_dev,
873 const struct iio_chan_spec *chan,
874 enum iio_event_type type,
875 enum iio_event_direction dir,
878 struct mma8452_data *data = iio_priv(indio_dev);
879 const struct mma_chip_info *chip = data->chip_info;
882 ret = mma8452_set_runtime_pm_state(data->client, state);
887 case IIO_EV_DIR_FALLING:
888 return mma8452_set_freefall_mode(data, state);
889 case IIO_EV_DIR_RISING:
890 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
895 if (mma8452_freefall_mode_enabled(data)) {
896 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
897 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
898 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
899 val |= MMA8452_FF_MT_CFG_OAE;
901 val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
903 if (mma8452_freefall_mode_enabled(data))
906 val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
909 val |= chip->ev_cfg_ele;
911 return mma8452_change_config(data, chip->ev_cfg, val);
917 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
919 struct mma8452_data *data = iio_priv(indio_dev);
920 s64 ts = iio_get_time_ns();
923 src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
927 if (mma8452_freefall_mode_enabled(data)) {
928 iio_push_event(indio_dev,
929 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
930 IIO_MOD_X_AND_Y_AND_Z,
937 if (src & data->chip_info->ev_src_xe)
938 iio_push_event(indio_dev,
939 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
944 if (src & data->chip_info->ev_src_ye)
945 iio_push_event(indio_dev,
946 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
951 if (src & data->chip_info->ev_src_ze)
952 iio_push_event(indio_dev,
953 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
959 static irqreturn_t mma8452_interrupt(int irq, void *p)
961 struct iio_dev *indio_dev = p;
962 struct mma8452_data *data = iio_priv(indio_dev);
963 const struct mma_chip_info *chip = data->chip_info;
967 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
971 if (src & MMA8452_INT_DRDY) {
972 iio_trigger_poll_chained(indio_dev->trig);
976 if ((src & MMA8452_INT_TRANS &&
977 chip->ev_src == MMA8452_TRANSIENT_SRC) ||
978 (src & MMA8452_INT_FF_MT &&
979 chip->ev_src == MMA8452_FF_MT_SRC)) {
980 mma8452_transient_interrupt(indio_dev);
987 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
989 struct iio_poll_func *pf = p;
990 struct iio_dev *indio_dev = pf->indio_dev;
991 struct mma8452_data *data = iio_priv(indio_dev);
992 u8 buffer[16]; /* 3 16-bit channels + padding + ts */
995 ret = mma8452_read(data, (__be16 *)buffer);
999 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
1003 iio_trigger_notify_done(indio_dev->trig);
1008 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1009 unsigned reg, unsigned writeval,
1013 struct mma8452_data *data = iio_priv(indio_dev);
1015 if (reg > MMA8452_MAX_REG)
1019 return mma8452_change_config(data, reg, writeval);
1021 ret = i2c_smbus_read_byte_data(data->client, reg);
1030 static const struct iio_event_spec mma8452_freefall_event[] = {
1032 .type = IIO_EV_TYPE_MAG,
1033 .dir = IIO_EV_DIR_FALLING,
1034 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1035 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1036 BIT(IIO_EV_INFO_PERIOD) |
1037 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1041 static const struct iio_event_spec mma8652_freefall_event[] = {
1043 .type = IIO_EV_TYPE_MAG,
1044 .dir = IIO_EV_DIR_FALLING,
1045 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1046 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1047 BIT(IIO_EV_INFO_PERIOD)
1051 static const struct iio_event_spec mma8452_transient_event[] = {
1053 .type = IIO_EV_TYPE_MAG,
1054 .dir = IIO_EV_DIR_RISING,
1055 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1056 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1057 BIT(IIO_EV_INFO_PERIOD) |
1058 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1062 static const struct iio_event_spec mma8452_motion_event[] = {
1064 .type = IIO_EV_TYPE_MAG,
1065 .dir = IIO_EV_DIR_RISING,
1066 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1067 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1068 BIT(IIO_EV_INFO_PERIOD)
1073 * Threshold is configured in fixed 8G/127 steps regardless of
1074 * currently selected scale for measurement.
1076 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1078 static struct attribute *mma8452_event_attributes[] = {
1079 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1083 static struct attribute_group mma8452_event_attribute_group = {
1084 .attrs = mma8452_event_attributes,
1087 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1088 .type = IIO_ACCEL, \
1090 .channel2 = modifier, \
1092 .event_spec = mma8452_freefall_event, \
1093 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1096 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1097 .type = IIO_ACCEL, \
1099 .channel2 = modifier, \
1101 .event_spec = mma8652_freefall_event, \
1102 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1105 #define MMA8452_CHANNEL(axis, idx, bits) { \
1106 .type = IIO_ACCEL, \
1108 .channel2 = IIO_MOD_##axis, \
1109 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1110 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1111 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1112 BIT(IIO_CHAN_INFO_SCALE) | \
1113 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1114 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1115 .scan_index = idx, \
1118 .realbits = (bits), \
1119 .storagebits = 16, \
1120 .shift = 16 - (bits), \
1121 .endianness = IIO_BE, \
1123 .event_spec = mma8452_transient_event, \
1124 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1127 #define MMA8652_CHANNEL(axis, idx, bits) { \
1128 .type = IIO_ACCEL, \
1130 .channel2 = IIO_MOD_##axis, \
1131 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1132 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1133 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1134 BIT(IIO_CHAN_INFO_SCALE) | \
1135 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1136 .scan_index = idx, \
1139 .realbits = (bits), \
1140 .storagebits = 16, \
1141 .shift = 16 - (bits), \
1142 .endianness = IIO_BE, \
1144 .event_spec = mma8452_motion_event, \
1145 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1148 static const struct iio_chan_spec mma8451_channels[] = {
1149 MMA8452_CHANNEL(X, idx_x, 14),
1150 MMA8452_CHANNEL(Y, idx_y, 14),
1151 MMA8452_CHANNEL(Z, idx_z, 14),
1152 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1153 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1156 static const struct iio_chan_spec mma8452_channels[] = {
1157 MMA8452_CHANNEL(X, idx_x, 12),
1158 MMA8452_CHANNEL(Y, idx_y, 12),
1159 MMA8452_CHANNEL(Z, idx_z, 12),
1160 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1161 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1164 static const struct iio_chan_spec mma8453_channels[] = {
1165 MMA8452_CHANNEL(X, idx_x, 10),
1166 MMA8452_CHANNEL(Y, idx_y, 10),
1167 MMA8452_CHANNEL(Z, idx_z, 10),
1168 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1169 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1172 static const struct iio_chan_spec mma8652_channels[] = {
1173 MMA8652_CHANNEL(X, idx_x, 12),
1174 MMA8652_CHANNEL(Y, idx_y, 12),
1175 MMA8652_CHANNEL(Z, idx_z, 12),
1176 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1177 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1180 static const struct iio_chan_spec mma8653_channels[] = {
1181 MMA8652_CHANNEL(X, idx_x, 10),
1182 MMA8652_CHANNEL(Y, idx_y, 10),
1183 MMA8652_CHANNEL(Z, idx_z, 10),
1184 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1185 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1197 static const struct mma_chip_info mma_chip_info_table[] = {
1199 .chip_id = MMA8451_DEVICE_ID,
1200 .channels = mma8451_channels,
1201 .num_channels = ARRAY_SIZE(mma8451_channels),
1203 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1204 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1206 * The userspace interface uses m/s^2 and we declare micro units
1207 * So scale factor for 12 bit here is given by:
1208 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1210 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1211 .ev_cfg = MMA8452_TRANSIENT_CFG,
1212 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1213 .ev_cfg_chan_shift = 1,
1214 .ev_src = MMA8452_TRANSIENT_SRC,
1215 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1216 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1217 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1218 .ev_ths = MMA8452_TRANSIENT_THS,
1219 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1220 .ev_count = MMA8452_TRANSIENT_COUNT,
1223 .chip_id = MMA8452_DEVICE_ID,
1224 .channels = mma8452_channels,
1225 .num_channels = ARRAY_SIZE(mma8452_channels),
1226 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1227 .ev_cfg = MMA8452_TRANSIENT_CFG,
1228 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1229 .ev_cfg_chan_shift = 1,
1230 .ev_src = MMA8452_TRANSIENT_SRC,
1231 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1232 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1233 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1234 .ev_ths = MMA8452_TRANSIENT_THS,
1235 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1236 .ev_count = MMA8452_TRANSIENT_COUNT,
1239 .chip_id = MMA8453_DEVICE_ID,
1240 .channels = mma8453_channels,
1241 .num_channels = ARRAY_SIZE(mma8453_channels),
1242 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1243 .ev_cfg = MMA8452_TRANSIENT_CFG,
1244 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1245 .ev_cfg_chan_shift = 1,
1246 .ev_src = MMA8452_TRANSIENT_SRC,
1247 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1248 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1249 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1250 .ev_ths = MMA8452_TRANSIENT_THS,
1251 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1252 .ev_count = MMA8452_TRANSIENT_COUNT,
1255 .chip_id = MMA8652_DEVICE_ID,
1256 .channels = mma8652_channels,
1257 .num_channels = ARRAY_SIZE(mma8652_channels),
1258 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1259 .ev_cfg = MMA8452_FF_MT_CFG,
1260 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1261 .ev_cfg_chan_shift = 3,
1262 .ev_src = MMA8452_FF_MT_SRC,
1263 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1264 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1265 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1266 .ev_ths = MMA8452_FF_MT_THS,
1267 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1268 .ev_count = MMA8452_FF_MT_COUNT,
1271 .chip_id = MMA8653_DEVICE_ID,
1272 .channels = mma8653_channels,
1273 .num_channels = ARRAY_SIZE(mma8653_channels),
1274 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1275 .ev_cfg = MMA8452_FF_MT_CFG,
1276 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1277 .ev_cfg_chan_shift = 3,
1278 .ev_src = MMA8452_FF_MT_SRC,
1279 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1280 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1281 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1282 .ev_ths = MMA8452_FF_MT_THS,
1283 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1284 .ev_count = MMA8452_FF_MT_COUNT,
1287 .chip_id = FXLS8471_DEVICE_ID,
1288 .channels = mma8451_channels,
1289 .num_channels = ARRAY_SIZE(mma8451_channels),
1290 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1291 .ev_cfg = MMA8452_TRANSIENT_CFG,
1292 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1293 .ev_cfg_chan_shift = 1,
1294 .ev_src = MMA8452_TRANSIENT_SRC,
1295 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1296 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1297 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1298 .ev_ths = MMA8452_TRANSIENT_THS,
1299 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1300 .ev_count = MMA8452_TRANSIENT_COUNT,
1304 static struct attribute *mma8452_attributes[] = {
1305 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1306 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1307 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1308 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1312 static const struct attribute_group mma8452_group = {
1313 .attrs = mma8452_attributes,
1316 static const struct iio_info mma8452_info = {
1317 .attrs = &mma8452_group,
1318 .read_raw = &mma8452_read_raw,
1319 .write_raw = &mma8452_write_raw,
1320 .event_attrs = &mma8452_event_attribute_group,
1321 .read_event_value = &mma8452_read_thresh,
1322 .write_event_value = &mma8452_write_thresh,
1323 .read_event_config = &mma8452_read_event_config,
1324 .write_event_config = &mma8452_write_event_config,
1325 .debugfs_reg_access = &mma8452_reg_access_dbg,
1326 .driver_module = THIS_MODULE,
1329 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1331 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1334 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1335 struct mma8452_data *data = iio_priv(indio_dev);
1338 ret = mma8452_set_runtime_pm_state(data->client, state);
1342 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1347 reg |= MMA8452_INT_DRDY;
1349 reg &= ~MMA8452_INT_DRDY;
1351 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1354 static int mma8452_validate_device(struct iio_trigger *trig,
1355 struct iio_dev *indio_dev)
1357 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
1359 if (indio != indio_dev)
1365 static const struct iio_trigger_ops mma8452_trigger_ops = {
1366 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1367 .validate_device = mma8452_validate_device,
1368 .owner = THIS_MODULE,
1371 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1373 struct mma8452_data *data = iio_priv(indio_dev);
1374 struct iio_trigger *trig;
1377 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1383 trig->dev.parent = &data->client->dev;
1384 trig->ops = &mma8452_trigger_ops;
1385 iio_trigger_set_drvdata(trig, indio_dev);
1387 ret = iio_trigger_register(trig);
1391 indio_dev->trig = trig;
1396 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1398 if (indio_dev->trig)
1399 iio_trigger_unregister(indio_dev->trig);
1402 static int mma8452_reset(struct i2c_client *client)
1407 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1408 MMA8452_CTRL_REG2_RST);
1412 for (i = 0; i < 10; i++) {
1413 usleep_range(100, 200);
1414 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1416 continue; /* I2C comm reset */
1419 if (!(ret & MMA8452_CTRL_REG2_RST))
1426 static const struct of_device_id mma8452_dt_ids[] = {
1427 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1428 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1429 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1430 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1431 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1432 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1435 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1437 static int mma8452_probe(struct i2c_client *client,
1438 const struct i2c_device_id *id)
1440 struct mma8452_data *data;
1441 struct iio_dev *indio_dev;
1443 const struct of_device_id *match;
1445 match = of_match_device(mma8452_dt_ids, &client->dev);
1447 dev_err(&client->dev, "unknown device model\n");
1451 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1455 data = iio_priv(indio_dev);
1456 data->client = client;
1457 mutex_init(&data->lock);
1458 data->chip_info = match->data;
1460 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1465 case MMA8451_DEVICE_ID:
1466 case MMA8452_DEVICE_ID:
1467 case MMA8453_DEVICE_ID:
1468 case MMA8652_DEVICE_ID:
1469 case MMA8653_DEVICE_ID:
1470 case FXLS8471_DEVICE_ID:
1471 if (ret == data->chip_info->chip_id)
1477 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1478 match->compatible, data->chip_info->chip_id);
1480 i2c_set_clientdata(client, indio_dev);
1481 indio_dev->info = &mma8452_info;
1482 indio_dev->name = id->name;
1483 indio_dev->dev.parent = &client->dev;
1484 indio_dev->modes = INDIO_DIRECT_MODE;
1485 indio_dev->channels = data->chip_info->channels;
1486 indio_dev->num_channels = data->chip_info->num_channels;
1487 indio_dev->available_scan_masks = mma8452_scan_masks;
1489 ret = mma8452_reset(client);
1493 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1494 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1500 * By default set transient threshold to max to avoid events if
1501 * enabling without configuring threshold.
1503 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1504 MMA8452_TRANSIENT_THS_MASK);
1510 * Although we enable the interrupt sources once and for
1511 * all here the event detection itself is not enabled until
1512 * userspace asks for it by mma8452_write_event_config()
1514 int supported_interrupts = MMA8452_INT_DRDY |
1517 int enabled_interrupts = MMA8452_INT_TRANS |
1521 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1523 if (irq2 == client->irq) {
1524 dev_dbg(&client->dev, "using interrupt line INT2\n");
1526 ret = i2c_smbus_write_byte_data(client,
1528 supported_interrupts);
1532 dev_dbg(&client->dev, "using interrupt line INT1\n");
1535 ret = i2c_smbus_write_byte_data(client,
1537 enabled_interrupts);
1541 ret = mma8452_trigger_setup(indio_dev);
1546 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1547 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1548 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1551 goto trigger_cleanup;
1553 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1554 mma8452_trigger_handler, NULL);
1556 goto trigger_cleanup;
1559 ret = devm_request_threaded_irq(&client->dev,
1561 NULL, mma8452_interrupt,
1562 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1563 client->name, indio_dev);
1565 goto buffer_cleanup;
1568 ret = pm_runtime_set_active(&client->dev);
1570 goto buffer_cleanup;
1572 pm_runtime_enable(&client->dev);
1573 pm_runtime_set_autosuspend_delay(&client->dev,
1574 MMA8452_AUTO_SUSPEND_DELAY_MS);
1575 pm_runtime_use_autosuspend(&client->dev);
1577 ret = iio_device_register(indio_dev);
1579 goto buffer_cleanup;
1581 ret = mma8452_set_freefall_mode(data, false);
1588 iio_triggered_buffer_cleanup(indio_dev);
1591 mma8452_trigger_cleanup(indio_dev);
1596 static int mma8452_remove(struct i2c_client *client)
1598 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1600 iio_device_unregister(indio_dev);
1602 pm_runtime_disable(&client->dev);
1603 pm_runtime_set_suspended(&client->dev);
1604 pm_runtime_put_noidle(&client->dev);
1606 iio_triggered_buffer_cleanup(indio_dev);
1607 mma8452_trigger_cleanup(indio_dev);
1608 mma8452_standby(iio_priv(indio_dev));
1614 static int mma8452_runtime_suspend(struct device *dev)
1616 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1617 struct mma8452_data *data = iio_priv(indio_dev);
1620 mutex_lock(&data->lock);
1621 ret = mma8452_standby(data);
1622 mutex_unlock(&data->lock);
1624 dev_err(&data->client->dev, "powering off device failed\n");
1631 static int mma8452_runtime_resume(struct device *dev)
1633 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1634 struct mma8452_data *data = iio_priv(indio_dev);
1637 ret = mma8452_active(data);
1641 ret = mma8452_get_odr_index(data);
1642 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1644 usleep_range(sleep_val * 1000, 20000);
1646 msleep_interruptible(sleep_val);
1652 #ifdef CONFIG_PM_SLEEP
1653 static int mma8452_suspend(struct device *dev)
1655 return mma8452_standby(iio_priv(i2c_get_clientdata(
1656 to_i2c_client(dev))));
1659 static int mma8452_resume(struct device *dev)
1661 return mma8452_active(iio_priv(i2c_get_clientdata(
1662 to_i2c_client(dev))));
1666 static const struct dev_pm_ops mma8452_pm_ops = {
1667 SET_SYSTEM_SLEEP_PM_OPS(mma8452_suspend, mma8452_resume)
1668 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1669 mma8452_runtime_resume, NULL)
1672 static const struct i2c_device_id mma8452_id[] = {
1673 { "mma8451", mma8451 },
1674 { "mma8452", mma8452 },
1675 { "mma8453", mma8453 },
1676 { "mma8652", mma8652 },
1677 { "mma8653", mma8653 },
1678 { "fxls8471", fxls8471 },
1681 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1683 static struct i2c_driver mma8452_driver = {
1686 .of_match_table = of_match_ptr(mma8452_dt_ids),
1687 .pm = &mma8452_pm_ops,
1689 .probe = mma8452_probe,
1690 .remove = mma8452_remove,
1691 .id_table = mma8452_id,
1693 module_i2c_driver(mma8452_driver);
1695 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1696 MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
1697 MODULE_LICENSE("GPL");