1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_idle.c - native hardware idle loop for modern Intel processors
5 * Copyright (c) 2013 - 2020, Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
11 * intel_idle is a cpuidle driver that loads on all Intel CPUs with MWAIT
12 * in lieu of the legacy ACPI processor_idle driver. The intent is to
13 * make Linux more efficient on these processors, as intel_idle knows
14 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
20 * All CPUs have same idle states as boot CPU
22 * Chipset BM_STS (bus master status) bit is a NOP
23 * for preventing entry into deep C-states
25 * CPU will flush caches as needed when entering a C-state via MWAIT
26 * (in contrast to entering ACPI C3, in which case the WBINVD
27 * instruction needs to be executed to flush the caches)
33 * ACPI has a .suspend hack to turn off deep c-statees during suspend
34 * to avoid complications with the lapic timer workaround.
35 * Have not seen issues with suspend, but may need same workaround here.
39 /* un-comment DEBUG to enable pr_debug() statements */
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/acpi.h>
45 #include <linux/kernel.h>
46 #include <linux/cpuidle.h>
47 #include <linux/tick.h>
48 #include <trace/events/power.h>
49 #include <linux/sched.h>
50 #include <linux/notifier.h>
51 #include <linux/cpu.h>
52 #include <linux/moduleparam.h>
53 #include <asm/cpu_device_id.h>
54 #include <asm/intel-family.h>
55 #include <asm/mwait.h>
58 #define INTEL_IDLE_VERSION "0.5.1"
60 static struct cpuidle_driver intel_idle_driver = {
64 /* intel_idle.max_cstate=0 disables driver */
65 static int max_cstate = CPUIDLE_STATE_MAX - 1;
66 static unsigned int disabled_states_mask;
68 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
70 static unsigned long auto_demotion_disable_flags;
71 static bool disable_promotion_to_c1e;
74 struct cpuidle_state *state_table;
77 * Hardware C-state auto-demotion may not always be optimal.
78 * Indicate which enable bits to clear here.
80 unsigned long auto_demotion_disable_flags;
81 bool byt_auto_demotion_disable_flag;
82 bool disable_promotion_to_c1e;
86 static const struct idle_cpu *icpu __initdata;
87 static struct cpuidle_state *cpuidle_state_table __initdata;
89 static unsigned int mwait_substates __initdata;
92 * Enable interrupts before entering the C-state. On some platforms and for
93 * some C-states, this may measurably decrease interrupt latency.
95 #define CPUIDLE_FLAG_IRQ_ENABLE BIT(14)
98 * Enable this state by default even if the ACPI _CST does not list it.
100 #define CPUIDLE_FLAG_ALWAYS_ENABLE BIT(15)
103 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
104 * the C-state (top nibble) and sub-state (bottom nibble)
105 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
107 * We store the hint at the top of our "flags" for each state.
109 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
110 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
113 * intel_idle - Ask the processor to enter the given idle state.
114 * @dev: cpuidle device of the target CPU.
115 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
116 * @index: Target idle state index.
118 * Use the MWAIT instruction to notify the processor that the CPU represented by
119 * @dev is idle and it can try to enter the idle state corresponding to @index.
121 * If the local APIC timer is not known to be reliable in the target idle state,
122 * enable one-shot tick broadcasting for the target CPU before executing MWAIT.
124 * Optionally call leave_mm() for the target CPU upfront to avoid wakeups due to
125 * flushing user TLBs.
127 * Must be called under local_irq_disable().
129 static __cpuidle int intel_idle(struct cpuidle_device *dev,
130 struct cpuidle_driver *drv, int index)
132 struct cpuidle_state *state = &drv->states[index];
133 unsigned long eax = flg2MWAIT(state->flags);
134 unsigned long ecx = 1; /* break on interrupt flag */
136 if (state->flags & CPUIDLE_FLAG_IRQ_ENABLE)
139 mwait_idle_with_hints(eax, ecx);
145 * intel_idle_s2idle - Ask the processor to enter the given idle state.
146 * @dev: cpuidle device of the target CPU.
147 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
148 * @index: Target idle state index.
150 * Use the MWAIT instruction to notify the processor that the CPU represented by
151 * @dev is idle and it can try to enter the idle state corresponding to @index.
153 * Invoked as a suspend-to-idle callback routine with frozen user space, frozen
154 * scheduler tick and suspended scheduler clock on the target CPU.
156 static __cpuidle int intel_idle_s2idle(struct cpuidle_device *dev,
157 struct cpuidle_driver *drv, int index)
159 unsigned long eax = flg2MWAIT(drv->states[index].flags);
160 unsigned long ecx = 1; /* break on interrupt flag */
162 mwait_idle_with_hints(eax, ecx);
168 * States are indexed by the cstate number,
169 * which is also the index into the MWAIT hint array.
170 * Thus C0 is a dummy.
172 static struct cpuidle_state nehalem_cstates[] __initdata = {
175 .desc = "MWAIT 0x00",
176 .flags = MWAIT2flg(0x00),
178 .target_residency = 6,
179 .enter = &intel_idle,
180 .enter_s2idle = intel_idle_s2idle, },
183 .desc = "MWAIT 0x01",
184 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
186 .target_residency = 20,
187 .enter = &intel_idle,
188 .enter_s2idle = intel_idle_s2idle, },
191 .desc = "MWAIT 0x10",
192 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
194 .target_residency = 80,
195 .enter = &intel_idle,
196 .enter_s2idle = intel_idle_s2idle, },
199 .desc = "MWAIT 0x20",
200 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
202 .target_residency = 800,
203 .enter = &intel_idle,
204 .enter_s2idle = intel_idle_s2idle, },
209 static struct cpuidle_state snb_cstates[] __initdata = {
212 .desc = "MWAIT 0x00",
213 .flags = MWAIT2flg(0x00),
215 .target_residency = 2,
216 .enter = &intel_idle,
217 .enter_s2idle = intel_idle_s2idle, },
220 .desc = "MWAIT 0x01",
221 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
223 .target_residency = 20,
224 .enter = &intel_idle,
225 .enter_s2idle = intel_idle_s2idle, },
228 .desc = "MWAIT 0x10",
229 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
231 .target_residency = 211,
232 .enter = &intel_idle,
233 .enter_s2idle = intel_idle_s2idle, },
236 .desc = "MWAIT 0x20",
237 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
239 .target_residency = 345,
240 .enter = &intel_idle,
241 .enter_s2idle = intel_idle_s2idle, },
244 .desc = "MWAIT 0x30",
245 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
247 .target_residency = 345,
248 .enter = &intel_idle,
249 .enter_s2idle = intel_idle_s2idle, },
254 static struct cpuidle_state byt_cstates[] __initdata = {
257 .desc = "MWAIT 0x00",
258 .flags = MWAIT2flg(0x00),
260 .target_residency = 1,
261 .enter = &intel_idle,
262 .enter_s2idle = intel_idle_s2idle, },
265 .desc = "MWAIT 0x58",
266 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
268 .target_residency = 275,
269 .enter = &intel_idle,
270 .enter_s2idle = intel_idle_s2idle, },
273 .desc = "MWAIT 0x52",
274 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
276 .target_residency = 560,
277 .enter = &intel_idle,
278 .enter_s2idle = intel_idle_s2idle, },
281 .desc = "MWAIT 0x60",
282 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
283 .exit_latency = 1200,
284 .target_residency = 4000,
285 .enter = &intel_idle,
286 .enter_s2idle = intel_idle_s2idle, },
289 .desc = "MWAIT 0x64",
290 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
291 .exit_latency = 10000,
292 .target_residency = 20000,
293 .enter = &intel_idle,
294 .enter_s2idle = intel_idle_s2idle, },
299 static struct cpuidle_state cht_cstates[] __initdata = {
302 .desc = "MWAIT 0x00",
303 .flags = MWAIT2flg(0x00),
305 .target_residency = 1,
306 .enter = &intel_idle,
307 .enter_s2idle = intel_idle_s2idle, },
310 .desc = "MWAIT 0x58",
311 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
313 .target_residency = 275,
314 .enter = &intel_idle,
315 .enter_s2idle = intel_idle_s2idle, },
318 .desc = "MWAIT 0x52",
319 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
321 .target_residency = 560,
322 .enter = &intel_idle,
323 .enter_s2idle = intel_idle_s2idle, },
326 .desc = "MWAIT 0x60",
327 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
328 .exit_latency = 1200,
329 .target_residency = 4000,
330 .enter = &intel_idle,
331 .enter_s2idle = intel_idle_s2idle, },
334 .desc = "MWAIT 0x64",
335 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
336 .exit_latency = 10000,
337 .target_residency = 20000,
338 .enter = &intel_idle,
339 .enter_s2idle = intel_idle_s2idle, },
344 static struct cpuidle_state ivb_cstates[] __initdata = {
347 .desc = "MWAIT 0x00",
348 .flags = MWAIT2flg(0x00),
350 .target_residency = 1,
351 .enter = &intel_idle,
352 .enter_s2idle = intel_idle_s2idle, },
355 .desc = "MWAIT 0x01",
356 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
358 .target_residency = 20,
359 .enter = &intel_idle,
360 .enter_s2idle = intel_idle_s2idle, },
363 .desc = "MWAIT 0x10",
364 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
366 .target_residency = 156,
367 .enter = &intel_idle,
368 .enter_s2idle = intel_idle_s2idle, },
371 .desc = "MWAIT 0x20",
372 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
374 .target_residency = 300,
375 .enter = &intel_idle,
376 .enter_s2idle = intel_idle_s2idle, },
379 .desc = "MWAIT 0x30",
380 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
382 .target_residency = 300,
383 .enter = &intel_idle,
384 .enter_s2idle = intel_idle_s2idle, },
389 static struct cpuidle_state ivt_cstates[] __initdata = {
392 .desc = "MWAIT 0x00",
393 .flags = MWAIT2flg(0x00),
395 .target_residency = 1,
396 .enter = &intel_idle,
397 .enter_s2idle = intel_idle_s2idle, },
400 .desc = "MWAIT 0x01",
401 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
403 .target_residency = 80,
404 .enter = &intel_idle,
405 .enter_s2idle = intel_idle_s2idle, },
408 .desc = "MWAIT 0x10",
409 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
411 .target_residency = 156,
412 .enter = &intel_idle,
413 .enter_s2idle = intel_idle_s2idle, },
416 .desc = "MWAIT 0x20",
417 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
419 .target_residency = 300,
420 .enter = &intel_idle,
421 .enter_s2idle = intel_idle_s2idle, },
426 static struct cpuidle_state ivt_cstates_4s[] __initdata = {
429 .desc = "MWAIT 0x00",
430 .flags = MWAIT2flg(0x00),
432 .target_residency = 1,
433 .enter = &intel_idle,
434 .enter_s2idle = intel_idle_s2idle, },
437 .desc = "MWAIT 0x01",
438 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
440 .target_residency = 250,
441 .enter = &intel_idle,
442 .enter_s2idle = intel_idle_s2idle, },
445 .desc = "MWAIT 0x10",
446 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
448 .target_residency = 300,
449 .enter = &intel_idle,
450 .enter_s2idle = intel_idle_s2idle, },
453 .desc = "MWAIT 0x20",
454 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
456 .target_residency = 400,
457 .enter = &intel_idle,
458 .enter_s2idle = intel_idle_s2idle, },
463 static struct cpuidle_state ivt_cstates_8s[] __initdata = {
466 .desc = "MWAIT 0x00",
467 .flags = MWAIT2flg(0x00),
469 .target_residency = 1,
470 .enter = &intel_idle,
471 .enter_s2idle = intel_idle_s2idle, },
474 .desc = "MWAIT 0x01",
475 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
477 .target_residency = 500,
478 .enter = &intel_idle,
479 .enter_s2idle = intel_idle_s2idle, },
482 .desc = "MWAIT 0x10",
483 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
485 .target_residency = 600,
486 .enter = &intel_idle,
487 .enter_s2idle = intel_idle_s2idle, },
490 .desc = "MWAIT 0x20",
491 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
493 .target_residency = 700,
494 .enter = &intel_idle,
495 .enter_s2idle = intel_idle_s2idle, },
500 static struct cpuidle_state hsw_cstates[] __initdata = {
503 .desc = "MWAIT 0x00",
504 .flags = MWAIT2flg(0x00),
506 .target_residency = 2,
507 .enter = &intel_idle,
508 .enter_s2idle = intel_idle_s2idle, },
511 .desc = "MWAIT 0x01",
512 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
514 .target_residency = 20,
515 .enter = &intel_idle,
516 .enter_s2idle = intel_idle_s2idle, },
519 .desc = "MWAIT 0x10",
520 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
522 .target_residency = 100,
523 .enter = &intel_idle,
524 .enter_s2idle = intel_idle_s2idle, },
527 .desc = "MWAIT 0x20",
528 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
530 .target_residency = 400,
531 .enter = &intel_idle,
532 .enter_s2idle = intel_idle_s2idle, },
535 .desc = "MWAIT 0x32",
536 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
538 .target_residency = 500,
539 .enter = &intel_idle,
540 .enter_s2idle = intel_idle_s2idle, },
543 .desc = "MWAIT 0x40",
544 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
546 .target_residency = 900,
547 .enter = &intel_idle,
548 .enter_s2idle = intel_idle_s2idle, },
551 .desc = "MWAIT 0x50",
552 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
554 .target_residency = 1800,
555 .enter = &intel_idle,
556 .enter_s2idle = intel_idle_s2idle, },
559 .desc = "MWAIT 0x60",
560 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
561 .exit_latency = 2600,
562 .target_residency = 7700,
563 .enter = &intel_idle,
564 .enter_s2idle = intel_idle_s2idle, },
568 static struct cpuidle_state bdw_cstates[] __initdata = {
571 .desc = "MWAIT 0x00",
572 .flags = MWAIT2flg(0x00),
574 .target_residency = 2,
575 .enter = &intel_idle,
576 .enter_s2idle = intel_idle_s2idle, },
579 .desc = "MWAIT 0x01",
580 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
582 .target_residency = 20,
583 .enter = &intel_idle,
584 .enter_s2idle = intel_idle_s2idle, },
587 .desc = "MWAIT 0x10",
588 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
590 .target_residency = 100,
591 .enter = &intel_idle,
592 .enter_s2idle = intel_idle_s2idle, },
595 .desc = "MWAIT 0x20",
596 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
598 .target_residency = 400,
599 .enter = &intel_idle,
600 .enter_s2idle = intel_idle_s2idle, },
603 .desc = "MWAIT 0x32",
604 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
606 .target_residency = 500,
607 .enter = &intel_idle,
608 .enter_s2idle = intel_idle_s2idle, },
611 .desc = "MWAIT 0x40",
612 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
614 .target_residency = 900,
615 .enter = &intel_idle,
616 .enter_s2idle = intel_idle_s2idle, },
619 .desc = "MWAIT 0x50",
620 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
622 .target_residency = 1800,
623 .enter = &intel_idle,
624 .enter_s2idle = intel_idle_s2idle, },
627 .desc = "MWAIT 0x60",
628 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
629 .exit_latency = 2600,
630 .target_residency = 7700,
631 .enter = &intel_idle,
632 .enter_s2idle = intel_idle_s2idle, },
637 static struct cpuidle_state skl_cstates[] __initdata = {
640 .desc = "MWAIT 0x00",
641 .flags = MWAIT2flg(0x00),
643 .target_residency = 2,
644 .enter = &intel_idle,
645 .enter_s2idle = intel_idle_s2idle, },
648 .desc = "MWAIT 0x01",
649 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
651 .target_residency = 20,
652 .enter = &intel_idle,
653 .enter_s2idle = intel_idle_s2idle, },
656 .desc = "MWAIT 0x10",
657 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
659 .target_residency = 100,
660 .enter = &intel_idle,
661 .enter_s2idle = intel_idle_s2idle, },
664 .desc = "MWAIT 0x20",
665 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
667 .target_residency = 200,
668 .enter = &intel_idle,
669 .enter_s2idle = intel_idle_s2idle, },
672 .desc = "MWAIT 0x33",
673 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
675 .target_residency = 800,
676 .enter = &intel_idle,
677 .enter_s2idle = intel_idle_s2idle, },
680 .desc = "MWAIT 0x40",
681 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
683 .target_residency = 800,
684 .enter = &intel_idle,
685 .enter_s2idle = intel_idle_s2idle, },
688 .desc = "MWAIT 0x50",
689 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
691 .target_residency = 5000,
692 .enter = &intel_idle,
693 .enter_s2idle = intel_idle_s2idle, },
696 .desc = "MWAIT 0x60",
697 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
699 .target_residency = 5000,
700 .enter = &intel_idle,
701 .enter_s2idle = intel_idle_s2idle, },
706 static struct cpuidle_state skx_cstates[] __initdata = {
709 .desc = "MWAIT 0x00",
710 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE,
712 .target_residency = 2,
713 .enter = &intel_idle,
714 .enter_s2idle = intel_idle_s2idle, },
717 .desc = "MWAIT 0x01",
718 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
720 .target_residency = 20,
721 .enter = &intel_idle,
722 .enter_s2idle = intel_idle_s2idle, },
725 .desc = "MWAIT 0x20",
726 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
728 .target_residency = 600,
729 .enter = &intel_idle,
730 .enter_s2idle = intel_idle_s2idle, },
735 static struct cpuidle_state icx_cstates[] __initdata = {
738 .desc = "MWAIT 0x00",
739 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE,
741 .target_residency = 1,
742 .enter = &intel_idle,
743 .enter_s2idle = intel_idle_s2idle, },
746 .desc = "MWAIT 0x01",
747 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
749 .target_residency = 4,
750 .enter = &intel_idle,
751 .enter_s2idle = intel_idle_s2idle, },
754 .desc = "MWAIT 0x20",
755 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
757 .target_residency = 600,
758 .enter = &intel_idle,
759 .enter_s2idle = intel_idle_s2idle, },
764 static struct cpuidle_state atom_cstates[] __initdata = {
767 .desc = "MWAIT 0x00",
768 .flags = MWAIT2flg(0x00),
770 .target_residency = 20,
771 .enter = &intel_idle,
772 .enter_s2idle = intel_idle_s2idle, },
775 .desc = "MWAIT 0x10",
776 .flags = MWAIT2flg(0x10),
778 .target_residency = 80,
779 .enter = &intel_idle,
780 .enter_s2idle = intel_idle_s2idle, },
783 .desc = "MWAIT 0x30",
784 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
786 .target_residency = 400,
787 .enter = &intel_idle,
788 .enter_s2idle = intel_idle_s2idle, },
791 .desc = "MWAIT 0x52",
792 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
794 .target_residency = 560,
795 .enter = &intel_idle,
796 .enter_s2idle = intel_idle_s2idle, },
800 static struct cpuidle_state tangier_cstates[] __initdata = {
803 .desc = "MWAIT 0x00",
804 .flags = MWAIT2flg(0x00),
806 .target_residency = 4,
807 .enter = &intel_idle,
808 .enter_s2idle = intel_idle_s2idle, },
811 .desc = "MWAIT 0x30",
812 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
814 .target_residency = 400,
815 .enter = &intel_idle,
816 .enter_s2idle = intel_idle_s2idle, },
819 .desc = "MWAIT 0x52",
820 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
822 .target_residency = 560,
823 .enter = &intel_idle,
824 .enter_s2idle = intel_idle_s2idle, },
827 .desc = "MWAIT 0x60",
828 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
829 .exit_latency = 1200,
830 .target_residency = 4000,
831 .enter = &intel_idle,
832 .enter_s2idle = intel_idle_s2idle, },
835 .desc = "MWAIT 0x64",
836 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
837 .exit_latency = 10000,
838 .target_residency = 20000,
839 .enter = &intel_idle,
840 .enter_s2idle = intel_idle_s2idle, },
844 static struct cpuidle_state avn_cstates[] __initdata = {
847 .desc = "MWAIT 0x00",
848 .flags = MWAIT2flg(0x00),
850 .target_residency = 2,
851 .enter = &intel_idle,
852 .enter_s2idle = intel_idle_s2idle, },
855 .desc = "MWAIT 0x51",
856 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
858 .target_residency = 45,
859 .enter = &intel_idle,
860 .enter_s2idle = intel_idle_s2idle, },
864 static struct cpuidle_state knl_cstates[] __initdata = {
867 .desc = "MWAIT 0x00",
868 .flags = MWAIT2flg(0x00),
870 .target_residency = 2,
871 .enter = &intel_idle,
872 .enter_s2idle = intel_idle_s2idle },
875 .desc = "MWAIT 0x10",
876 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
878 .target_residency = 500,
879 .enter = &intel_idle,
880 .enter_s2idle = intel_idle_s2idle },
885 static struct cpuidle_state bxt_cstates[] __initdata = {
888 .desc = "MWAIT 0x00",
889 .flags = MWAIT2flg(0x00),
891 .target_residency = 2,
892 .enter = &intel_idle,
893 .enter_s2idle = intel_idle_s2idle, },
896 .desc = "MWAIT 0x01",
897 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
899 .target_residency = 20,
900 .enter = &intel_idle,
901 .enter_s2idle = intel_idle_s2idle, },
904 .desc = "MWAIT 0x20",
905 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
907 .target_residency = 133,
908 .enter = &intel_idle,
909 .enter_s2idle = intel_idle_s2idle, },
912 .desc = "MWAIT 0x31",
913 .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
915 .target_residency = 155,
916 .enter = &intel_idle,
917 .enter_s2idle = intel_idle_s2idle, },
920 .desc = "MWAIT 0x40",
921 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
922 .exit_latency = 1000,
923 .target_residency = 1000,
924 .enter = &intel_idle,
925 .enter_s2idle = intel_idle_s2idle, },
928 .desc = "MWAIT 0x50",
929 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
930 .exit_latency = 2000,
931 .target_residency = 2000,
932 .enter = &intel_idle,
933 .enter_s2idle = intel_idle_s2idle, },
936 .desc = "MWAIT 0x60",
937 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
938 .exit_latency = 10000,
939 .target_residency = 10000,
940 .enter = &intel_idle,
941 .enter_s2idle = intel_idle_s2idle, },
946 static struct cpuidle_state dnv_cstates[] __initdata = {
949 .desc = "MWAIT 0x00",
950 .flags = MWAIT2flg(0x00),
952 .target_residency = 2,
953 .enter = &intel_idle,
954 .enter_s2idle = intel_idle_s2idle, },
957 .desc = "MWAIT 0x01",
958 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
960 .target_residency = 20,
961 .enter = &intel_idle,
962 .enter_s2idle = intel_idle_s2idle, },
965 .desc = "MWAIT 0x20",
966 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
968 .target_residency = 500,
969 .enter = &intel_idle,
970 .enter_s2idle = intel_idle_s2idle, },
976 * Note, depending on HW and FW revision, SnowRidge SoC may or may not support
977 * C6, and this is indicated in the CPUID mwait leaf.
979 static struct cpuidle_state snr_cstates[] __initdata = {
982 .desc = "MWAIT 0x00",
983 .flags = MWAIT2flg(0x00),
985 .target_residency = 2,
986 .enter = &intel_idle,
987 .enter_s2idle = intel_idle_s2idle, },
990 .desc = "MWAIT 0x01",
991 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
993 .target_residency = 25,
994 .enter = &intel_idle,
995 .enter_s2idle = intel_idle_s2idle, },
998 .desc = "MWAIT 0x20",
999 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
1000 .exit_latency = 130,
1001 .target_residency = 500,
1002 .enter = &intel_idle,
1003 .enter_s2idle = intel_idle_s2idle, },
1008 static const struct idle_cpu idle_cpu_nehalem __initconst = {
1009 .state_table = nehalem_cstates,
1010 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
1011 .disable_promotion_to_c1e = true,
1014 static const struct idle_cpu idle_cpu_nhx __initconst = {
1015 .state_table = nehalem_cstates,
1016 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
1017 .disable_promotion_to_c1e = true,
1021 static const struct idle_cpu idle_cpu_atom __initconst = {
1022 .state_table = atom_cstates,
1025 static const struct idle_cpu idle_cpu_tangier __initconst = {
1026 .state_table = tangier_cstates,
1029 static const struct idle_cpu idle_cpu_lincroft __initconst = {
1030 .state_table = atom_cstates,
1031 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
1034 static const struct idle_cpu idle_cpu_snb __initconst = {
1035 .state_table = snb_cstates,
1036 .disable_promotion_to_c1e = true,
1039 static const struct idle_cpu idle_cpu_snx __initconst = {
1040 .state_table = snb_cstates,
1041 .disable_promotion_to_c1e = true,
1045 static const struct idle_cpu idle_cpu_byt __initconst = {
1046 .state_table = byt_cstates,
1047 .disable_promotion_to_c1e = true,
1048 .byt_auto_demotion_disable_flag = true,
1051 static const struct idle_cpu idle_cpu_cht __initconst = {
1052 .state_table = cht_cstates,
1053 .disable_promotion_to_c1e = true,
1054 .byt_auto_demotion_disable_flag = true,
1057 static const struct idle_cpu idle_cpu_ivb __initconst = {
1058 .state_table = ivb_cstates,
1059 .disable_promotion_to_c1e = true,
1062 static const struct idle_cpu idle_cpu_ivt __initconst = {
1063 .state_table = ivt_cstates,
1064 .disable_promotion_to_c1e = true,
1068 static const struct idle_cpu idle_cpu_hsw __initconst = {
1069 .state_table = hsw_cstates,
1070 .disable_promotion_to_c1e = true,
1073 static const struct idle_cpu idle_cpu_hsx __initconst = {
1074 .state_table = hsw_cstates,
1075 .disable_promotion_to_c1e = true,
1079 static const struct idle_cpu idle_cpu_bdw __initconst = {
1080 .state_table = bdw_cstates,
1081 .disable_promotion_to_c1e = true,
1084 static const struct idle_cpu idle_cpu_bdx __initconst = {
1085 .state_table = bdw_cstates,
1086 .disable_promotion_to_c1e = true,
1090 static const struct idle_cpu idle_cpu_skl __initconst = {
1091 .state_table = skl_cstates,
1092 .disable_promotion_to_c1e = true,
1095 static const struct idle_cpu idle_cpu_skx __initconst = {
1096 .state_table = skx_cstates,
1097 .disable_promotion_to_c1e = true,
1101 static const struct idle_cpu idle_cpu_icx __initconst = {
1102 .state_table = icx_cstates,
1103 .disable_promotion_to_c1e = true,
1107 static const struct idle_cpu idle_cpu_avn __initconst = {
1108 .state_table = avn_cstates,
1109 .disable_promotion_to_c1e = true,
1113 static const struct idle_cpu idle_cpu_knl __initconst = {
1114 .state_table = knl_cstates,
1118 static const struct idle_cpu idle_cpu_bxt __initconst = {
1119 .state_table = bxt_cstates,
1120 .disable_promotion_to_c1e = true,
1123 static const struct idle_cpu idle_cpu_dnv __initconst = {
1124 .state_table = dnv_cstates,
1125 .disable_promotion_to_c1e = true,
1129 static const struct idle_cpu idle_cpu_snr __initconst = {
1130 .state_table = snr_cstates,
1131 .disable_promotion_to_c1e = true,
1135 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
1136 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &idle_cpu_nhx),
1137 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &idle_cpu_nehalem),
1138 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_G, &idle_cpu_nehalem),
1139 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE, &idle_cpu_nehalem),
1140 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP, &idle_cpu_nhx),
1141 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX, &idle_cpu_nhx),
1142 X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL, &idle_cpu_atom),
1143 X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL_MID, &idle_cpu_lincroft),
1144 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX, &idle_cpu_nhx),
1145 X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &idle_cpu_snb),
1146 X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &idle_cpu_snx),
1147 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL, &idle_cpu_atom),
1148 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &idle_cpu_byt),
1149 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &idle_cpu_tangier),
1150 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &idle_cpu_cht),
1151 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &idle_cpu_ivb),
1152 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &idle_cpu_ivt),
1153 X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &idle_cpu_hsw),
1154 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &idle_cpu_hsx),
1155 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &idle_cpu_hsw),
1156 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &idle_cpu_hsw),
1157 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, &idle_cpu_avn),
1158 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &idle_cpu_bdw),
1159 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &idle_cpu_bdw),
1160 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &idle_cpu_bdx),
1161 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &idle_cpu_bdx),
1162 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &idle_cpu_skl),
1163 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &idle_cpu_skl),
1164 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &idle_cpu_skl),
1165 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &idle_cpu_skl),
1166 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &idle_cpu_skx),
1167 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &idle_cpu_icx),
1168 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &idle_cpu_icx),
1169 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl),
1170 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl),
1171 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &idle_cpu_bxt),
1172 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &idle_cpu_bxt),
1173 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &idle_cpu_dnv),
1174 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &idle_cpu_snr),
1178 static const struct x86_cpu_id intel_mwait_ids[] __initconst = {
1179 X86_MATCH_VENDOR_FAM_FEATURE(INTEL, 6, X86_FEATURE_MWAIT, NULL),
1183 static bool __init intel_idle_max_cstate_reached(int cstate)
1185 if (cstate + 1 > max_cstate) {
1186 pr_info("max_cstate %d reached\n", max_cstate);
1192 static bool __init intel_idle_state_needs_timer_stop(struct cpuidle_state *state)
1194 unsigned long eax = flg2MWAIT(state->flags);
1196 if (boot_cpu_has(X86_FEATURE_ARAT))
1200 * Switch over to one-shot tick broadcast if the target C-state
1201 * is deeper than C1.
1203 return !!((eax >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK);
1206 #ifdef CONFIG_ACPI_PROCESSOR_CSTATE
1207 #include <acpi/processor.h>
1209 static bool no_acpi __read_mostly;
1210 module_param(no_acpi, bool, 0444);
1211 MODULE_PARM_DESC(no_acpi, "Do not use ACPI _CST for building the idle states list");
1213 static bool force_use_acpi __read_mostly; /* No effect if no_acpi is set. */
1214 module_param_named(use_acpi, force_use_acpi, bool, 0444);
1215 MODULE_PARM_DESC(use_acpi, "Use ACPI _CST for building the idle states list");
1217 static struct acpi_processor_power acpi_state_table __initdata;
1220 * intel_idle_cst_usable - Check if the _CST information can be used.
1222 * Check if all of the C-states listed by _CST in the max_cstate range are
1223 * ACPI_CSTATE_FFH, which means that they should be entered via MWAIT.
1225 static bool __init intel_idle_cst_usable(void)
1229 limit = min_t(int, min_t(int, CPUIDLE_STATE_MAX, max_cstate + 1),
1230 acpi_state_table.count);
1232 for (cstate = 1; cstate < limit; cstate++) {
1233 struct acpi_processor_cx *cx = &acpi_state_table.states[cstate];
1235 if (cx->entry_method != ACPI_CSTATE_FFH)
1242 static bool __init intel_idle_acpi_cst_extract(void)
1247 pr_debug("Not allowed to use ACPI _CST\n");
1251 for_each_possible_cpu(cpu) {
1252 struct acpi_processor *pr = per_cpu(processors, cpu);
1257 if (acpi_processor_evaluate_cst(pr->handle, cpu, &acpi_state_table))
1260 acpi_state_table.count++;
1262 if (!intel_idle_cst_usable())
1265 if (!acpi_processor_claim_cst_control())
1271 acpi_state_table.count = 0;
1272 pr_debug("ACPI _CST not found or not usable\n");
1276 static void __init intel_idle_init_cstates_acpi(struct cpuidle_driver *drv)
1278 int cstate, limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1281 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1282 * the interesting states are ACPI_CSTATE_FFH.
1284 for (cstate = 1; cstate < limit; cstate++) {
1285 struct acpi_processor_cx *cx;
1286 struct cpuidle_state *state;
1288 if (intel_idle_max_cstate_reached(cstate - 1))
1291 cx = &acpi_state_table.states[cstate];
1293 state = &drv->states[drv->state_count++];
1295 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d_ACPI", cstate);
1296 strlcpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1297 state->exit_latency = cx->latency;
1299 * For C1-type C-states use the same number for both the exit
1300 * latency and target residency, because that is the case for
1301 * C1 in the majority of the static C-states tables above.
1302 * For the other types of C-states, however, set the target
1303 * residency to 3 times the exit latency which should lead to
1304 * a reasonable balance between energy-efficiency and
1305 * performance in the majority of interesting cases.
1307 state->target_residency = cx->latency;
1308 if (cx->type > ACPI_STATE_C1)
1309 state->target_residency *= 3;
1311 state->flags = MWAIT2flg(cx->address);
1312 if (cx->type > ACPI_STATE_C2)
1313 state->flags |= CPUIDLE_FLAG_TLB_FLUSHED;
1315 if (disabled_states_mask & BIT(cstate))
1316 state->flags |= CPUIDLE_FLAG_OFF;
1318 if (intel_idle_state_needs_timer_stop(state))
1319 state->flags |= CPUIDLE_FLAG_TIMER_STOP;
1321 state->enter = intel_idle;
1322 state->enter_s2idle = intel_idle_s2idle;
1326 static bool __init intel_idle_off_by_default(u32 mwait_hint)
1331 * If there are no _CST C-states, do not disable any C-states by
1334 if (!acpi_state_table.count)
1337 limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1339 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1340 * the interesting states are ACPI_CSTATE_FFH.
1342 for (cstate = 1; cstate < limit; cstate++) {
1343 if (acpi_state_table.states[cstate].address == mwait_hint)
1348 #else /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1349 #define force_use_acpi (false)
1351 static inline bool intel_idle_acpi_cst_extract(void) { return false; }
1352 static inline void intel_idle_init_cstates_acpi(struct cpuidle_driver *drv) { }
1353 static inline bool intel_idle_off_by_default(u32 mwait_hint) { return false; }
1354 #endif /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1357 * ivt_idle_state_table_update - Tune the idle states table for Ivy Town.
1359 * Tune IVT multi-socket targets.
1360 * Assumption: num_sockets == (max_package_num + 1).
1362 static void __init ivt_idle_state_table_update(void)
1364 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
1365 int cpu, package_num, num_sockets = 1;
1367 for_each_online_cpu(cpu) {
1368 package_num = topology_physical_package_id(cpu);
1369 if (package_num + 1 > num_sockets) {
1370 num_sockets = package_num + 1;
1372 if (num_sockets > 4) {
1373 cpuidle_state_table = ivt_cstates_8s;
1379 if (num_sockets > 2)
1380 cpuidle_state_table = ivt_cstates_4s;
1382 /* else, 1 and 2 socket systems use default ivt_cstates */
1386 * irtl_2_usec - IRTL to microseconds conversion.
1387 * @irtl: IRTL MSR value.
1389 * Translate the IRTL (Interrupt Response Time Limit) MSR value to microseconds.
1391 static unsigned long long __init irtl_2_usec(unsigned long long irtl)
1393 static const unsigned int irtl_ns_units[] __initconst = {
1394 1, 32, 1024, 32768, 1048576, 33554432, 0, 0
1396 unsigned long long ns;
1401 ns = irtl_ns_units[(irtl >> 10) & 0x7];
1403 return div_u64((irtl & 0x3FF) * ns, NSEC_PER_USEC);
1407 * bxt_idle_state_table_update - Fix up the Broxton idle states table.
1409 * On BXT, trust the IRTL (Interrupt Response Time Limit) MSR to show the
1410 * definitive maximum latency and use the same value for target_residency.
1412 static void __init bxt_idle_state_table_update(void)
1414 unsigned long long msr;
1417 rdmsrl(MSR_PKGC6_IRTL, msr);
1418 usec = irtl_2_usec(msr);
1420 bxt_cstates[2].exit_latency = usec;
1421 bxt_cstates[2].target_residency = usec;
1424 rdmsrl(MSR_PKGC7_IRTL, msr);
1425 usec = irtl_2_usec(msr);
1427 bxt_cstates[3].exit_latency = usec;
1428 bxt_cstates[3].target_residency = usec;
1431 rdmsrl(MSR_PKGC8_IRTL, msr);
1432 usec = irtl_2_usec(msr);
1434 bxt_cstates[4].exit_latency = usec;
1435 bxt_cstates[4].target_residency = usec;
1438 rdmsrl(MSR_PKGC9_IRTL, msr);
1439 usec = irtl_2_usec(msr);
1441 bxt_cstates[5].exit_latency = usec;
1442 bxt_cstates[5].target_residency = usec;
1445 rdmsrl(MSR_PKGC10_IRTL, msr);
1446 usec = irtl_2_usec(msr);
1448 bxt_cstates[6].exit_latency = usec;
1449 bxt_cstates[6].target_residency = usec;
1455 * sklh_idle_state_table_update - Fix up the Sky Lake idle states table.
1457 * On SKL-H (model 0x5e) skip C8 and C9 if C10 is enabled and SGX disabled.
1459 static void __init sklh_idle_state_table_update(void)
1461 unsigned long long msr;
1462 unsigned int eax, ebx, ecx, edx;
1465 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1466 if (max_cstate <= 7)
1469 /* if PC10 not present in CPUID.MWAIT.EDX */
1470 if ((mwait_substates & (0xF << 28)) == 0)
1473 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1475 /* PC10 is not enabled in PKG C-state limit */
1476 if ((msr & 0xF) != 8)
1480 cpuid(7, &eax, &ebx, &ecx, &edx);
1482 /* if SGX is present */
1483 if (ebx & (1 << 2)) {
1485 rdmsrl(MSR_IA32_FEAT_CTL, msr);
1487 /* if SGX is enabled */
1488 if (msr & (1 << 18))
1492 skl_cstates[5].flags |= CPUIDLE_FLAG_UNUSABLE; /* C8-SKL */
1493 skl_cstates[6].flags |= CPUIDLE_FLAG_UNUSABLE; /* C9-SKL */
1497 * skx_idle_state_table_update - Adjust the Sky Lake/Cascade Lake
1498 * idle states table.
1500 static void __init skx_idle_state_table_update(void)
1502 unsigned long long msr;
1504 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1507 * 000b: C0/C1 (no package C-state support)
1509 * 010b: C6 (non-retention)
1510 * 011b: C6 (retention)
1511 * 111b: No Package C state limits.
1513 if ((msr & 0x7) < 2) {
1515 * Uses the CC6 + PC0 latency and 3 times of
1516 * latency for target_residency if the PC6
1517 * is disabled in BIOS. This is consistent
1518 * with how intel_idle driver uses _CST
1519 * to set the target_residency.
1521 skx_cstates[2].exit_latency = 92;
1522 skx_cstates[2].target_residency = 276;
1526 static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)
1528 unsigned int mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint) + 1;
1529 unsigned int num_substates = (mwait_substates >> mwait_cstate * 4) &
1530 MWAIT_SUBSTATE_MASK;
1532 /* Ignore the C-state if there are NO sub-states in CPUID for it. */
1533 if (num_substates == 0)
1536 if (mwait_cstate > 2 && !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1537 mark_tsc_unstable("TSC halts in idle states deeper than C2");
1542 static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
1546 switch (boot_cpu_data.x86_model) {
1547 case INTEL_FAM6_IVYBRIDGE_X:
1548 ivt_idle_state_table_update();
1550 case INTEL_FAM6_ATOM_GOLDMONT:
1551 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
1552 bxt_idle_state_table_update();
1554 case INTEL_FAM6_SKYLAKE:
1555 sklh_idle_state_table_update();
1557 case INTEL_FAM6_SKYLAKE_X:
1558 skx_idle_state_table_update();
1562 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
1563 unsigned int mwait_hint;
1565 if (intel_idle_max_cstate_reached(cstate))
1568 if (!cpuidle_state_table[cstate].enter &&
1569 !cpuidle_state_table[cstate].enter_s2idle)
1572 /* If marked as unusable, skip this state. */
1573 if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_UNUSABLE) {
1574 pr_debug("state %s is disabled\n",
1575 cpuidle_state_table[cstate].name);
1579 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
1580 if (!intel_idle_verify_cstate(mwait_hint))
1583 /* Structure copy. */
1584 drv->states[drv->state_count] = cpuidle_state_table[cstate];
1586 if ((disabled_states_mask & BIT(drv->state_count)) ||
1587 ((icpu->use_acpi || force_use_acpi) &&
1588 intel_idle_off_by_default(mwait_hint) &&
1589 !(cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_ALWAYS_ENABLE)))
1590 drv->states[drv->state_count].flags |= CPUIDLE_FLAG_OFF;
1592 if (intel_idle_state_needs_timer_stop(&drv->states[drv->state_count]))
1593 drv->states[drv->state_count].flags |= CPUIDLE_FLAG_TIMER_STOP;
1598 if (icpu->byt_auto_demotion_disable_flag) {
1599 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1600 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1605 * intel_idle_cpuidle_driver_init - Create the list of available idle states.
1606 * @drv: cpuidle driver structure to initialize.
1608 static void __init intel_idle_cpuidle_driver_init(struct cpuidle_driver *drv)
1610 cpuidle_poll_state_init(drv);
1612 if (disabled_states_mask & BIT(0))
1613 drv->states[0].flags |= CPUIDLE_FLAG_OFF;
1615 drv->state_count = 1;
1618 intel_idle_init_cstates_icpu(drv);
1620 intel_idle_init_cstates_acpi(drv);
1623 static void auto_demotion_disable(void)
1625 unsigned long long msr_bits;
1627 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1628 msr_bits &= ~auto_demotion_disable_flags;
1629 wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1632 static void c1e_promotion_disable(void)
1634 unsigned long long msr_bits;
1636 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
1638 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
1642 * intel_idle_cpu_init - Register the target CPU with the cpuidle core.
1643 * @cpu: CPU to initialize.
1645 * Register a cpuidle device object for @cpu and update its MSRs in accordance
1646 * with the processor model flags.
1648 static int intel_idle_cpu_init(unsigned int cpu)
1650 struct cpuidle_device *dev;
1652 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1655 if (cpuidle_register_device(dev)) {
1656 pr_debug("cpuidle_register_device %d failed!\n", cpu);
1660 if (auto_demotion_disable_flags)
1661 auto_demotion_disable();
1663 if (disable_promotion_to_c1e)
1664 c1e_promotion_disable();
1669 static int intel_idle_cpu_online(unsigned int cpu)
1671 struct cpuidle_device *dev;
1673 if (!boot_cpu_has(X86_FEATURE_ARAT))
1674 tick_broadcast_enable();
1677 * Some systems can hotplug a cpu at runtime after
1678 * the kernel has booted, we have to initialize the
1679 * driver in this case
1681 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1682 if (!dev->registered)
1683 return intel_idle_cpu_init(cpu);
1689 * intel_idle_cpuidle_devices_uninit - Unregister all cpuidle devices.
1691 static void __init intel_idle_cpuidle_devices_uninit(void)
1695 for_each_online_cpu(i)
1696 cpuidle_unregister_device(per_cpu_ptr(intel_idle_cpuidle_devices, i));
1699 static int __init intel_idle_init(void)
1701 const struct x86_cpu_id *id;
1702 unsigned int eax, ebx, ecx;
1705 /* Do not load intel_idle at all for now if idle= is passed */
1706 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1709 if (max_cstate == 0) {
1710 pr_debug("disabled\n");
1714 id = x86_match_cpu(intel_idle_ids);
1716 if (!boot_cpu_has(X86_FEATURE_MWAIT)) {
1717 pr_debug("Please enable MWAIT in BIOS SETUP\n");
1721 id = x86_match_cpu(intel_mwait_ids);
1726 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1729 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
1731 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
1732 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
1736 pr_debug("MWAIT substates: 0x%x\n", mwait_substates);
1738 icpu = (const struct idle_cpu *)id->driver_data;
1740 cpuidle_state_table = icpu->state_table;
1741 auto_demotion_disable_flags = icpu->auto_demotion_disable_flags;
1742 disable_promotion_to_c1e = icpu->disable_promotion_to_c1e;
1743 if (icpu->use_acpi || force_use_acpi)
1744 intel_idle_acpi_cst_extract();
1745 } else if (!intel_idle_acpi_cst_extract()) {
1749 pr_debug("v" INTEL_IDLE_VERSION " model 0x%X\n",
1750 boot_cpu_data.x86_model);
1752 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1753 if (!intel_idle_cpuidle_devices)
1756 intel_idle_cpuidle_driver_init(&intel_idle_driver);
1758 retval = cpuidle_register_driver(&intel_idle_driver);
1760 struct cpuidle_driver *drv = cpuidle_get_driver();
1761 printk(KERN_DEBUG pr_fmt("intel_idle yielding to %s\n"),
1762 drv ? drv->name : "none");
1763 goto init_driver_fail;
1766 retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online",
1767 intel_idle_cpu_online, NULL);
1771 pr_debug("Local APIC timer is reliable in %s\n",
1772 boot_cpu_has(X86_FEATURE_ARAT) ? "all C-states" : "C1");
1777 intel_idle_cpuidle_devices_uninit();
1778 cpuidle_unregister_driver(&intel_idle_driver);
1780 free_percpu(intel_idle_cpuidle_devices);
1784 device_initcall(intel_idle_init);
1787 * We are not really modular, but we used to support that. Meaning we also
1788 * support "intel_idle.max_cstate=..." at boot and also a read-only export of
1789 * it at /sys/module/intel_idle/parameters/max_cstate -- so using module_param
1790 * is the easiest way (currently) to continue doing that.
1792 module_param(max_cstate, int, 0444);
1794 * The positions of the bits that are set in this number are the indices of the
1795 * idle states to be disabled by default (as reflected by the names of the
1796 * corresponding idle state directories in sysfs, "state0", "state1" ...
1797 * "state<i>" ..., where <i> is the index of the given state).
1799 module_param_named(states_off, disabled_states_mask, uint, 0444);
1800 MODULE_PARM_DESC(states_off, "Mask of disabled idle states");