3 * Copyright (c) 2002-2007 Xilinx Inc.
4 * Copyright (c) 2009-2010 Intel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 * This code was implemented by Mocean Laboratories AB when porting linux
21 * to the automotive development board Russellville. The copyright holder
22 * as seen in the header is Intel corporation.
23 * Mocean Laboratories forked off the GNU/Linux platform work into a
24 * separate company called Pelagicore AB, which committed the code to the
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/init.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/delay.h>
37 #include <linux/platform_device.h>
38 #include <linux/i2c.h>
39 #include <linux/interrupt.h>
40 #include <linux/wait.h>
41 #include <linux/i2c-xiic.h>
43 #include <linux/slab.h>
46 #define DRIVER_NAME "xiic-i2c"
48 enum xilinx_i2c_state {
55 * struct xiic_i2c - Internal representation of the XIIC I2C bus
56 * @base: Memory base of the HW registers
57 * @wait: Wait queue for callers
58 * @adap: Kernel adapter representation
59 * @tx_msg: Messages from above to be sent
60 * @lock: Mutual exclusion
61 * @tx_pos: Current pos in TX message
62 * @nmsgs: Number of messages in tx_msg
64 * @rx_msg: Current RX message
65 * @rx_pos: Position within current RX message
69 wait_queue_head_t wait;
70 struct i2c_adapter adap;
71 struct i2c_msg *tx_msg;
75 enum xilinx_i2c_state state;
76 struct i2c_msg *rx_msg;
81 #define XIIC_MSB_OFFSET 0
82 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
85 * Register offsets in bytes from RegisterBase. Three is added to the
86 * base offset to access LSB (IBM style) of the word
88 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
89 #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
90 #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
91 #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
92 #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
93 #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
94 #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
95 #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
96 #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
97 #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
99 /* Control Register masks */
100 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
101 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
102 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
103 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
104 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
105 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
106 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
108 /* Status Register masks */
109 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
110 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
111 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
112 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
113 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
114 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
115 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
116 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
118 /* Interrupt Status Register masks Interrupt occurs when... */
119 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
120 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
121 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
122 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
123 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
124 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
125 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
126 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
128 /* The following constants specify the depth of the FIFOs */
129 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
130 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
132 /* The following constants specify groups of interrupts that are typically
133 * enabled or disables at the same time
135 #define XIIC_TX_INTERRUPTS \
136 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
138 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
140 /* The following constants are used with the following macros to specify the
141 * operation, a read or write operation.
143 #define XIIC_READ_OPERATION 1
144 #define XIIC_WRITE_OPERATION 0
147 * Tx Fifo upper bit masks.
149 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
150 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
153 * The following constants define the register offsets for the Interrupt
154 * registers. There are some holes in the memory map for reserved addresses
155 * to allow other registers to be added and still match the memory map of the
156 * interrupt controller registers
158 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
159 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
160 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
161 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
163 #define XIIC_RESET_MASK 0xAUL
166 * The following constant is used for the device global interrupt enable
167 * register, to enable all interrupts for the device, this is the only bit
170 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL
172 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
173 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
175 static void xiic_start_xfer(struct xiic_i2c *i2c);
176 static void __xiic_start_xfer(struct xiic_i2c *i2c);
178 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
180 iowrite8(value, i2c->base + reg);
183 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
185 return ioread8(i2c->base + reg);
188 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
190 iowrite16(value, i2c->base + reg);
193 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
195 iowrite32(value, i2c->base + reg);
198 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
200 return ioread32(i2c->base + reg);
203 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
205 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
206 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
209 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
211 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
212 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
215 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
217 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
218 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
221 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
223 xiic_irq_clr(i2c, mask);
224 xiic_irq_en(i2c, mask);
227 static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
230 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
231 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
232 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
233 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
236 static void xiic_reinit(struct xiic_i2c *i2c)
238 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
240 /* Set receive Fifo depth to maximum (zero based). */
241 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
244 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
246 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
247 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
249 /* make sure RX fifo is empty */
250 xiic_clear_rx_fifo(i2c);
252 /* Enable interrupts */
253 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
255 xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK);
258 static void xiic_deinit(struct xiic_i2c *i2c)
262 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
264 /* Disable IIC Device. */
265 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
266 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
269 static void xiic_read_rx(struct xiic_i2c *i2c)
274 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
276 dev_dbg(i2c->adap.dev.parent,
277 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n",
278 __func__, bytes_in_fifo, xiic_rx_space(i2c),
279 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
280 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
282 if (bytes_in_fifo > xiic_rx_space(i2c))
283 bytes_in_fifo = xiic_rx_space(i2c);
285 for (i = 0; i < bytes_in_fifo; i++)
286 i2c->rx_msg->buf[i2c->rx_pos++] =
287 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
289 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
290 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
291 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1);
294 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
296 /* return the actual space left in the FIFO */
297 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
300 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
302 u8 fifo_space = xiic_tx_fifo_space(i2c);
303 int len = xiic_tx_space(i2c);
305 len = (len > fifo_space) ? fifo_space : len;
307 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
308 __func__, len, fifo_space);
311 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
312 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
313 /* last message in transfer -> STOP */
314 data |= XIIC_TX_DYN_STOP_MASK;
315 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
317 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
321 static void xiic_wakeup(struct xiic_i2c *i2c, int code)
330 static void xiic_process(struct xiic_i2c *i2c)
335 /* Get the interrupt Status from the IPIF. There is no clearing of
336 * interrupts in the IPIF. Interrupts must be cleared at the source.
337 * To find which interrupts are pending; AND interrupts pending with
340 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
341 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
344 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
345 __func__, ier, isr, pend);
346 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
347 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
348 i2c->tx_msg, i2c->nmsgs);
350 /* Do not processes a devices interrupts if the device has no
356 /* Service requesting interrupt */
357 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
358 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
359 !(pend & XIIC_INTR_RX_FULL_MASK))) {
360 /* bus arbritration lost, or...
361 * Transmit error _OR_ RX completed
362 * if this happens when RX_FULL is not set
363 * this is probably a TX error
366 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
368 /* dynamic mode seem to suffer from problems if we just flushes
369 * fifos and the next message is a TX with len 0 (only addr)
370 * reset the IP instead of just flush fifos
375 xiic_wakeup(i2c, STATE_ERROR);
377 } else if (pend & XIIC_INTR_RX_FULL_MASK) {
378 /* Receive register/FIFO is full */
380 clr = XIIC_INTR_RX_FULL_MASK;
382 dev_dbg(i2c->adap.dev.parent,
383 "%s unexpexted RX IRQ\n", __func__);
384 xiic_clear_rx_fifo(i2c);
389 if (xiic_rx_space(i2c) == 0) {
390 /* this is the last part of the message */
393 /* also clear TX error if there (RX complete) */
394 clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
396 dev_dbg(i2c->adap.dev.parent,
397 "%s end of message, nmsgs: %d\n",
398 __func__, i2c->nmsgs);
400 /* send next message if this wasn't the last,
401 * otherwise the transfer will be finialise when
402 * receiving the bus not busy interrupt
404 if (i2c->nmsgs > 1) {
407 dev_dbg(i2c->adap.dev.parent,
408 "%s will start next...\n", __func__);
410 __xiic_start_xfer(i2c);
413 } else if (pend & XIIC_INTR_BNB_MASK) {
414 /* IIC bus has transitioned to not busy */
415 clr = XIIC_INTR_BNB_MASK;
417 /* The bus is not busy, disable BusNotBusy interrupt */
418 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
423 if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
424 xiic_tx_space(i2c) == 0)
425 xiic_wakeup(i2c, STATE_DONE);
427 xiic_wakeup(i2c, STATE_ERROR);
429 } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
430 /* Transmit register/FIFO is empty or ½ empty */
433 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK);
436 dev_dbg(i2c->adap.dev.parent,
437 "%s unexpexted TX IRQ\n", __func__);
441 xiic_fill_tx_fifo(i2c);
443 /* current message sent and there is space in the fifo */
444 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
445 dev_dbg(i2c->adap.dev.parent,
446 "%s end of message sent, nmsgs: %d\n",
447 __func__, i2c->nmsgs);
448 if (i2c->nmsgs > 1) {
451 __xiic_start_xfer(i2c);
453 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
455 dev_dbg(i2c->adap.dev.parent,
456 "%s Got TX IRQ but no more to do...\n",
459 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
460 /* current frame is sent and is last,
461 * make sure to disable tx half
463 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
465 /* got IRQ which is not acked */
466 dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n",
471 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
473 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
476 static int xiic_bus_busy(struct xiic_i2c *i2c)
478 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
480 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
483 static int xiic_busy(struct xiic_i2c *i2c)
491 /* for instance if previous transfer was terminated due to TX error
492 * it might be that the bus is on it's way to become available
493 * give it at most 3 ms to wake
495 err = xiic_bus_busy(i2c);
496 while (err && tries--) {
498 err = xiic_bus_busy(i2c);
504 static void xiic_start_recv(struct xiic_i2c *i2c)
507 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
509 /* Clear and enable Rx full interrupt. */
510 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
512 /* we want to get all but last byte, because the TX_ERROR IRQ is used
513 * to inidicate error ACK on the address, and negative ack on the last
514 * received byte, so to not mix them receive all but last.
515 * In the case where there is only one byte to receive
516 * we can check if ERROR and RX full is set at the same time
518 rx_watermark = msg->len;
519 if (rx_watermark > IIC_RX_FIFO_DEPTH)
520 rx_watermark = IIC_RX_FIFO_DEPTH;
521 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
523 if (!(msg->flags & I2C_M_NOSTART))
524 /* write the address */
525 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
526 (msg->addr << 1) | XIIC_READ_OPERATION |
527 XIIC_TX_DYN_START_MASK);
529 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
531 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
532 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
534 /* very last, enable bus not busy as well */
535 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
537 /* the message is tx:ed */
538 i2c->tx_pos = msg->len;
541 static void xiic_start_send(struct xiic_i2c *i2c)
543 struct i2c_msg *msg = i2c->tx_msg;
545 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
547 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
548 __func__, msg, msg->len);
549 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
550 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
551 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
553 if (!(msg->flags & I2C_M_NOSTART)) {
554 /* write the address */
555 u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION |
556 XIIC_TX_DYN_START_MASK;
557 if ((i2c->nmsgs == 1) && msg->len == 0)
558 /* no data and last message -> add STOP */
559 data |= XIIC_TX_DYN_STOP_MASK;
561 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
564 xiic_fill_tx_fifo(i2c);
566 /* Clear any pending Tx empty, Tx Error and then enable them. */
567 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
571 static irqreturn_t xiic_isr(int irq, void *dev_id)
573 struct xiic_i2c *i2c = dev_id;
575 spin_lock(&i2c->lock);
576 /* disable interrupts globally */
577 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
579 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
583 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
584 spin_unlock(&i2c->lock);
589 static void __xiic_start_xfer(struct xiic_i2c *i2c)
592 int fifo_space = xiic_tx_fifo_space(i2c);
593 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
594 __func__, i2c->tx_msg, fifo_space);
601 i2c->state = STATE_START;
602 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
610 if (i2c->tx_msg->flags & I2C_M_RD) {
611 /* we dont date putting several reads in the FIFO */
612 xiic_start_recv(i2c);
615 xiic_start_send(i2c);
616 if (xiic_tx_space(i2c) != 0) {
617 /* the message could not be completely sent */
622 fifo_space = xiic_tx_fifo_space(i2c);
625 /* there are more messages or the current one could not be completely
626 * put into the FIFO, also enable the half empty interrupt
628 if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
629 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
633 static void xiic_start_xfer(struct xiic_i2c *i2c)
637 spin_lock_irqsave(&i2c->lock, flags);
639 /* disable interrupts globally */
640 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
641 spin_unlock_irqrestore(&i2c->lock, flags);
643 __xiic_start_xfer(i2c);
644 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
647 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
649 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
652 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
653 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
655 err = xiic_busy(i2c);
662 xiic_start_xfer(i2c);
664 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
665 (i2c->state == STATE_DONE), HZ))
666 return (i2c->state == STATE_DONE) ? num : -EIO;
675 static u32 xiic_func(struct i2c_adapter *adap)
677 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
680 static const struct i2c_algorithm xiic_algorithm = {
681 .master_xfer = xiic_xfer,
682 .functionality = xiic_func,
685 static struct i2c_adapter xiic_adapter = {
686 .owner = THIS_MODULE,
688 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
689 .algo = &xiic_algorithm,
693 static int xiic_i2c_probe(struct platform_device *pdev)
695 struct xiic_i2c *i2c;
696 struct xiic_i2c_platform_data *pdata;
697 struct resource *res;
701 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
705 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
706 i2c->base = devm_ioremap_resource(&pdev->dev, res);
707 if (IS_ERR(i2c->base))
708 return PTR_ERR(i2c->base);
710 irq = platform_get_irq(pdev, 0);
714 pdata = dev_get_platdata(&pdev->dev);
716 /* hook up driver to tree */
717 platform_set_drvdata(pdev, i2c);
718 i2c->adap = xiic_adapter;
719 i2c_set_adapdata(&i2c->adap, i2c);
720 i2c->adap.dev.parent = &pdev->dev;
721 i2c->adap.dev.of_node = pdev->dev.of_node;
723 spin_lock_init(&i2c->lock);
724 init_waitqueue_head(&i2c->wait);
726 ret = devm_request_irq(&pdev->dev, irq, xiic_isr, 0, pdev->name, i2c);
728 dev_err(&pdev->dev, "Cannot claim IRQ\n");
734 /* add i2c adapter to i2c tree */
735 ret = i2c_add_adapter(&i2c->adap);
737 dev_err(&pdev->dev, "Failed to add adapter\n");
743 /* add in known devices to the bus */
744 for (i = 0; i < pdata->num_devices; i++)
745 i2c_new_device(&i2c->adap, pdata->devices + i);
751 static int xiic_i2c_remove(struct platform_device *pdev)
753 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
755 /* remove adapter & data */
756 i2c_del_adapter(&i2c->adap);
763 #if defined(CONFIG_OF)
764 static const struct of_device_id xiic_of_match[] = {
765 { .compatible = "xlnx,xps-iic-2.00.a", },
768 MODULE_DEVICE_TABLE(of, xiic_of_match);
771 static struct platform_driver xiic_i2c_driver = {
772 .probe = xiic_i2c_probe,
773 .remove = xiic_i2c_remove,
775 .owner = THIS_MODULE,
777 .of_match_table = of_match_ptr(xiic_of_match),
781 module_platform_driver(xiic_i2c_driver);
783 MODULE_AUTHOR("info@mocean-labs.com");
784 MODULE_DESCRIPTION("Xilinx I2C bus driver");
785 MODULE_LICENSE("GPL v2");
786 MODULE_ALIAS("platform:"DRIVER_NAME);