drivers/i2c/busses/i2c-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * drivers/i2c/busses/i2c-tegra.c
   4  *
   5  * Copyright (C) 2010 Google, Inc.
   6  * Author: Colin Cross <ccross@android.com>
   7  */
   8
   9 #include <linux/bitfield.h>
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/err.h>
  15 #include <linux/i2c.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/irq.h>
  21 #include <linux/kernel.h>
  22 #include <linux/ktime.h>
  23 #include <linux/module.h>
  24 #include <linux/of_device.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/reset.h>
  29
  30 #define BYTES_PER_FIFO_WORD 4
  31
  32 #define I2C_CNFG                                0x000
  33 #define I2C_CNFG_DEBOUNCE_CNT                   GENMASK(14, 12)
  34 #define I2C_CNFG_PACKET_MODE_EN                 BIT(10)
  35 #define I2C_CNFG_NEW_MASTER_FSM                 BIT(11)
  36 #define I2C_CNFG_MULTI_MASTER_MODE              BIT(17)
  37 #define I2C_STATUS                              0x01c
  38 #define I2C_SL_CNFG                             0x020
  39 #define I2C_SL_CNFG_NACK                        BIT(1)
  40 #define I2C_SL_CNFG_NEWSL                       BIT(2)
  41 #define I2C_SL_ADDR1                            0x02c
  42 #define I2C_SL_ADDR2                            0x030
  43 #define I2C_TLOW_SEXT                           0x034
  44 #define I2C_TX_FIFO                             0x050
  45 #define I2C_RX_FIFO                             0x054
  46 #define I2C_PACKET_TRANSFER_STATUS              0x058
  47 #define I2C_FIFO_CONTROL                        0x05c
  48 #define I2C_FIFO_CONTROL_TX_FLUSH               BIT(1)
  49 #define I2C_FIFO_CONTROL_RX_FLUSH               BIT(0)
  50 #define I2C_FIFO_CONTROL_TX_TRIG(x)             (((x) - 1) << 5)
  51 #define I2C_FIFO_CONTROL_RX_TRIG(x)             (((x) - 1) << 2)
  52 #define I2C_FIFO_STATUS                         0x060
  53 #define I2C_FIFO_STATUS_TX                      GENMASK(7, 4)
  54 #define I2C_FIFO_STATUS_RX                      GENMASK(3, 0)
  55 #define I2C_INT_MASK                            0x064
  56 #define I2C_INT_STATUS                          0x068
  57 #define I2C_INT_BUS_CLR_DONE                    BIT(11)
  58 #define I2C_INT_PACKET_XFER_COMPLETE            BIT(7)
  59 #define I2C_INT_NO_ACK                          BIT(3)
  60 #define I2C_INT_ARBITRATION_LOST                BIT(2)
  61 #define I2C_INT_TX_FIFO_DATA_REQ                BIT(1)
  62 #define I2C_INT_RX_FIFO_DATA_REQ                BIT(0)
  63 #define I2C_CLK_DIVISOR                         0x06c
  64 #define I2C_CLK_DIVISOR_STD_FAST_MODE           GENMASK(31, 16)
  65 #define I2C_CLK_DIVISOR_HSMODE                  GENMASK(15, 0)
  66
  67 #define DVC_CTRL_REG1                           0x000
  68 #define DVC_CTRL_REG1_INTR_EN                   BIT(10)
  69 #define DVC_CTRL_REG3                           0x008
  70 #define DVC_CTRL_REG3_SW_PROG                   BIT(26)
  71 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          BIT(30)
  72 #define DVC_STATUS                              0x00c
  73 #define DVC_STATUS_I2C_DONE_INTR                BIT(30)
  74
  75 #define I2C_ERR_NONE                            0x00
  76 #define I2C_ERR_NO_ACK                          BIT(0)
  77 #define I2C_ERR_ARBITRATION_LOST                BIT(1)
  78 #define I2C_ERR_UNKNOWN_INTERRUPT               BIT(2)
  79 #define I2C_ERR_RX_BUFFER_OVERFLOW              BIT(3)
  80
  81 #define PACKET_HEADER0_HEADER_SIZE              GENMASK(29, 28)
  82 #define PACKET_HEADER0_PACKET_ID                GENMASK(23, 16)
  83 #define PACKET_HEADER0_CONT_ID                  GENMASK(15, 12)
  84 #define PACKET_HEADER0_PROTOCOL                 GENMASK(7, 4)
  85 #define PACKET_HEADER0_PROTOCOL_I2C             1
  86
  87 #define I2C_HEADER_CONT_ON_NAK                  BIT(21)
  88 #define I2C_HEADER_READ                         BIT(19)
  89 #define I2C_HEADER_10BIT_ADDR                   BIT(18)
  90 #define I2C_HEADER_IE_ENABLE                    BIT(17)
  91 #define I2C_HEADER_REPEAT_START                 BIT(16)
  92 #define I2C_HEADER_CONTINUE_XFER                BIT(15)
  93 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
  94
  95 #define I2C_BUS_CLEAR_CNFG                      0x084
  96 #define I2C_BC_SCLK_THRESHOLD                   GENMASK(23, 16)
  97 #define I2C_BC_STOP_COND                        BIT(2)
  98 #define I2C_BC_TERMINATE                        BIT(1)
  99 #define I2C_BC_ENABLE                           BIT(0)
 100 #define I2C_BUS_CLEAR_STATUS                    0x088
 101 #define I2C_BC_STATUS                           BIT(0)
 102
 103 #define I2C_CONFIG_LOAD                         0x08c
 104 #define I2C_MSTR_CONFIG_LOAD                    BIT(0)
 105
 106 #define I2C_CLKEN_OVERRIDE                      0x090
 107 #define I2C_MST_CORE_CLKEN_OVR                  BIT(0)
 108
 109 #define I2C_INTERFACE_TIMING_0                  0x094
 110 #define  I2C_INTERFACE_TIMING_THIGH             GENMASK(13, 8)
 111 #define  I2C_INTERFACE_TIMING_TLOW              GENMASK(5, 0)
 112 #define I2C_INTERFACE_TIMING_1                  0x098
 113 #define  I2C_INTERFACE_TIMING_TBUF              GENMASK(29, 24)
 114 #define  I2C_INTERFACE_TIMING_TSU_STO           GENMASK(21, 16)
 115 #define  I2C_INTERFACE_TIMING_THD_STA           GENMASK(13, 8)
 116 #define  I2C_INTERFACE_TIMING_TSU_STA           GENMASK(5, 0)
 117
 118 #define I2C_HS_INTERFACE_TIMING_0               0x09c
 119 #define  I2C_HS_INTERFACE_TIMING_THIGH          GENMASK(13, 8)
 120 #define  I2C_HS_INTERFACE_TIMING_TLOW           GENMASK(5, 0)
 121 #define I2C_HS_INTERFACE_TIMING_1               0x0a0
 122 #define  I2C_HS_INTERFACE_TIMING_TSU_STO        GENMASK(21, 16)
 123 #define  I2C_HS_INTERFACE_TIMING_THD_STA        GENMASK(13, 8)
 124 #define  I2C_HS_INTERFACE_TIMING_TSU_STA        GENMASK(5, 0)
 125
 126 #define I2C_MST_FIFO_CONTROL                    0x0b4
 127 #define I2C_MST_FIFO_CONTROL_RX_FLUSH           BIT(0)
 128 #define I2C_MST_FIFO_CONTROL_TX_FLUSH           BIT(1)
 129 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x)         (((x) - 1) <<  4)
 130 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x)         (((x) - 1) << 16)
 131
 132 #define I2C_MST_FIFO_STATUS                     0x0b8
 133 #define I2C_MST_FIFO_STATUS_TX                  GENMASK(23, 16)
 134 #define I2C_MST_FIFO_STATUS_RX                  GENMASK(7, 0)
 135
 136 /* configuration load timeout in microseconds */
 137 #define I2C_CONFIG_LOAD_TIMEOUT                 1000000
 138
 139 /* Packet header size in bytes */
 140 #define I2C_PACKET_HEADER_SIZE                  12
 141
 142 /*
 143  * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
 144  * avoid DMA overhead, otherwise external APB DMA controller will be used.
 145  * Note that the actual MAX PIO length is 20 bytes because 32 bytes include
 146  * I2C_PACKET_HEADER_SIZE.
 147  */
 148 #define I2C_PIO_MODE_PREFERRED_LEN              32
 149
 150 /*
 151  * msg_end_type: The bus control which need to be send at end of transfer.
 152  * @MSG_END_STOP: Send stop pulse at end of transfer.
 153  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 154  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 155  *              stop or repeat start.
 156  */
 157 enum msg_end_type {
 158         MSG_END_STOP,
 159         MSG_END_REPEAT_START,
 160         MSG_END_CONTINUE,
 161 };
 162
 163 /**
 164  * struct tegra_i2c_hw_feature : Different HW support on Tegra
 165  * @has_continue_xfer_support: Continue transfer supports.
 166  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 167  *              complete interrupt per packet basis.
 168  * @has_config_load_reg: Has the config load register to load the new
 169  *              configuration.
 170  * @clk_divisor_hs_mode: Clock divisor in HS mode.
 171  * @clk_divisor_std_mode: Clock divisor in standard mode. It is
 172  *              applicable if there is no fast clock source i.e. single clock
 173  *              source.
 174  * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
 175  *              applicable if there is no fast clock source i.e. single clock
 176  *              source.
 177  * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
 178  *              applicable if there is no fast clock source (i.e. single
 179  *              clock source).
 180  * @has_multi_master_mode: The I2C controller supports running in single-master
 181  *              or multi-master mode.
 182  * @has_slcg_override_reg: The I2C controller supports a register that
 183  *              overrides the second level clock gating.
 184  * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
 185  *              provides additional features and allows for longer messages to
 186  *              be transferred in one go.
 187  * @quirks: i2c adapter quirks for limiting write/read transfer size and not
 188  *              allowing 0 length transfers.
 189  * @supports_bus_clear: Bus Clear support to recover from bus hang during
 190  *              SDA stuck low from device for some unknown reasons.
 191  * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
 192  * @tlow_std_mode: Low period of the clock in standard mode.
 193  * @thigh_std_mode: High period of the clock in standard mode.
 194  * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
 195  * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
 196  * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
 197  *              in standard mode.
 198  * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
 199  *              conditions in fast/fast-plus modes.
 200  * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
 201  *              in HS mode.
 202  * @has_interface_timing_reg: Has interface timing register to program the tuned
 203  *              timing settings.
 204  */
 205 struct tegra_i2c_hw_feature {
 206         bool has_continue_xfer_support;
 207         bool has_per_pkt_xfer_complete_irq;
 208         bool has_config_load_reg;
 209         u32 clk_divisor_hs_mode;
 210         u32 clk_divisor_std_mode;
 211         u32 clk_divisor_fast_mode;
 212         u32 clk_divisor_fast_plus_mode;
 213         bool has_multi_master_mode;
 214         bool has_slcg_override_reg;
 215         bool has_mst_fifo;
 216         const struct i2c_adapter_quirks *quirks;
 217         bool supports_bus_clear;
 218         bool has_apb_dma;
 219         u32 tlow_std_mode;
 220         u32 thigh_std_mode;
 221         u32 tlow_fast_fastplus_mode;
 222         u32 thigh_fast_fastplus_mode;
 223         u32 setup_hold_time_std_mode;
 224         u32 setup_hold_time_fast_fast_plus_mode;
 225         u32 setup_hold_time_hs_mode;
 226         bool has_interface_timing_reg;
 227 };
 228
 229 /**
 230  * struct tegra_i2c_dev - per device I2C context
 231  * @dev: device reference for power management
 232  * @hw: Tegra I2C HW feature
 233  * @adapter: core I2C layer adapter information
 234  * @div_clk: clock reference for div clock of I2C controller
 235  * @clocks: array of I2C controller clocks
 236  * @nclocks: number of clocks in the array
 237  * @rst: reset control for the I2C controller
 238  * @base: ioremapped registers cookie
 239  * @base_phys: physical base address of the I2C controller
 240  * @cont_id: I2C controller ID, used for packet header
 241  * @irq: IRQ number of transfer complete interrupt
 242  * @is_dvc: identifies the DVC I2C controller, has a different register layout
 243  * @is_vi: identifies the VI I2C controller, has a different register layout
 244  * @msg_complete: transfer completion notifier
 245  * @msg_err: error code for completed message
 246  * @msg_buf: pointer to current message data
 247  * @msg_buf_remaining: size of unsent data in the message buffer
 248  * @msg_read: identifies read transfers
 249  * @bus_clk_rate: current I2C bus clock rate
 250  * @is_multimaster_mode: track if I2C controller is in multi-master mode
 251  * @tx_dma_chan: DMA transmit channel
 252  * @rx_dma_chan: DMA receive channel
 253  * @dma_phys: handle to DMA resources
 254  * @dma_buf: pointer to allocated DMA buffer
 255  * @dma_buf_size: DMA buffer size
 256  * @is_curr_dma_xfer: indicates active DMA transfer
 257  * @dma_complete: DMA completion notifier
 258  * @is_curr_atomic_xfer: indicates active atomic transfer
 259  */
 260 struct tegra_i2c_dev {
 261         struct device *dev;
 262         const struct tegra_i2c_hw_feature *hw;
 263         struct i2c_adapter adapter;
 264         struct clk *div_clk;
 265         struct clk_bulk_data clocks[2];
 266         unsigned int nclocks;
 267         struct reset_control *rst;
 268         void __iomem *base;
 269         phys_addr_t base_phys;
 270         unsigned int cont_id;
 271         unsigned int irq;
 272         bool is_dvc;
 273         bool is_vi;
 274         struct completion msg_complete;
 275         int msg_err;
 276         u8 *msg_buf;
 277         size_t msg_buf_remaining;
 278         bool msg_read;
 279         u32 bus_clk_rate;
 280         bool is_multimaster_mode;
 281         struct dma_chan *tx_dma_chan;
 282         struct dma_chan *rx_dma_chan;
 283         dma_addr_t dma_phys;
 284         u32 *dma_buf;
 285         unsigned int dma_buf_size;
 286         bool is_curr_dma_xfer;
 287         struct completion dma_complete;
 288         bool is_curr_atomic_xfer;
 289 };
 290
 291 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 292                        unsigned long reg)
 293 {
 294         writel_relaxed(val, i2c_dev->base + reg);
 295 }
 296
 297 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 298 {
 299         return readl_relaxed(i2c_dev->base + reg);
 300 }
 301
 302 /*
 303  * i2c_writel and i2c_readl will offset the register if necessary to talk
 304  * to the I2C block inside the DVC block
 305  */
 306 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 307                                         unsigned long reg)
 308 {
 309         if (i2c_dev->is_dvc)
 310                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 311         else if (i2c_dev->is_vi)
 312                 reg = 0xc00 + (reg << 2);
 313         return reg;
 314 }
 315
 316 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 317                        unsigned long reg)
 318 {
 319         writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 320
 321         /* Read back register to make sure that register writes completed */
 322         if (reg != I2C_TX_FIFO)
 323                 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 324 }
 325
 326 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 327 {
 328         return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 329 }
 330
 331 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 332                         unsigned long reg, unsigned int len)
 333 {
 334         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 335 }
 336
 337 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 338                        unsigned long reg, unsigned int len)
 339 {
 340         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 341 }
 342
 343 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 344 {
 345         u32 int_mask;
 346
 347         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
 348         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 349 }
 350
 351 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 352 {
 353         u32 int_mask;
 354
 355         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
 356         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 357 }
 358
 359 static void tegra_i2c_dma_complete(void *args)
 360 {
 361         struct tegra_i2c_dev *i2c_dev = args;
 362
 363         complete(&i2c_dev->dma_complete);
 364 }
 365
 366 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
 367 {
 368         struct dma_async_tx_descriptor *dma_desc;
 369         enum dma_transfer_direction dir;
 370         struct dma_chan *chan;
 371
 372         dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
 373         reinit_completion(&i2c_dev->dma_complete);
 374         dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
 375         chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan;
 376         dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys,
 377                                                len, dir, DMA_PREP_INTERRUPT |
 378                                                DMA_CTRL_ACK);
 379         if (!dma_desc) {
 380                 dev_err(i2c_dev->dev, "failed to get DMA descriptor\n");
 381                 return -EINVAL;
 382         }
 383
 384         dma_desc->callback = tegra_i2c_dma_complete;
 385         dma_desc->callback_param = i2c_dev;
 386         dmaengine_submit(dma_desc);
 387         dma_async_issue_pending(chan);
 388         return 0;
 389 }
 390
 391 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
 392 {
 393         if (i2c_dev->dma_buf) {
 394                 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
 395                                   i2c_dev->dma_buf, i2c_dev->dma_phys);
 396                 i2c_dev->dma_buf = NULL;
 397         }
 398
 399         if (i2c_dev->tx_dma_chan) {
 400                 dma_release_channel(i2c_dev->tx_dma_chan);
 401                 i2c_dev->tx_dma_chan = NULL;
 402         }
 403
 404         if (i2c_dev->rx_dma_chan) {
 405                 dma_release_channel(i2c_dev->rx_dma_chan);
 406                 i2c_dev->rx_dma_chan = NULL;
 407         }
 408 }
 409
 410 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
 411 {
 412         struct dma_chan *chan;
 413         u32 *dma_buf;
 414         dma_addr_t dma_phys;
 415         int err;
 416
 417         if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi)
 418                 return 0;
 419
 420         if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
 421                 dev_dbg(i2c_dev->dev, "Support for APB DMA not enabled!\n");
 422                 return 0;
 423         }
 424
 425         chan = dma_request_chan(i2c_dev->dev, "rx");
 426         if (IS_ERR(chan)) {
 427                 err = PTR_ERR(chan);
 428                 goto err_out;
 429         }
 430
 431         i2c_dev->rx_dma_chan = chan;
 432
 433         chan = dma_request_chan(i2c_dev->dev, "tx");
 434         if (IS_ERR(chan)) {
 435                 err = PTR_ERR(chan);
 436                 goto err_out;
 437         }
 438
 439         i2c_dev->tx_dma_chan = chan;
 440
 441         i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len +
 442                                 I2C_PACKET_HEADER_SIZE;
 443
 444         dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
 445                                      &dma_phys, GFP_KERNEL | __GFP_NOWARN);
 446         if (!dma_buf) {
 447                 dev_err(i2c_dev->dev, "failed to allocate the DMA buffer\n");
 448                 err = -ENOMEM;
 449                 goto err_out;
 450         }
 451
 452         i2c_dev->dma_buf = dma_buf;
 453         i2c_dev->dma_phys = dma_phys;
 454         return 0;
 455
 456 err_out:
 457         tegra_i2c_release_dma(i2c_dev);
 458         if (err != -EPROBE_DEFER) {
 459                 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
 460                 dev_err(i2c_dev->dev, "falling back to PIO\n");
 461                 return 0;
 462         }
 463
 464         return err;
 465 }
 466
 467 /*
 468  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 469  * block.  This block is identical to the rest of the I2C blocks, except that
 470  * it only supports master mode, it has registers moved around, and it needs
 471  * some extra init to get it into I2C mode.  The register moves are handled
 472  * by i2c_readl and i2c_writel
 473  */
 474 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 475 {
 476         u32 val;
 477
 478         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 479         val |= DVC_CTRL_REG3_SW_PROG;
 480         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 481         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 482
 483         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 484         val |= DVC_CTRL_REG1_INTR_EN;
 485         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 486 }
 487
 488 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
 489 {
 490         u32 value;
 491
 492         value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) |
 493                 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4);
 494         i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0);
 495
 496         value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) |
 497                 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) |
 498                 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) |
 499                 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4);
 500         i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1);
 501
 502         value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) |
 503                 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8);
 504         i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0);
 505
 506         value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) |
 507                 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) |
 508                 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11);
 509         i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1);
 510
 511         value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND;
 512         i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG);
 513
 514         i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
 515 }
 516
 517 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 518 {
 519         u32 mask, val, offset, reg_offset;
 520         void __iomem *addr;
 521         int err;
 522
 523         if (i2c_dev->hw->has_mst_fifo) {
 524                 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
 525                        I2C_MST_FIFO_CONTROL_RX_FLUSH;
 526                 offset = I2C_MST_FIFO_CONTROL;
 527         } else {
 528                 mask = I2C_FIFO_CONTROL_TX_FLUSH |
 529                        I2C_FIFO_CONTROL_RX_FLUSH;
 530                 offset = I2C_FIFO_CONTROL;
 531         }
 532
 533         val = i2c_readl(i2c_dev, offset);
 534         val |= mask;
 535         i2c_writel(i2c_dev, val, offset);
 536
 537         reg_offset = tegra_i2c_reg_addr(i2c_dev, offset);
 538         addr = i2c_dev->base + reg_offset;
 539
 540         if (i2c_dev->is_curr_atomic_xfer)
 541                 err = readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask),
 542                                                         1000, 1000000);
 543         else
 544                 err = readl_relaxed_poll_timeout(addr, val, !(val & mask),
 545                                                  1000, 1000000);
 546
 547         if (err) {
 548                 dev_err(i2c_dev->dev, "failed to flush FIFO\n");
 549                 return err;
 550         }
 551         return 0;
 552 }
 553
 554 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
 555 {
 556         unsigned long reg_offset;
 557         void __iomem *addr;
 558         u32 val;
 559         int err;
 560
 561         if (i2c_dev->hw->has_config_load_reg) {
 562                 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
 563                 addr = i2c_dev->base + reg_offset;
 564                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 565
 566                 if (i2c_dev->is_curr_atomic_xfer)
 567                         err = readl_relaxed_poll_timeout_atomic(
 568                                                 addr, val, val == 0, 1000,
 569                                                 I2C_CONFIG_LOAD_TIMEOUT);
 570                 else
 571                         err = readl_relaxed_poll_timeout(
 572                                                 addr, val, val == 0, 1000,
 573                                                 I2C_CONFIG_LOAD_TIMEOUT);
 574
 575                 if (err) {
 576                         dev_warn(i2c_dev->dev,
 577                                  "timeout waiting for config load\n");
 578                         return err;
 579                 }
 580         }
 581
 582         return 0;
 583 }
 584
 585 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 586 {
 587         u32 val;
 588         int err;
 589         u32 clk_divisor, clk_multiplier;
 590         u32 non_hs_mode;
 591         u32 tsu_thd;
 592         u8 tlow, thigh;
 593
 594         /*
 595          * The reset shouldn't ever fail in practice. The failure will be a
 596          * sign of a severe problem that needs to be resolved. Still we don't
 597          * want to fail the initialization completely because this may break
 598          * kernel boot up since voltage regulators use I2C. Hence, we will
 599          * emit a noisy warning on error, which won't stay unnoticed and
 600          * won't hose machine entirely.
 601          */
 602         err = reset_control_reset(i2c_dev->rst);
 603         WARN_ON_ONCE(err);
 604
 605         if (i2c_dev->is_dvc)
 606                 tegra_dvc_init(i2c_dev);
 607
 608         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 609               FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2);
 610
 611         if (i2c_dev->hw->has_multi_master_mode)
 612                 val |= I2C_CNFG_MULTI_MASTER_MODE;
 613
 614         i2c_writel(i2c_dev, val, I2C_CNFG);
 615         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 616
 617         if (i2c_dev->is_vi)
 618                 tegra_i2c_vi_init(i2c_dev);
 619
 620         switch (i2c_dev->bus_clk_rate) {
 621         case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
 622         default:
 623                 tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
 624                 thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
 625                 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
 626
 627                 if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ)
 628                         non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
 629                 else
 630                         non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
 631                 break;
 632
 633         case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
 634                 tlow = i2c_dev->hw->tlow_std_mode;
 635                 thigh = i2c_dev->hw->thigh_std_mode;
 636                 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
 637                 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
 638                 break;
 639         }
 640
 641         /* Make sure clock divisor programmed correctly */
 642         clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
 643                                  i2c_dev->hw->clk_divisor_hs_mode) |
 644                       FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
 645         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 646
 647         if (i2c_dev->hw->has_interface_timing_reg) {
 648                 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
 649                       FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
 650                 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
 651         }
 652
 653         /*
 654          * configure setup and hold times only when tsu_thd is non-zero.
 655          * otherwise, preserve the chip default values
 656          */
 657         if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
 658                 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
 659
 660         clk_multiplier  = tlow + thigh + 2;
 661         clk_multiplier *= non_hs_mode + 1;
 662
 663         err = clk_set_rate(i2c_dev->div_clk,
 664                            i2c_dev->bus_clk_rate * clk_multiplier);
 665         if (err) {
 666                 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
 667                 return err;
 668         }
 669
 670         if (!i2c_dev->is_dvc && !i2c_dev->is_vi) {
 671                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 672
 673                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 674                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 675                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 676                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 677         }
 678
 679         err = tegra_i2c_flush_fifos(i2c_dev);
 680         if (err)
 681                 return err;
 682
 683         if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
 684                 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
 685
 686         err = tegra_i2c_wait_for_config_load(i2c_dev);
 687         if (err)
 688                 return err;
 689
 690         return 0;
 691 }
 692
 693 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
 694 {
 695         u32 cnfg;
 696
 697         /*
 698          * NACK interrupt is generated before the I2C controller generates
 699          * the STOP condition on the bus. So wait for 2 clock periods
 700          * before disabling the controller so that the STOP condition has
 701          * been delivered properly.
 702          */
 703         udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 704
 705         cnfg = i2c_readl(i2c_dev, I2C_CNFG);
 706         if (cnfg & I2C_CNFG_PACKET_MODE_EN)
 707                 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
 708
 709         return tegra_i2c_wait_for_config_load(i2c_dev);
 710 }
 711
 712 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 713 {
 714         u32 val;
 715         unsigned int rx_fifo_avail;
 716         u8 *buf = i2c_dev->msg_buf;
 717         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 718         unsigned int words_to_transfer;
 719
 720         /*
 721          * Catch overflow due to message fully sent
 722          * before the check for RX FIFO availability.
 723          */
 724         if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
 725                 return -EINVAL;
 726
 727         if (i2c_dev->hw->has_mst_fifo) {
 728                 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 729                 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val);
 730         } else {
 731                 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 732                 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val);
 733         }
 734
 735         /* Rounds down to not include partial word at the end of buf */
 736         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 737         if (words_to_transfer > rx_fifo_avail)
 738                 words_to_transfer = rx_fifo_avail;
 739
 740         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 741
 742         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 743         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 744         rx_fifo_avail -= words_to_transfer;
 745
 746         /*
 747          * If there is a partial word at the end of buf, handle it manually to
 748          * prevent overwriting past the end of buf
 749          */
 750         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 751                 /*
 752                  * buf_remaining > 3 check not needed as rx_fifo_avail == 0
 753                  * when (words_to_transfer was > rx_fifo_avail) earlier
 754                  * in this function.
 755                  */
 756                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 757                 val = cpu_to_le32(val);
 758                 memcpy(buf, &val, buf_remaining);
 759                 buf_remaining = 0;
 760                 rx_fifo_avail--;
 761         }
 762
 763         /* RX FIFO must be drained, otherwise it's an Overflow case. */
 764         if (WARN_ON_ONCE(rx_fifo_avail))
 765                 return -EINVAL;
 766
 767         i2c_dev->msg_buf_remaining = buf_remaining;
 768         i2c_dev->msg_buf = buf;
 769
 770         return 0;
 771 }
 772
 773 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 774 {
 775         u32 val;
 776         unsigned int tx_fifo_avail;
 777         u8 *buf = i2c_dev->msg_buf;
 778         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 779         unsigned int words_to_transfer;
 780
 781         if (i2c_dev->hw->has_mst_fifo) {
 782                 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 783                 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val);
 784         } else {
 785                 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 786                 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val);
 787         }
 788
 789         /* Rounds down to not include partial word at the end of buf */
 790         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 791
 792         /* It's very common to have < 4 bytes, so optimize that case. */
 793         if (words_to_transfer) {
 794                 if (words_to_transfer > tx_fifo_avail)
 795                         words_to_transfer = tx_fifo_avail;
 796
 797                 /*
 798                  * Update state before writing to FIFO.  Note that this may
 799                  * cause us to finish writing all bytes (AKA buf_remaining
 800                  * goes to 0), hence we have a potential for an interrupt
 801                  * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt
 802                  * is disabled at this point.
 803                  */
 804                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 805                 tx_fifo_avail -= words_to_transfer;
 806                 i2c_dev->msg_buf_remaining = buf_remaining;
 807                 i2c_dev->msg_buf = buf +
 808                         words_to_transfer * BYTES_PER_FIFO_WORD;
 809
 810                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 811
 812                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 813         }
 814
 815         /*
 816          * If there is a partial word at the end of buf, handle it manually to
 817          * prevent reading past the end of buf, which could cross a page
 818          * boundary and fault.
 819          */
 820         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 821                 /*
 822                  * buf_remaining > 3 check not needed as tx_fifo_avail == 0
 823                  * when (words_to_transfer was > tx_fifo_avail) earlier
 824                  * in this function for non-zero words_to_transfer.
 825                  */
 826                 memcpy(&val, buf, buf_remaining);
 827                 val = le32_to_cpu(val);
 828
 829                 i2c_dev->msg_buf_remaining = 0;
 830                 i2c_dev->msg_buf = NULL;
 831
 832                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 833         }
 834
 835         return 0;
 836 }
 837
 838 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 839 {
 840         u32 status;
 841         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 842         struct tegra_i2c_dev *i2c_dev = dev_id;
 843
 844         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 845
 846         if (status == 0) {
 847                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 848                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 849                          i2c_readl(i2c_dev, I2C_STATUS),
 850                          i2c_readl(i2c_dev, I2C_CNFG));
 851                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 852                 goto err;
 853         }
 854
 855         if (status & status_err) {
 856                 tegra_i2c_disable_packet_mode(i2c_dev);
 857                 if (status & I2C_INT_NO_ACK)
 858                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 859                 if (status & I2C_INT_ARBITRATION_LOST)
 860                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 861                 goto err;
 862         }
 863
 864         /*
 865          * I2C transfer is terminated during the bus clear so skip
 866          * processing the other interrupts.
 867          */
 868         if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
 869                 goto err;
 870
 871         if (!i2c_dev->is_curr_dma_xfer) {
 872                 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 873                         if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
 874                                 /*
 875                                  * Overflow error condition: message fully sent,
 876                                  * with no XFER_COMPLETE interrupt but hardware
 877                                  * asks to transfer more.
 878                                  */
 879                                 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
 880                                 goto err;
 881                         }
 882                 }
 883
 884                 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 885                         if (i2c_dev->msg_buf_remaining)
 886                                 tegra_i2c_fill_tx_fifo(i2c_dev);
 887                         else
 888                                 tegra_i2c_mask_irq(i2c_dev,
 889                                                    I2C_INT_TX_FIFO_DATA_REQ);
 890                 }
 891         }
 892
 893         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 894         if (i2c_dev->is_dvc)
 895                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 896
 897         /*
 898          * During message read XFER_COMPLETE interrupt is triggered prior to
 899          * DMA completion and during message write XFER_COMPLETE interrupt is
 900          * triggered after DMA completion.
 901          * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer.
 902          * so forcing msg_buf_remaining to 0 in DMA mode.
 903          */
 904         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 905                 if (i2c_dev->is_curr_dma_xfer)
 906                         i2c_dev->msg_buf_remaining = 0;
 907                 /*
 908                  * Underflow error condition: XFER_COMPLETE before message
 909                  * fully sent.
 910                  */
 911                 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
 912                         i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 913                         goto err;
 914                 }
 915                 complete(&i2c_dev->msg_complete);
 916         }
 917         goto done;
 918 err:
 919         /* An error occurred, mask all interrupts */
 920         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 921                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 922                 I2C_INT_RX_FIFO_DATA_REQ);
 923         if (i2c_dev->hw->supports_bus_clear)
 924                 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
 925         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 926         if (i2c_dev->is_dvc)
 927                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 928
 929         if (i2c_dev->is_curr_dma_xfer) {
 930                 if (i2c_dev->msg_read)
 931                         dmaengine_terminate_async(i2c_dev->rx_dma_chan);
 932                 else
 933                         dmaengine_terminate_async(i2c_dev->tx_dma_chan);
 934
 935                 complete(&i2c_dev->dma_complete);
 936         }
 937
 938         complete(&i2c_dev->msg_complete);
 939 done:
 940         return IRQ_HANDLED;
 941 }
 942
 943 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
 944                                        size_t len)
 945 {
 946         u32 val, reg;
 947         u8 dma_burst;
 948         struct dma_slave_config slv_config = {0};
 949         struct dma_chan *chan;
 950         int ret;
 951         unsigned long reg_offset;
 952
 953         if (i2c_dev->hw->has_mst_fifo)
 954                 reg = I2C_MST_FIFO_CONTROL;
 955         else
 956                 reg = I2C_FIFO_CONTROL;
 957
 958         if (i2c_dev->is_curr_dma_xfer) {
 959                 if (len & 0xF)
 960                         dma_burst = 1;
 961                 else if (len & 0x10)
 962                         dma_burst = 4;
 963                 else
 964                         dma_burst = 8;
 965
 966                 if (i2c_dev->msg_read) {
 967                         chan = i2c_dev->rx_dma_chan;
 968                         reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
 969                         slv_config.src_addr = i2c_dev->base_phys + reg_offset;
 970                         slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 971                         slv_config.src_maxburst = dma_burst;
 972
 973                         if (i2c_dev->hw->has_mst_fifo)
 974                                 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
 975                         else
 976                                 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
 977                 } else {
 978                         chan = i2c_dev->tx_dma_chan;
 979                         reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
 980                         slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
 981                         slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 982                         slv_config.dst_maxburst = dma_burst;
 983
 984                         if (i2c_dev->hw->has_mst_fifo)
 985                                 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
 986                         else
 987                                 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
 988                 }
 989
 990                 slv_config.device_fc = true;
 991                 ret = dmaengine_slave_config(chan, &slv_config);
 992                 if (ret < 0) {
 993                         dev_err(i2c_dev->dev, "DMA slave config failed: %d\n",
 994                                 ret);
 995                         dev_err(i2c_dev->dev, "falling back to PIO\n");
 996                         tegra_i2c_release_dma(i2c_dev);
 997                         i2c_dev->is_curr_dma_xfer = false;
 998                 } else {
 999                         goto out;
1000                 }
1001         }
1002
1003         if (i2c_dev->hw->has_mst_fifo)
1004                 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
1005                       I2C_MST_FIFO_CONTROL_RX_TRIG(1);
1006         else
1007                 val = I2C_FIFO_CONTROL_TX_TRIG(8) |
1008                       I2C_FIFO_CONTROL_RX_TRIG(1);
1009 out:
1010         i2c_writel(i2c_dev, val, reg);
1011 }
1012
1013 static unsigned long
1014 tegra_i2c_poll_completion_timeout(struct tegra_i2c_dev *i2c_dev,
1015                                   struct completion *complete,
1016                                   unsigned int timeout_ms)
1017 {
1018         ktime_t ktime = ktime_get();
1019         ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms);
1020
1021         do {
1022                 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
1023
1024                 if (status)
1025                         tegra_i2c_isr(i2c_dev->irq, i2c_dev);
1026
1027                 if (completion_done(complete)) {
1028                         s64 delta = ktime_ms_delta(ktimeout, ktime);
1029
1030                         return msecs_to_jiffies(delta) ?: 1;
1031                 }
1032
1033                 ktime = ktime_get();
1034
1035         } while (ktime_before(ktime, ktimeout));
1036
1037         return 0;
1038 }
1039
1040 static unsigned long
1041 tegra_i2c_wait_completion_timeout(struct tegra_i2c_dev *i2c_dev,
1042                                   struct completion *complete,
1043                                   unsigned int timeout_ms)
1044 {
1045         unsigned long ret;
1046
1047         if (i2c_dev->is_curr_atomic_xfer) {
1048                 ret = tegra_i2c_poll_completion_timeout(i2c_dev, complete,
1049                                                         timeout_ms);
1050         } else {
1051                 enable_irq(i2c_dev->irq);
1052                 ret = wait_for_completion_timeout(complete,
1053                                                   msecs_to_jiffies(timeout_ms));
1054                 disable_irq(i2c_dev->irq);
1055
1056                 /*
1057                  * Under some rare circumstances (like running KASAN +
1058                  * NFS root) CPU, which handles interrupt, may stuck in
1059                  * uninterruptible state for a significant time.  In this
1060                  * case we will get timeout if I2C transfer is running on
1061                  * a sibling CPU, despite of IRQ being raised.
1062                  *
1063                  * In order to handle this rare condition, the IRQ status
1064                  * needs to be checked after timeout.
1065                  */
1066                 if (ret == 0)
1067                         ret = tegra_i2c_poll_completion_timeout(i2c_dev,
1068                                                                 complete, 0);
1069         }
1070
1071         return ret;
1072 }
1073
1074 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
1075 {
1076         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1077         int err;
1078         unsigned long time_left;
1079         u32 reg;
1080
1081         reinit_completion(&i2c_dev->msg_complete);
1082         reg = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND |
1083               I2C_BC_TERMINATE;
1084         i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1085
1086         err = tegra_i2c_wait_for_config_load(i2c_dev);
1087         if (err)
1088                 return err;
1089
1090         reg |= I2C_BC_ENABLE;
1091         i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1092         tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1093
1094         time_left = tegra_i2c_wait_completion_timeout(
1095                         i2c_dev, &i2c_dev->msg_complete, 50);
1096         tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1097
1098         if (time_left == 0) {
1099                 dev_err(i2c_dev->dev, "timed out for bus clear\n");
1100                 return -ETIMEDOUT;
1101         }
1102
1103         reg = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1104         if (!(reg & I2C_BC_STATUS)) {
1105                 dev_err(i2c_dev->dev,
1106                         "un-recovered arbitration lost\n");
1107                 return -EIO;
1108         }
1109
1110         return -EAGAIN;
1111 }
1112
1113 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1114                               struct i2c_msg *msg,
1115                               enum msg_end_type end_state)
1116 {
1117         u32 packet_header;
1118         u32 int_mask;
1119         unsigned long time_left;
1120         size_t xfer_size;
1121         u32 *buffer = NULL;
1122         int err = 0;
1123         bool dma;
1124         u16 xfer_time = 100;
1125
1126         err = tegra_i2c_flush_fifos(i2c_dev);
1127         if (err)
1128                 return err;
1129
1130         i2c_dev->msg_buf = msg->buf;
1131         i2c_dev->msg_buf_remaining = msg->len;
1132         i2c_dev->msg_err = I2C_ERR_NONE;
1133         i2c_dev->msg_read = !!(msg->flags & I2C_M_RD);
1134         reinit_completion(&i2c_dev->msg_complete);
1135
1136         if (i2c_dev->msg_read)
1137                 xfer_size = msg->len;
1138         else
1139                 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE;
1140
1141         xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1142         i2c_dev->is_curr_dma_xfer = (xfer_size > I2C_PIO_MODE_PREFERRED_LEN) &&
1143                                     i2c_dev->dma_buf &&
1144                                     !i2c_dev->is_curr_atomic_xfer;
1145         tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1146         dma = i2c_dev->is_curr_dma_xfer;
1147         /*
1148          * Transfer time in mSec = Total bits / transfer rate
1149          * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1150          */
1151         xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1152                                         i2c_dev->bus_clk_rate);
1153
1154         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1155         tegra_i2c_unmask_irq(i2c_dev, int_mask);
1156         if (dma) {
1157                 if (i2c_dev->msg_read) {
1158                         dma_sync_single_for_device(i2c_dev->dev,
1159                                                    i2c_dev->dma_phys,
1160                                                    xfer_size,
1161                                                    DMA_FROM_DEVICE);
1162                         err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1163                         if (err < 0) {
1164                                 dev_err(i2c_dev->dev,
1165                                         "starting RX DMA failed, err %d\n",
1166                                         err);
1167                                 return err;
1168                         }
1169
1170                 } else {
1171                         dma_sync_single_for_cpu(i2c_dev->dev,
1172                                                 i2c_dev->dma_phys,
1173                                                 xfer_size,
1174                                                 DMA_TO_DEVICE);
1175                         buffer = i2c_dev->dma_buf;
1176                 }
1177         }
1178
1179         packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) |
1180                         FIELD_PREP(PACKET_HEADER0_PROTOCOL,
1181                                    PACKET_HEADER0_PROTOCOL_I2C) |
1182                         FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) |
1183                         FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1);
1184         if (dma && !i2c_dev->msg_read)
1185                 *buffer++ = packet_header;
1186         else
1187                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1188
1189         packet_header = msg->len - 1;
1190         if (dma && !i2c_dev->msg_read)
1191                 *buffer++ = packet_header;
1192         else
1193                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1194
1195         packet_header = I2C_HEADER_IE_ENABLE;
1196         if (end_state == MSG_END_CONTINUE)
1197                 packet_header |= I2C_HEADER_CONTINUE_XFER;
1198         else if (end_state == MSG_END_REPEAT_START)
1199                 packet_header |= I2C_HEADER_REPEAT_START;
1200         if (msg->flags & I2C_M_TEN) {
1201                 packet_header |= msg->addr;
1202                 packet_header |= I2C_HEADER_10BIT_ADDR;
1203         } else {
1204                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1205         }
1206         if (msg->flags & I2C_M_IGNORE_NAK)
1207                 packet_header |= I2C_HEADER_CONT_ON_NAK;
1208         if (msg->flags & I2C_M_RD)
1209                 packet_header |= I2C_HEADER_READ;
1210         if (dma && !i2c_dev->msg_read)
1211                 *buffer++ = packet_header;
1212         else
1213                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1214
1215         if (!i2c_dev->msg_read) {
1216                 if (dma) {
1217                         memcpy(buffer, msg->buf, msg->len);
1218                         dma_sync_single_for_device(i2c_dev->dev,
1219                                                    i2c_dev->dma_phys,
1220                                                    xfer_size,
1221                                                    DMA_TO_DEVICE);
1222                         err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1223                         if (err < 0) {
1224                                 dev_err(i2c_dev->dev,
1225                                         "starting TX DMA failed, err %d\n",
1226                                         err);
1227                                 return err;
1228                         }
1229                 } else {
1230                         tegra_i2c_fill_tx_fifo(i2c_dev);
1231                 }
1232         }
1233
1234         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1235                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1236         if (!dma) {
1237                 if (msg->flags & I2C_M_RD)
1238                         int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1239                 else if (i2c_dev->msg_buf_remaining)
1240                         int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1241         }
1242
1243         tegra_i2c_unmask_irq(i2c_dev, int_mask);
1244         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
1245                 i2c_readl(i2c_dev, I2C_INT_MASK));
1246
1247         if (dma) {
1248                 time_left = tegra_i2c_wait_completion_timeout(
1249                                 i2c_dev, &i2c_dev->dma_complete, xfer_time);
1250
1251                 /*
1252                  * Synchronize DMA first, since dmaengine_terminate_sync()
1253                  * performs synchronization after the transfer's termination
1254                  * and we want to get a completion if transfer succeeded.
1255                  */
1256                 dmaengine_synchronize(i2c_dev->msg_read ?
1257                                       i2c_dev->rx_dma_chan :
1258                                       i2c_dev->tx_dma_chan);
1259
1260                 dmaengine_terminate_sync(i2c_dev->msg_read ?
1261                                          i2c_dev->rx_dma_chan :
1262                                          i2c_dev->tx_dma_chan);
1263
1264                 if (!time_left && !completion_done(&i2c_dev->dma_complete)) {
1265                         dev_err(i2c_dev->dev, "DMA transfer timeout\n");
1266                         tegra_i2c_init(i2c_dev);
1267                         return -ETIMEDOUT;
1268                 }
1269
1270                 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
1271                         dma_sync_single_for_cpu(i2c_dev->dev,
1272                                                 i2c_dev->dma_phys,
1273                                                 xfer_size,
1274                                                 DMA_FROM_DEVICE);
1275                         memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf,
1276                                msg->len);
1277                 }
1278         }
1279
1280         time_left = tegra_i2c_wait_completion_timeout(
1281                         i2c_dev, &i2c_dev->msg_complete, xfer_time);
1282
1283         tegra_i2c_mask_irq(i2c_dev, int_mask);
1284
1285         if (time_left == 0) {
1286                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
1287                 tegra_i2c_init(i2c_dev);
1288                 return -ETIMEDOUT;
1289         }
1290
1291         dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1292                 time_left, completion_done(&i2c_dev->msg_complete),
1293                 i2c_dev->msg_err);
1294
1295         i2c_dev->is_curr_dma_xfer = false;
1296         if (i2c_dev->msg_err == I2C_ERR_NONE)
1297                 return 0;
1298
1299         tegra_i2c_init(i2c_dev);
1300         /* start recovery upon arbitration loss in single master mode */
1301         if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1302                 if (!i2c_dev->is_multimaster_mode)
1303                         return i2c_recover_bus(&i2c_dev->adapter);
1304                 return -EAGAIN;
1305         }
1306
1307         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1308                 if (msg->flags & I2C_M_IGNORE_NAK)
1309                         return 0;
1310                 return -EREMOTEIO;
1311         }
1312
1313         return -EIO;
1314 }
1315
1316 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1317                           int num)
1318 {
1319         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1320         int i;
1321         int ret;
1322
1323         ret = pm_runtime_get_sync(i2c_dev->dev);
1324         if (ret < 0) {
1325                 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1326                 pm_runtime_put_noidle(i2c_dev->dev);
1327                 return ret;
1328         }
1329
1330         for (i = 0; i < num; i++) {
1331                 enum msg_end_type end_type = MSG_END_STOP;
1332
1333                 if (i < (num - 1)) {
1334                         if (msgs[i + 1].flags & I2C_M_NOSTART)
1335                                 end_type = MSG_END_CONTINUE;
1336                         else
1337                                 end_type = MSG_END_REPEAT_START;
1338                 }
1339                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1340                 if (ret)
1341                         break;
1342         }
1343
1344         pm_runtime_put(i2c_dev->dev);
1345
1346         return ret ?: i;
1347 }
1348
1349 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap,
1350                                  struct i2c_msg msgs[], int num)
1351 {
1352         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1353         int ret;
1354
1355         i2c_dev->is_curr_atomic_xfer = true;
1356         ret = tegra_i2c_xfer(adap, msgs, num);
1357         i2c_dev->is_curr_atomic_xfer = false;
1358
1359         return ret;
1360 }
1361
1362 static u32 tegra_i2c_func(struct i2c_adapter *adap)
1363 {
1364         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1365         u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
1366                   I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
1367
1368         if (i2c_dev->hw->has_continue_xfer_support)
1369                 ret |= I2C_FUNC_NOSTART;
1370         return ret;
1371 }
1372
1373 static const struct i2c_algorithm tegra_i2c_algo = {
1374         .master_xfer            = tegra_i2c_xfer,
1375         .master_xfer_atomic     = tegra_i2c_xfer_atomic,
1376         .functionality          = tegra_i2c_func,
1377 };
1378
1379 /* payload size is only 12 bit */
1380 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
1381         .flags = I2C_AQ_NO_ZERO_LEN,
1382         .max_read_len = SZ_4K,
1383         .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1384 };
1385
1386 static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
1387         .flags = I2C_AQ_NO_ZERO_LEN,
1388         .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1389 };
1390
1391 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1392         .recover_bus = tegra_i2c_issue_bus_clear,
1393 };
1394
1395 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
1396         .has_continue_xfer_support = false,
1397         .has_per_pkt_xfer_complete_irq = false,
1398         .clk_divisor_hs_mode = 3,
1399         .clk_divisor_std_mode = 0,
1400         .clk_divisor_fast_mode = 0,
1401         .clk_divisor_fast_plus_mode = 0,
1402         .has_config_load_reg = false,
1403         .has_multi_master_mode = false,
1404         .has_slcg_override_reg = false,
1405         .has_mst_fifo = false,
1406         .quirks = &tegra_i2c_quirks,
1407         .supports_bus_clear = false,
1408         .has_apb_dma = true,
1409         .tlow_std_mode = 0x4,
1410         .thigh_std_mode = 0x2,
1411         .tlow_fast_fastplus_mode = 0x4,
1412         .thigh_fast_fastplus_mode = 0x2,
1413         .setup_hold_time_std_mode = 0x0,
1414         .setup_hold_time_fast_fast_plus_mode = 0x0,
1415         .setup_hold_time_hs_mode = 0x0,
1416         .has_interface_timing_reg = false,
1417 };
1418
1419 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
1420         .has_continue_xfer_support = true,
1421         .has_per_pkt_xfer_complete_irq = false,
1422         .clk_divisor_hs_mode = 3,
1423         .clk_divisor_std_mode = 0,
1424         .clk_divisor_fast_mode = 0,
1425         .clk_divisor_fast_plus_mode = 0,
1426         .has_config_load_reg = false,
1427         .has_multi_master_mode = false,
1428         .has_slcg_override_reg = false,
1429         .has_mst_fifo = false,
1430         .quirks = &tegra_i2c_quirks,
1431         .supports_bus_clear = false,
1432         .has_apb_dma = true,
1433         .tlow_std_mode = 0x4,
1434         .thigh_std_mode = 0x2,
1435         .tlow_fast_fastplus_mode = 0x4,
1436         .thigh_fast_fastplus_mode = 0x2,
1437         .setup_hold_time_std_mode = 0x0,
1438         .setup_hold_time_fast_fast_plus_mode = 0x0,
1439         .setup_hold_time_hs_mode = 0x0,
1440         .has_interface_timing_reg = false,
1441 };
1442
1443 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
1444         .has_continue_xfer_support = true,
1445         .has_per_pkt_xfer_complete_irq = true,
1446         .clk_divisor_hs_mode = 1,
1447         .clk_divisor_std_mode = 0x19,
1448         .clk_divisor_fast_mode = 0x19,
1449         .clk_divisor_fast_plus_mode = 0x10,
1450         .has_config_load_reg = false,
1451         .has_multi_master_mode = false,
1452         .has_slcg_override_reg = false,
1453         .has_mst_fifo = false,
1454         .quirks = &tegra_i2c_quirks,
1455         .supports_bus_clear = true,
1456         .has_apb_dma = true,
1457         .tlow_std_mode = 0x4,
1458         .thigh_std_mode = 0x2,
1459         .tlow_fast_fastplus_mode = 0x4,
1460         .thigh_fast_fastplus_mode = 0x2,
1461         .setup_hold_time_std_mode = 0x0,
1462         .setup_hold_time_fast_fast_plus_mode = 0x0,
1463         .setup_hold_time_hs_mode = 0x0,
1464         .has_interface_timing_reg = false,
1465 };
1466
1467 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
1468         .has_continue_xfer_support = true,
1469         .has_per_pkt_xfer_complete_irq = true,
1470         .clk_divisor_hs_mode = 1,
1471         .clk_divisor_std_mode = 0x19,
1472         .clk_divisor_fast_mode = 0x19,
1473         .clk_divisor_fast_plus_mode = 0x10,
1474         .has_config_load_reg = true,
1475         .has_multi_master_mode = false,
1476         .has_slcg_override_reg = true,
1477         .has_mst_fifo = false,
1478         .quirks = &tegra_i2c_quirks,
1479         .supports_bus_clear = true,
1480         .has_apb_dma = true,
1481         .tlow_std_mode = 0x4,
1482         .thigh_std_mode = 0x2,
1483         .tlow_fast_fastplus_mode = 0x4,
1484         .thigh_fast_fastplus_mode = 0x2,
1485         .setup_hold_time_std_mode = 0x0,
1486         .setup_hold_time_fast_fast_plus_mode = 0x0,
1487         .setup_hold_time_hs_mode = 0x0,
1488         .has_interface_timing_reg = true,
1489 };
1490
1491 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
1492         .has_continue_xfer_support = true,
1493         .has_per_pkt_xfer_complete_irq = true,
1494         .clk_divisor_hs_mode = 1,
1495         .clk_divisor_std_mode = 0x19,
1496         .clk_divisor_fast_mode = 0x19,
1497         .clk_divisor_fast_plus_mode = 0x10,
1498         .has_config_load_reg = true,
1499         .has_multi_master_mode = false,
1500         .has_slcg_override_reg = true,
1501         .has_mst_fifo = false,
1502         .quirks = &tegra_i2c_quirks,
1503         .supports_bus_clear = true,
1504         .has_apb_dma = true,
1505         .tlow_std_mode = 0x4,
1506         .thigh_std_mode = 0x2,
1507         .tlow_fast_fastplus_mode = 0x4,
1508         .thigh_fast_fastplus_mode = 0x2,
1509         .setup_hold_time_std_mode = 0,
1510         .setup_hold_time_fast_fast_plus_mode = 0,
1511         .setup_hold_time_hs_mode = 0,
1512         .has_interface_timing_reg = true,
1513 };
1514
1515 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
1516         .has_continue_xfer_support = true,
1517         .has_per_pkt_xfer_complete_irq = true,
1518         .clk_divisor_hs_mode = 1,
1519         .clk_divisor_std_mode = 0x16,
1520         .clk_divisor_fast_mode = 0x19,
1521         .clk_divisor_fast_plus_mode = 0x10,
1522         .has_config_load_reg = true,
1523         .has_multi_master_mode = false,
1524         .has_slcg_override_reg = true,
1525         .has_mst_fifo = false,
1526         .quirks = &tegra_i2c_quirks,
1527         .supports_bus_clear = true,
1528         .has_apb_dma = false,
1529         .tlow_std_mode = 0x4,
1530         .thigh_std_mode = 0x3,
1531         .tlow_fast_fastplus_mode = 0x4,
1532         .thigh_fast_fastplus_mode = 0x2,
1533         .setup_hold_time_std_mode = 0,
1534         .setup_hold_time_fast_fast_plus_mode = 0,
1535         .setup_hold_time_hs_mode = 0,
1536         .has_interface_timing_reg = true,
1537 };
1538
1539 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
1540         .has_continue_xfer_support = true,
1541         .has_per_pkt_xfer_complete_irq = true,
1542         .clk_divisor_hs_mode = 1,
1543         .clk_divisor_std_mode = 0x4f,
1544         .clk_divisor_fast_mode = 0x3c,
1545         .clk_divisor_fast_plus_mode = 0x16,
1546         .has_config_load_reg = true,
1547         .has_multi_master_mode = true,
1548         .has_slcg_override_reg = true,
1549         .has_mst_fifo = true,
1550         .quirks = &tegra194_i2c_quirks,
1551         .supports_bus_clear = true,
1552         .has_apb_dma = false,
1553         .tlow_std_mode = 0x8,
1554         .thigh_std_mode = 0x7,
1555         .tlow_fast_fastplus_mode = 0x2,
1556         .thigh_fast_fastplus_mode = 0x2,
1557         .setup_hold_time_std_mode = 0x08080808,
1558         .setup_hold_time_fast_fast_plus_mode = 0x02020202,
1559         .setup_hold_time_hs_mode = 0x090909,
1560         .has_interface_timing_reg = true,
1561 };
1562
1563 /* Match table for of_platform binding */
1564 static const struct of_device_id tegra_i2c_of_match[] = {
1565         { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1566         { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1567         { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
1568         { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1569         { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1570         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1571         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1572         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1573         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1574         {},
1575 };
1576 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1577
1578 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
1579 {
1580         struct device_node *np = i2c_dev->dev->of_node;
1581         int ret;
1582         bool multi_mode;
1583
1584         ret = of_property_read_u32(np, "clock-frequency",
1585                                    &i2c_dev->bus_clk_rate);
1586         if (ret)
1587                 i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */
1588
1589         multi_mode = of_property_read_bool(np, "multi-master");
1590         i2c_dev->is_multimaster_mode = multi_mode;
1591
1592         if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc"))
1593                 i2c_dev->is_dvc = true;
1594
1595         if (of_device_is_compatible(np, "nvidia,tegra210-i2c-vi"))
1596                 i2c_dev->is_vi = true;
1597 }
1598
1599 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev)
1600 {
1601         int err;
1602
1603         i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk";
1604
1605         if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw)
1606                 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk";
1607
1608         if (i2c_dev->is_vi)
1609                 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow";
1610
1611         err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks,
1612                                 i2c_dev->clocks);
1613         if (err)
1614                 return err;
1615
1616         err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks);
1617         if (err)
1618                 return err;
1619
1620         i2c_dev->div_clk = i2c_dev->clocks[0].clk;
1621
1622         if (!i2c_dev->is_multimaster_mode)
1623                 return 0;
1624
1625         err = clk_enable(i2c_dev->div_clk);
1626         if (err) {
1627                 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err);
1628                 goto unprepare_clocks;
1629         }
1630
1631         return 0;
1632
1633 unprepare_clocks:
1634         clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1635
1636         return err;
1637 }
1638
1639 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev)
1640 {
1641         if (i2c_dev->is_multimaster_mode)
1642                 clk_disable(i2c_dev->div_clk);
1643
1644         clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1645 }
1646
1647 static int tegra_i2c_probe(struct platform_device *pdev)
1648 {
1649         struct device *dev = &pdev->dev;
1650         struct tegra_i2c_dev *i2c_dev;
1651         struct resource *res;
1652         int ret;
1653
1654         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1655         if (!i2c_dev)
1656                 return -ENOMEM;
1657
1658         platform_set_drvdata(pdev, i2c_dev);
1659
1660         init_completion(&i2c_dev->msg_complete);
1661         init_completion(&i2c_dev->dma_complete);
1662
1663         i2c_dev->hw = of_device_get_match_data(&pdev->dev);
1664         i2c_dev->cont_id = pdev->id;
1665         i2c_dev->dev = &pdev->dev;
1666
1667         i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1668         if (IS_ERR(i2c_dev->base))
1669                 return PTR_ERR(i2c_dev->base);
1670
1671         i2c_dev->base_phys = res->start;
1672
1673         ret = platform_get_irq(pdev, 0);
1674         if (ret < 0)
1675                 return ret;
1676
1677         i2c_dev->irq = ret;
1678
1679         /* interrupt will be enabled during of transfer time */
1680         irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
1681
1682         ret = devm_request_irq(&pdev->dev, i2c_dev->irq, tegra_i2c_isr,
1683                                IRQF_NO_SUSPEND, dev_name(&pdev->dev),
1684                                i2c_dev);
1685         if (ret)
1686                 return ret;
1687
1688         i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c");
1689         if (IS_ERR(i2c_dev->rst)) {
1690                 dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->rst),
1691                               "failed to get reset control\n");
1692                 return PTR_ERR(i2c_dev->rst);
1693         }
1694
1695         tegra_i2c_parse_dt(i2c_dev);
1696
1697         ret = tegra_i2c_init_clocks(i2c_dev);
1698         if (ret)
1699                 return ret;
1700
1701         ret = tegra_i2c_init_dma(i2c_dev);
1702         if (ret)
1703                 goto release_clocks;
1704
1705         /*
1706          * VI I2C is in VE power domain which is not always on and not
1707          * an IRQ safe. So, IRQ safe device can't be attached to a non-IRQ
1708          * safe domain as it prevents powering off the PM domain.
1709          * Also, VI I2C device don't need to use runtime IRQ safe as it will
1710          * not be used for atomic transfers.
1711          */
1712         if (!i2c_dev->is_vi)
1713                 pm_runtime_irq_safe(&pdev->dev);
1714         pm_runtime_enable(&pdev->dev);
1715         ret = pm_runtime_get_sync(i2c_dev->dev);
1716         if (ret < 0) {
1717                 dev_err(dev, "runtime resume failed\n");
1718                 goto put_rpm;
1719         }
1720
1721         ret = tegra_i2c_init(i2c_dev);
1722         if (ret)
1723                 goto put_rpm;
1724
1725         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1726         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1727         i2c_dev->adapter.dev.parent = &pdev->dev;
1728         i2c_dev->adapter.retries = 1;
1729         i2c_dev->adapter.timeout = 6 * HZ;
1730         i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1731         i2c_dev->adapter.owner = THIS_MODULE;
1732         i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1733         i2c_dev->adapter.algo = &tegra_i2c_algo;
1734         i2c_dev->adapter.nr = pdev->id;
1735
1736         if (i2c_dev->hw->supports_bus_clear)
1737                 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
1738
1739         strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
1740                 sizeof(i2c_dev->adapter.name));
1741
1742         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1743         if (ret)
1744                 goto put_rpm;
1745
1746         pm_runtime_put(&pdev->dev);
1747
1748         return 0;
1749
1750 put_rpm:
1751         pm_runtime_put_sync(&pdev->dev);
1752         pm_runtime_disable(&pdev->dev);
1753
1754         tegra_i2c_release_dma(i2c_dev);
1755 release_clocks:
1756         tegra_i2c_release_clocks(i2c_dev);
1757
1758         return ret;
1759 }
1760
1761 static int tegra_i2c_remove(struct platform_device *pdev)
1762 {
1763         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1764
1765         i2c_del_adapter(&i2c_dev->adapter);
1766
1767         pm_runtime_disable(&pdev->dev);
1768
1769         tegra_i2c_release_dma(i2c_dev);
1770         tegra_i2c_release_clocks(i2c_dev);
1771         return 0;
1772 }
1773
1774 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
1775 {
1776         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1777         int ret;
1778
1779         ret = pinctrl_pm_select_default_state(i2c_dev->dev);
1780         if (ret)
1781                 return ret;
1782
1783         ret = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks);
1784         if (ret)
1785                 return ret;
1786
1787         /*
1788          * VI I2C device is attached to VE power domain which goes through
1789          * power ON/OFF during PM runtime resume/suspend. So, controller
1790          * should go through reset and need to re-initialize after power
1791          * domain ON.
1792          */
1793         if (i2c_dev->is_vi) {
1794                 ret = tegra_i2c_init(i2c_dev);
1795                 if (ret)
1796                         goto disable_clocks;
1797         }
1798
1799         return 0;
1800
1801 disable_clocks:
1802         clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
1803
1804         return ret;
1805 }
1806
1807 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev)
1808 {
1809         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1810
1811         clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
1812
1813         return pinctrl_pm_select_idle_state(i2c_dev->dev);
1814 }
1815
1816 static int __maybe_unused tegra_i2c_suspend(struct device *dev)
1817 {
1818         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1819         int err = 0;
1820
1821         i2c_mark_adapter_suspended(&i2c_dev->adapter);
1822
1823         if (!pm_runtime_status_suspended(dev))
1824                 err = tegra_i2c_runtime_suspend(dev);
1825
1826         return err;
1827 }
1828
1829 static int __maybe_unused tegra_i2c_resume(struct device *dev)
1830 {
1831         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1832         int err;
1833
1834         /*
1835          * We need to ensure that clocks are enabled so that registers can be
1836          * restored in tegra_i2c_init().
1837          */
1838         err = tegra_i2c_runtime_resume(dev);
1839         if (err)
1840                 return err;
1841
1842         err = tegra_i2c_init(i2c_dev);
1843         if (err)
1844                 return err;
1845
1846         /*
1847          * In case we are runtime suspended, disable clocks again so that we
1848          * don't unbalance the clock reference counts during the next runtime
1849          * resume transition.
1850          */
1851         if (pm_runtime_status_suspended(dev)) {
1852                 err = tegra_i2c_runtime_suspend(dev);
1853                 if (err)
1854                         return err;
1855         }
1856
1857         i2c_mark_adapter_resumed(&i2c_dev->adapter);
1858
1859         return 0;
1860 }
1861
1862 static const struct dev_pm_ops tegra_i2c_pm = {
1863         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
1864         SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1865                            NULL)
1866 };
1867
1868 static struct platform_driver tegra_i2c_driver = {
1869         .probe   = tegra_i2c_probe,
1870         .remove  = tegra_i2c_remove,
1871         .driver  = {
1872                 .name  = "tegra-i2c",
1873                 .of_match_table = tegra_i2c_of_match,
1874                 .pm    = &tegra_i2c_pm,
1875         },
1876 };
1877
1878 module_platform_driver(tegra_i2c_driver);
1879
1880 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1881 MODULE_AUTHOR("Colin Cross");
1882 MODULE_LICENSE("GPL v2");