drivers/i2c/busses/i2c-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * drivers/i2c/busses/i2c-tegra.c
   4  *
   5  * Copyright (C) 2010 Google, Inc.
   6  * Author: Colin Cross <ccross@android.com>
   7  */
   8
   9 #include <linux/bitfield.h>
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/err.h>
  15 #include <linux/i2c.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/irq.h>
  21 #include <linux/kernel.h>
  22 #include <linux/ktime.h>
  23 #include <linux/module.h>
  24 #include <linux/of_device.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/reset.h>
  29
  30 #define BYTES_PER_FIFO_WORD 4
  31
  32 #define I2C_CNFG                                0x000
  33 #define I2C_CNFG_DEBOUNCE_CNT                   GENMASK(14, 12)
  34 #define I2C_CNFG_PACKET_MODE_EN                 BIT(10)
  35 #define I2C_CNFG_NEW_MASTER_FSM                 BIT(11)
  36 #define I2C_CNFG_MULTI_MASTER_MODE              BIT(17)
  37 #define I2C_STATUS                              0x01c
  38 #define I2C_SL_CNFG                             0x020
  39 #define I2C_SL_CNFG_NACK                        BIT(1)
  40 #define I2C_SL_CNFG_NEWSL                       BIT(2)
  41 #define I2C_SL_ADDR1                            0x02c
  42 #define I2C_SL_ADDR2                            0x030
  43 #define I2C_TLOW_SEXT                           0x034
  44 #define I2C_TX_FIFO                             0x050
  45 #define I2C_RX_FIFO                             0x054
  46 #define I2C_PACKET_TRANSFER_STATUS              0x058
  47 #define I2C_FIFO_CONTROL                        0x05c
  48 #define I2C_FIFO_CONTROL_TX_FLUSH               BIT(1)
  49 #define I2C_FIFO_CONTROL_RX_FLUSH               BIT(0)
  50 #define I2C_FIFO_CONTROL_TX_TRIG(x)             (((x) - 1) << 5)
  51 #define I2C_FIFO_CONTROL_RX_TRIG(x)             (((x) - 1) << 2)
  52 #define I2C_FIFO_STATUS                         0x060
  53 #define I2C_FIFO_STATUS_TX                      GENMASK(7, 4)
  54 #define I2C_FIFO_STATUS_RX                      GENMASK(3, 0)
  55 #define I2C_INT_MASK                            0x064
  56 #define I2C_INT_STATUS                          0x068
  57 #define I2C_INT_BUS_CLR_DONE                    BIT(11)
  58 #define I2C_INT_PACKET_XFER_COMPLETE            BIT(7)
  59 #define I2C_INT_NO_ACK                          BIT(3)
  60 #define I2C_INT_ARBITRATION_LOST                BIT(2)
  61 #define I2C_INT_TX_FIFO_DATA_REQ                BIT(1)
  62 #define I2C_INT_RX_FIFO_DATA_REQ                BIT(0)
  63 #define I2C_CLK_DIVISOR                         0x06c
  64 #define I2C_CLK_DIVISOR_STD_FAST_MODE           GENMASK(31, 16)
  65 #define I2C_CLK_DIVISOR_HSMODE                  GENMASK(15, 0)
  66
  67 #define DVC_CTRL_REG1                           0x000
  68 #define DVC_CTRL_REG1_INTR_EN                   BIT(10)
  69 #define DVC_CTRL_REG3                           0x008
  70 #define DVC_CTRL_REG3_SW_PROG                   BIT(26)
  71 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          BIT(30)
  72 #define DVC_STATUS                              0x00c
  73 #define DVC_STATUS_I2C_DONE_INTR                BIT(30)
  74
  75 #define I2C_ERR_NONE                            0x00
  76 #define I2C_ERR_NO_ACK                          BIT(0)
  77 #define I2C_ERR_ARBITRATION_LOST                BIT(1)
  78 #define I2C_ERR_UNKNOWN_INTERRUPT               BIT(2)
  79 #define I2C_ERR_RX_BUFFER_OVERFLOW              BIT(3)
  80
  81 #define PACKET_HEADER0_HEADER_SIZE              GENMASK(29, 28)
  82 #define PACKET_HEADER0_PACKET_ID                GENMASK(23, 16)
  83 #define PACKET_HEADER0_CONT_ID                  GENMASK(15, 12)
  84 #define PACKET_HEADER0_PROTOCOL                 GENMASK(7, 4)
  85 #define PACKET_HEADER0_PROTOCOL_I2C             1
  86
  87 #define I2C_HEADER_CONT_ON_NAK                  BIT(21)
  88 #define I2C_HEADER_READ                         BIT(19)
  89 #define I2C_HEADER_10BIT_ADDR                   BIT(18)
  90 #define I2C_HEADER_IE_ENABLE                    BIT(17)
  91 #define I2C_HEADER_REPEAT_START                 BIT(16)
  92 #define I2C_HEADER_CONTINUE_XFER                BIT(15)
  93 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
  94
  95 #define I2C_BUS_CLEAR_CNFG                      0x084
  96 #define I2C_BC_SCLK_THRESHOLD                   GENMASK(23, 16)
  97 #define I2C_BC_STOP_COND                        BIT(2)
  98 #define I2C_BC_TERMINATE                        BIT(1)
  99 #define I2C_BC_ENABLE                           BIT(0)
 100 #define I2C_BUS_CLEAR_STATUS                    0x088
 101 #define I2C_BC_STATUS                           BIT(0)
 102
 103 #define I2C_CONFIG_LOAD                         0x08c
 104 #define I2C_MSTR_CONFIG_LOAD                    BIT(0)
 105
 106 #define I2C_CLKEN_OVERRIDE                      0x090
 107 #define I2C_MST_CORE_CLKEN_OVR                  BIT(0)
 108
 109 #define I2C_INTERFACE_TIMING_0                  0x094
 110 #define  I2C_INTERFACE_TIMING_THIGH             GENMASK(13, 8)
 111 #define  I2C_INTERFACE_TIMING_TLOW              GENMASK(5, 0)
 112 #define I2C_INTERFACE_TIMING_1                  0x098
 113 #define  I2C_INTERFACE_TIMING_TBUF              GENMASK(29, 24)
 114 #define  I2C_INTERFACE_TIMING_TSU_STO           GENMASK(21, 16)
 115 #define  I2C_INTERFACE_TIMING_THD_STA           GENMASK(13, 8)
 116 #define  I2C_INTERFACE_TIMING_TSU_STA           GENMASK(5, 0)
 117
 118 #define I2C_HS_INTERFACE_TIMING_0               0x09c
 119 #define  I2C_HS_INTERFACE_TIMING_THIGH          GENMASK(13, 8)
 120 #define  I2C_HS_INTERFACE_TIMING_TLOW           GENMASK(5, 0)
 121 #define I2C_HS_INTERFACE_TIMING_1               0x0a0
 122 #define  I2C_HS_INTERFACE_TIMING_TSU_STO        GENMASK(21, 16)
 123 #define  I2C_HS_INTERFACE_TIMING_THD_STA        GENMASK(13, 8)
 124 #define  I2C_HS_INTERFACE_TIMING_TSU_STA        GENMASK(5, 0)
 125
 126 #define I2C_MST_FIFO_CONTROL                    0x0b4
 127 #define I2C_MST_FIFO_CONTROL_RX_FLUSH           BIT(0)
 128 #define I2C_MST_FIFO_CONTROL_TX_FLUSH           BIT(1)
 129 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x)         (((x) - 1) <<  4)
 130 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x)         (((x) - 1) << 16)
 131
 132 #define I2C_MST_FIFO_STATUS                     0x0b8
 133 #define I2C_MST_FIFO_STATUS_TX                  GENMASK(23, 16)
 134 #define I2C_MST_FIFO_STATUS_RX                  GENMASK(7, 0)
 135
 136 /* configuration load timeout in microseconds */
 137 #define I2C_CONFIG_LOAD_TIMEOUT                 1000000
 138
 139 /* Packet header size in bytes */
 140 #define I2C_PACKET_HEADER_SIZE                  12
 141
 142 /*
 143  * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
 144  * avoid DMA overhead, otherwise external APB DMA controller will be used.
 145  * Note that the actual MAX PIO length is 20 bytes because 32 bytes include
 146  * I2C_PACKET_HEADER_SIZE.
 147  */
 148 #define I2C_PIO_MODE_PREFERRED_LEN              32
 149
 150 /*
 151  * msg_end_type: The bus control which need to be send at end of transfer.
 152  * @MSG_END_STOP: Send stop pulse at end of transfer.
 153  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 154  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 155  *              stop or repeat start.
 156  */
 157 enum msg_end_type {
 158         MSG_END_STOP,
 159         MSG_END_REPEAT_START,
 160         MSG_END_CONTINUE,
 161 };
 162
 163 /**
 164  * struct tegra_i2c_hw_feature : Different HW support on Tegra
 165  * @has_continue_xfer_support: Continue transfer supports.
 166  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 167  *              complete interrupt per packet basis.
 168  * @has_single_clk_source: The I2C controller has single clock source. Tegra30
 169  *              and earlier SoCs have two clock sources i.e. div-clk and
 170  *              fast-clk.
 171  * @has_config_load_reg: Has the config load register to load the new
 172  *              configuration.
 173  * @clk_divisor_hs_mode: Clock divisor in HS mode.
 174  * @clk_divisor_std_mode: Clock divisor in standard mode. It is
 175  *              applicable if there is no fast clock source i.e. single clock
 176  *              source.
 177  * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
 178  *              applicable if there is no fast clock source i.e. single clock
 179  *              source.
 180  * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
 181  *              applicable if there is no fast clock source (i.e. single
 182  *              clock source).
 183  * @has_multi_master_mode: The I2C controller supports running in single-master
 184  *              or multi-master mode.
 185  * @has_slcg_override_reg: The I2C controller supports a register that
 186  *              overrides the second level clock gating.
 187  * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
 188  *              provides additional features and allows for longer messages to
 189  *              be transferred in one go.
 190  * @quirks: i2c adapter quirks for limiting write/read transfer size and not
 191  *              allowing 0 length transfers.
 192  * @supports_bus_clear: Bus Clear support to recover from bus hang during
 193  *              SDA stuck low from device for some unknown reasons.
 194  * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
 195  * @tlow_std_mode: Low period of the clock in standard mode.
 196  * @thigh_std_mode: High period of the clock in standard mode.
 197  * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
 198  * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
 199  * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
 200  *              in standard mode.
 201  * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
 202  *              conditions in fast/fast-plus modes.
 203  * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
 204  *              in HS mode.
 205  * @has_interface_timing_reg: Has interface timing register to program the tuned
 206  *              timing settings.
 207  */
 208 struct tegra_i2c_hw_feature {
 209         bool has_continue_xfer_support;
 210         bool has_per_pkt_xfer_complete_irq;
 211         bool has_single_clk_source;
 212         bool has_config_load_reg;
 213         int clk_divisor_hs_mode;
 214         int clk_divisor_std_mode;
 215         int clk_divisor_fast_mode;
 216         u16 clk_divisor_fast_plus_mode;
 217         bool has_multi_master_mode;
 218         bool has_slcg_override_reg;
 219         bool has_mst_fifo;
 220         const struct i2c_adapter_quirks *quirks;
 221         bool supports_bus_clear;
 222         bool has_apb_dma;
 223         u8 tlow_std_mode;
 224         u8 thigh_std_mode;
 225         u8 tlow_fast_fastplus_mode;
 226         u8 thigh_fast_fastplus_mode;
 227         u32 setup_hold_time_std_mode;
 228         u32 setup_hold_time_fast_fast_plus_mode;
 229         u32 setup_hold_time_hs_mode;
 230         bool has_interface_timing_reg;
 231 };
 232
 233 /**
 234  * struct tegra_i2c_dev - per device I2C context
 235  * @dev: device reference for power management
 236  * @hw: Tegra I2C HW feature
 237  * @adapter: core I2C layer adapter information
 238  * @div_clk: clock reference for div clock of I2C controller
 239  * @fast_clk: clock reference for fast clock of I2C controller
 240  * @rst: reset control for the I2C controller
 241  * @base: ioremapped registers cookie
 242  * @base_phys: physical base address of the I2C controller
 243  * @cont_id: I2C controller ID, used for packet header
 244  * @irq: IRQ number of transfer complete interrupt
 245  * @is_dvc: identifies the DVC I2C controller, has a different register layout
 246  * @is_vi: identifies the VI I2C controller, has a different register layout
 247  * @msg_complete: transfer completion notifier
 248  * @msg_err: error code for completed message
 249  * @msg_buf: pointer to current message data
 250  * @msg_buf_remaining: size of unsent data in the message buffer
 251  * @msg_read: identifies read transfers
 252  * @bus_clk_rate: current I2C bus clock rate
 253  * @clk_divisor_non_hs_mode: clock divider for non-high-speed modes
 254  * @is_multimaster_mode: track if I2C controller is in multi-master mode
 255  * @tx_dma_chan: DMA transmit channel
 256  * @rx_dma_chan: DMA receive channel
 257  * @dma_phys: handle to DMA resources
 258  * @dma_buf: pointer to allocated DMA buffer
 259  * @dma_buf_size: DMA buffer size
 260  * @is_curr_dma_xfer: indicates active DMA transfer
 261  * @dma_complete: DMA completion notifier
 262  * @is_curr_atomic_xfer: indicates active atomic transfer
 263  */
 264 struct tegra_i2c_dev {
 265         struct device *dev;
 266         const struct tegra_i2c_hw_feature *hw;
 267         struct i2c_adapter adapter;
 268         struct clk *div_clk;
 269         struct clk *fast_clk;
 270         struct clk *slow_clk;
 271         struct reset_control *rst;
 272         void __iomem *base;
 273         phys_addr_t base_phys;
 274         int cont_id;
 275         int irq;
 276         int is_dvc;
 277         bool is_vi;
 278         struct completion msg_complete;
 279         int msg_err;
 280         u8 *msg_buf;
 281         size_t msg_buf_remaining;
 282         int msg_read;
 283         u32 bus_clk_rate;
 284         u16 clk_divisor_non_hs_mode;
 285         bool is_multimaster_mode;
 286         struct dma_chan *tx_dma_chan;
 287         struct dma_chan *rx_dma_chan;
 288         dma_addr_t dma_phys;
 289         u32 *dma_buf;
 290         unsigned int dma_buf_size;
 291         bool is_curr_dma_xfer;
 292         struct completion dma_complete;
 293         bool is_curr_atomic_xfer;
 294 };
 295
 296 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 297                        unsigned long reg)
 298 {
 299         writel_relaxed(val, i2c_dev->base + reg);
 300 }
 301
 302 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 303 {
 304         return readl_relaxed(i2c_dev->base + reg);
 305 }
 306
 307 /*
 308  * i2c_writel and i2c_readl will offset the register if necessary to talk
 309  * to the I2C block inside the DVC block
 310  */
 311 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 312                                         unsigned long reg)
 313 {
 314         if (i2c_dev->is_dvc)
 315                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 316         else if (i2c_dev->is_vi)
 317                 reg = 0xc00 + (reg << 2);
 318         return reg;
 319 }
 320
 321 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 322                        unsigned long reg)
 323 {
 324         writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 325
 326         /* Read back register to make sure that register writes completed */
 327         if (reg != I2C_TX_FIFO)
 328                 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 329 }
 330
 331 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 332 {
 333         return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 334 }
 335
 336 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 337                         unsigned long reg, int len)
 338 {
 339         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 340 }
 341
 342 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 343                        unsigned long reg, int len)
 344 {
 345         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 346 }
 347
 348 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 349 {
 350         u32 int_mask;
 351
 352         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
 353         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 354 }
 355
 356 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 357 {
 358         u32 int_mask;
 359
 360         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
 361         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 362 }
 363
 364 static void tegra_i2c_dma_complete(void *args)
 365 {
 366         struct tegra_i2c_dev *i2c_dev = args;
 367
 368         complete(&i2c_dev->dma_complete);
 369 }
 370
 371 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
 372 {
 373         struct dma_async_tx_descriptor *dma_desc;
 374         enum dma_transfer_direction dir;
 375         struct dma_chan *chan;
 376
 377         dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
 378         reinit_completion(&i2c_dev->dma_complete);
 379         dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
 380         chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan;
 381         dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys,
 382                                                len, dir, DMA_PREP_INTERRUPT |
 383                                                DMA_CTRL_ACK);
 384         if (!dma_desc) {
 385                 dev_err(i2c_dev->dev, "failed to get DMA descriptor\n");
 386                 return -EINVAL;
 387         }
 388
 389         dma_desc->callback = tegra_i2c_dma_complete;
 390         dma_desc->callback_param = i2c_dev;
 391         dmaengine_submit(dma_desc);
 392         dma_async_issue_pending(chan);
 393         return 0;
 394 }
 395
 396 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
 397 {
 398         if (i2c_dev->dma_buf) {
 399                 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
 400                                   i2c_dev->dma_buf, i2c_dev->dma_phys);
 401                 i2c_dev->dma_buf = NULL;
 402         }
 403
 404         if (i2c_dev->tx_dma_chan) {
 405                 dma_release_channel(i2c_dev->tx_dma_chan);
 406                 i2c_dev->tx_dma_chan = NULL;
 407         }
 408
 409         if (i2c_dev->rx_dma_chan) {
 410                 dma_release_channel(i2c_dev->rx_dma_chan);
 411                 i2c_dev->rx_dma_chan = NULL;
 412         }
 413 }
 414
 415 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
 416 {
 417         struct dma_chan *chan;
 418         u32 *dma_buf;
 419         dma_addr_t dma_phys;
 420         int err;
 421
 422         if (!i2c_dev->hw->has_apb_dma)
 423                 return 0;
 424
 425         if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
 426                 dev_dbg(i2c_dev->dev, "Support for APB DMA not enabled!\n");
 427                 return 0;
 428         }
 429
 430         chan = dma_request_chan(i2c_dev->dev, "rx");
 431         if (IS_ERR(chan)) {
 432                 err = PTR_ERR(chan);
 433                 goto err_out;
 434         }
 435
 436         i2c_dev->rx_dma_chan = chan;
 437
 438         chan = dma_request_chan(i2c_dev->dev, "tx");
 439         if (IS_ERR(chan)) {
 440                 err = PTR_ERR(chan);
 441                 goto err_out;
 442         }
 443
 444         i2c_dev->tx_dma_chan = chan;
 445
 446         dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
 447                                      &dma_phys, GFP_KERNEL | __GFP_NOWARN);
 448         if (!dma_buf) {
 449                 dev_err(i2c_dev->dev, "failed to allocate the DMA buffer\n");
 450                 err = -ENOMEM;
 451                 goto err_out;
 452         }
 453
 454         i2c_dev->dma_buf = dma_buf;
 455         i2c_dev->dma_phys = dma_phys;
 456         return 0;
 457
 458 err_out:
 459         tegra_i2c_release_dma(i2c_dev);
 460         if (err != -EPROBE_DEFER) {
 461                 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
 462                 dev_err(i2c_dev->dev, "falling back to PIO\n");
 463                 return 0;
 464         }
 465
 466         return err;
 467 }
 468
 469 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 470 {
 471         unsigned long timeout = jiffies + HZ;
 472         unsigned int offset;
 473         u32 mask, val;
 474
 475         if (i2c_dev->hw->has_mst_fifo) {
 476                 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
 477                        I2C_MST_FIFO_CONTROL_RX_FLUSH;
 478                 offset = I2C_MST_FIFO_CONTROL;
 479         } else {
 480                 mask = I2C_FIFO_CONTROL_TX_FLUSH |
 481                        I2C_FIFO_CONTROL_RX_FLUSH;
 482                 offset = I2C_FIFO_CONTROL;
 483         }
 484
 485         val = i2c_readl(i2c_dev, offset);
 486         val |= mask;
 487         i2c_writel(i2c_dev, val, offset);
 488
 489         while (i2c_readl(i2c_dev, offset) & mask) {
 490                 if (time_after(jiffies, timeout)) {
 491                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 492                         return -ETIMEDOUT;
 493                 }
 494                 usleep_range(1000, 2000);
 495         }
 496         return 0;
 497 }
 498
 499 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 500 {
 501         u32 val;
 502         int rx_fifo_avail;
 503         u8 *buf = i2c_dev->msg_buf;
 504         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 505         int words_to_transfer;
 506
 507         /*
 508          * Catch overflow due to message fully sent
 509          * before the check for RX FIFO availability.
 510          */
 511         if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
 512                 return -EINVAL;
 513
 514         if (i2c_dev->hw->has_mst_fifo) {
 515                 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 516                 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val);
 517         } else {
 518                 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 519                 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val);
 520         }
 521
 522         /* Rounds down to not include partial word at the end of buf */
 523         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 524         if (words_to_transfer > rx_fifo_avail)
 525                 words_to_transfer = rx_fifo_avail;
 526
 527         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 528
 529         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 530         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 531         rx_fifo_avail -= words_to_transfer;
 532
 533         /*
 534          * If there is a partial word at the end of buf, handle it manually to
 535          * prevent overwriting past the end of buf
 536          */
 537         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 538                 /*
 539                  * buf_remaining > 3 check not needed as rx_fifo_avail == 0
 540                  * when (words_to_transfer was > rx_fifo_avail) earlier
 541                  * in this function.
 542                  */
 543                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 544                 val = cpu_to_le32(val);
 545                 memcpy(buf, &val, buf_remaining);
 546                 buf_remaining = 0;
 547                 rx_fifo_avail--;
 548         }
 549
 550         /* RX FIFO must be drained, otherwise it's an Overflow case. */
 551         if (WARN_ON_ONCE(rx_fifo_avail))
 552                 return -EINVAL;
 553
 554         i2c_dev->msg_buf_remaining = buf_remaining;
 555         i2c_dev->msg_buf = buf;
 556
 557         return 0;
 558 }
 559
 560 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 561 {
 562         u32 val;
 563         int tx_fifo_avail;
 564         u8 *buf = i2c_dev->msg_buf;
 565         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 566         int words_to_transfer;
 567
 568         if (i2c_dev->hw->has_mst_fifo) {
 569                 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 570                 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val);
 571         } else {
 572                 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 573                 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val);
 574         }
 575
 576         /* Rounds down to not include partial word at the end of buf */
 577         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 578
 579         /* It's very common to have < 4 bytes, so optimize that case. */
 580         if (words_to_transfer) {
 581                 if (words_to_transfer > tx_fifo_avail)
 582                         words_to_transfer = tx_fifo_avail;
 583
 584                 /*
 585                  * Update state before writing to FIFO.  If this casues us
 586                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 587                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 588                  * not maskable).  We need to make sure that the isr sees
 589                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 590                  */
 591                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 592                 tx_fifo_avail -= words_to_transfer;
 593                 i2c_dev->msg_buf_remaining = buf_remaining;
 594                 i2c_dev->msg_buf = buf +
 595                         words_to_transfer * BYTES_PER_FIFO_WORD;
 596                 barrier();
 597
 598                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 599
 600                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 601         }
 602
 603         /*
 604          * If there is a partial word at the end of buf, handle it manually to
 605          * prevent reading past the end of buf, which could cross a page
 606          * boundary and fault.
 607          */
 608         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 609                 /*
 610                  * buf_remaining > 3 check not needed as tx_fifo_avail == 0
 611                  * when (words_to_transfer was > tx_fifo_avail) earlier
 612                  * in this function for non-zero words_to_transfer.
 613                  */
 614                 memcpy(&val, buf, buf_remaining);
 615                 val = le32_to_cpu(val);
 616
 617                 /* Again update before writing to FIFO to make sure isr sees. */
 618                 i2c_dev->msg_buf_remaining = 0;
 619                 i2c_dev->msg_buf = NULL;
 620                 barrier();
 621
 622                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 623         }
 624
 625         return 0;
 626 }
 627
 628 /*
 629  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 630  * block.  This block is identical to the rest of the I2C blocks, except that
 631  * it only supports master mode, it has registers moved around, and it needs
 632  * some extra init to get it into I2C mode.  The register moves are handled
 633  * by i2c_readl and i2c_writel
 634  */
 635 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 636 {
 637         u32 val;
 638
 639         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 640         val |= DVC_CTRL_REG3_SW_PROG;
 641         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 642         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 643
 644         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 645         val |= DVC_CTRL_REG1_INTR_EN;
 646         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 647 }
 648
 649 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
 650 {
 651         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 652         int ret;
 653
 654         ret = pinctrl_pm_select_default_state(i2c_dev->dev);
 655         if (ret)
 656                 return ret;
 657
 658         if (!i2c_dev->hw->has_single_clk_source) {
 659                 ret = clk_enable(i2c_dev->fast_clk);
 660                 if (ret < 0) {
 661                         dev_err(i2c_dev->dev,
 662                                 "Enabling fast clk failed, err %d\n", ret);
 663                         return ret;
 664                 }
 665         }
 666
 667         if (i2c_dev->slow_clk) {
 668                 ret = clk_enable(i2c_dev->slow_clk);
 669                 if (ret < 0) {
 670                         dev_err(dev, "failed to enable slow clock: %d\n", ret);
 671                         return ret;
 672                 }
 673         }
 674
 675         ret = clk_enable(i2c_dev->div_clk);
 676         if (ret < 0) {
 677                 dev_err(i2c_dev->dev,
 678                         "Enabling div clk failed, err %d\n", ret);
 679                 clk_disable(i2c_dev->fast_clk);
 680                 return ret;
 681         }
 682
 683         return 0;
 684 }
 685
 686 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev)
 687 {
 688         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 689
 690         clk_disable(i2c_dev->div_clk);
 691
 692         if (i2c_dev->slow_clk)
 693                 clk_disable(i2c_dev->slow_clk);
 694
 695         if (!i2c_dev->hw->has_single_clk_source)
 696                 clk_disable(i2c_dev->fast_clk);
 697
 698         return pinctrl_pm_select_idle_state(i2c_dev->dev);
 699 }
 700
 701 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
 702 {
 703         unsigned long reg_offset;
 704         void __iomem *addr;
 705         u32 val;
 706         int err;
 707
 708         if (i2c_dev->hw->has_config_load_reg) {
 709                 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
 710                 addr = i2c_dev->base + reg_offset;
 711                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 712
 713                 if (i2c_dev->is_curr_atomic_xfer)
 714                         err = readl_relaxed_poll_timeout_atomic(
 715                                                 addr, val, val == 0, 1000,
 716                                                 I2C_CONFIG_LOAD_TIMEOUT);
 717                 else
 718                         err = readl_relaxed_poll_timeout(
 719                                                 addr, val, val == 0, 1000,
 720                                                 I2C_CONFIG_LOAD_TIMEOUT);
 721
 722                 if (err) {
 723                         dev_warn(i2c_dev->dev,
 724                                  "timeout waiting for config load\n");
 725                         return err;
 726                 }
 727         }
 728
 729         return 0;
 730 }
 731
 732 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
 733 {
 734         u32 value;
 735
 736         value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) |
 737                 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4);
 738         i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0);
 739
 740         value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) |
 741                 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) |
 742                 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) |
 743                 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4);
 744         i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1);
 745
 746         value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) |
 747                 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8);
 748         i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0);
 749
 750         value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) |
 751                 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) |
 752                 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11);
 753         i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1);
 754
 755         value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND;
 756         i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG);
 757
 758         i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
 759 }
 760
 761 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit)
 762 {
 763         u32 val;
 764         int err;
 765         u32 clk_divisor, clk_multiplier;
 766         u32 tsu_thd;
 767         u8 tlow, thigh;
 768
 769         reset_control_assert(i2c_dev->rst);
 770         udelay(2);
 771         reset_control_deassert(i2c_dev->rst);
 772
 773         if (i2c_dev->is_dvc)
 774                 tegra_dvc_init(i2c_dev);
 775
 776         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 777               FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2);
 778
 779         if (i2c_dev->hw->has_multi_master_mode)
 780                 val |= I2C_CNFG_MULTI_MASTER_MODE;
 781
 782         i2c_writel(i2c_dev, val, I2C_CNFG);
 783         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 784
 785         if (i2c_dev->is_vi)
 786                 tegra_i2c_vi_init(i2c_dev);
 787
 788         /* Make sure clock divisor programmed correctly */
 789         clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
 790                                  i2c_dev->hw->clk_divisor_hs_mode) |
 791                       FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE,
 792                                  i2c_dev->clk_divisor_non_hs_mode);
 793         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 794
 795         if (i2c_dev->bus_clk_rate > I2C_MAX_STANDARD_MODE_FREQ &&
 796             i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
 797                 tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
 798                 thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
 799                 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
 800         } else {
 801                 tlow = i2c_dev->hw->tlow_std_mode;
 802                 thigh = i2c_dev->hw->thigh_std_mode;
 803                 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
 804         }
 805
 806         if (i2c_dev->hw->has_interface_timing_reg) {
 807                 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
 808                       FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
 809                 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
 810         }
 811
 812         /*
 813          * configure setup and hold times only when tsu_thd is non-zero.
 814          * otherwise, preserve the chip default values
 815          */
 816         if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
 817                 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
 818
 819         if (!clk_reinit) {
 820                 clk_multiplier = (tlow + thigh + 2);
 821                 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
 822                 err = clk_set_rate(i2c_dev->div_clk,
 823                                    i2c_dev->bus_clk_rate * clk_multiplier);
 824                 if (err) {
 825                         dev_err(i2c_dev->dev,
 826                                 "failed changing clock rate: %d\n", err);
 827                         return err;
 828                 }
 829         }
 830
 831         if (!i2c_dev->is_dvc && !i2c_dev->is_vi) {
 832                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 833
 834                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 835                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 836                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 837                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 838         }
 839
 840         err = tegra_i2c_flush_fifos(i2c_dev);
 841         if (err)
 842                 return err;
 843
 844         if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
 845                 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
 846
 847         err = tegra_i2c_wait_for_config_load(i2c_dev);
 848         if (err)
 849                 return err;
 850
 851         return 0;
 852 }
 853
 854 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
 855 {
 856         u32 cnfg;
 857
 858         /*
 859          * NACK interrupt is generated before the I2C controller generates
 860          * the STOP condition on the bus. So wait for 2 clock periods
 861          * before disabling the controller so that the STOP condition has
 862          * been delivered properly.
 863          */
 864         udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 865
 866         cnfg = i2c_readl(i2c_dev, I2C_CNFG);
 867         if (cnfg & I2C_CNFG_PACKET_MODE_EN)
 868                 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
 869
 870         return tegra_i2c_wait_for_config_load(i2c_dev);
 871 }
 872
 873 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 874 {
 875         u32 status;
 876         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 877         struct tegra_i2c_dev *i2c_dev = dev_id;
 878
 879         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 880
 881         if (status == 0) {
 882                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 883                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 884                          i2c_readl(i2c_dev, I2C_STATUS),
 885                          i2c_readl(i2c_dev, I2C_CNFG));
 886                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 887                 goto err;
 888         }
 889
 890         if (unlikely(status & status_err)) {
 891                 tegra_i2c_disable_packet_mode(i2c_dev);
 892                 if (status & I2C_INT_NO_ACK)
 893                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 894                 if (status & I2C_INT_ARBITRATION_LOST)
 895                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 896                 goto err;
 897         }
 898
 899         /*
 900          * I2C transfer is terminated during the bus clear so skip
 901          * processing the other interrupts.
 902          */
 903         if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
 904                 goto err;
 905
 906         if (!i2c_dev->is_curr_dma_xfer) {
 907                 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 908                         if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
 909                                 /*
 910                                  * Overflow error condition: message fully sent,
 911                                  * with no XFER_COMPLETE interrupt but hardware
 912                                  * asks to transfer more.
 913                                  */
 914                                 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
 915                                 goto err;
 916                         }
 917                 }
 918
 919                 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 920                         if (i2c_dev->msg_buf_remaining)
 921                                 tegra_i2c_fill_tx_fifo(i2c_dev);
 922                         else
 923                                 tegra_i2c_mask_irq(i2c_dev,
 924                                                    I2C_INT_TX_FIFO_DATA_REQ);
 925                 }
 926         }
 927
 928         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 929         if (i2c_dev->is_dvc)
 930                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 931
 932         /*
 933          * During message read XFER_COMPLETE interrupt is triggered prior to
 934          * DMA completion and during message write XFER_COMPLETE interrupt is
 935          * triggered after DMA completion.
 936          * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer.
 937          * so forcing msg_buf_remaining to 0 in DMA mode.
 938          */
 939         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 940                 if (i2c_dev->is_curr_dma_xfer)
 941                         i2c_dev->msg_buf_remaining = 0;
 942                 /*
 943                  * Underflow error condition: XFER_COMPLETE before message
 944                  * fully sent.
 945                  */
 946                 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
 947                         i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 948                         goto err;
 949                 }
 950                 complete(&i2c_dev->msg_complete);
 951         }
 952         goto done;
 953 err:
 954         /* An error occurred, mask all interrupts */
 955         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 956                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 957                 I2C_INT_RX_FIFO_DATA_REQ);
 958         if (i2c_dev->hw->supports_bus_clear)
 959                 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
 960         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 961         if (i2c_dev->is_dvc)
 962                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 963
 964         if (i2c_dev->is_curr_dma_xfer) {
 965                 if (i2c_dev->msg_read)
 966                         dmaengine_terminate_async(i2c_dev->rx_dma_chan);
 967                 else
 968                         dmaengine_terminate_async(i2c_dev->tx_dma_chan);
 969
 970                 complete(&i2c_dev->dma_complete);
 971         }
 972
 973         complete(&i2c_dev->msg_complete);
 974 done:
 975         return IRQ_HANDLED;
 976 }
 977
 978 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
 979                                        size_t len)
 980 {
 981         u32 val, reg;
 982         u8 dma_burst;
 983         struct dma_slave_config slv_config = {0};
 984         struct dma_chan *chan;
 985         int ret;
 986         unsigned long reg_offset;
 987
 988         if (i2c_dev->hw->has_mst_fifo)
 989                 reg = I2C_MST_FIFO_CONTROL;
 990         else
 991                 reg = I2C_FIFO_CONTROL;
 992
 993         if (i2c_dev->is_curr_dma_xfer) {
 994                 if (len & 0xF)
 995                         dma_burst = 1;
 996                 else if (len & 0x10)
 997                         dma_burst = 4;
 998                 else
 999                         dma_burst = 8;
1000
1001                 if (i2c_dev->msg_read) {
1002                         chan = i2c_dev->rx_dma_chan;
1003                         reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
1004                         slv_config.src_addr = i2c_dev->base_phys + reg_offset;
1005                         slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1006                         slv_config.src_maxburst = dma_burst;
1007
1008                         if (i2c_dev->hw->has_mst_fifo)
1009                                 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
1010                         else
1011                                 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
1012                 } else {
1013                         chan = i2c_dev->tx_dma_chan;
1014                         reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
1015                         slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
1016                         slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1017                         slv_config.dst_maxburst = dma_burst;
1018
1019                         if (i2c_dev->hw->has_mst_fifo)
1020                                 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
1021                         else
1022                                 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
1023                 }
1024
1025                 slv_config.device_fc = true;
1026                 ret = dmaengine_slave_config(chan, &slv_config);
1027                 if (ret < 0) {
1028                         dev_err(i2c_dev->dev, "DMA slave config failed: %d\n",
1029                                 ret);
1030                         dev_err(i2c_dev->dev, "falling back to PIO\n");
1031                         tegra_i2c_release_dma(i2c_dev);
1032                         i2c_dev->is_curr_dma_xfer = false;
1033                 } else {
1034                         goto out;
1035                 }
1036         }
1037
1038         if (i2c_dev->hw->has_mst_fifo)
1039                 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
1040                       I2C_MST_FIFO_CONTROL_RX_TRIG(1);
1041         else
1042                 val = I2C_FIFO_CONTROL_TX_TRIG(8) |
1043                       I2C_FIFO_CONTROL_RX_TRIG(1);
1044 out:
1045         i2c_writel(i2c_dev, val, reg);
1046 }
1047
1048 static unsigned long
1049 tegra_i2c_poll_completion_timeout(struct tegra_i2c_dev *i2c_dev,
1050                                   struct completion *complete,
1051                                   unsigned int timeout_ms)
1052 {
1053         ktime_t ktime = ktime_get();
1054         ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms);
1055
1056         do {
1057                 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
1058
1059                 if (status)
1060                         tegra_i2c_isr(i2c_dev->irq, i2c_dev);
1061
1062                 if (completion_done(complete)) {
1063                         s64 delta = ktime_ms_delta(ktimeout, ktime);
1064
1065                         return msecs_to_jiffies(delta) ?: 1;
1066                 }
1067
1068                 ktime = ktime_get();
1069
1070         } while (ktime_before(ktime, ktimeout));
1071
1072         return 0;
1073 }
1074
1075 static unsigned long
1076 tegra_i2c_wait_completion_timeout(struct tegra_i2c_dev *i2c_dev,
1077                                   struct completion *complete,
1078                                   unsigned int timeout_ms)
1079 {
1080         unsigned long ret;
1081
1082         if (i2c_dev->is_curr_atomic_xfer) {
1083                 ret = tegra_i2c_poll_completion_timeout(i2c_dev, complete,
1084                                                         timeout_ms);
1085         } else {
1086                 enable_irq(i2c_dev->irq);
1087                 ret = wait_for_completion_timeout(complete,
1088                                                   msecs_to_jiffies(timeout_ms));
1089                 disable_irq(i2c_dev->irq);
1090
1091                 /*
1092                  * Under some rare circumstances (like running KASAN +
1093                  * NFS root) CPU, which handles interrupt, may stuck in
1094                  * uninterruptible state for a significant time.  In this
1095                  * case we will get timeout if I2C transfer is running on
1096                  * a sibling CPU, despite of IRQ being raised.
1097                  *
1098                  * In order to handle this rare condition, the IRQ status
1099                  * needs to be checked after timeout.
1100                  */
1101                 if (ret == 0)
1102                         ret = tegra_i2c_poll_completion_timeout(i2c_dev,
1103                                                                 complete, 0);
1104         }
1105
1106         return ret;
1107 }
1108
1109 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
1110 {
1111         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1112         int err;
1113         unsigned long time_left;
1114         u32 reg;
1115
1116         reinit_completion(&i2c_dev->msg_complete);
1117         reg = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND |
1118               I2C_BC_TERMINATE;
1119         i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1120         if (i2c_dev->hw->has_config_load_reg) {
1121                 err = tegra_i2c_wait_for_config_load(i2c_dev);
1122                 if (err)
1123                         return err;
1124         }
1125
1126         reg |= I2C_BC_ENABLE;
1127         i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1128         tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1129
1130         time_left = tegra_i2c_wait_completion_timeout(
1131                         i2c_dev, &i2c_dev->msg_complete, 50);
1132         if (time_left == 0) {
1133                 dev_err(i2c_dev->dev, "timed out for bus clear\n");
1134                 return -ETIMEDOUT;
1135         }
1136
1137         reg = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1138         if (!(reg & I2C_BC_STATUS)) {
1139                 dev_err(i2c_dev->dev,
1140                         "un-recovered arbitration lost\n");
1141                 return -EIO;
1142         }
1143
1144         return -EAGAIN;
1145 }
1146
1147 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1148                               struct i2c_msg *msg,
1149                               enum msg_end_type end_state)
1150 {
1151         u32 packet_header;
1152         u32 int_mask;
1153         unsigned long time_left;
1154         size_t xfer_size;
1155         u32 *buffer = NULL;
1156         int err = 0;
1157         bool dma;
1158         u16 xfer_time = 100;
1159
1160         tegra_i2c_flush_fifos(i2c_dev);
1161
1162         i2c_dev->msg_buf = msg->buf;
1163         i2c_dev->msg_buf_remaining = msg->len;
1164         i2c_dev->msg_err = I2C_ERR_NONE;
1165         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
1166         reinit_completion(&i2c_dev->msg_complete);
1167
1168         if (i2c_dev->msg_read)
1169                 xfer_size = msg->len;
1170         else
1171                 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE;
1172
1173         xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1174         i2c_dev->is_curr_dma_xfer = (xfer_size > I2C_PIO_MODE_PREFERRED_LEN) &&
1175                                     i2c_dev->dma_buf &&
1176                                     !i2c_dev->is_curr_atomic_xfer;
1177         tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1178         dma = i2c_dev->is_curr_dma_xfer;
1179         /*
1180          * Transfer time in mSec = Total bits / transfer rate
1181          * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1182          */
1183         xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1184                                         i2c_dev->bus_clk_rate);
1185
1186         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1187         tegra_i2c_unmask_irq(i2c_dev, int_mask);
1188         if (dma) {
1189                 if (i2c_dev->msg_read) {
1190                         dma_sync_single_for_device(i2c_dev->dev,
1191                                                    i2c_dev->dma_phys,
1192                                                    xfer_size,
1193                                                    DMA_FROM_DEVICE);
1194                         err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1195                         if (err < 0) {
1196                                 dev_err(i2c_dev->dev,
1197                                         "starting RX DMA failed, err %d\n",
1198                                         err);
1199                                 return err;
1200                         }
1201
1202                 } else {
1203                         dma_sync_single_for_cpu(i2c_dev->dev,
1204                                                 i2c_dev->dma_phys,
1205                                                 xfer_size,
1206                                                 DMA_TO_DEVICE);
1207                         buffer = i2c_dev->dma_buf;
1208                 }
1209         }
1210
1211         packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) |
1212                         FIELD_PREP(PACKET_HEADER0_PROTOCOL,
1213                                    PACKET_HEADER0_PROTOCOL_I2C) |
1214                         FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) |
1215                         FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1);
1216         if (dma && !i2c_dev->msg_read)
1217                 *buffer++ = packet_header;
1218         else
1219                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1220
1221         packet_header = msg->len - 1;
1222         if (dma && !i2c_dev->msg_read)
1223                 *buffer++ = packet_header;
1224         else
1225                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1226
1227         packet_header = I2C_HEADER_IE_ENABLE;
1228         if (end_state == MSG_END_CONTINUE)
1229                 packet_header |= I2C_HEADER_CONTINUE_XFER;
1230         else if (end_state == MSG_END_REPEAT_START)
1231                 packet_header |= I2C_HEADER_REPEAT_START;
1232         if (msg->flags & I2C_M_TEN) {
1233                 packet_header |= msg->addr;
1234                 packet_header |= I2C_HEADER_10BIT_ADDR;
1235         } else {
1236                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1237         }
1238         if (msg->flags & I2C_M_IGNORE_NAK)
1239                 packet_header |= I2C_HEADER_CONT_ON_NAK;
1240         if (msg->flags & I2C_M_RD)
1241                 packet_header |= I2C_HEADER_READ;
1242         if (dma && !i2c_dev->msg_read)
1243                 *buffer++ = packet_header;
1244         else
1245                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1246
1247         if (!i2c_dev->msg_read) {
1248                 if (dma) {
1249                         memcpy(buffer, msg->buf, msg->len);
1250                         dma_sync_single_for_device(i2c_dev->dev,
1251                                                    i2c_dev->dma_phys,
1252                                                    xfer_size,
1253                                                    DMA_TO_DEVICE);
1254                         err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1255                         if (err < 0) {
1256                                 dev_err(i2c_dev->dev,
1257                                         "starting TX DMA failed, err %d\n",
1258                                         err);
1259                                 return err;
1260                         }
1261                 } else {
1262                         tegra_i2c_fill_tx_fifo(i2c_dev);
1263                 }
1264         }
1265
1266         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1267                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1268         if (!dma) {
1269                 if (msg->flags & I2C_M_RD)
1270                         int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1271                 else if (i2c_dev->msg_buf_remaining)
1272                         int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1273         }
1274
1275         tegra_i2c_unmask_irq(i2c_dev, int_mask);
1276         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
1277                 i2c_readl(i2c_dev, I2C_INT_MASK));
1278
1279         if (dma) {
1280                 time_left = tegra_i2c_wait_completion_timeout(
1281                                 i2c_dev, &i2c_dev->dma_complete, xfer_time);
1282
1283                 /*
1284                  * Synchronize DMA first, since dmaengine_terminate_sync()
1285                  * performs synchronization after the transfer's termination
1286                  * and we want to get a completion if transfer succeeded.
1287                  */
1288                 dmaengine_synchronize(i2c_dev->msg_read ?
1289                                       i2c_dev->rx_dma_chan :
1290                                       i2c_dev->tx_dma_chan);
1291
1292                 dmaengine_terminate_sync(i2c_dev->msg_read ?
1293                                          i2c_dev->rx_dma_chan :
1294                                          i2c_dev->tx_dma_chan);
1295
1296                 if (!time_left && !completion_done(&i2c_dev->dma_complete)) {
1297                         dev_err(i2c_dev->dev, "DMA transfer timeout\n");
1298                         tegra_i2c_init(i2c_dev, true);
1299                         return -ETIMEDOUT;
1300                 }
1301
1302                 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
1303                         dma_sync_single_for_cpu(i2c_dev->dev,
1304                                                 i2c_dev->dma_phys,
1305                                                 xfer_size,
1306                                                 DMA_FROM_DEVICE);
1307                         memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf,
1308                                msg->len);
1309                 }
1310         }
1311
1312         time_left = tegra_i2c_wait_completion_timeout(
1313                         i2c_dev, &i2c_dev->msg_complete, xfer_time);
1314
1315         tegra_i2c_mask_irq(i2c_dev, int_mask);
1316
1317         if (time_left == 0) {
1318                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
1319                 tegra_i2c_init(i2c_dev, true);
1320                 return -ETIMEDOUT;
1321         }
1322
1323         dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1324                 time_left, completion_done(&i2c_dev->msg_complete),
1325                 i2c_dev->msg_err);
1326
1327         i2c_dev->is_curr_dma_xfer = false;
1328         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
1329                 return 0;
1330
1331         tegra_i2c_init(i2c_dev, true);
1332         /* start recovery upon arbitration loss in single master mode */
1333         if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1334                 if (!i2c_dev->is_multimaster_mode)
1335                         return i2c_recover_bus(&i2c_dev->adapter);
1336                 return -EAGAIN;
1337         }
1338
1339         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1340                 if (msg->flags & I2C_M_IGNORE_NAK)
1341                         return 0;
1342                 return -EREMOTEIO;
1343         }
1344
1345         return -EIO;
1346 }
1347
1348 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1349                           int num)
1350 {
1351         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1352         int i;
1353         int ret;
1354
1355         ret = pm_runtime_get_sync(i2c_dev->dev);
1356         if (ret < 0) {
1357                 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1358                 return ret;
1359         }
1360
1361         for (i = 0; i < num; i++) {
1362                 enum msg_end_type end_type = MSG_END_STOP;
1363
1364                 if (i < (num - 1)) {
1365                         if (msgs[i + 1].flags & I2C_M_NOSTART)
1366                                 end_type = MSG_END_CONTINUE;
1367                         else
1368                                 end_type = MSG_END_REPEAT_START;
1369                 }
1370                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1371                 if (ret)
1372                         break;
1373         }
1374
1375         pm_runtime_put(i2c_dev->dev);
1376
1377         return ret ?: i;
1378 }
1379
1380 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap,
1381                                  struct i2c_msg msgs[], int num)
1382 {
1383         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1384         int ret;
1385
1386         i2c_dev->is_curr_atomic_xfer = true;
1387         ret = tegra_i2c_xfer(adap, msgs, num);
1388         i2c_dev->is_curr_atomic_xfer = false;
1389
1390         return ret;
1391 }
1392
1393 static u32 tegra_i2c_func(struct i2c_adapter *adap)
1394 {
1395         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1396         u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
1397                   I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
1398
1399         if (i2c_dev->hw->has_continue_xfer_support)
1400                 ret |= I2C_FUNC_NOSTART;
1401         return ret;
1402 }
1403
1404 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
1405 {
1406         struct device_node *np = i2c_dev->dev->of_node;
1407         int ret;
1408         bool multi_mode;
1409
1410         ret = of_property_read_u32(np, "clock-frequency",
1411                                    &i2c_dev->bus_clk_rate);
1412         if (ret)
1413                 i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */
1414
1415         multi_mode = of_property_read_bool(np, "multi-master");
1416         i2c_dev->is_multimaster_mode = multi_mode;
1417 }
1418
1419 static const struct i2c_algorithm tegra_i2c_algo = {
1420         .master_xfer            = tegra_i2c_xfer,
1421         .master_xfer_atomic     = tegra_i2c_xfer_atomic,
1422         .functionality          = tegra_i2c_func,
1423 };
1424
1425 /* payload size is only 12 bit */
1426 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
1427         .flags = I2C_AQ_NO_ZERO_LEN,
1428         .max_read_len = SZ_4K,
1429         .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1430 };
1431
1432 static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
1433         .flags = I2C_AQ_NO_ZERO_LEN,
1434         .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1435 };
1436
1437 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1438         .recover_bus = tegra_i2c_issue_bus_clear,
1439 };
1440
1441 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
1442         .has_continue_xfer_support = false,
1443         .has_per_pkt_xfer_complete_irq = false,
1444         .has_single_clk_source = false,
1445         .clk_divisor_hs_mode = 3,
1446         .clk_divisor_std_mode = 0,
1447         .clk_divisor_fast_mode = 0,
1448         .clk_divisor_fast_plus_mode = 0,
1449         .has_config_load_reg = false,
1450         .has_multi_master_mode = false,
1451         .has_slcg_override_reg = false,
1452         .has_mst_fifo = false,
1453         .quirks = &tegra_i2c_quirks,
1454         .supports_bus_clear = false,
1455         .has_apb_dma = true,
1456         .tlow_std_mode = 0x4,
1457         .thigh_std_mode = 0x2,
1458         .tlow_fast_fastplus_mode = 0x4,
1459         .thigh_fast_fastplus_mode = 0x2,
1460         .setup_hold_time_std_mode = 0x0,
1461         .setup_hold_time_fast_fast_plus_mode = 0x0,
1462         .setup_hold_time_hs_mode = 0x0,
1463         .has_interface_timing_reg = false,
1464 };
1465
1466 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
1467         .has_continue_xfer_support = true,
1468         .has_per_pkt_xfer_complete_irq = false,
1469         .has_single_clk_source = false,
1470         .clk_divisor_hs_mode = 3,
1471         .clk_divisor_std_mode = 0,
1472         .clk_divisor_fast_mode = 0,
1473         .clk_divisor_fast_plus_mode = 0,
1474         .has_config_load_reg = false,
1475         .has_multi_master_mode = false,
1476         .has_slcg_override_reg = false,
1477         .has_mst_fifo = false,
1478         .quirks = &tegra_i2c_quirks,
1479         .supports_bus_clear = false,
1480         .has_apb_dma = true,
1481         .tlow_std_mode = 0x4,
1482         .thigh_std_mode = 0x2,
1483         .tlow_fast_fastplus_mode = 0x4,
1484         .thigh_fast_fastplus_mode = 0x2,
1485         .setup_hold_time_std_mode = 0x0,
1486         .setup_hold_time_fast_fast_plus_mode = 0x0,
1487         .setup_hold_time_hs_mode = 0x0,
1488         .has_interface_timing_reg = false,
1489 };
1490
1491 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
1492         .has_continue_xfer_support = true,
1493         .has_per_pkt_xfer_complete_irq = true,
1494         .has_single_clk_source = true,
1495         .clk_divisor_hs_mode = 1,
1496         .clk_divisor_std_mode = 0x19,
1497         .clk_divisor_fast_mode = 0x19,
1498         .clk_divisor_fast_plus_mode = 0x10,
1499         .has_config_load_reg = false,
1500         .has_multi_master_mode = false,
1501         .has_slcg_override_reg = false,
1502         .has_mst_fifo = false,
1503         .quirks = &tegra_i2c_quirks,
1504         .supports_bus_clear = true,
1505         .has_apb_dma = true,
1506         .tlow_std_mode = 0x4,
1507         .thigh_std_mode = 0x2,
1508         .tlow_fast_fastplus_mode = 0x4,
1509         .thigh_fast_fastplus_mode = 0x2,
1510         .setup_hold_time_std_mode = 0x0,
1511         .setup_hold_time_fast_fast_plus_mode = 0x0,
1512         .setup_hold_time_hs_mode = 0x0,
1513         .has_interface_timing_reg = false,
1514 };
1515
1516 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
1517         .has_continue_xfer_support = true,
1518         .has_per_pkt_xfer_complete_irq = true,
1519         .has_single_clk_source = true,
1520         .clk_divisor_hs_mode = 1,
1521         .clk_divisor_std_mode = 0x19,
1522         .clk_divisor_fast_mode = 0x19,
1523         .clk_divisor_fast_plus_mode = 0x10,
1524         .has_config_load_reg = true,
1525         .has_multi_master_mode = false,
1526         .has_slcg_override_reg = true,
1527         .has_mst_fifo = false,
1528         .quirks = &tegra_i2c_quirks,
1529         .supports_bus_clear = true,
1530         .has_apb_dma = true,
1531         .tlow_std_mode = 0x4,
1532         .thigh_std_mode = 0x2,
1533         .tlow_fast_fastplus_mode = 0x4,
1534         .thigh_fast_fastplus_mode = 0x2,
1535         .setup_hold_time_std_mode = 0x0,
1536         .setup_hold_time_fast_fast_plus_mode = 0x0,
1537         .setup_hold_time_hs_mode = 0x0,
1538         .has_interface_timing_reg = true,
1539 };
1540
1541 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
1542         .has_continue_xfer_support = true,
1543         .has_per_pkt_xfer_complete_irq = true,
1544         .has_single_clk_source = true,
1545         .clk_divisor_hs_mode = 1,
1546         .clk_divisor_std_mode = 0x19,
1547         .clk_divisor_fast_mode = 0x19,
1548         .clk_divisor_fast_plus_mode = 0x10,
1549         .has_config_load_reg = true,
1550         .has_multi_master_mode = false,
1551         .has_slcg_override_reg = true,
1552         .has_mst_fifo = false,
1553         .quirks = &tegra_i2c_quirks,
1554         .supports_bus_clear = true,
1555         .has_apb_dma = true,
1556         .tlow_std_mode = 0x4,
1557         .thigh_std_mode = 0x2,
1558         .tlow_fast_fastplus_mode = 0x4,
1559         .thigh_fast_fastplus_mode = 0x2,
1560         .setup_hold_time_std_mode = 0,
1561         .setup_hold_time_fast_fast_plus_mode = 0,
1562         .setup_hold_time_hs_mode = 0,
1563         .has_interface_timing_reg = true,
1564 };
1565
1566 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
1567         .has_continue_xfer_support = true,
1568         .has_per_pkt_xfer_complete_irq = true,
1569         .has_single_clk_source = true,
1570         .clk_divisor_hs_mode = 1,
1571         .clk_divisor_std_mode = 0x16,
1572         .clk_divisor_fast_mode = 0x19,
1573         .clk_divisor_fast_plus_mode = 0x10,
1574         .has_config_load_reg = true,
1575         .has_multi_master_mode = false,
1576         .has_slcg_override_reg = true,
1577         .has_mst_fifo = false,
1578         .quirks = &tegra_i2c_quirks,
1579         .supports_bus_clear = true,
1580         .has_apb_dma = false,
1581         .tlow_std_mode = 0x4,
1582         .thigh_std_mode = 0x3,
1583         .tlow_fast_fastplus_mode = 0x4,
1584         .thigh_fast_fastplus_mode = 0x2,
1585         .setup_hold_time_std_mode = 0,
1586         .setup_hold_time_fast_fast_plus_mode = 0,
1587         .setup_hold_time_hs_mode = 0,
1588         .has_interface_timing_reg = true,
1589 };
1590
1591 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
1592         .has_continue_xfer_support = true,
1593         .has_per_pkt_xfer_complete_irq = true,
1594         .has_single_clk_source = true,
1595         .clk_divisor_hs_mode = 1,
1596         .clk_divisor_std_mode = 0x4f,
1597         .clk_divisor_fast_mode = 0x3c,
1598         .clk_divisor_fast_plus_mode = 0x16,
1599         .has_config_load_reg = true,
1600         .has_multi_master_mode = true,
1601         .has_slcg_override_reg = true,
1602         .has_mst_fifo = true,
1603         .quirks = &tegra194_i2c_quirks,
1604         .supports_bus_clear = true,
1605         .has_apb_dma = false,
1606         .tlow_std_mode = 0x8,
1607         .thigh_std_mode = 0x7,
1608         .tlow_fast_fastplus_mode = 0x2,
1609         .thigh_fast_fastplus_mode = 0x2,
1610         .setup_hold_time_std_mode = 0x08080808,
1611         .setup_hold_time_fast_fast_plus_mode = 0x02020202,
1612         .setup_hold_time_hs_mode = 0x090909,
1613         .has_interface_timing_reg = true,
1614 };
1615
1616 /* Match table for of_platform binding */
1617 static const struct of_device_id tegra_i2c_of_match[] = {
1618         { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1619         { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1620         { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
1621         { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1622         { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1623         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1624         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1625         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1626         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1627         {},
1628 };
1629 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1630
1631 static int tegra_i2c_probe(struct platform_device *pdev)
1632 {
1633         struct device *dev = &pdev->dev;
1634         struct tegra_i2c_dev *i2c_dev;
1635         struct resource *res;
1636         struct clk *div_clk;
1637         struct clk *fast_clk;
1638         void __iomem *base;
1639         phys_addr_t base_phys;
1640         int irq;
1641         int ret;
1642
1643         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1644         base_phys = res->start;
1645         base = devm_ioremap_resource(&pdev->dev, res);
1646         if (IS_ERR(base))
1647                 return PTR_ERR(base);
1648
1649         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1650         if (!res) {
1651                 dev_err(&pdev->dev, "no irq resource\n");
1652                 return -EINVAL;
1653         }
1654         irq = res->start;
1655
1656         div_clk = devm_clk_get(&pdev->dev, "div-clk");
1657         if (IS_ERR(div_clk)) {
1658                 if (PTR_ERR(div_clk) != -EPROBE_DEFER)
1659                         dev_err(&pdev->dev, "missing controller clock\n");
1660
1661                 return PTR_ERR(div_clk);
1662         }
1663
1664         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1665         if (!i2c_dev)
1666                 return -ENOMEM;
1667
1668         i2c_dev->base = base;
1669         i2c_dev->base_phys = base_phys;
1670         i2c_dev->div_clk = div_clk;
1671         i2c_dev->adapter.algo = &tegra_i2c_algo;
1672         i2c_dev->adapter.retries = 1;
1673         i2c_dev->adapter.timeout = 6 * HZ;
1674         i2c_dev->irq = irq;
1675         i2c_dev->cont_id = pdev->id;
1676         i2c_dev->dev = &pdev->dev;
1677
1678         i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c");
1679         if (IS_ERR(i2c_dev->rst)) {
1680                 dev_err(&pdev->dev, "missing controller reset\n");
1681                 return PTR_ERR(i2c_dev->rst);
1682         }
1683
1684         tegra_i2c_parse_dt(i2c_dev);
1685
1686         i2c_dev->hw = of_device_get_match_data(&pdev->dev);
1687         i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
1688                                                   "nvidia,tegra20-i2c-dvc");
1689         i2c_dev->is_vi = of_device_is_compatible(dev->of_node,
1690                                                  "nvidia,tegra210-i2c-vi");
1691         i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1692         i2c_dev->dma_buf_size = i2c_dev->adapter.quirks->max_write_len +
1693                                 I2C_PACKET_HEADER_SIZE;
1694         init_completion(&i2c_dev->msg_complete);
1695         init_completion(&i2c_dev->dma_complete);
1696
1697         if (!i2c_dev->hw->has_single_clk_source) {
1698                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
1699                 if (IS_ERR(fast_clk)) {
1700                         dev_err(&pdev->dev, "missing fast clock\n");
1701                         return PTR_ERR(fast_clk);
1702                 }
1703                 i2c_dev->fast_clk = fast_clk;
1704         }
1705
1706         if (i2c_dev->is_vi) {
1707                 i2c_dev->slow_clk = devm_clk_get(dev, "slow");
1708                 if (IS_ERR(i2c_dev->slow_clk)) {
1709                         if (PTR_ERR(i2c_dev->slow_clk) != -EPROBE_DEFER)
1710                                 dev_err(dev, "failed to get slow clock: %ld\n",
1711                                         PTR_ERR(i2c_dev->slow_clk));
1712
1713                         return PTR_ERR(i2c_dev->slow_clk);
1714                 }
1715         }
1716
1717         platform_set_drvdata(pdev, i2c_dev);
1718
1719         if (!i2c_dev->hw->has_single_clk_source) {
1720                 ret = clk_prepare(i2c_dev->fast_clk);
1721                 if (ret < 0) {
1722                         dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1723                         return ret;
1724                 }
1725         }
1726
1727         if (i2c_dev->slow_clk) {
1728                 ret = clk_prepare(i2c_dev->slow_clk);
1729                 if (ret < 0) {
1730                         dev_err(dev, "failed to prepare slow clock: %d\n", ret);
1731                         goto unprepare_fast_clk;
1732                 }
1733         }
1734
1735         if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ &&
1736             i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_PLUS_FREQ)
1737                 i2c_dev->clk_divisor_non_hs_mode =
1738                                 i2c_dev->hw->clk_divisor_fast_plus_mode;
1739         else if (i2c_dev->bus_clk_rate > I2C_MAX_STANDARD_MODE_FREQ &&
1740                  i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_FREQ)
1741                 i2c_dev->clk_divisor_non_hs_mode =
1742                                 i2c_dev->hw->clk_divisor_fast_mode;
1743         else
1744                 i2c_dev->clk_divisor_non_hs_mode =
1745                                 i2c_dev->hw->clk_divisor_std_mode;
1746
1747         ret = clk_prepare(i2c_dev->div_clk);
1748         if (ret < 0) {
1749                 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1750                 goto unprepare_slow_clk;
1751         }
1752
1753         pm_runtime_irq_safe(&pdev->dev);
1754         pm_runtime_enable(&pdev->dev);
1755         if (!pm_runtime_enabled(&pdev->dev)) {
1756                 ret = tegra_i2c_runtime_resume(&pdev->dev);
1757                 if (ret < 0) {
1758                         dev_err(&pdev->dev, "runtime resume failed\n");
1759                         goto unprepare_div_clk;
1760                 }
1761         } else {
1762                 ret = pm_runtime_get_sync(i2c_dev->dev);
1763                 if (ret < 0) {
1764                         dev_err(&pdev->dev, "runtime resume failed\n");
1765                         goto disable_rpm;
1766                 }
1767         }
1768
1769         if (i2c_dev->is_multimaster_mode) {
1770                 ret = clk_enable(i2c_dev->div_clk);
1771                 if (ret < 0) {
1772                         dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
1773                                 ret);
1774                         goto put_rpm;
1775                 }
1776         }
1777
1778         if (i2c_dev->hw->supports_bus_clear)
1779                 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
1780
1781         ret = tegra_i2c_init_dma(i2c_dev);
1782         if (ret < 0)
1783                 goto disable_div_clk;
1784
1785         ret = tegra_i2c_init(i2c_dev, false);
1786         if (ret) {
1787                 dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
1788                 goto release_dma;
1789         }
1790
1791         irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
1792
1793         ret = devm_request_irq(&pdev->dev, i2c_dev->irq, tegra_i2c_isr,
1794                                IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c_dev);
1795         if (ret) {
1796                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
1797                 goto release_dma;
1798         }
1799
1800         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1801         i2c_dev->adapter.owner = THIS_MODULE;
1802         i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1803         strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
1804                 sizeof(i2c_dev->adapter.name));
1805         i2c_dev->adapter.dev.parent = &pdev->dev;
1806         i2c_dev->adapter.nr = pdev->id;
1807         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1808
1809         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1810         if (ret)
1811                 goto release_dma;
1812
1813         pm_runtime_put(&pdev->dev);
1814
1815         return 0;
1816
1817 release_dma:
1818         tegra_i2c_release_dma(i2c_dev);
1819
1820 disable_div_clk:
1821         if (i2c_dev->is_multimaster_mode)
1822                 clk_disable(i2c_dev->div_clk);
1823
1824 put_rpm:
1825         if (pm_runtime_enabled(&pdev->dev))
1826                 pm_runtime_put_sync(&pdev->dev);
1827         else
1828                 tegra_i2c_runtime_suspend(&pdev->dev);
1829
1830 disable_rpm:
1831         if (pm_runtime_enabled(&pdev->dev))
1832                 pm_runtime_disable(&pdev->dev);
1833
1834 unprepare_div_clk:
1835         clk_unprepare(i2c_dev->div_clk);
1836
1837 unprepare_slow_clk:
1838         if (i2c_dev->is_vi)
1839                 clk_unprepare(i2c_dev->slow_clk);
1840
1841 unprepare_fast_clk:
1842         if (!i2c_dev->hw->has_single_clk_source)
1843                 clk_unprepare(i2c_dev->fast_clk);
1844
1845         return ret;
1846 }
1847
1848 static int tegra_i2c_remove(struct platform_device *pdev)
1849 {
1850         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1851
1852         i2c_del_adapter(&i2c_dev->adapter);
1853
1854         if (i2c_dev->is_multimaster_mode)
1855                 clk_disable(i2c_dev->div_clk);
1856
1857         pm_runtime_disable(&pdev->dev);
1858         if (!pm_runtime_status_suspended(&pdev->dev))
1859                 tegra_i2c_runtime_suspend(&pdev->dev);
1860
1861         clk_unprepare(i2c_dev->div_clk);
1862
1863         if (i2c_dev->slow_clk)
1864                 clk_unprepare(i2c_dev->slow_clk);
1865
1866         if (!i2c_dev->hw->has_single_clk_source)
1867                 clk_unprepare(i2c_dev->fast_clk);
1868
1869         tegra_i2c_release_dma(i2c_dev);
1870         return 0;
1871 }
1872
1873 static int __maybe_unused tegra_i2c_suspend(struct device *dev)
1874 {
1875         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1876         int err = 0;
1877
1878         i2c_mark_adapter_suspended(&i2c_dev->adapter);
1879
1880         if (!pm_runtime_status_suspended(dev))
1881                 err = tegra_i2c_runtime_suspend(dev);
1882
1883         return err;
1884 }
1885
1886 static int __maybe_unused tegra_i2c_resume(struct device *dev)
1887 {
1888         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1889         int err;
1890
1891         /*
1892          * We need to ensure that clocks are enabled so that registers can be
1893          * restored in tegra_i2c_init().
1894          */
1895         err = tegra_i2c_runtime_resume(dev);
1896         if (err)
1897                 return err;
1898
1899         err = tegra_i2c_init(i2c_dev, false);
1900         if (err)
1901                 return err;
1902
1903         /*
1904          * In case we are runtime suspended, disable clocks again so that we
1905          * don't unbalance the clock reference counts during the next runtime
1906          * resume transition.
1907          */
1908         if (pm_runtime_status_suspended(dev)) {
1909                 err = tegra_i2c_runtime_suspend(dev);
1910                 if (err)
1911                         return err;
1912         }
1913
1914         i2c_mark_adapter_resumed(&i2c_dev->adapter);
1915
1916         return 0;
1917 }
1918
1919 static const struct dev_pm_ops tegra_i2c_pm = {
1920         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
1921         SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1922                            NULL)
1923 };
1924
1925 static struct platform_driver tegra_i2c_driver = {
1926         .probe   = tegra_i2c_probe,
1927         .remove  = tegra_i2c_remove,
1928         .driver  = {
1929                 .name  = "tegra-i2c",
1930                 .of_match_table = tegra_i2c_of_match,
1931                 .pm    = &tegra_i2c_pm,
1932         },
1933 };
1934
1935 module_platform_driver(tegra_i2c_driver);
1936
1937 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1938 MODULE_AUTHOR("Colin Cross");
1939 MODULE_LICENSE("GPL v2");