drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/err.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/of_device.h>
  29 #include <linux/module.h>
  30 #include <linux/reset.h>
  31 #include <linux/pinctrl/consumer.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/iopoll.h>
  34
  35 #include <asm/unaligned.h>
  36
  37 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  38 #define BYTES_PER_FIFO_WORD 4
  39
  40 #define I2C_CNFG                                0x000
  41 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  42 #define I2C_CNFG_PACKET_MODE_EN                 BIT(10)
  43 #define I2C_CNFG_NEW_MASTER_FSM                 BIT(11)
  44 #define I2C_CNFG_MULTI_MASTER_MODE              BIT(17)
  45 #define I2C_STATUS                              0x01C
  46 #define I2C_SL_CNFG                             0x020
  47 #define I2C_SL_CNFG_NACK                        BIT(1)
  48 #define I2C_SL_CNFG_NEWSL                       BIT(2)
  49 #define I2C_SL_ADDR1                            0x02c
  50 #define I2C_SL_ADDR2                            0x030
  51 #define I2C_TX_FIFO                             0x050
  52 #define I2C_RX_FIFO                             0x054
  53 #define I2C_PACKET_TRANSFER_STATUS              0x058
  54 #define I2C_FIFO_CONTROL                        0x05c
  55 #define I2C_FIFO_CONTROL_TX_FLUSH               BIT(1)
  56 #define I2C_FIFO_CONTROL_RX_FLUSH               BIT(0)
  57 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  58 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  59 #define I2C_FIFO_STATUS                         0x060
  60 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  61 #define I2C_FIFO_STATUS_TX_SHIFT                4
  62 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  63 #define I2C_FIFO_STATUS_RX_SHIFT                0
  64 #define I2C_INT_MASK                            0x064
  65 #define I2C_INT_STATUS                          0x068
  66 #define I2C_INT_PACKET_XFER_COMPLETE            BIT(7)
  67 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       BIT(6)
  68 #define I2C_INT_TX_FIFO_OVERFLOW                BIT(5)
  69 #define I2C_INT_RX_FIFO_UNDERFLOW               BIT(4)
  70 #define I2C_INT_NO_ACK                          BIT(3)
  71 #define I2C_INT_ARBITRATION_LOST                BIT(2)
  72 #define I2C_INT_TX_FIFO_DATA_REQ                BIT(1)
  73 #define I2C_INT_RX_FIFO_DATA_REQ                BIT(0)
  74 #define I2C_CLK_DIVISOR                         0x06c
  75 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
  76 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
  77
  78 #define DVC_CTRL_REG1                           0x000
  79 #define DVC_CTRL_REG1_INTR_EN                   BIT(10)
  80 #define DVC_CTRL_REG2                           0x004
  81 #define DVC_CTRL_REG3                           0x008
  82 #define DVC_CTRL_REG3_SW_PROG                   BIT(26)
  83 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          BIT(30)
  84 #define DVC_STATUS                              0x00c
  85 #define DVC_STATUS_I2C_DONE_INTR                BIT(30)
  86
  87 #define I2C_ERR_NONE                            0x00
  88 #define I2C_ERR_NO_ACK                          0x01
  89 #define I2C_ERR_ARBITRATION_LOST                0x02
  90 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  91
  92 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  93 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  94 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  95 #define PACKET_HEADER0_PROTOCOL_I2C             BIT(4)
  96
  97 #define I2C_HEADER_HIGHSPEED_MODE               BIT(22)
  98 #define I2C_HEADER_CONT_ON_NAK                  BIT(21)
  99 #define I2C_HEADER_SEND_START_BYTE              BIT(20)
 100 #define I2C_HEADER_READ                         BIT(19)
 101 #define I2C_HEADER_10BIT_ADDR                   BIT(18)
 102 #define I2C_HEADER_IE_ENABLE                    BIT(17)
 103 #define I2C_HEADER_REPEAT_START                 BIT(16)
 104 #define I2C_HEADER_CONTINUE_XFER                BIT(15)
 105 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
 106 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 107
 108 #define I2C_CONFIG_LOAD                         0x08C
 109 #define I2C_MSTR_CONFIG_LOAD                    BIT(0)
 110 #define I2C_SLV_CONFIG_LOAD                     BIT(1)
 111 #define I2C_TIMEOUT_CONFIG_LOAD                 BIT(2)
 112
 113 #define I2C_CLKEN_OVERRIDE                      0x090
 114 #define I2C_MST_CORE_CLKEN_OVR                  BIT(0)
 115
 116 #define I2C_CONFIG_LOAD_TIMEOUT                 1000000
 117
 118 #define I2C_MST_FIFO_CONTROL                    0x0b4
 119 #define I2C_MST_FIFO_CONTROL_RX_FLUSH           BIT(0)
 120 #define I2C_MST_FIFO_CONTROL_TX_FLUSH           BIT(1)
 121 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x)         (((x) - 1) <<  4)
 122 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x)         (((x) - 1) << 16)
 123
 124 #define I2C_MST_FIFO_STATUS                     0x0b8
 125 #define I2C_MST_FIFO_STATUS_RX_MASK             0xff
 126 #define I2C_MST_FIFO_STATUS_RX_SHIFT            0
 127 #define I2C_MST_FIFO_STATUS_TX_MASK             0xff0000
 128 #define I2C_MST_FIFO_STATUS_TX_SHIFT            16
 129
 130 /*
 131  * msg_end_type: The bus control which need to be send at end of transfer.
 132  * @MSG_END_STOP: Send stop pulse at end of transfer.
 133  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 134  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 135  *              stop or repeat start.
 136  */
 137 enum msg_end_type {
 138         MSG_END_STOP,
 139         MSG_END_REPEAT_START,
 140         MSG_END_CONTINUE,
 141 };
 142
 143 /**
 144  * struct tegra_i2c_hw_feature : Different HW support on Tegra
 145  * @has_continue_xfer_support: Continue transfer supports.
 146  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 147  *              complete interrupt per packet basis.
 148  * @has_single_clk_source: The i2c controller has single clock source. Tegra30
 149  *              and earlier Socs has two clock sources i.e. div-clk and
 150  *              fast-clk.
 151  * @has_config_load_reg: Has the config load register to load the new
 152  *              configuration.
 153  * @clk_divisor_hs_mode: Clock divisor in HS mode.
 154  * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
 155  *              applicable if there is no fast clock source i.e. single clock
 156  *              source.
 157  */
 158
 159 struct tegra_i2c_hw_feature {
 160         bool has_continue_xfer_support;
 161         bool has_per_pkt_xfer_complete_irq;
 162         bool has_single_clk_source;
 163         bool has_config_load_reg;
 164         int clk_divisor_hs_mode;
 165         int clk_divisor_std_fast_mode;
 166         u16 clk_divisor_fast_plus_mode;
 167         bool has_multi_master_mode;
 168         bool has_slcg_override_reg;
 169         bool has_mst_fifo;
 170 };
 171
 172 /**
 173  * struct tegra_i2c_dev - per device i2c context
 174  * @dev: device reference for power management
 175  * @hw: Tegra i2c hw feature.
 176  * @adapter: core i2c layer adapter information
 177  * @div_clk: clock reference for div clock of i2c controller.
 178  * @fast_clk: clock reference for fast clock of i2c controller.
 179  * @base: ioremapped registers cookie
 180  * @cont_id: i2c controller id, used for for packet header
 181  * @irq: irq number of transfer complete interrupt
 182  * @is_dvc: identifies the DVC i2c controller, has a different register layout
 183  * @msg_complete: transfer completion notifier
 184  * @msg_err: error code for completed message
 185  * @msg_buf: pointer to current message data
 186  * @msg_buf_remaining: size of unsent data in the message buffer
 187  * @msg_read: identifies read transfers
 188  * @bus_clk_rate: current i2c bus clock rate
 189  */
 190 struct tegra_i2c_dev {
 191         struct device *dev;
 192         const struct tegra_i2c_hw_feature *hw;
 193         struct i2c_adapter adapter;
 194         struct clk *div_clk;
 195         struct clk *fast_clk;
 196         struct reset_control *rst;
 197         void __iomem *base;
 198         int cont_id;
 199         int irq;
 200         bool irq_disabled;
 201         int is_dvc;
 202         struct completion msg_complete;
 203         int msg_err;
 204         u8 *msg_buf;
 205         size_t msg_buf_remaining;
 206         int msg_read;
 207         u32 bus_clk_rate;
 208         u16 clk_divisor_non_hs_mode;
 209         bool is_multimaster_mode;
 210         spinlock_t xfer_lock;
 211 };
 212
 213 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 214                        unsigned long reg)
 215 {
 216         writel(val, i2c_dev->base + reg);
 217 }
 218
 219 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 220 {
 221         return readl(i2c_dev->base + reg);
 222 }
 223
 224 /*
 225  * i2c_writel and i2c_readl will offset the register if necessary to talk
 226  * to the I2C block inside the DVC block
 227  */
 228 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 229         unsigned long reg)
 230 {
 231         if (i2c_dev->is_dvc)
 232                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 233         return reg;
 234 }
 235
 236 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 237         unsigned long reg)
 238 {
 239         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 240
 241         /* Read back register to make sure that register writes completed */
 242         if (reg != I2C_TX_FIFO)
 243                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 244 }
 245
 246 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 247 {
 248         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 249 }
 250
 251 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 252         unsigned long reg, int len)
 253 {
 254         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 255 }
 256
 257 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 258         unsigned long reg, int len)
 259 {
 260         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 261 }
 262
 263 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 264 {
 265         u32 int_mask;
 266
 267         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
 268         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 269 }
 270
 271 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 272 {
 273         u32 int_mask;
 274
 275         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
 276         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 277 }
 278
 279 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 280 {
 281         unsigned long timeout = jiffies + HZ;
 282         unsigned int offset;
 283         u32 mask, val;
 284
 285         if (i2c_dev->hw->has_mst_fifo) {
 286                 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
 287                        I2C_MST_FIFO_CONTROL_RX_FLUSH;
 288                 offset = I2C_MST_FIFO_CONTROL;
 289         } else {
 290                 mask = I2C_FIFO_CONTROL_TX_FLUSH |
 291                        I2C_FIFO_CONTROL_RX_FLUSH;
 292                 offset = I2C_FIFO_CONTROL;
 293         }
 294
 295         val = i2c_readl(i2c_dev, offset);
 296         val |= mask;
 297         i2c_writel(i2c_dev, val, offset);
 298
 299         while (i2c_readl(i2c_dev, offset) & mask) {
 300                 if (time_after(jiffies, timeout)) {
 301                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 302                         return -ETIMEDOUT;
 303                 }
 304                 msleep(1);
 305         }
 306         return 0;
 307 }
 308
 309 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 310 {
 311         u32 val;
 312         int rx_fifo_avail;
 313         u8 *buf = i2c_dev->msg_buf;
 314         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 315         int words_to_transfer;
 316
 317         if (i2c_dev->hw->has_mst_fifo) {
 318                 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 319                 rx_fifo_avail = (val & I2C_MST_FIFO_STATUS_RX_MASK) >>
 320                         I2C_MST_FIFO_STATUS_RX_SHIFT;
 321         } else {
 322                 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 323                 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 324                         I2C_FIFO_STATUS_RX_SHIFT;
 325         }
 326
 327         /* Rounds down to not include partial word at the end of buf */
 328         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 329         if (words_to_transfer > rx_fifo_avail)
 330                 words_to_transfer = rx_fifo_avail;
 331
 332         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 333
 334         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 335         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 336         rx_fifo_avail -= words_to_transfer;
 337
 338         /*
 339          * If there is a partial word at the end of buf, handle it manually to
 340          * prevent overwriting past the end of buf
 341          */
 342         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 343                 BUG_ON(buf_remaining > 3);
 344                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 345                 val = cpu_to_le32(val);
 346                 memcpy(buf, &val, buf_remaining);
 347                 buf_remaining = 0;
 348                 rx_fifo_avail--;
 349         }
 350
 351         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 352         i2c_dev->msg_buf_remaining = buf_remaining;
 353         i2c_dev->msg_buf = buf;
 354
 355         return 0;
 356 }
 357
 358 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 359 {
 360         u32 val;
 361         int tx_fifo_avail;
 362         u8 *buf = i2c_dev->msg_buf;
 363         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 364         int words_to_transfer;
 365
 366         if (i2c_dev->hw->has_mst_fifo) {
 367                 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 368                 tx_fifo_avail = (val & I2C_MST_FIFO_STATUS_TX_MASK) >>
 369                         I2C_MST_FIFO_STATUS_TX_SHIFT;
 370         } else {
 371                 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 372                 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 373                         I2C_FIFO_STATUS_TX_SHIFT;
 374         }
 375
 376         /* Rounds down to not include partial word at the end of buf */
 377         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 378
 379         /* It's very common to have < 4 bytes, so optimize that case. */
 380         if (words_to_transfer) {
 381                 if (words_to_transfer > tx_fifo_avail)
 382                         words_to_transfer = tx_fifo_avail;
 383
 384                 /*
 385                  * Update state before writing to FIFO.  If this casues us
 386                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 387                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 388                  * not maskable).  We need to make sure that the isr sees
 389                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 390                  */
 391                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 392                 tx_fifo_avail -= words_to_transfer;
 393                 i2c_dev->msg_buf_remaining = buf_remaining;
 394                 i2c_dev->msg_buf = buf +
 395                         words_to_transfer * BYTES_PER_FIFO_WORD;
 396                 barrier();
 397
 398                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 399
 400                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 401         }
 402
 403         /*
 404          * If there is a partial word at the end of buf, handle it manually to
 405          * prevent reading past the end of buf, which could cross a page
 406          * boundary and fault.
 407          */
 408         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 409                 BUG_ON(buf_remaining > 3);
 410                 memcpy(&val, buf, buf_remaining);
 411                 val = le32_to_cpu(val);
 412
 413                 /* Again update before writing to FIFO to make sure isr sees. */
 414                 i2c_dev->msg_buf_remaining = 0;
 415                 i2c_dev->msg_buf = NULL;
 416                 barrier();
 417
 418                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 419         }
 420
 421         return 0;
 422 }
 423
 424 /*
 425  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 426  * block.  This block is identical to the rest of the I2C blocks, except that
 427  * it only supports master mode, it has registers moved around, and it needs
 428  * some extra init to get it into I2C mode.  The register moves are handled
 429  * by i2c_readl and i2c_writel
 430  */
 431 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 432 {
 433         u32 val;
 434
 435         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 436         val |= DVC_CTRL_REG3_SW_PROG;
 437         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 438         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 439
 440         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 441         val |= DVC_CTRL_REG1_INTR_EN;
 442         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 443 }
 444
 445 static int tegra_i2c_runtime_resume(struct device *dev)
 446 {
 447         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 448         int ret;
 449
 450         ret = pinctrl_pm_select_default_state(i2c_dev->dev);
 451         if (ret)
 452                 return ret;
 453
 454         if (!i2c_dev->hw->has_single_clk_source) {
 455                 ret = clk_enable(i2c_dev->fast_clk);
 456                 if (ret < 0) {
 457                         dev_err(i2c_dev->dev,
 458                                 "Enabling fast clk failed, err %d\n", ret);
 459                         return ret;
 460                 }
 461         }
 462
 463         ret = clk_enable(i2c_dev->div_clk);
 464         if (ret < 0) {
 465                 dev_err(i2c_dev->dev,
 466                         "Enabling div clk failed, err %d\n", ret);
 467                 clk_disable(i2c_dev->fast_clk);
 468                 return ret;
 469         }
 470
 471         return 0;
 472 }
 473
 474 static int tegra_i2c_runtime_suspend(struct device *dev)
 475 {
 476         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 477
 478         clk_disable(i2c_dev->div_clk);
 479         if (!i2c_dev->hw->has_single_clk_source)
 480                 clk_disable(i2c_dev->fast_clk);
 481
 482         return pinctrl_pm_select_idle_state(i2c_dev->dev);
 483 }
 484
 485 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
 486 {
 487         unsigned long reg_offset;
 488         void __iomem *addr;
 489         u32 val;
 490         int err;
 491
 492         if (i2c_dev->hw->has_config_load_reg) {
 493                 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
 494                 addr = i2c_dev->base + reg_offset;
 495                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 496                 if (in_interrupt())
 497                         err = readl_poll_timeout_atomic(addr, val, val == 0,
 498                                         1000, I2C_CONFIG_LOAD_TIMEOUT);
 499                 else
 500                         err = readl_poll_timeout(addr, val, val == 0,
 501                                         1000, I2C_CONFIG_LOAD_TIMEOUT);
 502
 503                 if (err) {
 504                         dev_warn(i2c_dev->dev,
 505                                  "timeout waiting for config load\n");
 506                         return err;
 507                 }
 508         }
 509
 510         return 0;
 511 }
 512
 513 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 514 {
 515         u32 val;
 516         int err;
 517         u32 clk_divisor;
 518
 519         err = pm_runtime_get_sync(i2c_dev->dev);
 520         if (err < 0) {
 521                 dev_err(i2c_dev->dev, "runtime resume failed %d\n", err);
 522                 return err;
 523         }
 524
 525         reset_control_assert(i2c_dev->rst);
 526         udelay(2);
 527         reset_control_deassert(i2c_dev->rst);
 528
 529         if (i2c_dev->is_dvc)
 530                 tegra_dvc_init(i2c_dev);
 531
 532         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 533                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 534
 535         if (i2c_dev->hw->has_multi_master_mode)
 536                 val |= I2C_CNFG_MULTI_MASTER_MODE;
 537
 538         i2c_writel(i2c_dev, val, I2C_CNFG);
 539         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 540
 541         /* Make sure clock divisor programmed correctly */
 542         clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
 543         clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
 544                                         I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
 545         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 546
 547         if (!i2c_dev->is_dvc) {
 548                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 549
 550                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 551                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 552                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 553                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 554         }
 555
 556         if (i2c_dev->hw->has_mst_fifo) {
 557                 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
 558                       I2C_MST_FIFO_CONTROL_RX_TRIG(1);
 559                 i2c_writel(i2c_dev, val, I2C_MST_FIFO_CONTROL);
 560         } else {
 561                 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 562                         0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 563                 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 564         }
 565
 566         err = tegra_i2c_flush_fifos(i2c_dev);
 567         if (err)
 568                 goto err;
 569
 570         if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
 571                 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
 572
 573         err = tegra_i2c_wait_for_config_load(i2c_dev);
 574         if (err)
 575                 goto err;
 576
 577         if (i2c_dev->irq_disabled) {
 578                 i2c_dev->irq_disabled = false;
 579                 enable_irq(i2c_dev->irq);
 580         }
 581
 582 err:
 583         pm_runtime_put(i2c_dev->dev);
 584         return err;
 585 }
 586
 587 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
 588 {
 589         u32 cnfg;
 590
 591         /*
 592          * NACK interrupt is generated before the I2C controller generates
 593          * the STOP condition on the bus. So wait for 2 clock periods
 594          * before disabling the controller so that the STOP condition has
 595          * been delivered properly.
 596          */
 597         udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 598
 599         cnfg = i2c_readl(i2c_dev, I2C_CNFG);
 600         if (cnfg & I2C_CNFG_PACKET_MODE_EN)
 601                 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
 602
 603         return tegra_i2c_wait_for_config_load(i2c_dev);
 604 }
 605
 606 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 607 {
 608         u32 status;
 609         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 610         struct tegra_i2c_dev *i2c_dev = dev_id;
 611         unsigned long flags;
 612
 613         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 614
 615         spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
 616         if (status == 0) {
 617                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 618                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 619                          i2c_readl(i2c_dev, I2C_STATUS),
 620                          i2c_readl(i2c_dev, I2C_CNFG));
 621                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 622
 623                 if (!i2c_dev->irq_disabled) {
 624                         disable_irq_nosync(i2c_dev->irq);
 625                         i2c_dev->irq_disabled = true;
 626                 }
 627                 goto err;
 628         }
 629
 630         if (unlikely(status & status_err)) {
 631                 tegra_i2c_disable_packet_mode(i2c_dev);
 632                 if (status & I2C_INT_NO_ACK)
 633                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 634                 if (status & I2C_INT_ARBITRATION_LOST)
 635                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 636                 goto err;
 637         }
 638
 639         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 640                 if (i2c_dev->msg_buf_remaining)
 641                         tegra_i2c_empty_rx_fifo(i2c_dev);
 642                 else
 643                         BUG();
 644         }
 645
 646         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 647                 if (i2c_dev->msg_buf_remaining)
 648                         tegra_i2c_fill_tx_fifo(i2c_dev);
 649                 else
 650                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 651         }
 652
 653         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 654         if (i2c_dev->is_dvc)
 655                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 656
 657         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 658                 BUG_ON(i2c_dev->msg_buf_remaining);
 659                 complete(&i2c_dev->msg_complete);
 660         }
 661         goto done;
 662 err:
 663         /* An error occurred, mask all interrupts */
 664         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 665                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 666                 I2C_INT_RX_FIFO_DATA_REQ);
 667         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 668         if (i2c_dev->is_dvc)
 669                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 670
 671         complete(&i2c_dev->msg_complete);
 672 done:
 673         spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
 674         return IRQ_HANDLED;
 675 }
 676
 677 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 678         struct i2c_msg *msg, enum msg_end_type end_state)
 679 {
 680         u32 packet_header;
 681         u32 int_mask;
 682         unsigned long time_left;
 683         unsigned long flags;
 684
 685         tegra_i2c_flush_fifos(i2c_dev);
 686
 687         i2c_dev->msg_buf = msg->buf;
 688         i2c_dev->msg_buf_remaining = msg->len;
 689         i2c_dev->msg_err = I2C_ERR_NONE;
 690         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 691         reinit_completion(&i2c_dev->msg_complete);
 692
 693         spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
 694
 695         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 696         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 697
 698         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 699                         PACKET_HEADER0_PROTOCOL_I2C |
 700                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 701                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 702         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 703
 704         packet_header = msg->len - 1;
 705         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 706
 707         packet_header = I2C_HEADER_IE_ENABLE;
 708         if (end_state == MSG_END_CONTINUE)
 709                 packet_header |= I2C_HEADER_CONTINUE_XFER;
 710         else if (end_state == MSG_END_REPEAT_START)
 711                 packet_header |= I2C_HEADER_REPEAT_START;
 712         if (msg->flags & I2C_M_TEN) {
 713                 packet_header |= msg->addr;
 714                 packet_header |= I2C_HEADER_10BIT_ADDR;
 715         } else {
 716                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 717         }
 718         if (msg->flags & I2C_M_IGNORE_NAK)
 719                 packet_header |= I2C_HEADER_CONT_ON_NAK;
 720         if (msg->flags & I2C_M_RD)
 721                 packet_header |= I2C_HEADER_READ;
 722         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 723
 724         if (!(msg->flags & I2C_M_RD))
 725                 tegra_i2c_fill_tx_fifo(i2c_dev);
 726
 727         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
 728                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
 729         if (msg->flags & I2C_M_RD)
 730                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 731         else if (i2c_dev->msg_buf_remaining)
 732                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 733
 734         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 735         spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
 736         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 737                 i2c_readl(i2c_dev, I2C_INT_MASK));
 738
 739         time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
 740                                                 TEGRA_I2C_TIMEOUT);
 741         tegra_i2c_mask_irq(i2c_dev, int_mask);
 742
 743         if (time_left == 0) {
 744                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 745
 746                 tegra_i2c_init(i2c_dev);
 747                 return -ETIMEDOUT;
 748         }
 749
 750         dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
 751                 time_left, completion_done(&i2c_dev->msg_complete),
 752                 i2c_dev->msg_err);
 753
 754         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 755                 return 0;
 756
 757         tegra_i2c_init(i2c_dev);
 758         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 759                 if (msg->flags & I2C_M_IGNORE_NAK)
 760                         return 0;
 761                 return -EREMOTEIO;
 762         }
 763
 764         return -EIO;
 765 }
 766
 767 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 768         int num)
 769 {
 770         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 771         int i;
 772         int ret = 0;
 773
 774         ret = pm_runtime_get_sync(i2c_dev->dev);
 775         if (ret < 0) {
 776                 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
 777                 return ret;
 778         }
 779
 780         for (i = 0; i < num; i++) {
 781                 enum msg_end_type end_type = MSG_END_STOP;
 782
 783                 if (i < (num - 1)) {
 784                         if (msgs[i + 1].flags & I2C_M_NOSTART)
 785                                 end_type = MSG_END_CONTINUE;
 786                         else
 787                                 end_type = MSG_END_REPEAT_START;
 788                 }
 789                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
 790                 if (ret)
 791                         break;
 792         }
 793
 794         pm_runtime_put(i2c_dev->dev);
 795
 796         return ret ?: i;
 797 }
 798
 799 static u32 tegra_i2c_func(struct i2c_adapter *adap)
 800 {
 801         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 802         u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 803                   I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
 804
 805         if (i2c_dev->hw->has_continue_xfer_support)
 806                 ret |= I2C_FUNC_NOSTART;
 807         return ret;
 808 }
 809
 810 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
 811 {
 812         struct device_node *np = i2c_dev->dev->of_node;
 813         int ret;
 814
 815         ret = of_property_read_u32(np, "clock-frequency",
 816                         &i2c_dev->bus_clk_rate);
 817         if (ret)
 818                 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
 819
 820         i2c_dev->is_multimaster_mode = of_property_read_bool(np,
 821                         "multi-master");
 822 }
 823
 824 static const struct i2c_algorithm tegra_i2c_algo = {
 825         .master_xfer    = tegra_i2c_xfer,
 826         .functionality  = tegra_i2c_func,
 827 };
 828
 829 /* payload size is only 12 bit */
 830 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
 831         .flags = I2C_AQ_NO_ZERO_LEN,
 832         .max_read_len = 4096,
 833         .max_write_len = 4096,
 834 };
 835
 836 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
 837         .has_continue_xfer_support = false,
 838         .has_per_pkt_xfer_complete_irq = false,
 839         .has_single_clk_source = false,
 840         .clk_divisor_hs_mode = 3,
 841         .clk_divisor_std_fast_mode = 0,
 842         .clk_divisor_fast_plus_mode = 0,
 843         .has_config_load_reg = false,
 844         .has_multi_master_mode = false,
 845         .has_slcg_override_reg = false,
 846         .has_mst_fifo = false,
 847 };
 848
 849 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
 850         .has_continue_xfer_support = true,
 851         .has_per_pkt_xfer_complete_irq = false,
 852         .has_single_clk_source = false,
 853         .clk_divisor_hs_mode = 3,
 854         .clk_divisor_std_fast_mode = 0,
 855         .clk_divisor_fast_plus_mode = 0,
 856         .has_config_load_reg = false,
 857         .has_multi_master_mode = false,
 858         .has_slcg_override_reg = false,
 859         .has_mst_fifo = false,
 860 };
 861
 862 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
 863         .has_continue_xfer_support = true,
 864         .has_per_pkt_xfer_complete_irq = true,
 865         .has_single_clk_source = true,
 866         .clk_divisor_hs_mode = 1,
 867         .clk_divisor_std_fast_mode = 0x19,
 868         .clk_divisor_fast_plus_mode = 0x10,
 869         .has_config_load_reg = false,
 870         .has_multi_master_mode = false,
 871         .has_slcg_override_reg = false,
 872         .has_mst_fifo = false,
 873 };
 874
 875 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
 876         .has_continue_xfer_support = true,
 877         .has_per_pkt_xfer_complete_irq = true,
 878         .has_single_clk_source = true,
 879         .clk_divisor_hs_mode = 1,
 880         .clk_divisor_std_fast_mode = 0x19,
 881         .clk_divisor_fast_plus_mode = 0x10,
 882         .has_config_load_reg = true,
 883         .has_multi_master_mode = false,
 884         .has_slcg_override_reg = true,
 885         .has_mst_fifo = false,
 886 };
 887
 888 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
 889         .has_continue_xfer_support = true,
 890         .has_per_pkt_xfer_complete_irq = true,
 891         .has_single_clk_source = true,
 892         .clk_divisor_hs_mode = 1,
 893         .clk_divisor_std_fast_mode = 0x19,
 894         .clk_divisor_fast_plus_mode = 0x10,
 895         .has_config_load_reg = true,
 896         .has_multi_master_mode = true,
 897         .has_slcg_override_reg = true,
 898         .has_mst_fifo = false,
 899 };
 900
 901 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
 902         .has_continue_xfer_support = true,
 903         .has_per_pkt_xfer_complete_irq = true,
 904         .has_single_clk_source = true,
 905         .clk_divisor_hs_mode = 1,
 906         .clk_divisor_std_fast_mode = 0x19,
 907         .clk_divisor_fast_plus_mode = 0x10,
 908         .has_config_load_reg = true,
 909         .has_multi_master_mode = true,
 910         .has_slcg_override_reg = true,
 911         .has_mst_fifo = true,
 912 };
 913
 914 /* Match table for of_platform binding */
 915 static const struct of_device_id tegra_i2c_of_match[] = {
 916         { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
 917         { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
 918         { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
 919         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
 920         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
 921         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
 922         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
 923         {},
 924 };
 925 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
 926
 927 static int tegra_i2c_probe(struct platform_device *pdev)
 928 {
 929         struct tegra_i2c_dev *i2c_dev;
 930         struct resource *res;
 931         struct clk *div_clk;
 932         struct clk *fast_clk;
 933         void __iomem *base;
 934         int irq;
 935         int ret = 0;
 936         int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
 937
 938         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 939         base = devm_ioremap_resource(&pdev->dev, res);
 940         if (IS_ERR(base))
 941                 return PTR_ERR(base);
 942
 943         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 944         if (!res) {
 945                 dev_err(&pdev->dev, "no irq resource\n");
 946                 return -EINVAL;
 947         }
 948         irq = res->start;
 949
 950         div_clk = devm_clk_get(&pdev->dev, "div-clk");
 951         if (IS_ERR(div_clk)) {
 952                 dev_err(&pdev->dev, "missing controller clock\n");
 953                 return PTR_ERR(div_clk);
 954         }
 955
 956         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
 957         if (!i2c_dev)
 958                 return -ENOMEM;
 959
 960         i2c_dev->base = base;
 961         i2c_dev->div_clk = div_clk;
 962         i2c_dev->adapter.algo = &tegra_i2c_algo;
 963         i2c_dev->adapter.quirks = &tegra_i2c_quirks;
 964         i2c_dev->irq = irq;
 965         i2c_dev->cont_id = pdev->id;
 966         i2c_dev->dev = &pdev->dev;
 967
 968         i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c");
 969         if (IS_ERR(i2c_dev->rst)) {
 970                 dev_err(&pdev->dev, "missing controller reset\n");
 971                 return PTR_ERR(i2c_dev->rst);
 972         }
 973
 974         tegra_i2c_parse_dt(i2c_dev);
 975
 976         i2c_dev->hw = of_device_get_match_data(&pdev->dev);
 977         i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
 978                                                   "nvidia,tegra20-i2c-dvc");
 979         init_completion(&i2c_dev->msg_complete);
 980         spin_lock_init(&i2c_dev->xfer_lock);
 981
 982         if (!i2c_dev->hw->has_single_clk_source) {
 983                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
 984                 if (IS_ERR(fast_clk)) {
 985                         dev_err(&pdev->dev, "missing fast clock\n");
 986                         return PTR_ERR(fast_clk);
 987                 }
 988                 i2c_dev->fast_clk = fast_clk;
 989         }
 990
 991         platform_set_drvdata(pdev, i2c_dev);
 992
 993         if (!i2c_dev->hw->has_single_clk_source) {
 994                 ret = clk_prepare(i2c_dev->fast_clk);
 995                 if (ret < 0) {
 996                         dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
 997                         return ret;
 998                 }
 999         }
1000
1001         i2c_dev->clk_divisor_non_hs_mode =
1002                         i2c_dev->hw->clk_divisor_std_fast_mode;
1003         if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
1004                 (i2c_dev->bus_clk_rate == 1000000))
1005                 i2c_dev->clk_divisor_non_hs_mode =
1006                         i2c_dev->hw->clk_divisor_fast_plus_mode;
1007
1008         clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
1009         ret = clk_set_rate(i2c_dev->div_clk,
1010                            i2c_dev->bus_clk_rate * clk_multiplier);
1011         if (ret) {
1012                 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
1013                 goto unprepare_fast_clk;
1014         }
1015
1016         ret = clk_prepare(i2c_dev->div_clk);
1017         if (ret < 0) {
1018                 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1019                 goto unprepare_fast_clk;
1020         }
1021
1022         pm_runtime_enable(&pdev->dev);
1023         if (!pm_runtime_enabled(&pdev->dev)) {
1024                 ret = tegra_i2c_runtime_resume(&pdev->dev);
1025                 if (ret < 0) {
1026                         dev_err(&pdev->dev, "runtime resume failed\n");
1027                         goto unprepare_div_clk;
1028                 }
1029         }
1030
1031         if (i2c_dev->is_multimaster_mode) {
1032                 ret = clk_enable(i2c_dev->div_clk);
1033                 if (ret < 0) {
1034                         dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
1035                                 ret);
1036                         goto disable_rpm;
1037                 }
1038         }
1039
1040         ret = tegra_i2c_init(i2c_dev);
1041         if (ret) {
1042                 dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
1043                 goto disable_div_clk;
1044         }
1045
1046         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
1047                         tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
1048         if (ret) {
1049                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
1050                 goto disable_div_clk;
1051         }
1052
1053         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1054         i2c_dev->adapter.owner = THIS_MODULE;
1055         i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1056         strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
1057                 sizeof(i2c_dev->adapter.name));
1058         i2c_dev->adapter.dev.parent = &pdev->dev;
1059         i2c_dev->adapter.nr = pdev->id;
1060         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1061
1062         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1063         if (ret)
1064                 goto disable_div_clk;
1065
1066         return 0;
1067
1068 disable_div_clk:
1069         if (i2c_dev->is_multimaster_mode)
1070                 clk_disable(i2c_dev->div_clk);
1071
1072 disable_rpm:
1073         pm_runtime_disable(&pdev->dev);
1074         if (!pm_runtime_status_suspended(&pdev->dev))
1075                 tegra_i2c_runtime_suspend(&pdev->dev);
1076
1077 unprepare_div_clk:
1078         clk_unprepare(i2c_dev->div_clk);
1079
1080 unprepare_fast_clk:
1081         if (!i2c_dev->hw->has_single_clk_source)
1082                 clk_unprepare(i2c_dev->fast_clk);
1083
1084         return ret;
1085 }
1086
1087 static int tegra_i2c_remove(struct platform_device *pdev)
1088 {
1089         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1090
1091         i2c_del_adapter(&i2c_dev->adapter);
1092
1093         if (i2c_dev->is_multimaster_mode)
1094                 clk_disable(i2c_dev->div_clk);
1095
1096         pm_runtime_disable(&pdev->dev);
1097         if (!pm_runtime_status_suspended(&pdev->dev))
1098                 tegra_i2c_runtime_suspend(&pdev->dev);
1099
1100         clk_unprepare(i2c_dev->div_clk);
1101         if (!i2c_dev->hw->has_single_clk_source)
1102                 clk_unprepare(i2c_dev->fast_clk);
1103
1104         return 0;
1105 }
1106
1107 #ifdef CONFIG_PM_SLEEP
1108 static const struct dev_pm_ops tegra_i2c_pm = {
1109         SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1110                            NULL)
1111 };
1112 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
1113 #else
1114 #define TEGRA_I2C_PM    NULL
1115 #endif
1116
1117 static struct platform_driver tegra_i2c_driver = {
1118         .probe   = tegra_i2c_probe,
1119         .remove  = tegra_i2c_remove,
1120         .driver  = {
1121                 .name  = "tegra-i2c",
1122                 .of_match_table = tegra_i2c_of_match,
1123                 .pm    = TEGRA_I2C_PM,
1124         },
1125 };
1126
1127 static int __init tegra_i2c_init_driver(void)
1128 {
1129         return platform_driver_register(&tegra_i2c_driver);
1130 }
1131
1132 static void __exit tegra_i2c_exit_driver(void)
1133 {
1134         platform_driver_unregister(&tegra_i2c_driver);
1135 }
1136
1137 subsys_initcall(tegra_i2c_init_driver);
1138 module_exit(tegra_i2c_exit_driver);
1139
1140 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1141 MODULE_AUTHOR("Colin Cross");
1142 MODULE_LICENSE("GPL v2");