1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
3 * Copyright (C) 2004,2005,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 I2C Controller
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
26 #include <linux/i2c.h>
27 #include <linux/init.h>
28 #include <linux/time.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/errno.h>
32 #include <linux/err.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clk.h>
36 #include <linux/cpufreq.h>
37 #include <linux/slab.h>
39 #include <linux/of_i2c.h>
40 #include <linux/of_gpio.h>
41 #include <linux/pinctrl/consumer.h>
45 #include <plat/regs-iic.h>
46 #include <linux/platform_data/i2c-s3c2410.h>
48 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
49 #define QUIRK_S3C2440 (1 << 0)
50 #define QUIRK_HDMIPHY (1 << 1)
51 #define QUIRK_NO_GPIO (1 << 2)
53 /* Max time to wait for bus to become idle after a xfer (in us) */
54 #define S3C2410_IDLE_TIMEOUT 5000
56 /* i2c controller state */
57 enum s3c24xx_i2c_state {
66 wait_queue_head_t wait;
68 unsigned int suspended:1;
75 unsigned int tx_setup;
78 enum s3c24xx_i2c_state state;
79 unsigned long clkrate;
84 struct i2c_adapter adap;
86 struct s3c2410_platform_i2c *pdata;
88 struct pinctrl *pctrl;
89 #ifdef CONFIG_CPU_FREQ
90 struct notifier_block freq_transition;
94 static struct platform_device_id s3c24xx_driver_ids[] = {
96 .name = "s3c2410-i2c",
99 .name = "s3c2440-i2c",
100 .driver_data = QUIRK_S3C2440,
102 .name = "s3c2440-hdmiphy-i2c",
103 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
106 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
109 static const struct of_device_id s3c24xx_i2c_match[] = {
110 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
111 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
112 { .compatible = "samsung,s3c2440-hdmiphy-i2c",
113 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
116 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
119 /* s3c24xx_get_device_quirks
121 * Get controller type either from device tree or platform device variant.
124 static inline unsigned int s3c24xx_get_device_quirks(struct platform_device *pdev)
126 if (pdev->dev.of_node) {
127 const struct of_device_id *match;
128 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
129 return (unsigned int)match->data;
132 return platform_get_device_id(pdev)->driver_data;
135 /* s3c24xx_i2c_master_complete
137 * complete the message and wake up the caller, using the given return code,
138 * or zero to mean ok.
141 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
143 dev_dbg(i2c->dev, "master_complete %d\n", ret);
155 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
159 tmp = readl(i2c->regs + S3C2410_IICCON);
160 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
163 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
167 tmp = readl(i2c->regs + S3C2410_IICCON);
168 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
171 /* irq enable/disable functions */
173 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
177 tmp = readl(i2c->regs + S3C2410_IICCON);
178 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
181 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
185 tmp = readl(i2c->regs + S3C2410_IICCON);
186 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
190 /* s3c24xx_i2c_message_start
192 * put the start of a message onto the bus
195 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
198 unsigned int addr = (msg->addr & 0x7f) << 1;
200 unsigned long iiccon;
203 stat |= S3C2410_IICSTAT_TXRXEN;
205 if (msg->flags & I2C_M_RD) {
206 stat |= S3C2410_IICSTAT_MASTER_RX;
209 stat |= S3C2410_IICSTAT_MASTER_TX;
211 if (msg->flags & I2C_M_REV_DIR_ADDR)
214 /* todo - check for whether ack wanted or not */
215 s3c24xx_i2c_enable_ack(i2c);
217 iiccon = readl(i2c->regs + S3C2410_IICCON);
218 writel(stat, i2c->regs + S3C2410_IICSTAT);
220 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
221 writeb(addr, i2c->regs + S3C2410_IICDS);
223 /* delay here to ensure the data byte has gotten onto the bus
224 * before the transaction is started */
226 ndelay(i2c->tx_setup);
228 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
229 writel(iiccon, i2c->regs + S3C2410_IICCON);
231 stat |= S3C2410_IICSTAT_START;
232 writel(stat, i2c->regs + S3C2410_IICSTAT);
235 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
237 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
239 dev_dbg(i2c->dev, "STOP\n");
242 * The datasheet says that the STOP sequence should be:
243 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP')
244 * 2) I2CCON.4 = 0 - Clear IRQPEND
245 * 3) Wait until the stop condition takes effect.
246 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN
248 * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
250 * However, after much experimentation, it appears that:
251 * a) normal buses automatically clear BUSY and transition from
252 * Master->Slave when they complete generating a STOP condition.
253 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4
254 * after starting the STOP generation here.
255 * b) HDMIPHY bus does neither, so there is no way to do step 3.
256 * There is no indication when this bus has finished generating
259 * In fact, we have found that as soon as the IRQPEND bit is cleared in
260 * step 2, the HDMIPHY bus generates the STOP condition, and then
261 * immediately starts transferring another data byte, even though the
262 * bus is supposedly stopped. This is presumably because the bus is
263 * still in "Master" mode, and its BUSY bit is still set.
265 * To avoid these extra post-STOP transactions on HDMI phy devices, we
266 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
267 * instead of first generating a proper STOP condition. This should
268 * float SDA & SCK terminating the transfer. Subsequent transfers
269 * start with a proper START condition, and proceed normally.
271 * The HDMIPHY bus is an internal bus that always has exactly two
272 * devices, the host as Master and the HDMIPHY device as the slave.
273 * Skipping the STOP condition has been tested on this bus and works.
275 if (i2c->quirks & QUIRK_HDMIPHY) {
276 /* Stop driving the I2C pins */
277 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
279 /* stop the transfer */
280 iicstat &= ~S3C2410_IICSTAT_START;
282 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
284 i2c->state = STATE_STOP;
286 s3c24xx_i2c_master_complete(i2c, ret);
287 s3c24xx_i2c_disable_irq(i2c);
290 /* helper functions to determine the current state in the set of
291 * messages we are sending */
295 * returns TRUE if the current message is the last in the set
298 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
300 return i2c->msg_idx >= (i2c->msg_num - 1);
305 * returns TRUE if we this is the last byte in the current message
308 static inline int is_msglast(struct s3c24xx_i2c *i2c)
310 return i2c->msg_ptr == i2c->msg->len-1;
315 * returns TRUE if we reached the end of the current message
318 static inline int is_msgend(struct s3c24xx_i2c *i2c)
320 return i2c->msg_ptr >= i2c->msg->len;
323 /* i2c_s3c_irq_nextbyte
325 * process an interrupt and work out what to do
328 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
334 switch (i2c->state) {
337 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
341 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
342 s3c24xx_i2c_disable_irq(i2c);
346 /* last thing we did was send a start condition on the
347 * bus, or started a new i2c message
350 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
351 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
352 /* ack was not received... */
354 dev_dbg(i2c->dev, "ack was not received\n");
355 s3c24xx_i2c_stop(i2c, -ENXIO);
359 if (i2c->msg->flags & I2C_M_RD)
360 i2c->state = STATE_READ;
362 i2c->state = STATE_WRITE;
364 /* terminate the transfer if there is nothing to do
365 * as this is used by the i2c probe to find devices. */
367 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
368 s3c24xx_i2c_stop(i2c, 0);
372 if (i2c->state == STATE_READ)
375 /* fall through to the write state, as we will need to
376 * send a byte as well */
379 /* we are writing data to the device... check for the
380 * end of the message, and if so, work out what to do
383 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
384 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
385 dev_dbg(i2c->dev, "WRITE: No Ack\n");
387 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
394 if (!is_msgend(i2c)) {
395 byte = i2c->msg->buf[i2c->msg_ptr++];
396 writeb(byte, i2c->regs + S3C2410_IICDS);
398 /* delay after writing the byte to allow the
399 * data setup time on the bus, as writing the
400 * data to the register causes the first bit
401 * to appear on SDA, and SCL will change as
402 * soon as the interrupt is acknowledged */
404 ndelay(i2c->tx_setup);
406 } else if (!is_lastmsg(i2c)) {
407 /* we need to go to the next i2c message */
409 dev_dbg(i2c->dev, "WRITE: Next Message\n");
415 /* check to see if we need to do another message */
416 if (i2c->msg->flags & I2C_M_NOSTART) {
418 if (i2c->msg->flags & I2C_M_RD) {
419 /* cannot do this, the controller
420 * forces us to send a new START
421 * when we change direction */
423 s3c24xx_i2c_stop(i2c, -EINVAL);
428 /* send the new start */
429 s3c24xx_i2c_message_start(i2c, i2c->msg);
430 i2c->state = STATE_START;
436 s3c24xx_i2c_stop(i2c, 0);
441 /* we have a byte of data in the data register, do
442 * something with it, and then work out whether we are
443 * going to do any more read/write
446 byte = readb(i2c->regs + S3C2410_IICDS);
447 i2c->msg->buf[i2c->msg_ptr++] = byte;
450 if (is_msglast(i2c)) {
451 /* last byte of buffer */
454 s3c24xx_i2c_disable_ack(i2c);
456 } else if (is_msgend(i2c)) {
457 /* ok, we've read the entire buffer, see if there
458 * is anything else we need to do */
460 if (is_lastmsg(i2c)) {
461 /* last message, send stop and complete */
462 dev_dbg(i2c->dev, "READ: Send Stop\n");
464 s3c24xx_i2c_stop(i2c, 0);
466 /* go to the next transfer */
467 dev_dbg(i2c->dev, "READ: Next Transfer\n");
478 /* acknowlegde the IRQ and get back on with the work */
481 tmp = readl(i2c->regs + S3C2410_IICCON);
482 tmp &= ~S3C2410_IICCON_IRQPEND;
483 writel(tmp, i2c->regs + S3C2410_IICCON);
490 * top level IRQ servicing routine
493 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
495 struct s3c24xx_i2c *i2c = dev_id;
496 unsigned long status;
499 status = readl(i2c->regs + S3C2410_IICSTAT);
501 if (status & S3C2410_IICSTAT_ARBITR) {
502 /* deal with arbitration loss */
503 dev_err(i2c->dev, "deal with arbitration loss\n");
506 if (i2c->state == STATE_IDLE) {
507 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
509 tmp = readl(i2c->regs + S3C2410_IICCON);
510 tmp &= ~S3C2410_IICCON_IRQPEND;
511 writel(tmp, i2c->regs + S3C2410_IICCON);
515 /* pretty much this leaves us with the fact that we've
516 * transmitted or received whatever byte we last sent */
518 i2c_s3c_irq_nextbyte(i2c, status);
525 /* s3c24xx_i2c_set_master
527 * get the i2c bus for a master transaction
530 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
532 unsigned long iicstat;
535 while (timeout-- > 0) {
536 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
538 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
547 /* s3c24xx_i2c_wait_idle
549 * wait for the i2c bus to become idle.
552 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
554 unsigned long iicstat;
559 /* ensure the stop has been through the bus */
561 dev_dbg(i2c->dev, "waiting for bus idle\n");
563 start = now = ktime_get();
566 * Most of the time, the bus is already idle within a few usec of the
567 * end of a transaction. However, really slow i2c devices can stretch
568 * the clock, delaying STOP generation.
570 * On slower SoCs this typically happens within a very small number of
571 * instructions so busy wait briefly to avoid scheduling overhead.
574 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
575 while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
577 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
581 * If we do get an appreciable delay as a compromise between idle
582 * detection latency for the normal, fast case, and system load in the
583 * slow device case, use an exponential back off in the polling loop,
584 * up to 1/10th of the total timeout, then continue to poll at a
585 * constant rate up to the timeout.
588 while ((iicstat & S3C2410_IICSTAT_START) &&
589 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
590 usleep_range(delay, 2 * delay);
591 if (delay < S3C2410_IDLE_TIMEOUT / 10)
594 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
597 if (iicstat & S3C2410_IICSTAT_START)
598 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
601 /* s3c24xx_i2c_doxfer
603 * this starts an i2c transfer
606 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
607 struct i2c_msg *msgs, int num)
609 unsigned long timeout;
615 ret = s3c24xx_i2c_set_master(i2c);
617 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
626 i2c->state = STATE_START;
628 s3c24xx_i2c_enable_irq(i2c);
629 s3c24xx_i2c_message_start(i2c, msgs);
631 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
635 /* having these next two as dev_err() makes life very
636 * noisy when doing an i2cdetect */
639 dev_dbg(i2c->dev, "timeout\n");
641 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
643 /* For QUIRK_HDMIPHY, bus is already disabled */
644 if (i2c->quirks & QUIRK_HDMIPHY)
647 s3c24xx_i2c_wait_idle(i2c);
655 * first port of call from the i2c bus code when an message needs
656 * transferring across the i2c bus.
659 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
660 struct i2c_msg *msgs, int num)
662 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
666 pm_runtime_get_sync(&adap->dev);
667 clk_prepare_enable(i2c->clk);
669 for (retry = 0; retry < adap->retries; retry++) {
671 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
673 if (ret != -EAGAIN) {
674 clk_disable_unprepare(i2c->clk);
675 pm_runtime_put(&adap->dev);
679 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
684 clk_disable_unprepare(i2c->clk);
685 pm_runtime_put(&adap->dev);
689 /* declare our i2c functionality */
690 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
692 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
693 I2C_FUNC_PROTOCOL_MANGLING;
696 /* i2c bus registration info */
698 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
699 .master_xfer = s3c24xx_i2c_xfer,
700 .functionality = s3c24xx_i2c_func,
703 /* s3c24xx_i2c_calcdivisor
705 * return the divisor settings for a given frequency
708 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
709 unsigned int *div1, unsigned int *divs)
711 unsigned int calc_divs = clkin / wanted;
712 unsigned int calc_div1;
714 if (calc_divs > (16*16))
719 calc_divs += calc_div1-1;
720 calc_divs /= calc_div1;
730 return clkin / (calc_divs * calc_div1);
733 /* s3c24xx_i2c_clockrate
735 * work out a divisor for the user requested frequency setting,
736 * either by the requested frequency, or scanning the acceptable
737 * range of frequencies until something is found
740 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
742 struct s3c2410_platform_i2c *pdata = i2c->pdata;
743 unsigned long clkin = clk_get_rate(i2c->clk);
744 unsigned int divs, div1;
745 unsigned long target_frequency;
749 i2c->clkrate = clkin;
750 clkin /= 1000; /* clkin now in KHz */
752 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
754 target_frequency = pdata->frequency ? pdata->frequency : 100000;
756 target_frequency /= 1000; /* Target frequency now in KHz */
758 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
760 if (freq > target_frequency) {
762 "Unable to achieve desired frequency %luKHz." \
763 " Lowest achievable %dKHz\n", target_frequency, freq);
769 iiccon = readl(i2c->regs + S3C2410_IICCON);
770 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
774 iiccon |= S3C2410_IICCON_TXDIV_512;
776 writel(iiccon, i2c->regs + S3C2410_IICCON);
778 if (i2c->quirks & QUIRK_S3C2440) {
779 unsigned long sda_delay;
781 if (pdata->sda_delay) {
782 sda_delay = clkin * pdata->sda_delay;
783 sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
784 sda_delay = DIV_ROUND_UP(sda_delay, 5);
787 sda_delay |= S3C2410_IICLC_FILTER_ON;
791 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
792 writel(sda_delay, i2c->regs + S3C2440_IICLC);
798 #ifdef CONFIG_CPU_FREQ
800 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
802 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
803 unsigned long val, void *data)
805 struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
810 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
812 /* if we're post-change and the input clock has slowed down
813 * or at pre-change and the clock is about to speed up, then
814 * adjust our clock rate. <0 is slow, >0 speedup.
817 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
818 (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
819 i2c_lock_adapter(&i2c->adap);
820 ret = s3c24xx_i2c_clockrate(i2c, &got);
821 i2c_unlock_adapter(&i2c->adap);
824 dev_err(i2c->dev, "cannot find frequency\n");
826 dev_info(i2c->dev, "setting freq %d\n", got);
832 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
834 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
836 return cpufreq_register_notifier(&i2c->freq_transition,
837 CPUFREQ_TRANSITION_NOTIFIER);
840 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
842 cpufreq_unregister_notifier(&i2c->freq_transition,
843 CPUFREQ_TRANSITION_NOTIFIER);
847 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
852 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
858 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
862 if (i2c->quirks & QUIRK_NO_GPIO)
865 for (idx = 0; idx < 2; idx++) {
866 gpio = of_get_gpio(i2c->dev->of_node, idx);
867 if (!gpio_is_valid(gpio)) {
868 dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
871 i2c->gpios[idx] = gpio;
873 ret = gpio_request(gpio, "i2c-bus");
875 dev_err(i2c->dev, "gpio [%d] request failed\n", gpio);
883 gpio_free(i2c->gpios[idx]);
887 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
891 if (i2c->quirks & QUIRK_NO_GPIO)
894 for (idx = 0; idx < 2; idx++)
895 gpio_free(i2c->gpios[idx]);
898 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
903 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
910 * initialise the controller, set the IO lines and frequency
913 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
915 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
916 struct s3c2410_platform_i2c *pdata;
919 /* get the plafrom data */
923 /* write slave address */
925 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
927 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
929 writel(iicon, i2c->regs + S3C2410_IICCON);
931 /* we need to work out the divisors for the clock... */
933 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
934 writel(0, i2c->regs + S3C2410_IICCON);
935 dev_err(i2c->dev, "cannot meet bus frequency required\n");
939 /* todo - check that the i2c lines aren't being dragged anywhere */
941 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
942 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
948 /* s3c24xx_i2c_parse_dt
950 * Parse the device tree node and retreive the platform data.
954 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
956 struct s3c2410_platform_i2c *pdata = i2c->pdata;
961 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
962 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
963 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
964 of_property_read_u32(np, "samsung,i2c-max-bus-freq",
965 (u32 *)&pdata->frequency);
969 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
977 * called by the bus driver when a suitable device is found
980 static int s3c24xx_i2c_probe(struct platform_device *pdev)
982 struct s3c24xx_i2c *i2c;
983 struct s3c2410_platform_i2c *pdata = NULL;
984 struct resource *res;
987 if (!pdev->dev.of_node) {
988 pdata = pdev->dev.platform_data;
990 dev_err(&pdev->dev, "no platform data\n");
995 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
997 dev_err(&pdev->dev, "no memory for state\n");
1001 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1007 i2c->quirks = s3c24xx_get_device_quirks(pdev);
1009 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1011 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1013 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1014 i2c->adap.owner = THIS_MODULE;
1015 i2c->adap.algo = &s3c24xx_i2c_algorithm;
1016 i2c->adap.retries = 2;
1017 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1020 init_waitqueue_head(&i2c->wait);
1022 /* find the clock and enable it */
1024 i2c->dev = &pdev->dev;
1025 i2c->clk = clk_get(&pdev->dev, "i2c");
1026 if (IS_ERR(i2c->clk)) {
1027 dev_err(&pdev->dev, "cannot get clock\n");
1032 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1034 clk_prepare_enable(i2c->clk);
1036 /* map the registers */
1038 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1040 dev_err(&pdev->dev, "cannot find IO resource\n");
1045 i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1047 if (IS_ERR(i2c->regs)) {
1048 ret = PTR_ERR(i2c->regs);
1052 dev_dbg(&pdev->dev, "registers %p (%p)\n",
1055 /* setup info block for the i2c core */
1057 i2c->adap.algo_data = i2c;
1058 i2c->adap.dev.parent = &pdev->dev;
1060 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1062 /* inititalise the i2c gpio lines */
1064 if (i2c->pdata->cfg_gpio) {
1065 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1066 } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) {
1071 /* initialise the i2c controller */
1073 ret = s3c24xx_i2c_init(i2c);
1077 /* find the IRQ for this unit (note, this relies on the init call to
1078 * ensure no current IRQs pending
1081 i2c->irq = ret = platform_get_irq(pdev, 0);
1083 dev_err(&pdev->dev, "cannot find IRQ\n");
1087 ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0,
1088 dev_name(&pdev->dev), i2c);
1091 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1095 ret = s3c24xx_i2c_register_cpufreq(i2c);
1097 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1101 /* Note, previous versions of the driver used i2c_add_adapter()
1102 * to add the bus at any number. We now pass the bus number via
1103 * the platform data, so if unset it will now default to always
1107 i2c->adap.nr = i2c->pdata->bus_num;
1108 i2c->adap.dev.of_node = pdev->dev.of_node;
1110 ret = i2c_add_numbered_adapter(&i2c->adap);
1112 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
1116 of_i2c_register_devices(&i2c->adap);
1117 platform_set_drvdata(pdev, i2c);
1119 pm_runtime_enable(&pdev->dev);
1120 pm_runtime_enable(&i2c->adap.dev);
1122 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1123 clk_disable_unprepare(i2c->clk);
1127 s3c24xx_i2c_deregister_cpufreq(i2c);
1130 free_irq(i2c->irq, i2c);
1133 clk_disable_unprepare(i2c->clk);
1140 /* s3c24xx_i2c_remove
1142 * called when device is removed from the bus
1145 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1147 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1149 pm_runtime_disable(&i2c->adap.dev);
1150 pm_runtime_disable(&pdev->dev);
1152 s3c24xx_i2c_deregister_cpufreq(i2c);
1154 i2c_del_adapter(&i2c->adap);
1155 free_irq(i2c->irq, i2c);
1157 clk_disable_unprepare(i2c->clk);
1160 if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1161 s3c24xx_i2c_dt_gpio_free(i2c);
1166 #ifdef CONFIG_PM_SLEEP
1167 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1169 struct platform_device *pdev = to_platform_device(dev);
1170 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1177 static int s3c24xx_i2c_resume(struct device *dev)
1179 struct platform_device *pdev = to_platform_device(dev);
1180 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1183 clk_prepare_enable(i2c->clk);
1184 s3c24xx_i2c_init(i2c);
1185 clk_disable_unprepare(i2c->clk);
1192 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1193 #ifdef CONFIG_PM_SLEEP
1194 .suspend_noirq = s3c24xx_i2c_suspend_noirq,
1195 .resume = s3c24xx_i2c_resume,
1199 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1201 #define S3C24XX_DEV_PM_OPS NULL
1204 /* device driver for platform bus bits */
1206 static struct platform_driver s3c24xx_i2c_driver = {
1207 .probe = s3c24xx_i2c_probe,
1208 .remove = s3c24xx_i2c_remove,
1209 .id_table = s3c24xx_driver_ids,
1211 .owner = THIS_MODULE,
1213 .pm = S3C24XX_DEV_PM_OPS,
1214 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1218 static int __init i2c_adap_s3c_init(void)
1220 return platform_driver_register(&s3c24xx_i2c_driver);
1222 subsys_initcall(i2c_adap_s3c_init);
1224 static void __exit i2c_adap_s3c_exit(void)
1226 platform_driver_unregister(&s3c24xx_i2c_driver);
1228 module_exit(i2c_adap_s3c_exit);
1230 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1231 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1232 MODULE_LICENSE("GPL");