drivers/i2c/busses/i2c-rzv2m.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for the Renesas RZ/V2M I2C unit
   4  *
   5  * Copyright (C) 2016-2022 Renesas Electronics Corporation
   6  */
   7
   8 #include <linux/bits.h>
   9 #include <linux/clk.h>
  10 #include <linux/device.h>
  11 #include <linux/err.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/i2c.h>
  16 #include <linux/jiffies.h>
  17 #include <linux/kernel.h>
  18 #include <linux/math64.h>
  19 #include <linux/module.h>
  20 #include <linux/mod_devicetable.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/reset.h>
  24
  25 /* Register offsets */
  26 #define IICB0DAT        0x00            /* Data Register */
  27 #define IICB0CTL0       0x08            /* Control Register 0 */
  28 #define IICB0TRG        0x0C            /* Trigger Register */
  29 #define IICB0STR0       0x10            /* Status Register 0 */
  30 #define IICB0CTL1       0x20            /* Control Register 1 */
  31 #define IICB0WL         0x24            /* Low Level Width Setting Reg */
  32 #define IICB0WH         0x28            /* How Level Width Setting Reg */
  33
  34 /* IICB0CTL0 */
  35 #define IICB0IICE       BIT(7)          /* I2C Enable */
  36 #define IICB0SLWT       BIT(1)          /* Interrupt Request Timing */
  37 #define IICB0SLAC       BIT(0)          /* Acknowledge */
  38
  39 /* IICB0TRG */
  40 #define IICB0WRET       BIT(2)          /* Quit Wait Trigger */
  41 #define IICB0STT        BIT(1)          /* Create Start Condition Trigger */
  42 #define IICB0SPT        BIT(0)          /* Create Stop Condition Trigger */
  43
  44 /* IICB0STR0 */
  45 #define IICB0SSAC       BIT(8)          /* Ack Flag */
  46 #define IICB0SSBS       BIT(6)          /* Bus Flag */
  47 #define IICB0SSSP       BIT(4)          /* Stop Condition Flag */
  48
  49 /* IICB0CTL1 */
  50 #define IICB0MDSC       BIT(7)          /* Bus Mode */
  51 #define IICB0SLSE       BIT(1)          /* Start condition output */
  52
  53 struct rzv2m_i2c_priv {
  54         void __iomem *base;
  55         struct i2c_adapter adap;
  56         struct clk *clk;
  57         int bus_mode;
  58         struct completion msg_tia_done;
  59         u32 iicb0wl;
  60         u32 iicb0wh;
  61 };
  62
  63 enum bcr_index {
  64         RZV2M_I2C_100K = 0,
  65         RZV2M_I2C_400K,
  66 };
  67
  68 struct bitrate_config {
  69         unsigned int percent_low;
  70         unsigned int min_hold_time_ns;
  71 };
  72
  73 static const struct bitrate_config bitrate_configs[] = {
  74         [RZV2M_I2C_100K] = { 47, 3450 },
  75         [RZV2M_I2C_400K] = { 52, 900 },
  76 };
  77
  78 static inline void bit_setl(void __iomem *addr, u32 val)
  79 {
  80         writel(readl(addr) | val, addr);
  81 }
  82
  83 static inline void bit_clrl(void __iomem *addr, u32 val)
  84 {
  85         writel(readl(addr) & ~val, addr);
  86 }
  87
  88 static irqreturn_t rzv2m_i2c_tia_irq_handler(int this_irq, void *dev_id)
  89 {
  90         struct rzv2m_i2c_priv *priv = dev_id;
  91
  92         complete(&priv->msg_tia_done);
  93
  94         return IRQ_HANDLED;
  95 }
  96
  97 /* Calculate IICB0WL and IICB0WH */
  98 static int rzv2m_i2c_clock_calculate(struct device *dev,
  99                                      struct rzv2m_i2c_priv *priv)
 100 {
 101         const struct bitrate_config *config;
 102         unsigned int hold_time_ns;
 103         unsigned int total_pclks;
 104         unsigned int trf_pclks;
 105         unsigned long pclk_hz;
 106         struct i2c_timings t;
 107         u32 trf_ns;
 108
 109         i2c_parse_fw_timings(dev, &t, true);
 110
 111         pclk_hz = clk_get_rate(priv->clk);
 112         total_pclks = pclk_hz / t.bus_freq_hz;
 113
 114         trf_ns = t.scl_rise_ns + t.scl_fall_ns;
 115         trf_pclks = mul_u64_u32_div(pclk_hz, trf_ns, NSEC_PER_SEC);
 116
 117         /* Config setting */
 118         switch (t.bus_freq_hz) {
 119         case I2C_MAX_FAST_MODE_FREQ:
 120                 priv->bus_mode = RZV2M_I2C_400K;
 121                 break;
 122         case I2C_MAX_STANDARD_MODE_FREQ:
 123                 priv->bus_mode = RZV2M_I2C_100K;
 124                 break;
 125         default:
 126                 dev_err(dev, "transfer speed is invalid\n");
 127                 return -EINVAL;
 128         }
 129         config = &bitrate_configs[priv->bus_mode];
 130
 131         /* IICB0WL = (percent_low / Transfer clock) x PCLK */
 132         priv->iicb0wl = total_pclks * config->percent_low / 100;
 133         if (priv->iicb0wl > (BIT(10) - 1))
 134                 return -EINVAL;
 135
 136         /* IICB0WH = ((percent_high / Transfer clock) x PCLK) - (tR + tF) */
 137         priv->iicb0wh = total_pclks - priv->iicb0wl - trf_pclks;
 138         if (priv->iicb0wh > (BIT(10) - 1))
 139                 return -EINVAL;
 140
 141         /*
 142          * Data hold time must be less than 0.9us in fast mode and
 143          * 3.45us in standard mode.
 144          * Data hold time = IICB0WL[9:2] / PCLK
 145          */
 146         hold_time_ns = div64_ul((u64)(priv->iicb0wl >> 2) * NSEC_PER_SEC, pclk_hz);
 147         if (hold_time_ns > config->min_hold_time_ns) {
 148                 dev_err(dev, "data hold time %dns is over %dns\n",
 149                         hold_time_ns, config->min_hold_time_ns);
 150                 return -EINVAL;
 151         }
 152
 153         return 0;
 154 }
 155
 156 static void rzv2m_i2c_init(struct rzv2m_i2c_priv *priv)
 157 {
 158         u32 i2c_ctl0;
 159         u32 i2c_ctl1;
 160
 161         /* i2c disable */
 162         writel(0, priv->base + IICB0CTL0);
 163
 164         /* IICB0CTL1 setting */
 165         i2c_ctl1 = IICB0SLSE;
 166         if (priv->bus_mode == RZV2M_I2C_400K)
 167                 i2c_ctl1 |= IICB0MDSC;
 168         writel(i2c_ctl1, priv->base + IICB0CTL1);
 169
 170         /* IICB0WL IICB0WH setting */
 171         writel(priv->iicb0wl, priv->base + IICB0WL);
 172         writel(priv->iicb0wh, priv->base + IICB0WH);
 173
 174         /* i2c enable after setting */
 175         i2c_ctl0 = IICB0SLWT | IICB0SLAC | IICB0IICE;
 176         writel(i2c_ctl0, priv->base + IICB0CTL0);
 177 }
 178
 179 static int rzv2m_i2c_write_with_ack(struct rzv2m_i2c_priv *priv, u32 data)
 180 {
 181         unsigned long time_left;
 182
 183         reinit_completion(&priv->msg_tia_done);
 184
 185         writel(data, priv->base + IICB0DAT);
 186
 187         time_left = wait_for_completion_timeout(&priv->msg_tia_done,
 188                                                 priv->adap.timeout);
 189         if (!time_left)
 190                 return -ETIMEDOUT;
 191
 192         /* Confirm ACK */
 193         if ((readl(priv->base + IICB0STR0) & IICB0SSAC) != IICB0SSAC)
 194                 return -ENXIO;
 195
 196         return 0;
 197 }
 198
 199 static int rzv2m_i2c_read_with_ack(struct rzv2m_i2c_priv *priv, u8 *data,
 200                                    bool last)
 201 {
 202         unsigned long time_left;
 203         u32 data_tmp;
 204
 205         reinit_completion(&priv->msg_tia_done);
 206
 207         /* Interrupt request timing : 8th clock */
 208         bit_clrl(priv->base + IICB0CTL0, IICB0SLWT);
 209
 210         /* Exit the wait state */
 211         writel(IICB0WRET, priv->base + IICB0TRG);
 212
 213         /* Wait for transaction */
 214         time_left = wait_for_completion_timeout(&priv->msg_tia_done,
 215                                                 priv->adap.timeout);
 216         if (!time_left)
 217                 return -ETIMEDOUT;
 218
 219         if (last) {
 220                 /* Disable ACK */
 221                 bit_clrl(priv->base + IICB0CTL0, IICB0SLAC);
 222
 223                 /* Read data*/
 224                 data_tmp = readl(priv->base + IICB0DAT);
 225
 226                 /* Interrupt request timing : 9th clock */
 227                 bit_setl(priv->base + IICB0CTL0, IICB0SLWT);
 228
 229                 /* Exit the wait state */
 230                 writel(IICB0WRET, priv->base + IICB0TRG);
 231
 232                 /* Wait for transaction */
 233                 time_left = wait_for_completion_timeout(&priv->msg_tia_done,
 234                                                         priv->adap.timeout);
 235                 if (!time_left)
 236                         return -ETIMEDOUT;
 237
 238                 /* Enable ACK */
 239                 bit_setl(priv->base + IICB0CTL0, IICB0SLAC);
 240         } else {
 241                 /* Read data */
 242                 data_tmp = readl(priv->base + IICB0DAT);
 243         }
 244
 245         *data = data_tmp;
 246
 247         return 0;
 248 }
 249
 250 static int rzv2m_i2c_send(struct rzv2m_i2c_priv *priv, struct i2c_msg *msg,
 251                           unsigned int *count)
 252 {
 253         unsigned int i;
 254         int ret;
 255
 256         for (i = 0; i < msg->len; i++) {
 257                 ret = rzv2m_i2c_write_with_ack(priv, msg->buf[i]);
 258                 if (ret < 0)
 259                         return ret;
 260         }
 261         *count = i;
 262
 263         return 0;
 264 }
 265
 266 static int rzv2m_i2c_receive(struct rzv2m_i2c_priv *priv, struct i2c_msg *msg,
 267                              unsigned int *count)
 268 {
 269         unsigned int i;
 270         int ret;
 271
 272         for (i = 0; i < msg->len; i++) {
 273                 ret = rzv2m_i2c_read_with_ack(priv, &msg->buf[i],
 274                                               (msg->len - 1) == i);
 275                 if (ret < 0)
 276                         return ret;
 277         }
 278         *count = i;
 279
 280         return 0;
 281 }
 282
 283 static int rzv2m_i2c_send_address(struct rzv2m_i2c_priv *priv,
 284                                   struct i2c_msg *msg)
 285 {
 286         u32 addr;
 287         int ret;
 288
 289         if (msg->flags & I2C_M_TEN) {
 290                 /*
 291                  * 10-bit address
 292                  *   addr_1: 5'b11110 | addr[9:8] | (R/nW)
 293                  *   addr_2: addr[7:0]
 294                  */
 295                 addr = 0xf0 | ((msg->addr & GENMASK(9, 8)) >> 7);
 296                 addr |= !!(msg->flags & I2C_M_RD);
 297                 /* Send 1st address(extend code) */
 298                 ret = rzv2m_i2c_write_with_ack(priv, addr);
 299                 if (ret)
 300                         return ret;
 301
 302                 /* Send 2nd address */
 303                 ret = rzv2m_i2c_write_with_ack(priv, msg->addr & 0xff);
 304         } else {
 305                 /* 7-bit address */
 306                 addr = i2c_8bit_addr_from_msg(msg);
 307                 ret = rzv2m_i2c_write_with_ack(priv, addr);
 308         }
 309
 310         return ret;
 311 }
 312
 313 static int rzv2m_i2c_stop_condition(struct rzv2m_i2c_priv *priv)
 314 {
 315         u32 value;
 316
 317         /* Send stop condition */
 318         writel(IICB0SPT, priv->base + IICB0TRG);
 319         return readl_poll_timeout(priv->base + IICB0STR0,
 320                                   value, value & IICB0SSSP,
 321                                   100, jiffies_to_usecs(priv->adap.timeout));
 322 }
 323
 324 static int rzv2m_i2c_master_xfer_msg(struct rzv2m_i2c_priv *priv,
 325                                   struct i2c_msg *msg, int stop)
 326 {
 327         unsigned int count = 0;
 328         int ret, read = !!(msg->flags & I2C_M_RD);
 329
 330         /* Send start condition */
 331         writel(IICB0STT, priv->base + IICB0TRG);
 332
 333         ret = rzv2m_i2c_send_address(priv, msg);
 334         if (!ret) {
 335                 if (read)
 336                         ret = rzv2m_i2c_receive(priv, msg, &count);
 337                 else
 338                         ret = rzv2m_i2c_send(priv, msg, &count);
 339
 340                 if (!ret && stop)
 341                         ret = rzv2m_i2c_stop_condition(priv);
 342         }
 343
 344         if (ret == -ENXIO)
 345                 rzv2m_i2c_stop_condition(priv);
 346         else if (ret < 0)
 347                 rzv2m_i2c_init(priv);
 348         else
 349                 ret = count;
 350
 351         return ret;
 352 }
 353
 354 static int rzv2m_i2c_master_xfer(struct i2c_adapter *adap,
 355                                  struct i2c_msg *msgs, int num)
 356 {
 357         struct rzv2m_i2c_priv *priv = i2c_get_adapdata(adap);
 358         struct device *dev = priv->adap.dev.parent;
 359         unsigned int i;
 360         int ret;
 361
 362         ret = pm_runtime_resume_and_get(dev);
 363         if (ret < 0)
 364                 return ret;
 365
 366         if (readl(priv->base + IICB0STR0) & IICB0SSBS) {
 367                 ret = -EAGAIN;
 368                 goto out;
 369         }
 370
 371         /* I2C main transfer */
 372         for (i = 0; i < num; i++) {
 373                 ret = rzv2m_i2c_master_xfer_msg(priv, &msgs[i], i == (num - 1));
 374                 if (ret < 0)
 375                         goto out;
 376         }
 377         ret = num;
 378
 379 out:
 380         pm_runtime_mark_last_busy(dev);
 381         pm_runtime_put_autosuspend(dev);
 382
 383         return ret;
 384 }
 385
 386 static u32 rzv2m_i2c_func(struct i2c_adapter *adap)
 387 {
 388         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 389                I2C_FUNC_10BIT_ADDR;
 390 }
 391
 392 static int rzv2m_i2c_disable(struct device *dev, struct rzv2m_i2c_priv *priv)
 393 {
 394         int ret;
 395
 396         ret = pm_runtime_resume_and_get(dev);
 397         if (ret < 0)
 398                 return ret;
 399
 400         bit_clrl(priv->base + IICB0CTL0, IICB0IICE);
 401         pm_runtime_put(dev);
 402
 403         return 0;
 404 }
 405
 406 static const struct i2c_adapter_quirks rzv2m_i2c_quirks = {
 407         .flags = I2C_AQ_NO_ZERO_LEN,
 408 };
 409
 410 static struct i2c_algorithm rzv2m_i2c_algo = {
 411         .master_xfer = rzv2m_i2c_master_xfer,
 412         .functionality = rzv2m_i2c_func,
 413 };
 414
 415 static int rzv2m_i2c_probe(struct platform_device *pdev)
 416 {
 417         struct device *dev = &pdev->dev;
 418         struct rzv2m_i2c_priv *priv;
 419         struct reset_control *rstc;
 420         struct i2c_adapter *adap;
 421         struct resource *res;
 422         int irq, ret;
 423
 424         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 425         if (!priv)
 426                 return -ENOMEM;
 427
 428         priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 429         if (IS_ERR(priv->base))
 430                 return PTR_ERR(priv->base);
 431
 432         priv->clk = devm_clk_get(dev, NULL);
 433         if (IS_ERR(priv->clk))
 434                 return dev_err_probe(dev, PTR_ERR(priv->clk), "Can't get clock\n");
 435
 436         rstc = devm_reset_control_get_shared(dev, NULL);
 437         if (IS_ERR(rstc))
 438                 return dev_err_probe(dev, PTR_ERR(rstc), "Missing reset ctrl\n");
 439         /*
 440          * The reset also affects other HW that is not under the control
 441          * of Linux. Therefore, all we can do is deassert the reset.
 442          */
 443         reset_control_deassert(rstc);
 444
 445         irq = platform_get_irq(pdev, 0);
 446         if (irq < 0)
 447                 return irq;
 448
 449         ret = devm_request_irq(dev, irq, rzv2m_i2c_tia_irq_handler, 0,
 450                                dev_name(dev), priv);
 451         if (ret < 0)
 452                 return dev_err_probe(dev, ret, "Unable to request irq %d\n", irq);
 453
 454         adap = &priv->adap;
 455         adap->nr = pdev->id;
 456         adap->algo = &rzv2m_i2c_algo;
 457         adap->quirks = &rzv2m_i2c_quirks;
 458         adap->dev.parent = dev;
 459         adap->owner = THIS_MODULE;
 460         device_set_node(&adap->dev, dev_fwnode(dev));
 461         i2c_set_adapdata(adap, priv);
 462         strscpy(adap->name, pdev->name, sizeof(adap->name));
 463         init_completion(&priv->msg_tia_done);
 464
 465         ret = rzv2m_i2c_clock_calculate(dev, priv);
 466         if (ret < 0)
 467                 return ret;
 468
 469         pm_runtime_enable(dev);
 470
 471         pm_runtime_get_sync(dev);
 472         rzv2m_i2c_init(priv);
 473         pm_runtime_put(dev);
 474
 475         platform_set_drvdata(pdev, priv);
 476
 477         ret = i2c_add_numbered_adapter(adap);
 478         if (ret < 0) {
 479                 rzv2m_i2c_disable(dev, priv);
 480                 pm_runtime_disable(dev);
 481         }
 482
 483         return ret;
 484 }
 485
 486 static void rzv2m_i2c_remove(struct platform_device *pdev)
 487 {
 488         struct rzv2m_i2c_priv *priv = platform_get_drvdata(pdev);
 489         struct device *dev = priv->adap.dev.parent;
 490
 491         i2c_del_adapter(&priv->adap);
 492         rzv2m_i2c_disable(dev, priv);
 493         pm_runtime_disable(dev);
 494 }
 495
 496 static int rzv2m_i2c_suspend(struct device *dev)
 497 {
 498         struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
 499
 500         return rzv2m_i2c_disable(dev, priv);
 501 }
 502
 503 static int rzv2m_i2c_resume(struct device *dev)
 504 {
 505         struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
 506         int ret;
 507
 508         ret = rzv2m_i2c_clock_calculate(dev, priv);
 509         if (ret < 0)
 510                 return ret;
 511
 512         ret = pm_runtime_resume_and_get(dev);
 513         if (ret < 0)
 514                 return ret;
 515
 516         rzv2m_i2c_init(priv);
 517         pm_runtime_put(dev);
 518
 519         return 0;
 520 }
 521
 522 static const struct of_device_id rzv2m_i2c_ids[] = {
 523         { .compatible = "renesas,rzv2m-i2c" },
 524         { }
 525 };
 526 MODULE_DEVICE_TABLE(of, rzv2m_i2c_ids);
 527
 528 static const struct dev_pm_ops rzv2m_i2c_pm_ops = {
 529         SYSTEM_SLEEP_PM_OPS(rzv2m_i2c_suspend, rzv2m_i2c_resume)
 530 };
 531
 532 static struct platform_driver rzv2m_i2c_driver = {
 533         .driver = {
 534                 .name = "rzv2m-i2c",
 535                 .of_match_table = rzv2m_i2c_ids,
 536                 .pm = pm_sleep_ptr(&rzv2m_i2c_pm_ops),
 537         },
 538         .probe  = rzv2m_i2c_probe,
 539         .remove_new = rzv2m_i2c_remove,
 540 };
 541 module_platform_driver(rzv2m_i2c_driver);
 542
 543 MODULE_DESCRIPTION("RZ/V2M I2C bus driver");
 544 MODULE_AUTHOR("Renesas Electronics Corporation");
 545 MODULE_LICENSE("GPL");