2 * Driver for I2C adapter in Rockchip RK3xxx SoC
4 * Max Schwarz <max.schwarz@online.de>
5 * based on the patches by Rockchip Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/i2c.h>
15 #include <linux/interrupt.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/platform_device.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/spinlock.h>
23 #include <linux/clk.h>
24 #include <linux/wait.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/regmap.h>
30 #define REG_CON 0x00 /* control register */
31 #define REG_CLKDIV 0x04 /* clock divisor register */
32 #define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */
33 #define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */
34 #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */
35 #define REG_MRXCNT 0x14 /* number of bytes to be received */
36 #define REG_IEN 0x18 /* interrupt enable */
37 #define REG_IPD 0x1c /* interrupt pending */
38 #define REG_FCNT 0x20 /* finished count */
40 /* Data buffer offsets */
41 #define TXBUFFER_BASE 0x100
42 #define RXBUFFER_BASE 0x200
45 #define REG_CON_EN BIT(0)
47 REG_CON_MOD_TX = 0, /* transmit data */
48 REG_CON_MOD_REGISTER_TX, /* select register and restart */
49 REG_CON_MOD_RX, /* receive data */
50 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes
53 #define REG_CON_MOD(mod) ((mod) << 1)
54 #define REG_CON_MOD_MASK (BIT(1) | BIT(2))
55 #define REG_CON_START BIT(3)
56 #define REG_CON_STOP BIT(4)
57 #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */
58 #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */
60 /* REG_MRXADDR bits */
61 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
63 /* REG_IEN/REG_IPD bits */
64 #define REG_INT_BTF BIT(0) /* a byte was transmitted */
65 #define REG_INT_BRF BIT(1) /* a byte was received */
66 #define REG_INT_MBTF BIT(2) /* master data transmit finished */
67 #define REG_INT_MBRF BIT(3) /* master data receive finished */
68 #define REG_INT_START BIT(4) /* START condition generated */
69 #define REG_INT_STOP BIT(5) /* STOP condition generated */
70 #define REG_INT_NAKRCV BIT(6) /* NACK received */
71 #define REG_INT_ALL 0x7f
74 #define WAIT_TIMEOUT 200 /* ms */
75 #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */
86 * @grf_offset: offset inside the grf regmap for setting the i2c type
88 struct rk3x_i2c_soc_data {
93 struct i2c_adapter adap;
95 struct rk3x_i2c_soc_data *soc_data;
97 /* Hardware resources */
102 unsigned int scl_frequency;
104 /* Synchronization & notification */
106 wait_queue_head_t wait;
109 /* Current message */
115 /* I2C state machine */
116 enum rk3x_i2c_state state;
117 unsigned int processed; /* sent/received bytes */
121 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value,
124 writel(value, i2c->regs + offset);
127 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset)
129 return readl(i2c->regs + offset);
132 /* Reset all interrupt pending bits */
133 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
135 i2c_writel(i2c, REG_INT_ALL, REG_IPD);
139 * Generate a START condition, which triggers a REG_INT_START interrupt.
141 static void rk3x_i2c_start(struct rk3x_i2c *i2c)
145 rk3x_i2c_clean_ipd(i2c);
146 i2c_writel(i2c, REG_INT_START, REG_IEN);
148 /* enable adapter with correct mode, send START condition */
149 val = REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
151 /* if we want to react to NACK, set ACTACK bit */
152 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
153 val |= REG_CON_ACTACK;
155 i2c_writel(i2c, val, REG_CON);
159 * Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
161 * @error: Error code to return in rk3x_i2c_xfer
163 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
171 if (i2c->is_last_msg) {
172 /* Enable stop interrupt */
173 i2c_writel(i2c, REG_INT_STOP, REG_IEN);
175 i2c->state = STATE_STOP;
177 ctrl = i2c_readl(i2c, REG_CON);
178 ctrl |= REG_CON_STOP;
179 i2c_writel(i2c, ctrl, REG_CON);
181 /* Signal rk3x_i2c_xfer to start the next message. */
183 i2c->state = STATE_IDLE;
186 * The HW is actually not capable of REPEATED START. But we can
187 * get the intended effect by resetting its internal state
188 * and issuing an ordinary START.
190 i2c_writel(i2c, 0, REG_CON);
192 /* signal that we are finished with the current msg */
198 * Setup a read according to i2c->msg
200 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
202 unsigned int len = i2c->msg->len - i2c->processed;
205 con = i2c_readl(i2c, REG_CON);
208 * The hw can read up to 32 bytes at a time. If we need more than one
209 * chunk, send an ACK after the last byte of the current chunk.
211 if (unlikely(len > 32)) {
213 con &= ~REG_CON_LASTACK;
215 con |= REG_CON_LASTACK;
218 /* make sure we are in plain RX mode if we read a second chunk */
219 if (i2c->processed != 0) {
220 con &= ~REG_CON_MOD_MASK;
221 con |= REG_CON_MOD(REG_CON_MOD_RX);
224 i2c_writel(i2c, con, REG_CON);
225 i2c_writel(i2c, len, REG_MRXCNT);
229 * Fill the transmit buffer with data from i2c->msg
231 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c)
238 for (i = 0; i < 8; ++i) {
240 for (j = 0; j < 4; ++j) {
241 if (i2c->processed == i2c->msg->len)
244 if (i2c->processed == 0 && cnt == 0)
245 byte = (i2c->addr & 0x7f) << 1;
247 byte = i2c->msg->buf[i2c->processed++];
249 val |= byte << (j * 8);
253 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i);
255 if (i2c->processed == i2c->msg->len)
259 i2c_writel(i2c, cnt, REG_MTXCNT);
263 /* IRQ handlers for individual states */
265 static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd)
267 if (!(ipd & REG_INT_START)) {
268 rk3x_i2c_stop(i2c, -EIO);
269 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd);
270 rk3x_i2c_clean_ipd(i2c);
275 i2c_writel(i2c, REG_INT_START, REG_IPD);
277 /* disable start bit */
278 i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON);
280 /* enable appropriate interrupts and transition */
281 if (i2c->mode == REG_CON_MOD_TX) {
282 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN);
283 i2c->state = STATE_WRITE;
284 rk3x_i2c_fill_transmit_buf(i2c);
286 /* in any other case, we are going to be reading. */
287 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN);
288 i2c->state = STATE_READ;
289 rk3x_i2c_prepare_read(i2c);
293 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd)
295 if (!(ipd & REG_INT_MBTF)) {
296 rk3x_i2c_stop(i2c, -EIO);
297 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd);
298 rk3x_i2c_clean_ipd(i2c);
303 i2c_writel(i2c, REG_INT_MBTF, REG_IPD);
305 /* are we finished? */
306 if (i2c->processed == i2c->msg->len)
307 rk3x_i2c_stop(i2c, i2c->error);
309 rk3x_i2c_fill_transmit_buf(i2c);
312 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd)
315 unsigned int len = i2c->msg->len - i2c->processed;
316 u32 uninitialized_var(val);
319 /* we only care for MBRF here. */
320 if (!(ipd & REG_INT_MBRF))
324 i2c_writel(i2c, REG_INT_MBRF, REG_IPD);
326 /* Can only handle a maximum of 32 bytes at a time */
330 /* read the data from receive buffer */
331 for (i = 0; i < len; ++i) {
333 val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4);
335 byte = (val >> ((i % 4) * 8)) & 0xff;
336 i2c->msg->buf[i2c->processed++] = byte;
339 /* are we finished? */
340 if (i2c->processed == i2c->msg->len)
341 rk3x_i2c_stop(i2c, i2c->error);
343 rk3x_i2c_prepare_read(i2c);
346 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd)
350 if (!(ipd & REG_INT_STOP)) {
351 rk3x_i2c_stop(i2c, -EIO);
352 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd);
353 rk3x_i2c_clean_ipd(i2c);
358 i2c_writel(i2c, REG_INT_STOP, REG_IPD);
360 /* disable STOP bit */
361 con = i2c_readl(i2c, REG_CON);
362 con &= ~REG_CON_STOP;
363 i2c_writel(i2c, con, REG_CON);
366 i2c->state = STATE_IDLE;
368 /* signal rk3x_i2c_xfer that we are finished */
372 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id)
374 struct rk3x_i2c *i2c = dev_id;
377 spin_lock(&i2c->lock);
379 ipd = i2c_readl(i2c, REG_IPD);
380 if (i2c->state == STATE_IDLE) {
381 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd);
382 rk3x_i2c_clean_ipd(i2c);
386 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
388 /* Clean interrupt bits we don't care about */
389 ipd &= ~(REG_INT_BRF | REG_INT_BTF);
391 if (ipd & REG_INT_NAKRCV) {
393 * We got a NACK in the last operation. Depending on whether
394 * IGNORE_NAK is set, we have to stop the operation and report
397 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD);
399 ipd &= ~REG_INT_NAKRCV;
401 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
402 rk3x_i2c_stop(i2c, -ENXIO);
405 /* is there anything left to handle? */
406 if (unlikely((ipd & REG_INT_ALL) == 0))
409 switch (i2c->state) {
411 rk3x_i2c_handle_start(i2c, ipd);
414 rk3x_i2c_handle_write(i2c, ipd);
417 rk3x_i2c_handle_read(i2c, ipd);
420 rk3x_i2c_handle_stop(i2c, ipd);
427 spin_unlock(&i2c->lock);
431 static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
433 unsigned long i2c_rate = clk_get_rate(i2c->clk);
436 /* SCL rate = (clk rate) / (8 * DIV) */
437 div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
439 /* The lower and upper half of the CLKDIV reg describe the length of
440 * SCL low & high periods. */
441 div = DIV_ROUND_UP(div, 2);
443 i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
447 * Setup I2C registers for an I2C operation specified by msgs, num.
449 * Must be called with i2c->lock held.
451 * @msgs: I2C msgs to process
452 * @num: Number of msgs
454 * returns: Number of I2C msgs processed or negative in case of error
456 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
458 u32 addr = (msgs[0].addr & 0x7f) << 1;
462 * The I2C adapter can issue a small (len < 4) write packet before
463 * reading. This speeds up SMBus-style register reads.
464 * The MRXADDR/MRXRADDR hold the slave address and the slave register
465 * address in this case.
468 if (num >= 2 && msgs[0].len < 4 &&
469 !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
473 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n",
476 /* Fill MRXRADDR with the register address(es) */
477 for (i = 0; i < msgs[0].len; ++i) {
478 reg_addr |= msgs[0].buf[i] << (i * 8);
479 reg_addr |= REG_MRXADDR_VALID(i);
482 /* msgs[0] is handled by hw. */
485 i2c->mode = REG_CON_MOD_REGISTER_TX;
487 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
488 i2c_writel(i2c, reg_addr, REG_MRXRADDR);
493 * We'll have to do it the boring way and process the msgs
497 if (msgs[0].flags & I2C_M_RD) {
498 addr |= 1; /* set read bit */
501 * We have to transmit the slave addr first. Use
502 * MOD_REGISTER_TX for that purpose.
504 i2c->mode = REG_CON_MOD_REGISTER_TX;
505 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0),
507 i2c_writel(i2c, 0, REG_MRXRADDR);
509 i2c->mode = REG_CON_MOD_TX;
517 i2c->addr = msgs[0].addr;
519 i2c->state = STATE_START;
523 rk3x_i2c_clean_ipd(i2c);
528 static int rk3x_i2c_xfer(struct i2c_adapter *adap,
529 struct i2c_msg *msgs, int num)
531 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
532 unsigned long timeout, flags;
536 spin_lock_irqsave(&i2c->lock, flags);
538 clk_enable(i2c->clk);
540 /* The clock rate might have changed, so setup the divider again */
541 rk3x_i2c_set_scl_rate(i2c, i2c->scl_frequency);
543 i2c->is_last_msg = false;
546 * Process msgs. We can handle more than one message at once (see
549 for (i = 0; i < num; i += ret) {
550 ret = rk3x_i2c_setup(i2c, msgs + i, num - i);
553 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n");
558 i2c->is_last_msg = true;
560 spin_unlock_irqrestore(&i2c->lock, flags);
564 timeout = wait_event_timeout(i2c->wait, !i2c->busy,
565 msecs_to_jiffies(WAIT_TIMEOUT));
567 spin_lock_irqsave(&i2c->lock, flags);
570 dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n",
571 i2c_readl(i2c, REG_IPD), i2c->state);
573 /* Force a STOP condition without interrupt */
574 i2c_writel(i2c, 0, REG_IEN);
575 i2c_writel(i2c, REG_CON_EN | REG_CON_STOP, REG_CON);
577 i2c->state = STATE_IDLE;
589 clk_disable(i2c->clk);
590 spin_unlock_irqrestore(&i2c->lock, flags);
595 static u32 rk3x_i2c_func(struct i2c_adapter *adap)
597 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
600 static const struct i2c_algorithm rk3x_i2c_algorithm = {
601 .master_xfer = rk3x_i2c_xfer,
602 .functionality = rk3x_i2c_func,
605 static struct rk3x_i2c_soc_data soc_data[3] = {
606 { .grf_offset = 0x154 }, /* rk3066 */
607 { .grf_offset = 0x0a4 }, /* rk3188 */
608 { .grf_offset = -1 }, /* no I2C switching needed */
611 static const struct of_device_id rk3x_i2c_match[] = {
612 { .compatible = "rockchip,rk3066-i2c", .data = (void *)&soc_data[0] },
613 { .compatible = "rockchip,rk3188-i2c", .data = (void *)&soc_data[1] },
614 { .compatible = "rockchip,rk3288-i2c", .data = (void *)&soc_data[2] },
618 static int rk3x_i2c_probe(struct platform_device *pdev)
620 struct device_node *np = pdev->dev.of_node;
621 const struct of_device_id *match;
622 struct rk3x_i2c *i2c;
623 struct resource *mem;
629 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
633 match = of_match_node(rk3x_i2c_match, np);
634 i2c->soc_data = (struct rk3x_i2c_soc_data *)match->data;
636 if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
637 &i2c->scl_frequency)) {
638 dev_info(&pdev->dev, "using default SCL frequency: %d\n",
640 i2c->scl_frequency = DEFAULT_SCL_RATE;
643 if (i2c->scl_frequency == 0 || i2c->scl_frequency > 400 * 1000) {
644 dev_warn(&pdev->dev, "invalid SCL frequency specified.\n");
645 dev_warn(&pdev->dev, "using default SCL frequency: %d\n",
647 i2c->scl_frequency = DEFAULT_SCL_RATE;
650 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
651 i2c->adap.owner = THIS_MODULE;
652 i2c->adap.algo = &rk3x_i2c_algorithm;
653 i2c->adap.retries = 3;
654 i2c->adap.dev.of_node = np;
655 i2c->adap.algo_data = i2c;
656 i2c->adap.dev.parent = &pdev->dev;
658 i2c->dev = &pdev->dev;
660 spin_lock_init(&i2c->lock);
661 init_waitqueue_head(&i2c->wait);
663 i2c->clk = devm_clk_get(&pdev->dev, NULL);
664 if (IS_ERR(i2c->clk)) {
665 dev_err(&pdev->dev, "cannot get clock\n");
666 return PTR_ERR(i2c->clk);
669 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
670 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
671 if (IS_ERR(i2c->regs))
672 return PTR_ERR(i2c->regs);
674 /* Try to set the I2C adapter number from dt */
675 bus_nr = of_alias_get_id(np, "i2c");
678 * Switch to new interface if the SoC also offers the old one.
679 * The control bit is located in the GRF register space.
681 if (i2c->soc_data->grf_offset >= 0) {
684 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
687 "rk3x-i2c needs 'rockchip,grf' property\n");
692 dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias");
696 /* 27+i: write mask, 11+i: value */
697 value = BIT(27 + bus_nr) | BIT(11 + bus_nr);
699 ret = regmap_write(grf, i2c->soc_data->grf_offset, value);
701 dev_err(i2c->dev, "Could not write to GRF: %d\n", ret);
707 irq = platform_get_irq(pdev, 0);
709 dev_err(&pdev->dev, "cannot find rk3x IRQ\n");
713 ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq,
714 0, dev_name(&pdev->dev), i2c);
716 dev_err(&pdev->dev, "cannot request IRQ\n");
720 platform_set_drvdata(pdev, i2c);
722 ret = clk_prepare(i2c->clk);
724 dev_err(&pdev->dev, "Could not prepare clock\n");
728 ret = i2c_add_adapter(&i2c->adap);
730 dev_err(&pdev->dev, "Could not register adapter\n");
734 dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs);
739 clk_unprepare(i2c->clk);
743 static int rk3x_i2c_remove(struct platform_device *pdev)
745 struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
747 i2c_del_adapter(&i2c->adap);
748 clk_unprepare(i2c->clk);
753 static struct platform_driver rk3x_i2c_driver = {
754 .probe = rk3x_i2c_probe,
755 .remove = rk3x_i2c_remove,
757 .owner = THIS_MODULE,
759 .of_match_table = rk3x_i2c_match,
763 module_platform_driver(rk3x_i2c_driver);
765 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
766 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
767 MODULE_LICENSE("GPL v2");