4 * I2C adapter for the PXA I2C bus access.
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly separated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/init.h>
26 #include <linux/time.h>
27 #include <linux/sched.h>
28 #include <linux/delay.h>
29 #include <linux/errno.h>
30 #include <linux/interrupt.h>
31 #include <linux/i2c-pxa.h>
32 #include <linux/platform_device.h>
33 #include <linux/err.h>
34 #include <linux/clk.h>
35 #include <linux/slab.h>
42 * I2C register offsets will be shifted 0 or 1 bit left, depending on
45 #define REG_SHIFT_0 (0 << 0)
46 #define REG_SHIFT_1 (1 << 0)
47 #define REG_SHIFT(d) ((d) & 0x1)
49 static const struct platform_device_id i2c_pxa_id_table[] = {
50 { "pxa2xx-i2c", REG_SHIFT_1 },
51 { "pxa3xx-pwri2c", REG_SHIFT_0 },
54 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
57 * I2C registers and bit definitions
65 #define ICR_START (1 << 0) /* start bit */
66 #define ICR_STOP (1 << 1) /* stop bit */
67 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
68 #define ICR_TB (1 << 3) /* transfer byte bit */
69 #define ICR_MA (1 << 4) /* master abort */
70 #define ICR_SCLE (1 << 5) /* master clock enable */
71 #define ICR_IUE (1 << 6) /* unit enable */
72 #define ICR_GCD (1 << 7) /* general call disable */
73 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
74 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
75 #define ICR_BEIE (1 << 10) /* enable bus error ints */
76 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
77 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
78 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
79 #define ICR_UR (1 << 14) /* unit reset */
80 #define ICR_FM (1 << 15) /* fast mode */
82 #define ISR_RWM (1 << 0) /* read/write mode */
83 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
84 #define ISR_UB (1 << 2) /* unit busy */
85 #define ISR_IBB (1 << 3) /* bus busy */
86 #define ISR_SSD (1 << 4) /* slave stop detected */
87 #define ISR_ALD (1 << 5) /* arbitration loss detected */
88 #define ISR_ITE (1 << 6) /* tx buffer empty */
89 #define ISR_IRF (1 << 7) /* rx buffer full */
90 #define ISR_GCAD (1 << 8) /* general call address detected */
91 #define ISR_SAD (1 << 9) /* slave address detected */
92 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
96 wait_queue_head_t wait;
100 unsigned int msg_ptr;
101 unsigned int slave_addr;
103 struct i2c_adapter adap;
105 #ifdef CONFIG_I2C_PXA_SLAVE
106 struct i2c_slave_client *slave;
109 unsigned int irqlogidx;
113 void __iomem *reg_base;
114 unsigned int reg_shift;
116 unsigned long iobase;
117 unsigned long iosize;
120 unsigned int use_pio :1;
121 unsigned int fast_mode :1;
124 #define _IBMR(i2c) ((i2c)->reg_base + (0x0 << (i2c)->reg_shift))
125 #define _IDBR(i2c) ((i2c)->reg_base + (0x4 << (i2c)->reg_shift))
126 #define _ICR(i2c) ((i2c)->reg_base + (0x8 << (i2c)->reg_shift))
127 #define _ISR(i2c) ((i2c)->reg_base + (0xc << (i2c)->reg_shift))
128 #define _ISAR(i2c) ((i2c)->reg_base + (0x10 << (i2c)->reg_shift))
131 * I2C Slave mode address
133 #define I2C_PXA_SLAVE_ADDR 0x1
142 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
145 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
147 printk("%s %08x: ", prefix, val);
149 const char *str = val & bits->mask ? bits->set : bits->unset;
156 static const struct bits isr_bits[] = {
157 PXA_BIT(ISR_RWM, "RX", "TX"),
158 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
159 PXA_BIT(ISR_UB, "Bsy", "Rdy"),
160 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
161 PXA_BIT(ISR_SSD, "SlaveStop", NULL),
162 PXA_BIT(ISR_ALD, "ALD", NULL),
163 PXA_BIT(ISR_ITE, "TxEmpty", NULL),
164 PXA_BIT(ISR_IRF, "RxFull", NULL),
165 PXA_BIT(ISR_GCAD, "GenCall", NULL),
166 PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
167 PXA_BIT(ISR_BED, "BusErr", NULL),
170 static void decode_ISR(unsigned int val)
172 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
176 static const struct bits icr_bits[] = {
177 PXA_BIT(ICR_START, "START", NULL),
178 PXA_BIT(ICR_STOP, "STOP", NULL),
179 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
180 PXA_BIT(ICR_TB, "TB", NULL),
181 PXA_BIT(ICR_MA, "MA", NULL),
182 PXA_BIT(ICR_SCLE, "SCLE", "scle"),
183 PXA_BIT(ICR_IUE, "IUE", "iue"),
184 PXA_BIT(ICR_GCD, "GCD", NULL),
185 PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
186 PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
187 PXA_BIT(ICR_BEIE, "BEIE", NULL),
188 PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
189 PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
190 PXA_BIT(ICR_SADIE, "SADIE", NULL),
191 PXA_BIT(ICR_UR, "UR", "ur"),
194 #ifdef CONFIG_I2C_PXA_SLAVE
195 static void decode_ICR(unsigned int val)
197 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
202 static unsigned int i2c_debug = DEBUG;
204 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
206 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
207 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
210 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
212 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
215 printk(KERN_ERR "i2c: error: %s\n", why);
216 printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
217 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
218 printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n",
219 readl(_ICR(i2c)), readl(_ISR(i2c)));
220 printk(KERN_DEBUG "i2c: log: ");
221 for (i = 0; i < i2c->irqlogidx; i++)
222 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
226 #else /* ifdef DEBUG */
230 #define show_state(i2c) do { } while (0)
231 #define decode_ISR(val) do { } while (0)
232 #define decode_ICR(val) do { } while (0)
233 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
235 #endif /* ifdef DEBUG / else */
237 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
238 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
240 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
242 return !(readl(_ICR(i2c)) & ICR_SCLE);
245 static void i2c_pxa_abort(struct pxa_i2c *i2c)
249 if (i2c_pxa_is_slavemode(i2c)) {
250 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
254 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
255 unsigned long icr = readl(_ICR(i2c));
258 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
260 writel(icr, _ICR(i2c));
268 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
272 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
274 int timeout = DEF_TIMEOUT;
276 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
277 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
287 return timeout < 0 ? I2C_RETRY : 0;
290 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
292 unsigned long timeout = jiffies + HZ*4;
294 while (time_before(jiffies, timeout)) {
296 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
297 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
299 if (readl(_ISR(i2c)) & ISR_SAD) {
301 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
305 /* wait for unit and bus being not busy, and we also do a
306 * quick check of the i2c lines themselves to ensure they've
309 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
311 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
319 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
324 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
327 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
329 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
330 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
331 if (!i2c_pxa_wait_master(i2c)) {
332 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
337 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
341 #ifdef CONFIG_I2C_PXA_SLAVE
342 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
344 unsigned long timeout = jiffies + HZ*1;
350 while (time_before(jiffies, timeout)) {
352 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
353 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
355 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
356 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
357 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
359 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
367 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
372 * clear the hold on the bus, and take of anything else
373 * that has been configured
375 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
380 udelay(100); /* simple delay */
382 /* we need to wait for the stop condition to end */
384 /* if we where in stop, then clear... */
385 if (readl(_ICR(i2c)) & ICR_STOP) {
387 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
390 if (!i2c_pxa_wait_slave(i2c)) {
391 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
397 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
398 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
401 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
402 decode_ICR(readl(_ICR(i2c)));
406 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
409 static void i2c_pxa_reset(struct pxa_i2c *i2c)
411 pr_debug("Resetting I2C Controller Unit\n");
413 /* abort any transfer currently under way */
416 /* reset according to 9.8 */
417 writel(ICR_UR, _ICR(i2c));
418 writel(I2C_ISR_INIT, _ISR(i2c));
419 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
421 writel(i2c->slave_addr, _ISAR(i2c));
423 /* set control register values */
424 writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
426 #ifdef CONFIG_I2C_PXA_SLAVE
427 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
428 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
431 i2c_pxa_set_slave(i2c, 0);
434 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
439 #ifdef CONFIG_I2C_PXA_SLAVE
444 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
447 /* what should we do here? */
451 if (i2c->slave != NULL)
452 ret = i2c->slave->read(i2c->slave->data);
454 writel(ret, _IDBR(i2c));
455 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
459 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
461 unsigned int byte = readl(_IDBR(i2c));
463 if (i2c->slave != NULL)
464 i2c->slave->write(i2c->slave->data, byte);
466 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
469 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
474 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
475 (isr & ISR_RWM) ? 'r' : 't');
477 if (i2c->slave != NULL)
478 i2c->slave->event(i2c->slave->data,
479 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
482 * slave could interrupt in the middle of us generating a
483 * start condition... if this happens, we'd better back off
484 * and stop holding the poor thing up
486 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
487 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
492 if ((readl(_IBMR(i2c)) & 2) == 2)
498 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
503 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
506 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
509 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
511 if (i2c->slave != NULL)
512 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
515 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
518 * If we have a master-mode message waiting,
519 * kick it off now that the slave has completed.
522 i2c_pxa_master_complete(i2c, I2C_RETRY);
525 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
528 /* what should we do here? */
530 writel(0, _IDBR(i2c));
531 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
535 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
537 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
540 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
545 * slave could interrupt in the middle of us generating a
546 * start condition... if this happens, we'd better back off
547 * and stop holding the poor thing up
549 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
550 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
555 if ((readl(_IBMR(i2c)) & 2) == 2)
561 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
566 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
569 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
572 i2c_pxa_master_complete(i2c, I2C_RETRY);
577 * PXA I2C Master mode
580 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
582 unsigned int addr = (msg->addr & 0x7f) << 1;
584 if (msg->flags & I2C_M_RD)
590 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
595 * Step 1: target slave address into IDBR
597 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
600 * Step 2: initiate the write.
602 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
603 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
606 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
611 * Clear the STOP and ACK flags
613 icr = readl(_ICR(i2c));
614 icr &= ~(ICR_STOP | ICR_ACKNAK);
615 writel(icr, _ICR(i2c));
618 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
620 /* make timeout the same as for interrupt based functions */
621 long timeout = 2 * DEF_TIMEOUT;
624 * Wait for the bus to become free.
626 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
633 dev_err(&i2c->adap.dev,
634 "i2c_pxa: timeout waiting for bus free\n");
641 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
646 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
647 struct i2c_msg *msg, int num)
649 unsigned long timeout = 500000; /* 5 seconds */
652 ret = i2c_pxa_pio_set_master(i2c);
662 i2c_pxa_start_message(i2c);
664 while (i2c->msg_num > 0 && --timeout) {
665 i2c_pxa_handler(0, i2c);
669 i2c_pxa_stop_message(i2c);
672 * We place the return code in i2c->msg_idx.
678 i2c_pxa_scream_blue_murder(i2c, "timeout");
684 * We are protected by the adapter bus mutex.
686 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
692 * Wait for the bus to become free.
694 ret = i2c_pxa_wait_bus_not_busy(i2c);
696 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
703 ret = i2c_pxa_set_master(i2c);
705 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
709 spin_lock_irq(&i2c->lock);
717 i2c_pxa_start_message(i2c);
719 spin_unlock_irq(&i2c->lock);
722 * The rest of the processing occurs in the interrupt handler.
724 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
725 i2c_pxa_stop_message(i2c);
728 * We place the return code in i2c->msg_idx.
733 i2c_pxa_scream_blue_murder(i2c, "timeout");
739 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
740 struct i2c_msg msgs[], int num)
742 struct pxa_i2c *i2c = adap->algo_data;
745 /* If the I2C controller is disabled we need to reset it
746 (probably due to a suspend/resume destroying state). We do
747 this here as we can then avoid worrying about resuming the
748 controller before its users. */
749 if (!(readl(_ICR(i2c)) & ICR_IUE))
752 for (i = adap->retries; i >= 0; i--) {
753 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
754 if (ret != I2C_RETRY)
758 dev_dbg(&adap->dev, "Retrying transmission\n");
761 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
764 i2c_pxa_set_slave(i2c, ret);
769 * i2c_pxa_master_complete - complete the message and wake up.
771 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
783 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
785 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
789 * If ISR_ALD is set, we lost arbitration.
793 * Do we need to do anything here? The PXA docs
794 * are vague about what happens.
796 i2c_pxa_scream_blue_murder(i2c, "ALD set");
799 * We ignore this error. We seem to see spurious ALDs
800 * for seemingly no reason. If we handle them as I think
801 * they should, we end up causing an I2C error, which
802 * is painful for some systems.
811 * I2C bus error - either the device NAK'd us, or
812 * something more serious happened. If we were NAK'd
813 * on the initial address phase, we can retry.
815 if (isr & ISR_ACKNAK) {
816 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
821 i2c_pxa_master_complete(i2c, ret);
822 } else if (isr & ISR_RWM) {
824 * Read mode. We have just sent the address byte, and
825 * now we must initiate the transfer.
827 if (i2c->msg_ptr == i2c->msg->len - 1 &&
828 i2c->msg_idx == i2c->msg_num - 1)
829 icr |= ICR_STOP | ICR_ACKNAK;
831 icr |= ICR_ALDIE | ICR_TB;
832 } else if (i2c->msg_ptr < i2c->msg->len) {
834 * Write mode. Write the next data byte.
836 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
838 icr |= ICR_ALDIE | ICR_TB;
841 * If this is the last byte of the last message, send
844 if (i2c->msg_ptr == i2c->msg->len &&
845 i2c->msg_idx == i2c->msg_num - 1)
847 } else if (i2c->msg_idx < i2c->msg_num - 1) {
849 * Next segment of the message.
856 * If we aren't doing a repeated start and address,
857 * go back and try to send the next byte. Note that
858 * we do not support switching the R/W direction here.
860 if (i2c->msg->flags & I2C_M_NOSTART)
864 * Write the next address.
866 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
869 * And trigger a repeated start, and send the byte.
872 icr |= ICR_START | ICR_TB;
874 if (i2c->msg->len == 0) {
876 * Device probes have a message length of zero
877 * and need the bus to be reset before it can
882 i2c_pxa_master_complete(i2c, 0);
885 i2c->icrlog[i2c->irqlogidx-1] = icr;
887 writel(icr, _ICR(i2c));
891 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
893 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
898 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
900 if (i2c->msg_ptr < i2c->msg->len) {
902 * If this is the last byte of the last
903 * message, send a STOP.
905 if (i2c->msg_ptr == i2c->msg->len - 1)
906 icr |= ICR_STOP | ICR_ACKNAK;
908 icr |= ICR_ALDIE | ICR_TB;
910 i2c_pxa_master_complete(i2c, 0);
913 i2c->icrlog[i2c->irqlogidx-1] = icr;
915 writel(icr, _ICR(i2c));
918 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
920 struct pxa_i2c *i2c = dev_id;
921 u32 isr = readl(_ISR(i2c));
923 if (i2c_debug > 2 && 0) {
924 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
925 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
929 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
930 i2c->isrlog[i2c->irqlogidx++] = isr;
935 * Always clear all pending IRQs.
937 writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
940 i2c_pxa_slave_start(i2c, isr);
942 i2c_pxa_slave_stop(i2c);
944 if (i2c_pxa_is_slavemode(i2c)) {
946 i2c_pxa_slave_txempty(i2c, isr);
948 i2c_pxa_slave_rxfull(i2c, isr);
949 } else if (i2c->msg) {
951 i2c_pxa_irq_txempty(i2c, isr);
953 i2c_pxa_irq_rxfull(i2c, isr);
955 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
962 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
964 struct pxa_i2c *i2c = adap->algo_data;
967 for (i = adap->retries; i >= 0; i--) {
968 ret = i2c_pxa_do_xfer(i2c, msgs, num);
969 if (ret != I2C_RETRY)
973 dev_dbg(&adap->dev, "Retrying transmission\n");
976 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
979 i2c_pxa_set_slave(i2c, ret);
983 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
985 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
988 static const struct i2c_algorithm i2c_pxa_algorithm = {
989 .master_xfer = i2c_pxa_xfer,
990 .functionality = i2c_pxa_functionality,
993 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
994 .master_xfer = i2c_pxa_pio_xfer,
995 .functionality = i2c_pxa_functionality,
998 static int i2c_pxa_probe(struct platform_device *dev)
1000 struct pxa_i2c *i2c;
1001 struct resource *res;
1002 struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
1003 const struct platform_device_id *id = platform_get_device_id(dev);
1007 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1008 irq = platform_get_irq(dev, 0);
1009 if (res == NULL || irq < 0)
1012 if (!request_mem_region(res->start, resource_size(res), res->name))
1015 i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
1021 i2c->adap.owner = THIS_MODULE;
1022 i2c->adap.retries = 5;
1024 spin_lock_init(&i2c->lock);
1025 init_waitqueue_head(&i2c->wait);
1028 * If "dev->id" is negative we consider it as zero.
1029 * The reason to do so is to avoid sysfs names that only make
1030 * sense when there are multiple adapters.
1032 i2c->adap.nr = dev->id != -1 ? dev->id : 0;
1033 snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u",
1036 i2c->clk = clk_get(&dev->dev, NULL);
1037 if (IS_ERR(i2c->clk)) {
1038 ret = PTR_ERR(i2c->clk);
1042 i2c->reg_base = ioremap(res->start, resource_size(res));
1043 if (!i2c->reg_base) {
1047 i2c->reg_shift = REG_SHIFT(id->driver_data);
1049 i2c->iobase = res->start;
1050 i2c->iosize = resource_size(res);
1054 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1056 #ifdef CONFIG_I2C_PXA_SLAVE
1058 i2c->slave_addr = plat->slave_addr;
1059 i2c->slave = plat->slave;
1063 clk_enable(i2c->clk);
1066 i2c->adap.class = plat->class;
1067 i2c->use_pio = plat->use_pio;
1068 i2c->fast_mode = plat->fast_mode;
1072 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1074 i2c->adap.algo = &i2c_pxa_algorithm;
1075 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
1076 i2c->adap.name, i2c);
1083 i2c->adap.algo_data = i2c;
1084 i2c->adap.dev.parent = &dev->dev;
1086 ret = i2c_add_numbered_adapter(&i2c->adap);
1088 printk(KERN_INFO "I2C: Failed to add bus\n");
1092 platform_set_drvdata(dev, i2c);
1094 #ifdef CONFIG_I2C_PXA_SLAVE
1095 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1096 dev_name(&i2c->adap.dev), i2c->slave_addr);
1098 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1099 dev_name(&i2c->adap.dev));
1107 clk_disable(i2c->clk);
1108 iounmap(i2c->reg_base);
1114 release_mem_region(res->start, resource_size(res));
1118 static int __exit i2c_pxa_remove(struct platform_device *dev)
1120 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1122 platform_set_drvdata(dev, NULL);
1124 i2c_del_adapter(&i2c->adap);
1126 free_irq(i2c->irq, i2c);
1128 clk_disable(i2c->clk);
1131 iounmap(i2c->reg_base);
1132 release_mem_region(i2c->iobase, i2c->iosize);
1139 static int i2c_pxa_suspend_noirq(struct device *dev)
1141 struct platform_device *pdev = to_platform_device(dev);
1142 struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1144 clk_disable(i2c->clk);
1149 static int i2c_pxa_resume_noirq(struct device *dev)
1151 struct platform_device *pdev = to_platform_device(dev);
1152 struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1154 clk_enable(i2c->clk);
1160 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1161 .suspend_noirq = i2c_pxa_suspend_noirq,
1162 .resume_noirq = i2c_pxa_resume_noirq,
1165 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1167 #define I2C_PXA_DEV_PM_OPS NULL
1170 static struct platform_driver i2c_pxa_driver = {
1171 .probe = i2c_pxa_probe,
1172 .remove = __exit_p(i2c_pxa_remove),
1174 .name = "pxa2xx-i2c",
1175 .owner = THIS_MODULE,
1176 .pm = I2C_PXA_DEV_PM_OPS,
1178 .id_table = i2c_pxa_id_table,
1181 static int __init i2c_adap_pxa_init(void)
1183 return platform_driver_register(&i2c_pxa_driver);
1186 static void __exit i2c_adap_pxa_exit(void)
1188 platform_driver_unregister(&i2c_pxa_driver);
1191 MODULE_LICENSE("GPL");
1192 MODULE_ALIAS("platform:pxa2xx-i2c");
1194 subsys_initcall(i2c_adap_pxa_init);
1195 module_exit(i2c_adap_pxa_exit);