2 * Freescale MXS I2C bus driver
4 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
5 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
7 * based on a (non-working) driver which was:
9 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
18 #include <linux/slab.h>
19 #include <linux/device.h>
20 #include <linux/module.h>
21 #include <linux/i2c.h>
22 #include <linux/err.h>
23 #include <linux/interrupt.h>
24 #include <linux/completion.h>
25 #include <linux/platform_device.h>
26 #include <linux/jiffies.h>
28 #include <linux/stmp_device.h>
30 #include <linux/of_device.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/dmaengine.h>
34 #define DRIVER_NAME "mxs-i2c"
36 #define MXS_I2C_CTRL0 (0x00)
37 #define MXS_I2C_CTRL0_SET (0x04)
38 #define MXS_I2C_CTRL0_CLR (0x08)
40 #define MXS_I2C_CTRL0_SFTRST 0x80000000
41 #define MXS_I2C_CTRL0_RUN 0x20000000
42 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
43 #define MXS_I2C_CTRL0_PIO_MODE 0x01000000
44 #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
45 #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
46 #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
47 #define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
48 #define MXS_I2C_CTRL0_DIRECTION 0x00010000
49 #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
51 #define MXS_I2C_TIMING0 (0x10)
52 #define MXS_I2C_TIMING1 (0x20)
53 #define MXS_I2C_TIMING2 (0x30)
55 #define MXS_I2C_CTRL1 (0x40)
56 #define MXS_I2C_CTRL1_SET (0x44)
57 #define MXS_I2C_CTRL1_CLR (0x48)
59 #define MXS_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
60 #define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
61 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
62 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
63 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
64 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
65 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
66 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
67 #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
69 #define MXS_I2C_STAT (0x50)
70 #define MXS_I2C_STAT_GOT_A_NAK 0x10000000
71 #define MXS_I2C_STAT_BUS_BUSY 0x00000800
72 #define MXS_I2C_STAT_CLK_GEN_BUSY 0x00000400
74 #define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
76 #define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
78 #define MXS_I2C_DEBUG0_DMAREQ 0x80000000
80 #define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
81 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
82 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
83 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
84 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
85 MXS_I2C_CTRL1_SLAVE_IRQ)
88 #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
89 MXS_I2C_CTRL0_PRE_SEND_START | \
90 MXS_I2C_CTRL0_MASTER_MODE | \
91 MXS_I2C_CTRL0_DIRECTION | \
92 MXS_I2C_CTRL0_XFER_COUNT(1))
94 #define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
95 MXS_I2C_CTRL0_MASTER_MODE | \
96 MXS_I2C_CTRL0_DIRECTION)
98 #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
99 MXS_I2C_CTRL0_MASTER_MODE)
101 enum mxs_i2c_devtype {
108 * struct mxs_i2c_dev - per device, private MXS-I2C data
110 * @dev: driver model device node
111 * @dev_type: distinguish i.MX23/i.MX28 features
112 * @regs: IO registers pointer
113 * @cmd_complete: completion object for transaction wait
114 * @cmd_err: error code for last transaction
115 * @adapter: i2c subsystem adapter node
119 enum mxs_i2c_devtype dev_type;
121 struct completion cmd_complete;
123 struct i2c_adapter adapter;
129 /* DMA support components */
130 struct dma_chan *dmach;
131 uint32_t pio_data[2];
133 struct scatterlist sg_io[2];
137 static int mxs_i2c_reset(struct mxs_i2c_dev *i2c)
139 int ret = stmp_reset_block(i2c->regs);
144 * Configure timing for the I2C block. The I2C TIMING2 register has to
145 * be programmed with this particular magic number. The rest is derived
146 * from the XTAL speed and requested I2C speed.
148 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
150 writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
151 writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
152 writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2);
154 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
159 static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
162 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
163 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
165 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
169 static void mxs_i2c_dma_irq_callback(void *param)
171 struct mxs_i2c_dev *i2c = param;
173 complete(&i2c->cmd_complete);
174 mxs_i2c_dma_finish(i2c);
177 static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
178 struct i2c_msg *msg, uint32_t flags)
180 struct dma_async_tx_descriptor *desc;
181 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
183 i2c->addr_data = i2c_8bit_addr_from_msg(msg);
185 if (msg->flags & I2C_M_RD) {
186 i2c->dma_read = true;
192 /* Queue the PIO register write transfer. */
193 i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
194 desc = dmaengine_prep_slave_sg(i2c->dmach,
195 (struct scatterlist *)&i2c->pio_data[0],
196 1, DMA_TRANS_NONE, 0);
199 "Failed to get PIO reg. write descriptor.\n");
200 goto select_init_pio_fail;
203 /* Queue the DMA data transfer. */
204 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
205 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
206 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
208 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
211 "Failed to get DMA data write descriptor.\n");
212 goto select_init_dma_fail;
219 /* Queue the PIO register write transfer. */
220 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
221 MXS_I2C_CTRL0_XFER_COUNT(msg->len);
222 desc = dmaengine_prep_slave_sg(i2c->dmach,
223 (struct scatterlist *)&i2c->pio_data[1],
224 1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
227 "Failed to get PIO reg. write descriptor.\n");
228 goto select_init_dma_fail;
231 /* Queue the DMA data transfer. */
232 sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
233 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
234 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
236 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
239 "Failed to get DMA data write descriptor.\n");
240 goto read_init_dma_fail;
243 i2c->dma_read = false;
249 /* Queue the PIO register write transfer. */
250 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
251 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
252 desc = dmaengine_prep_slave_sg(i2c->dmach,
253 (struct scatterlist *)&i2c->pio_data[0],
254 1, DMA_TRANS_NONE, 0);
257 "Failed to get PIO reg. write descriptor.\n");
258 goto write_init_pio_fail;
261 /* Queue the DMA data transfer. */
262 sg_init_table(i2c->sg_io, 2);
263 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
264 sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
265 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
266 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
268 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
271 "Failed to get DMA data write descriptor.\n");
272 goto write_init_dma_fail;
277 * The last descriptor must have this callback,
278 * to finish the DMA transaction.
280 desc->callback = mxs_i2c_dma_irq_callback;
281 desc->callback_param = i2c;
283 /* Start the transfer. */
284 dmaengine_submit(desc);
285 dma_async_issue_pending(i2c->dmach);
290 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
291 select_init_dma_fail:
292 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
293 select_init_pio_fail:
294 dmaengine_terminate_all(i2c->dmach);
297 /* Write failpath. */
299 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
301 dmaengine_terminate_all(i2c->dmach);
305 static int mxs_i2c_pio_wait_xfer_end(struct mxs_i2c_dev *i2c)
307 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
309 while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) {
310 if (readl(i2c->regs + MXS_I2C_CTRL1) &
311 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
313 if (time_after(jiffies, timeout))
321 static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c)
325 state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;
327 if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
328 i2c->cmd_err = -ENXIO;
329 else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
330 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
331 MXS_I2C_CTRL1_SLAVE_STOP_IRQ |
332 MXS_I2C_CTRL1_SLAVE_IRQ))
338 static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)
342 writel(cmd, i2c->regs + MXS_I2C_CTRL0);
344 /* readback makes sure the write is latched into hardware */
345 reg = readl(i2c->regs + MXS_I2C_CTRL0);
346 reg |= MXS_I2C_CTRL0_RUN;
347 writel(reg, i2c->regs + MXS_I2C_CTRL0);
351 * Start WRITE transaction on the I2C bus. By studying i.MX23 datasheet,
352 * CTRL0::PIO_MODE bit description clarifies the order in which the registers
353 * must be written during PIO mode operation. First, the CTRL0 register has
354 * to be programmed with all the necessary bits but the RUN bit. Then the
355 * payload has to be written into the DATA register. Finally, the transmission
356 * is executed by setting the RUN bit in CTRL0.
358 static void mxs_i2c_pio_trigger_write_cmd(struct mxs_i2c_dev *i2c, u32 cmd,
361 writel(cmd, i2c->regs + MXS_I2C_CTRL0);
363 if (i2c->dev_type == MXS_I2C_V1)
364 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET);
366 writel(data, i2c->regs + MXS_I2C_DATA(i2c));
367 writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET);
370 static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
371 struct i2c_msg *msg, uint32_t flags)
373 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
374 uint32_t addr_data = i2c_8bit_addr_from_msg(msg);
376 int i, ret, xlen = 0, xmit = 0;
379 /* Mute IRQs coming from this block. */
380 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
384 * - Enable CTRL0::PIO_MODE (1 << 24)
385 * - Enable CTRL1::ACK_MODE (1 << 27)
387 * WARNING! The MX23 is broken in some way, even if it claims
388 * to support PIO, when we try to transfer any amount of data
389 * that is not aligned to 4 bytes, the DMA engine will have
390 * bits in DEBUG1::DMA_BYTES_ENABLES still set even after the
391 * transfer. This in turn will mess up the next transfer as
392 * the block it emit one byte write onto the bus terminated
393 * with a NAK+STOP. A possible workaround is to reset the IP
394 * block after every PIO transmission, which might just work.
396 * NOTE: The CTRL0::PIO_MODE description is important, since
397 * it outlines how the PIO mode is really supposed to work.
399 if (msg->flags & I2C_M_RD) {
403 * This transfer MUST be limited to 4 bytes maximum. It is not
404 * possible to transfer more than four bytes via PIO, since we
405 * can not in any way make sure we can read the data from the
406 * DATA register fast enough. Besides, the RX FIFO is only four
407 * bytes deep, thus we can only really read up to four bytes at
408 * time. Finally, there is no bit indicating us that new data
409 * arrived at the FIFO and can thus be fetched from the DATA
412 BUG_ON(msg->len > 4);
414 /* SELECT command. */
415 mxs_i2c_pio_trigger_write_cmd(i2c, MXS_CMD_I2C_SELECT,
418 ret = mxs_i2c_pio_wait_xfer_end(i2c);
421 "PIO: Failed to send SELECT command!\n");
426 mxs_i2c_pio_trigger_cmd(i2c,
427 MXS_CMD_I2C_READ | flags |
428 MXS_I2C_CTRL0_XFER_COUNT(msg->len));
430 ret = mxs_i2c_pio_wait_xfer_end(i2c);
433 "PIO: Failed to send READ command!\n");
437 data = readl(i2c->regs + MXS_I2C_DATA(i2c));
438 for (i = 0; i < msg->len; i++) {
439 msg->buf[i] = data & 0xff;
444 * PIO WRITE transfer:
446 * The code below implements clock stretching to circumvent
447 * the possibility of kernel not being able to supply data
448 * fast enough. It is possible to transfer arbitrary amount
449 * of data using PIO write.
453 * The LSB of data buffer is the first byte blasted across
454 * the bus. Higher order bytes follow. Thus the following
458 data = addr_data << 24;
460 /* Start the transfer with START condition. */
461 start = MXS_I2C_CTRL0_PRE_SEND_START;
463 /* If the transfer is long, use clock stretching. */
465 start |= MXS_I2C_CTRL0_RETAIN_CLOCK;
467 for (i = 0; i < msg->len; i++) {
469 data |= (msg->buf[i] << 24);
473 /* This is the last transfer of the message. */
474 if (i + 1 == msg->len) {
475 /* Add optional STOP flag. */
477 /* Remove RETAIN_CLOCK bit. */
478 start &= ~MXS_I2C_CTRL0_RETAIN_CLOCK;
482 /* Four bytes are ready in the "data" variable. */
486 /* Nothing interesting happened, continue stuffing. */
491 * Compute the size of the transfer and shift the
494 * i = (4k + 0) .... xlen = 2
495 * i = (4k + 1) .... xlen = 3
496 * i = (4k + 2) .... xlen = 4
497 * i = (4k + 3) .... xlen = 1
505 data >>= (4 - xlen) * 8;
508 "PIO: len=%i pos=%i total=%i [W%s%s%s]\n",
510 start & MXS_I2C_CTRL0_PRE_SEND_START ? "S" : "",
511 start & MXS_I2C_CTRL0_POST_SEND_STOP ? "E" : "",
512 start & MXS_I2C_CTRL0_RETAIN_CLOCK ? "C" : "");
514 writel(MXS_I2C_DEBUG0_DMAREQ,
515 i2c->regs + MXS_I2C_DEBUG0_CLR(i2c));
517 mxs_i2c_pio_trigger_write_cmd(i2c,
518 start | MXS_I2C_CTRL0_MASTER_MODE |
519 MXS_I2C_CTRL0_DIRECTION |
520 MXS_I2C_CTRL0_XFER_COUNT(xlen), data);
522 /* The START condition is sent only once. */
523 start &= ~MXS_I2C_CTRL0_PRE_SEND_START;
525 /* Wait for the end of the transfer. */
526 ret = mxs_i2c_pio_wait_xfer_end(i2c);
529 "PIO: Failed to finish WRITE cmd!\n");
533 /* Check NAK here. */
534 ret = readl(i2c->regs + MXS_I2C_STAT) &
535 MXS_I2C_STAT_GOT_A_NAK;
543 /* make sure we capture any occurred error into cmd_err */
544 ret = mxs_i2c_pio_check_error_state(i2c);
547 /* Clear any dangling IRQs and re-enable interrupts. */
548 writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
549 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
551 /* Clear the PIO_MODE on i.MX23 */
552 if (i2c->dev_type == MXS_I2C_V1)
553 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR);
559 * Low level master read/write transaction.
561 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
564 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
568 unsigned long time_left;
570 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
572 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
573 msg->addr, msg->len, msg->flags, stop);
579 * The MX28 I2C IP block can only do PIO READ for transfer of to up
580 * 4 bytes of length. The write transfer is not limited as it can use
581 * clock stretching to avoid FIFO underruns.
583 if ((msg->flags & I2C_M_RD) && (msg->len <= 4))
585 if (!(msg->flags & I2C_M_RD) && (msg->len < 7))
590 ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
591 /* No need to reset the block if NAK was received. */
592 if (ret && (ret != -ENXIO))
595 reinit_completion(&i2c->cmd_complete);
596 ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
600 time_left = wait_for_completion_timeout(&i2c->cmd_complete,
601 msecs_to_jiffies(1000));
610 * If the transfer fails with a NAK from the slave the
611 * controller halts until it gets told to return to idle state.
613 writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,
614 i2c->regs + MXS_I2C_CTRL1_SET);
619 * The i.MX23 is strange. After each and every operation, it's I2C IP
620 * block must be reset, otherwise the IP block will misbehave. This can
621 * be observed on the bus by the block sending out one single byte onto
622 * the bus. In case such an error happens, bit 27 will be set in the
623 * DEBUG0 register. This bit is not documented in the i.MX23 datasheet
624 * and is marked as "TBD" instead. To reset this bit to a correct state,
625 * reset the whole block. Since the block reset does not take long, do
626 * reset the block after every transfer to play safe.
628 if (i2c->dev_type == MXS_I2C_V1)
631 dev_dbg(i2c->dev, "Done with err=%d\n", ret);
636 dev_dbg(i2c->dev, "Timeout!\n");
637 mxs_i2c_dma_finish(i2c);
638 ret = mxs_i2c_reset(i2c);
645 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
651 for (i = 0; i < num; i++) {
652 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
660 static u32 mxs_i2c_func(struct i2c_adapter *adap)
662 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
665 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
667 struct mxs_i2c_dev *i2c = dev_id;
668 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
673 if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
674 i2c->cmd_err = -ENXIO;
675 else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
676 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
677 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
678 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
681 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
686 static const struct i2c_algorithm mxs_i2c_algo = {
687 .master_xfer = mxs_i2c_xfer,
688 .functionality = mxs_i2c_func,
691 static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed)
693 /* The I2C block clock runs at 24MHz */
694 const uint32_t clk = 24000000;
696 uint16_t high_count, low_count, rcv_count, xmit_count;
697 uint32_t bus_free, leadin;
698 struct device *dev = i2c->dev;
700 divider = DIV_ROUND_UP(clk, speed);
704 * limit the divider, so that min(low_count, high_count)
709 "Speed too high (%u.%03u kHz), using %u.%03u kHz\n",
710 speed / 1000, speed % 1000,
711 clk / divider / 1000, clk / divider % 1000);
712 } else if (divider > 1897) {
714 * limit the divider, so that max(low_count, high_count)
719 "Speed too low (%u.%03u kHz), using %u.%03u kHz\n",
720 speed / 1000, speed % 1000,
721 clk / divider / 1000, clk / divider % 1000);
725 * The I2C spec specifies the following timing data:
726 * standard mode fast mode Bitfield name
727 * tLOW (SCL LOW period) 4700 ns 1300 ns
728 * tHIGH (SCL HIGH period) 4000 ns 600 ns
729 * tSU;DAT (data setup time) 250 ns 100 ns
730 * tHD;STA (START hold time) 4000 ns 600 ns
731 * tBUF (bus free time) 4700 ns 1300 ns
733 * The hardware (of the i.MX28 at least) seems to add 2 additional
734 * clock cycles to the low_count and 7 cycles to the high_count.
735 * This is compensated for by subtracting the respective constants
736 * from the values written to the timing registers.
738 if (speed > 100000) {
740 low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6));
741 high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6));
742 leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000);
743 bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000);
746 low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40));
747 high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40));
748 leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
749 bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
751 rcv_count = high_count * 3 / 8;
752 xmit_count = low_count * 3 / 8;
755 "speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n",
756 speed, clk / divider, divider, low_count, high_count,
757 xmit_count, rcv_count, leadin, bus_free);
761 i2c->timing0 = (high_count << 16) | rcv_count;
762 i2c->timing1 = (low_count << 16) | xmit_count;
763 i2c->timing2 = (bus_free << 16 | leadin);
766 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
769 struct device *dev = i2c->dev;
770 struct device_node *node = dev->of_node;
773 ret = of_property_read_u32(node, "clock-frequency", &speed);
775 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
779 mxs_i2c_derive_timing(i2c, speed);
784 static const struct platform_device_id mxs_i2c_devtype[] = {
787 .driver_data = MXS_I2C_V1,
790 .driver_data = MXS_I2C_V2,
791 }, { /* sentinel */ }
793 MODULE_DEVICE_TABLE(platform, mxs_i2c_devtype);
795 static const struct of_device_id mxs_i2c_dt_ids[] = {
796 { .compatible = "fsl,imx23-i2c", .data = &mxs_i2c_devtype[0], },
797 { .compatible = "fsl,imx28-i2c", .data = &mxs_i2c_devtype[1], },
800 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
802 static int mxs_i2c_probe(struct platform_device *pdev)
804 const struct of_device_id *of_id =
805 of_match_device(mxs_i2c_dt_ids, &pdev->dev);
806 struct device *dev = &pdev->dev;
807 struct mxs_i2c_dev *i2c;
808 struct i2c_adapter *adap;
809 struct resource *res;
812 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
817 const struct platform_device_id *device_id = of_id->data;
818 i2c->dev_type = device_id->driver_data;
821 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
822 i2c->regs = devm_ioremap_resource(&pdev->dev, res);
823 if (IS_ERR(i2c->regs))
824 return PTR_ERR(i2c->regs);
826 irq = platform_get_irq(pdev, 0);
830 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
836 init_completion(&i2c->cmd_complete);
839 err = mxs_i2c_get_ofdata(i2c);
845 i2c->dmach = dma_request_slave_channel(dev, "rx-tx");
847 dev_err(dev, "Failed to request dma\n");
851 platform_set_drvdata(pdev, i2c);
853 /* Do reset to enforce correct startup after pinmuxing */
854 err = mxs_i2c_reset(i2c);
858 adap = &i2c->adapter;
859 strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
860 adap->owner = THIS_MODULE;
861 adap->algo = &mxs_i2c_algo;
862 adap->dev.parent = dev;
864 adap->dev.of_node = pdev->dev.of_node;
865 i2c_set_adapdata(adap, i2c);
866 err = i2c_add_numbered_adapter(adap);
868 writel(MXS_I2C_CTRL0_SFTRST,
869 i2c->regs + MXS_I2C_CTRL0_SET);
876 static int mxs_i2c_remove(struct platform_device *pdev)
878 struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
880 i2c_del_adapter(&i2c->adapter);
883 dma_release_channel(i2c->dmach);
885 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
890 static struct platform_driver mxs_i2c_driver = {
893 .of_match_table = mxs_i2c_dt_ids,
895 .probe = mxs_i2c_probe,
896 .remove = mxs_i2c_remove,
899 static int __init mxs_i2c_init(void)
901 return platform_driver_register(&mxs_i2c_driver);
903 subsys_initcall(mxs_i2c_init);
905 static void __exit mxs_i2c_exit(void)
907 platform_driver_unregister(&mxs_i2c_driver);
909 module_exit(mxs_i2c_exit);
911 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
912 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
913 MODULE_DESCRIPTION("MXS I2C Bus Driver");
914 MODULE_LICENSE("GPL");
915 MODULE_ALIAS("platform:" DRIVER_NAME);