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50 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
51 * S12xx Product Family.
53 * Features supported by this driver:
56 * Block process call transaction no
60 #include <linux/module.h>
61 #include <linux/pci.h>
62 #include <linux/kernel.h>
63 #include <linux/stddef.h>
64 #include <linux/completion.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/i2c.h>
67 #include <linux/acpi.h>
68 #include <linux/interrupt.h>
70 #include <linux/io-64-nonatomic-lo-hi.h>
72 /* PCI Address Constants */
75 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
76 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59
77 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a
78 #define PCI_DEVICE_ID_INTEL_DNV_SMT 0x19ac
79 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15
81 #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */
82 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */
84 /* Hardware Descriptor Constants - Control Field */
85 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */
86 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */
87 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */
88 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */
89 #define ISMT_DESC_I2C 0x20 /* I2C Enable */
90 #define ISMT_DESC_INT 0x40 /* Interrupt */
91 #define ISMT_DESC_SOE 0x80 /* Stop On Error */
93 /* Hardware Descriptor Constants - Status Field */
94 #define ISMT_DESC_SCS 0x01 /* Success */
95 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */
96 #define ISMT_DESC_NAK 0x08 /* NAK Received */
97 #define ISMT_DESC_CRC 0x10 /* CRC Error */
98 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */
99 #define ISMT_DESC_COL 0x40 /* Collisions */
100 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */
103 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
105 /* iSMT General Register address offsets (SMBBAR + <addr>) */
106 #define ISMT_GR_GCTRL 0x000 /* General Control */
107 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */
108 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */
109 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */
110 #define ISMT_GR_ERRSTS 0x018 /* Error Status */
111 #define ISMT_GR_ERRINFO 0x01c /* Error Information */
113 /* iSMT Master Registers */
114 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
115 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */
116 #define ISMT_MSTR_MSTS 0x10c /* Master Status */
117 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */
118 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */
120 /* iSMT Miscellaneous Registers */
121 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */
123 /* General Control Register (GCTRL) bit definitions */
124 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */
125 #define ISMT_GCTRL_KILL 0x08 /* Kill */
126 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */
128 /* Master Control Register (MCTRL) bit definitions */
129 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */
130 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */
131 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */
133 /* Master Status Register (MSTS) bit definitions */
134 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */
135 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */
136 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */
137 #define ISMT_MSTS_IP 0x01 /* In Progress */
139 /* Master Descriptor Size (MDS) bit definitions */
140 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */
142 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
143 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */
144 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
145 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
146 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */
147 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */
150 /* MSI Control Register (MSICTL) bit definitions */
151 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
153 /* iSMT Hardware Descriptor */
155 u8 tgtaddr_rw; /* target address & r/w bit */
156 u8 wr_len_cmd; /* write length in bytes or a command */
157 u8 rd_len; /* read length */
158 u8 control; /* control bits */
159 u8 status; /* status bits */
160 u8 retry; /* collision retry and retry count */
161 u8 rxbytes; /* received bytes */
162 u8 txbytes; /* transmitted bytes */
163 u32 dptr_low; /* lower 32 bit of the data pointer */
164 u32 dptr_high; /* upper 32 bit of the data pointer */
168 struct i2c_adapter adapter;
169 void __iomem *smba; /* PCI BAR */
170 struct pci_dev *pci_dev;
171 struct ismt_desc *hw; /* descriptor virt base addr */
172 dma_addr_t io_rng_dma; /* descriptor HW base addr */
173 u8 head; /* ring buffer head pointer */
174 struct completion cmp; /* interrupt completion */
175 u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* temp R/W data buffer */
179 * ismt_ids - PCI device IDs supported by this driver
181 static const struct pci_device_id ismt_ids[] = {
182 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
183 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
184 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) },
185 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
189 MODULE_DEVICE_TABLE(pci, ismt_ids);
191 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
192 static unsigned int bus_speed;
193 module_param(bus_speed, uint, S_IRUGO);
194 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
197 * __ismt_desc_dump() - dump the contents of a specific descriptor
199 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
202 dev_dbg(dev, "Descriptor struct: %p\n", desc);
203 dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
204 dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
205 dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len);
206 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control);
207 dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status);
208 dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry);
209 dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes);
210 dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes);
211 dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low);
212 dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
215 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
216 * @priv: iSMT private data
218 static void ismt_desc_dump(struct ismt_priv *priv)
220 struct device *dev = &priv->pci_dev->dev;
221 struct ismt_desc *desc = &priv->hw[priv->head];
223 dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head);
224 __ismt_desc_dump(dev, desc);
228 * ismt_gen_reg_dump() - dump the iSMT General Registers
229 * @priv: iSMT private data
231 static void ismt_gen_reg_dump(struct ismt_priv *priv)
233 struct device *dev = &priv->pci_dev->dev;
235 dev_dbg(dev, "Dump of the iSMT General Registers\n");
236 dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n",
237 priv->smba + ISMT_GR_GCTRL,
238 readl(priv->smba + ISMT_GR_GCTRL));
239 dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n",
240 priv->smba + ISMT_GR_SMTICL,
241 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
242 dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n",
243 priv->smba + ISMT_GR_ERRINTMSK,
244 readl(priv->smba + ISMT_GR_ERRINTMSK));
245 dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n",
246 priv->smba + ISMT_GR_ERRAERMSK,
247 readl(priv->smba + ISMT_GR_ERRAERMSK));
248 dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n",
249 priv->smba + ISMT_GR_ERRSTS,
250 readl(priv->smba + ISMT_GR_ERRSTS));
251 dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n",
252 priv->smba + ISMT_GR_ERRINFO,
253 readl(priv->smba + ISMT_GR_ERRINFO));
257 * ismt_mstr_reg_dump() - dump the iSMT Master Registers
258 * @priv: iSMT private data
260 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
262 struct device *dev = &priv->pci_dev->dev;
264 dev_dbg(dev, "Dump of the iSMT Master Registers\n");
265 dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n",
266 priv->smba + ISMT_MSTR_MDBA,
267 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
268 dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n",
269 priv->smba + ISMT_MSTR_MCTRL,
270 readl(priv->smba + ISMT_MSTR_MCTRL));
271 dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n",
272 priv->smba + ISMT_MSTR_MSTS,
273 readl(priv->smba + ISMT_MSTR_MSTS));
274 dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n",
275 priv->smba + ISMT_MSTR_MDS,
276 readl(priv->smba + ISMT_MSTR_MDS));
277 dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n",
278 priv->smba + ISMT_MSTR_RPOLICY,
279 readl(priv->smba + ISMT_MSTR_RPOLICY));
280 dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n",
281 priv->smba + ISMT_SPGT,
282 readl(priv->smba + ISMT_SPGT));
286 * ismt_submit_desc() - add a descriptor to the ring
287 * @priv: iSMT private data
289 static void ismt_submit_desc(struct ismt_priv *priv)
294 ismt_desc_dump(priv);
295 ismt_gen_reg_dump(priv);
296 ismt_mstr_reg_dump(priv);
298 /* Set the FMHP (Firmware Master Head Pointer)*/
299 fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
300 val = readl(priv->smba + ISMT_MSTR_MCTRL);
301 writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
302 priv->smba + ISMT_MSTR_MCTRL);
304 /* Set the start bit */
305 val = readl(priv->smba + ISMT_MSTR_MCTRL);
306 writel(val | ISMT_MCTRL_SS,
307 priv->smba + ISMT_MSTR_MCTRL);
311 * ismt_process_desc() - handle the completion of the descriptor
312 * @desc: the iSMT hardware descriptor
313 * @data: data buffer from the upper layer
314 * @priv: ismt_priv struct holding our dma buffer
315 * @size: SMBus transaction type
316 * @read_write: flag to indicate if this is a read or write
318 static int ismt_process_desc(const struct ismt_desc *desc,
319 union i2c_smbus_data *data,
320 struct ismt_priv *priv, int size,
323 u8 *dma_buffer = priv->dma_buffer;
325 dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
326 __ismt_desc_dump(&priv->pci_dev->dev, desc);
328 if (desc->status & ISMT_DESC_SCS) {
329 if (read_write == I2C_SMBUS_WRITE &&
330 size != I2C_SMBUS_PROC_CALL)
335 case I2C_SMBUS_BYTE_DATA:
336 data->byte = dma_buffer[0];
338 case I2C_SMBUS_WORD_DATA:
339 case I2C_SMBUS_PROC_CALL:
340 data->word = dma_buffer[0] | (dma_buffer[1] << 8);
342 case I2C_SMBUS_BLOCK_DATA:
343 case I2C_SMBUS_I2C_BLOCK_DATA:
344 if (desc->rxbytes != dma_buffer[0] + 1)
347 memcpy(data->block, dma_buffer, desc->rxbytes);
353 if (likely(desc->status & ISMT_DESC_NAK))
356 if (desc->status & ISMT_DESC_CRC)
359 if (desc->status & ISMT_DESC_COL)
362 if (desc->status & ISMT_DESC_LPR)
365 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
372 * ismt_access() - process an SMBus command
373 * @adap: the i2c host adapter
374 * @addr: address of the i2c/SMBus target
375 * @flags: command options
376 * @read_write: read from or write to device
377 * @command: the i2c/SMBus command to issue
378 * @size: SMBus transaction type
379 * @data: read/write data buffer
381 static int ismt_access(struct i2c_adapter *adap, u16 addr,
382 unsigned short flags, char read_write, u8 command,
383 int size, union i2c_smbus_data *data)
386 unsigned long time_left;
387 dma_addr_t dma_addr = 0; /* address of the data buffer */
389 enum dma_data_direction dma_direction = 0;
390 struct ismt_desc *desc;
391 struct ismt_priv *priv = i2c_get_adapdata(adap);
392 struct device *dev = &priv->pci_dev->dev;
394 desc = &priv->hw[priv->head];
396 /* Initialize the DMA buffer */
397 memset(priv->dma_buffer, 0, sizeof(priv->dma_buffer));
399 /* Initialize the descriptor */
400 memset(desc, 0, sizeof(struct ismt_desc));
401 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
403 /* Initialize common control bits */
404 if (likely(pci_dev_msi_enabled(priv->pci_dev)))
405 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
407 desc->control = ISMT_DESC_FAIR;
409 if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
410 && (size != I2C_SMBUS_I2C_BLOCK_DATA))
411 desc->control |= ISMT_DESC_PEC;
414 case I2C_SMBUS_QUICK:
415 dev_dbg(dev, "I2C_SMBUS_QUICK\n");
419 if (read_write == I2C_SMBUS_WRITE) {
422 * The command field contains the write data
424 dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n");
425 desc->control |= ISMT_DESC_CWRL;
426 desc->wr_len_cmd = command;
429 dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n");
431 dma_direction = DMA_FROM_DEVICE;
436 case I2C_SMBUS_BYTE_DATA:
437 if (read_write == I2C_SMBUS_WRITE) {
440 * Command plus 1 data byte
442 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n");
443 desc->wr_len_cmd = 2;
445 dma_direction = DMA_TO_DEVICE;
446 priv->dma_buffer[0] = command;
447 priv->dma_buffer[1] = data->byte;
450 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n");
451 desc->control |= ISMT_DESC_CWRL;
452 desc->wr_len_cmd = command;
455 dma_direction = DMA_FROM_DEVICE;
459 case I2C_SMBUS_WORD_DATA:
460 if (read_write == I2C_SMBUS_WRITE) {
462 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n");
463 desc->wr_len_cmd = 3;
465 dma_direction = DMA_TO_DEVICE;
466 priv->dma_buffer[0] = command;
467 priv->dma_buffer[1] = data->word & 0xff;
468 priv->dma_buffer[2] = data->word >> 8;
471 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n");
472 desc->wr_len_cmd = command;
473 desc->control |= ISMT_DESC_CWRL;
476 dma_direction = DMA_FROM_DEVICE;
480 case I2C_SMBUS_PROC_CALL:
481 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
482 desc->wr_len_cmd = 3;
485 dma_direction = DMA_BIDIRECTIONAL;
486 priv->dma_buffer[0] = command;
487 priv->dma_buffer[1] = data->word & 0xff;
488 priv->dma_buffer[2] = data->word >> 8;
491 case I2C_SMBUS_BLOCK_DATA:
492 if (read_write == I2C_SMBUS_WRITE) {
494 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n");
495 dma_size = data->block[0] + 1;
496 dma_direction = DMA_TO_DEVICE;
497 desc->wr_len_cmd = dma_size;
498 desc->control |= ISMT_DESC_BLK;
499 priv->dma_buffer[0] = command;
500 memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1);
503 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n");
504 dma_size = I2C_SMBUS_BLOCK_MAX;
505 dma_direction = DMA_FROM_DEVICE;
506 desc->rd_len = dma_size;
507 desc->wr_len_cmd = command;
508 desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
512 case I2C_SMBUS_I2C_BLOCK_DATA:
513 /* Make sure the length is valid */
514 if (data->block[0] < 1)
517 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
518 data->block[0] = I2C_SMBUS_BLOCK_MAX;
520 if (read_write == I2C_SMBUS_WRITE) {
521 /* i2c Block Write */
522 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n");
523 dma_size = data->block[0] + 1;
524 dma_direction = DMA_TO_DEVICE;
525 desc->wr_len_cmd = dma_size;
526 desc->control |= ISMT_DESC_I2C;
527 priv->dma_buffer[0] = command;
528 memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1);
531 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n");
532 dma_size = data->block[0];
533 dma_direction = DMA_FROM_DEVICE;
534 desc->rd_len = dma_size;
535 desc->wr_len_cmd = command;
536 desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
538 * Per the "Table 15-15. I2C Commands",
539 * in the External Design Specification (EDS),
540 * (Document Number: 508084, Revision: 2.0),
541 * the _rw bit must be 0
543 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
548 dev_err(dev, "Unsupported transaction %d\n",
553 /* map the data buffer */
555 dev_dbg(dev, " dev=%p\n", dev);
556 dev_dbg(dev, " data=%p\n", data);
557 dev_dbg(dev, " dma_buffer=%p\n", priv->dma_buffer);
558 dev_dbg(dev, " dma_size=%d\n", dma_size);
559 dev_dbg(dev, " dma_direction=%d\n", dma_direction);
561 dma_addr = dma_map_single(dev,
566 if (dma_mapping_error(dev, dma_addr)) {
567 dev_err(dev, "Error in mapping dma buffer %p\n",
572 dev_dbg(dev, " dma_addr = 0x%016llX\n",
573 (unsigned long long)dma_addr);
575 desc->dptr_low = lower_32_bits(dma_addr);
576 desc->dptr_high = upper_32_bits(dma_addr);
579 reinit_completion(&priv->cmp);
581 /* Add the descriptor */
582 ismt_submit_desc(priv);
584 /* Now we wait for interrupt completion, 1s */
585 time_left = wait_for_completion_timeout(&priv->cmp, HZ*1);
587 /* unmap the data buffer */
589 dma_unmap_single(dev, dma_addr, dma_size, dma_direction);
591 if (unlikely(!time_left)) {
592 dev_err(dev, "completion wait timed out\n");
597 /* do any post processing of the descriptor here */
598 ret = ismt_process_desc(desc, data, priv, size, read_write);
601 /* Update the ring pointer */
603 priv->head %= ISMT_DESC_ENTRIES;
609 * ismt_func() - report which i2c commands are supported by this adapter
610 * @adap: the i2c host adapter
612 static u32 ismt_func(struct i2c_adapter *adap)
614 return I2C_FUNC_SMBUS_QUICK |
615 I2C_FUNC_SMBUS_BYTE |
616 I2C_FUNC_SMBUS_BYTE_DATA |
617 I2C_FUNC_SMBUS_WORD_DATA |
618 I2C_FUNC_SMBUS_PROC_CALL |
619 I2C_FUNC_SMBUS_BLOCK_DATA |
620 I2C_FUNC_SMBUS_I2C_BLOCK |
625 * smbus_algorithm - the adapter algorithm and supported functionality
626 * @smbus_xfer: the adapter algorithm
627 * @functionality: functionality supported by the adapter
629 static const struct i2c_algorithm smbus_algorithm = {
630 .smbus_xfer = ismt_access,
631 .functionality = ismt_func,
635 * ismt_handle_isr() - interrupt handler bottom half
636 * @priv: iSMT private data
638 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
640 complete(&priv->cmp);
647 * ismt_do_interrupt() - IRQ interrupt handler
648 * @vec: interrupt vector
649 * @data: iSMT private data
651 static irqreturn_t ismt_do_interrupt(int vec, void *data)
654 struct ismt_priv *priv = data;
657 * check to see it's our interrupt, return IRQ_NONE if not ours
658 * since we are sharing interrupt
660 val = readl(priv->smba + ISMT_MSTR_MSTS);
662 if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
665 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
666 priv->smba + ISMT_MSTR_MSTS);
668 return ismt_handle_isr(priv);
672 * ismt_do_msi_interrupt() - MSI interrupt handler
673 * @vec: interrupt vector
674 * @data: iSMT private data
676 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
678 return ismt_handle_isr(data);
682 * ismt_hw_init() - initialize the iSMT hardware
683 * @priv: iSMT private data
685 static void ismt_hw_init(struct ismt_priv *priv)
688 struct device *dev = &priv->pci_dev->dev;
690 /* initialize the Master Descriptor Base Address (MDBA) */
691 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
693 /* initialize the Master Control Register (MCTRL) */
694 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
696 /* initialize the Master Status Register (MSTS) */
697 writel(0, priv->smba + ISMT_MSTR_MSTS);
699 /* initialize the Master Descriptor Size (MDS) */
700 val = readl(priv->smba + ISMT_MSTR_MDS);
701 writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
702 priv->smba + ISMT_MSTR_MDS);
705 * Set the SMBus speed (could use this for slow HW debuggers)
708 val = readl(priv->smba + ISMT_SPGT);
715 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
716 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
717 priv->smba + ISMT_SPGT);
721 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
722 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
723 priv->smba + ISMT_SPGT);
727 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
728 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
729 priv->smba + ISMT_SPGT);
733 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
734 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
735 priv->smba + ISMT_SPGT);
739 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
743 val = readl(priv->smba + ISMT_SPGT);
745 switch (val & ISMT_SPGT_SPD_MASK) {
746 case ISMT_SPGT_SPD_80K:
749 case ISMT_SPGT_SPD_100K:
752 case ISMT_SPGT_SPD_400K:
755 case ISMT_SPGT_SPD_1M:
759 dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
763 * ismt_dev_init() - initialize the iSMT data structures
764 * @priv: iSMT private data
766 static int ismt_dev_init(struct ismt_priv *priv)
768 /* allocate memory for the descriptor */
769 priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
771 * sizeof(struct ismt_desc)),
777 memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)));
780 init_completion(&priv->cmp);
786 * ismt_int_init() - initialize interrupts
787 * @priv: iSMT private data
789 static int ismt_int_init(struct ismt_priv *priv)
793 /* Try using MSI interrupts */
794 err = pci_enable_msi(priv->pci_dev);
798 err = devm_request_irq(&priv->pci_dev->dev,
800 ismt_do_msi_interrupt,
805 pci_disable_msi(priv->pci_dev);
811 /* Try using legacy interrupts */
813 dev_warn(&priv->pci_dev->dev,
814 "Unable to use MSI interrupts, falling back to legacy\n");
816 err = devm_request_irq(&priv->pci_dev->dev,
823 dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
830 static struct pci_driver ismt_driver;
833 * ismt_probe() - probe for iSMT devices
834 * @pdev: PCI-Express device
835 * @id: PCI-Express device ID
838 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
841 struct ismt_priv *priv;
842 unsigned long start, len;
844 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
848 pci_set_drvdata(pdev, priv);
850 i2c_set_adapdata(&priv->adapter, priv);
851 priv->adapter.owner = THIS_MODULE;
852 priv->adapter.class = I2C_CLASS_HWMON;
853 priv->adapter.algo = &smbus_algorithm;
854 priv->adapter.dev.parent = &pdev->dev;
855 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
856 priv->adapter.retries = ISMT_MAX_RETRIES;
858 priv->pci_dev = pdev;
860 err = pcim_enable_device(pdev);
862 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
867 /* enable bus mastering */
868 pci_set_master(pdev);
870 /* Determine the address of the SMBus area */
871 start = pci_resource_start(pdev, SMBBAR);
872 len = pci_resource_len(pdev, SMBBAR);
873 if (!start || !len) {
875 "SMBus base address uninitialized, upgrade BIOS\n");
879 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
880 "SMBus iSMT adapter at %lx", start);
882 dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
883 dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
885 err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
887 dev_err(&pdev->dev, "ACPI resource conflict!\n");
891 err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
894 "Failed to request SMBus region 0x%lx-0x%lx\n",
899 priv->smba = pcim_iomap(pdev, SMBBAR, len);
901 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
905 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
906 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
907 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
908 (pci_set_consistent_dma_mask(pdev,
909 DMA_BIT_MASK(32)) != 0)) {
910 dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
916 err = ismt_dev_init(priv);
922 err = ismt_int_init(priv);
926 err = i2c_add_adapter(&priv->adapter);
933 * ismt_remove() - release driver resources
934 * @pdev: PCI-Express device
936 static void ismt_remove(struct pci_dev *pdev)
938 struct ismt_priv *priv = pci_get_drvdata(pdev);
940 i2c_del_adapter(&priv->adapter);
943 static struct pci_driver ismt_driver = {
944 .name = "ismt_smbus",
945 .id_table = ismt_ids,
947 .remove = ismt_remove,
950 module_pci_driver(ismt_driver);
952 MODULE_LICENSE("Dual BSD/GPL");
953 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
954 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");