1 // SPDX-License-Identifier: GPL-2.0-only
2 /* ------------------------------------------------------------------------- */
3 /* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */
4 /* ------------------------------------------------------------------------- */
5 /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
6 * <Peter dot Milne at D hyphen TACQ dot com>
8 * With acknowledgements to i2c-algo-ibm_ocp.c by
9 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
11 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
13 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
15 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
16 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
18 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
20 * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
21 * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
22 * - Make it work with IXP46x chips
23 * - Cleanup function names, coding style, etc
25 * - writing to slave address causes latchup on iop331.
26 * fix: driver refuses to address self.
29 #include <linux/interrupt.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <linux/errno.h>
35 #include <linux/platform_device.h>
36 #include <linux/i2c.h>
38 #include <linux/gpio.h>
40 #include "i2c-iop3xx.h"
42 /* global unit counter */
45 static inline unsigned char
46 iic_cook_addr(struct i2c_msg *msg)
50 addr = i2c_8bit_addr_from_msg(msg);
56 iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
58 /* Follows devman 9.3 */
59 __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
60 __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
61 __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
65 iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
67 u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;
70 * Every time unit enable is asserted, GPOD needs to be cleared
71 * on IOP3XX to avoid data corruption on the bus.
73 #if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X)
74 if (iop3xx_adap->id == 0) {
82 /* NB SR bits not same position as CR IE bits :-( */
83 iop3xx_adap->SR_enabled =
84 IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
85 IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;
87 cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
88 IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE;
90 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
94 iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
96 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
98 cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
99 IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);
101 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
105 * NB: the handler has to clear the source of the interrupt!
106 * Then it passes the SR flags of interest to BH via adap data
109 iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
111 struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
112 u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
114 if ((sr &= iop3xx_adap->SR_enabled)) {
115 __raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
116 iop3xx_adap->SR_received |= sr;
117 wake_up_interruptible(&iop3xx_adap->waitq);
122 /* check all error conditions, clear them , report most important */
124 iop3xx_i2c_error(u32 sr)
128 if ((sr & IOP3XX_ISR_BERRD)) {
129 if ( !rc ) rc = -I2C_ERR_BERR;
131 if ((sr & IOP3XX_ISR_ALD)) {
132 if ( !rc ) rc = -I2C_ERR_ALD;
138 iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
143 spin_lock_irqsave(&iop3xx_adap->lock, flags);
144 sr = iop3xx_adap->SR_received;
145 iop3xx_adap->SR_received = 0;
146 spin_unlock_irqrestore(&iop3xx_adap->lock, flags);
152 * sleep until interrupted, then recover and analyse the SR
155 typedef int (* compare_func)(unsigned test, unsigned mask);
156 /* returns 1 on correct comparison */
159 iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
160 unsigned flags, unsigned* status,
161 compare_func compare)
169 interrupted = wait_event_interruptible_timeout (
171 (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
174 if ((rc = iop3xx_i2c_error(sr)) < 0) {
177 } else if (!interrupted) {
189 * Concrete compare_funcs
192 all_bits_clear(unsigned test, unsigned mask)
194 return (test & mask) == 0;
198 any_bits_set(unsigned test, unsigned mask)
200 return (test & mask) != 0;
204 iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
206 return iop3xx_i2c_wait_event(
208 IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
209 status, any_bits_set);
213 iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
215 return iop3xx_i2c_wait_event(
217 IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
218 status, any_bits_set);
222 iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
224 return iop3xx_i2c_wait_event(
225 iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
229 iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
232 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
236 /* avoid writing to my slave address (hangs on 80331),
237 * forbidden in Intel developer manual
239 if (msg->addr == MYSAR) {
243 __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
245 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
246 cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;
248 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
249 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
255 iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
258 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
262 __raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
263 cr &= ~IOP3XX_ICR_MSTART;
265 cr |= IOP3XX_ICR_MSTOP;
267 cr &= ~IOP3XX_ICR_MSTOP;
269 cr |= IOP3XX_ICR_TBYTE;
270 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
271 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
277 iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
280 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
284 cr &= ~IOP3XX_ICR_MSTART;
287 cr |= IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK;
289 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
291 cr |= IOP3XX_ICR_TBYTE;
292 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
294 rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);
296 *byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);
302 iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
304 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
308 for (ii = 0; rc == 0 && ii != count; ++ii)
309 rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
314 iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
316 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
320 for (ii = 0; rc == 0 && ii != count; ++ii)
321 rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
327 * Description: This function implements combined transactions. Combined
328 * transactions consist of combinations of reading and writing blocks of data.
329 * FROM THE SAME ADDRESS
330 * Each transfer (i.e. a read or a write) is separated by a repeated start
334 iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
336 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
339 rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
344 if ((pmsg->flags&I2C_M_RD)) {
345 return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
347 return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
352 * master_xfer() - main read/write entry
355 iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
358 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
363 iop3xx_i2c_wait_idle(iop3xx_adap, &status);
364 iop3xx_i2c_reset(iop3xx_adap);
365 iop3xx_i2c_enable(iop3xx_adap);
367 for (im = 0; ret == 0 && im != num; im++) {
368 ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
371 iop3xx_i2c_transaction_cleanup(iop3xx_adap);
380 iop3xx_i2c_func(struct i2c_adapter *adap)
382 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
385 static const struct i2c_algorithm iop3xx_i2c_algo = {
386 .master_xfer = iop3xx_i2c_master_xfer,
387 .functionality = iop3xx_i2c_func,
391 iop3xx_i2c_remove(struct platform_device *pdev)
393 struct i2c_adapter *padapter = platform_get_drvdata(pdev);
394 struct i2c_algo_iop3xx_data *adapter_data =
395 (struct i2c_algo_iop3xx_data *)padapter->algo_data;
396 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
397 unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
400 * Disable the actual HW unit
402 cr &= ~(IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
403 IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE);
404 __raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);
406 iounmap(adapter_data->ioaddr);
407 release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
415 iop3xx_i2c_probe(struct platform_device *pdev)
417 struct resource *res;
419 struct i2c_adapter *new_adapter;
420 struct i2c_algo_iop3xx_data *adapter_data;
422 new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
428 adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
434 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
440 if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
445 /* set the adapter enumeration # */
446 adapter_data->id = i2c_id++;
448 adapter_data->ioaddr = ioremap(res->start, IOP3XX_I2C_IO_SIZE);
449 if (!adapter_data->ioaddr) {
454 irq = platform_get_irq(pdev, 0);
459 ret = request_irq(irq, iop3xx_i2c_irq_handler, 0,
460 pdev->name, adapter_data);
467 memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
468 new_adapter->owner = THIS_MODULE;
469 new_adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
470 new_adapter->dev.parent = &pdev->dev;
471 new_adapter->dev.of_node = pdev->dev.of_node;
472 new_adapter->nr = pdev->id;
475 * Default values...should these come in from board code?
477 new_adapter->timeout = HZ;
478 new_adapter->algo = &iop3xx_i2c_algo;
480 init_waitqueue_head(&adapter_data->waitq);
481 spin_lock_init(&adapter_data->lock);
483 iop3xx_i2c_reset(adapter_data);
484 iop3xx_i2c_enable(adapter_data);
486 platform_set_drvdata(pdev, new_adapter);
487 new_adapter->algo_data = adapter_data;
489 i2c_add_numbered_adapter(new_adapter);
494 iounmap(adapter_data->ioaddr);
497 release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
509 static const struct of_device_id i2c_iop3xx_match[] = {
510 { .compatible = "intel,iop3xx-i2c", },
511 { .compatible = "intel,ixp4xx-i2c", },
514 MODULE_DEVICE_TABLE(of, i2c_iop3xx_match);
516 static struct platform_driver iop3xx_i2c_driver = {
517 .probe = iop3xx_i2c_probe,
518 .remove = iop3xx_i2c_remove,
520 .name = "IOP3xx-I2C",
521 .of_match_table = i2c_iop3xx_match,
525 module_platform_driver(iop3xx_i2c_driver);
527 MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
528 MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
529 MODULE_LICENSE("GPL");
530 MODULE_ALIAS("platform:IOP3xx-I2C");