2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Supports the following Intel I/O Controller Hubs (ICH):
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 Cougar Point (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
53 Features supported by this driver:
57 Block process call transaction no
58 I2C block read transaction yes (doesn't use the block buffer)
61 See the file Documentation/i2c/busses/i2c-i801 for details.
64 #include <linux/module.h>
65 #include <linux/pci.h>
66 #include <linux/kernel.h>
67 #include <linux/stddef.h>
68 #include <linux/delay.h>
69 #include <linux/ioport.h>
70 #include <linux/init.h>
71 #include <linux/i2c.h>
72 #include <linux/acpi.h>
74 #include <linux/dmi.h>
75 #include <linux/slab.h>
77 /* I801 SMBus address offsets */
78 #define SMBHSTSTS(p) (0 + (p)->smba)
79 #define SMBHSTCNT(p) (2 + (p)->smba)
80 #define SMBHSTCMD(p) (3 + (p)->smba)
81 #define SMBHSTADD(p) (4 + (p)->smba)
82 #define SMBHSTDAT0(p) (5 + (p)->smba)
83 #define SMBHSTDAT1(p) (6 + (p)->smba)
84 #define SMBBLKDAT(p) (7 + (p)->smba)
85 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
86 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
87 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
89 /* PCI Address Constants */
91 #define SMBHSTCFG 0x040
93 /* Host configuration bits for SMBHSTCFG */
94 #define SMBHSTCFG_HST_EN 1
95 #define SMBHSTCFG_SMB_SMI_EN 2
96 #define SMBHSTCFG_I2C_EN 4
98 /* Auxillary control register bits, ICH4+ only */
99 #define SMBAUXCTL_CRC 1
100 #define SMBAUXCTL_E32B 2
102 /* kill bit for SMBHSTCNT */
103 #define SMBHSTCNT_KILL 2
106 #define MAX_TIMEOUT 100
107 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
109 /* I801 command constants */
110 #define I801_QUICK 0x00
111 #define I801_BYTE 0x04
112 #define I801_BYTE_DATA 0x08
113 #define I801_WORD_DATA 0x0C
114 #define I801_PROC_CALL 0x10 /* unimplemented */
115 #define I801_BLOCK_DATA 0x14
116 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
117 #define I801_BLOCK_LAST 0x34
118 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
119 #define I801_START 0x40
120 #define I801_PEC_EN 0x80 /* ICH3 and later */
122 /* I801 Hosts Status register bits */
123 #define SMBHSTSTS_BYTE_DONE 0x80
124 #define SMBHSTSTS_INUSE_STS 0x40
125 #define SMBHSTSTS_SMBALERT_STS 0x20
126 #define SMBHSTSTS_FAILED 0x10
127 #define SMBHSTSTS_BUS_ERR 0x08
128 #define SMBHSTSTS_DEV_ERR 0x04
129 #define SMBHSTSTS_INTR 0x02
130 #define SMBHSTSTS_HOST_BUSY 0x01
132 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
133 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
136 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
137 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
138 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
139 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
142 struct i2c_adapter adapter;
144 unsigned char original_hstcfg;
145 struct pci_dev *pci_dev;
146 unsigned int features;
149 static struct pci_driver i801_driver;
151 #define FEATURE_SMBUS_PEC (1 << 0)
152 #define FEATURE_BLOCK_BUFFER (1 << 1)
153 #define FEATURE_BLOCK_PROC (1 << 2)
154 #define FEATURE_I2C_BLOCK_READ (1 << 3)
156 static const char *i801_feature_names[] = {
159 "Block process call",
163 static unsigned int disable_features;
164 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
165 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
167 /* Make sure the SMBus host is ready to start transmitting.
168 Return 0 if it is, -EBUSY if it is not. */
169 static int i801_check_pre(struct i801_priv *priv)
173 status = inb_p(SMBHSTSTS(priv));
174 if (status & SMBHSTSTS_HOST_BUSY) {
175 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
179 status &= STATUS_FLAGS;
181 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
183 outb_p(status, SMBHSTSTS(priv));
184 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
186 dev_err(&priv->pci_dev->dev,
187 "Failed clearing status flags (%02x)\n",
196 /* Convert the status register to an error code, and clear it. */
197 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
201 /* If the SMBus is still busy, we give up */
203 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
204 /* try to stop the current command */
205 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
206 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
209 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
212 /* Check if it worked */
213 status = inb_p(SMBHSTSTS(priv));
214 if ((status & SMBHSTSTS_HOST_BUSY) ||
215 !(status & SMBHSTSTS_FAILED))
216 dev_err(&priv->pci_dev->dev,
217 "Failed terminating the transaction\n");
218 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
222 if (status & SMBHSTSTS_FAILED) {
224 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
226 if (status & SMBHSTSTS_DEV_ERR) {
228 dev_dbg(&priv->pci_dev->dev, "No response\n");
230 if (status & SMBHSTSTS_BUS_ERR) {
232 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
236 /* Clear error flags */
237 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
238 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
240 dev_warn(&priv->pci_dev->dev, "Failed clearing status "
241 "flags at end of transaction (%02x)\n",
249 static int i801_transaction(struct i801_priv *priv, int xact)
255 result = i801_check_pre(priv);
259 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
260 * INTREN, SMBSCMD are passed in xact */
261 outb_p(xact | I801_START, SMBHSTCNT(priv));
263 /* We will always wait for a fraction of a second! */
266 status = inb_p(SMBHSTSTS(priv));
267 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
269 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
273 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
277 /* wait for INTR bit as advised by Intel */
278 static void i801_wait_hwpec(struct i801_priv *priv)
285 status = inb_p(SMBHSTSTS(priv));
286 } while ((!(status & SMBHSTSTS_INTR))
287 && (timeout++ < MAX_TIMEOUT));
289 if (timeout > MAX_TIMEOUT)
290 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
292 outb_p(status, SMBHSTSTS(priv));
295 static int i801_block_transaction_by_block(struct i801_priv *priv,
296 union i2c_smbus_data *data,
297 char read_write, int hwpec)
302 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
304 /* Use 32-byte buffer to process this transaction */
305 if (read_write == I2C_SMBUS_WRITE) {
306 len = data->block[0];
307 outb_p(len, SMBHSTDAT0(priv));
308 for (i = 0; i < len; i++)
309 outb_p(data->block[i+1], SMBBLKDAT(priv));
312 status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
313 I801_PEC_EN * hwpec);
317 if (read_write == I2C_SMBUS_READ) {
318 len = inb_p(SMBHSTDAT0(priv));
319 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
322 data->block[0] = len;
323 for (i = 0; i < len; i++)
324 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
329 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
330 union i2c_smbus_data *data,
331 char read_write, int command,
340 result = i801_check_pre(priv);
344 len = data->block[0];
346 if (read_write == I2C_SMBUS_WRITE) {
347 outb_p(len, SMBHSTDAT0(priv));
348 outb_p(data->block[1], SMBBLKDAT(priv));
351 for (i = 1; i <= len; i++) {
352 if (i == len && read_write == I2C_SMBUS_READ) {
353 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
354 smbcmd = I801_I2C_BLOCK_LAST;
356 smbcmd = I801_BLOCK_LAST;
358 if (command == I2C_SMBUS_I2C_BLOCK_DATA
359 && read_write == I2C_SMBUS_READ)
360 smbcmd = I801_I2C_BLOCK_DATA;
362 smbcmd = I801_BLOCK_DATA;
364 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
367 outb_p(inb(SMBHSTCNT(priv)) | I801_START,
370 /* We will always wait for a fraction of a second! */
374 status = inb_p(SMBHSTSTS(priv));
375 } while ((!(status & SMBHSTSTS_BYTE_DONE))
376 && (timeout++ < MAX_TIMEOUT));
378 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
382 if (i == 1 && read_write == I2C_SMBUS_READ
383 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
384 len = inb_p(SMBHSTDAT0(priv));
385 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
386 dev_err(&priv->pci_dev->dev,
387 "Illegal SMBus block read size %d\n",
390 while (inb_p(SMBHSTSTS(priv)) &
392 outb_p(SMBHSTSTS_BYTE_DONE,
394 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
397 data->block[0] = len;
400 /* Retrieve/store value in SMBBLKDAT */
401 if (read_write == I2C_SMBUS_READ)
402 data->block[i] = inb_p(SMBBLKDAT(priv));
403 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
404 outb_p(data->block[i+1], SMBBLKDAT(priv));
406 /* signals SMBBLKDAT ready */
407 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
413 static int i801_set_block_buffer_mode(struct i801_priv *priv)
415 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
416 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
421 /* Block transaction function */
422 static int i801_block_transaction(struct i801_priv *priv,
423 union i2c_smbus_data *data, char read_write,
424 int command, int hwpec)
429 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
430 if (read_write == I2C_SMBUS_WRITE) {
431 /* set I2C_EN bit in configuration register */
432 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
433 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
434 hostc | SMBHSTCFG_I2C_EN);
435 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
436 dev_err(&priv->pci_dev->dev,
437 "I2C block read is unsupported!\n");
442 if (read_write == I2C_SMBUS_WRITE
443 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
444 if (data->block[0] < 1)
446 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
447 data->block[0] = I2C_SMBUS_BLOCK_MAX;
449 data->block[0] = 32; /* max for SMBus block reads */
452 /* Experience has shown that the block buffer can only be used for
453 SMBus (not I2C) block transactions, even though the datasheet
454 doesn't mention this limitation. */
455 if ((priv->features & FEATURE_BLOCK_BUFFER)
456 && command != I2C_SMBUS_I2C_BLOCK_DATA
457 && i801_set_block_buffer_mode(priv) == 0)
458 result = i801_block_transaction_by_block(priv, data,
461 result = i801_block_transaction_byte_by_byte(priv, data,
465 if (result == 0 && hwpec)
466 i801_wait_hwpec(priv);
468 if (command == I2C_SMBUS_I2C_BLOCK_DATA
469 && read_write == I2C_SMBUS_WRITE) {
470 /* restore saved configuration register value */
471 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
476 /* Return negative errno on error. */
477 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
478 unsigned short flags, char read_write, u8 command,
479 int size, union i2c_smbus_data *data)
484 struct i801_priv *priv = i2c_get_adapdata(adap);
486 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
487 && size != I2C_SMBUS_QUICK
488 && size != I2C_SMBUS_I2C_BLOCK_DATA;
491 case I2C_SMBUS_QUICK:
492 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
497 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
499 if (read_write == I2C_SMBUS_WRITE)
500 outb_p(command, SMBHSTCMD(priv));
503 case I2C_SMBUS_BYTE_DATA:
504 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
506 outb_p(command, SMBHSTCMD(priv));
507 if (read_write == I2C_SMBUS_WRITE)
508 outb_p(data->byte, SMBHSTDAT0(priv));
509 xact = I801_BYTE_DATA;
511 case I2C_SMBUS_WORD_DATA:
512 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
514 outb_p(command, SMBHSTCMD(priv));
515 if (read_write == I2C_SMBUS_WRITE) {
516 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
517 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
519 xact = I801_WORD_DATA;
521 case I2C_SMBUS_BLOCK_DATA:
522 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
524 outb_p(command, SMBHSTCMD(priv));
527 case I2C_SMBUS_I2C_BLOCK_DATA:
528 /* NB: page 240 of ICH5 datasheet shows that the R/#W
529 * bit should be cleared here, even when reading */
530 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
531 if (read_write == I2C_SMBUS_READ) {
532 /* NB: page 240 of ICH5 datasheet also shows
533 * that DATA1 is the cmd field when reading */
534 outb_p(command, SMBHSTDAT1(priv));
536 outb_p(command, SMBHSTCMD(priv));
540 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
545 if (hwpec) /* enable/disable hardware PEC */
546 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
548 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
552 ret = i801_block_transaction(priv, data, read_write, size,
555 ret = i801_transaction(priv, xact | ENABLE_INT9);
557 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
558 time, so we forcibly disable it after every transaction. Turn off
559 E32B for the same reason. */
561 outb_p(inb_p(SMBAUXCTL(priv)) &
562 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
568 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
571 switch (xact & 0x7f) {
572 case I801_BYTE: /* Result put in SMBHSTDAT0 */
574 data->byte = inb_p(SMBHSTDAT0(priv));
577 data->word = inb_p(SMBHSTDAT0(priv)) +
578 (inb_p(SMBHSTDAT1(priv)) << 8);
585 static u32 i801_func(struct i2c_adapter *adapter)
587 struct i801_priv *priv = i2c_get_adapdata(adapter);
589 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
590 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
591 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
592 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
593 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
594 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
597 static const struct i2c_algorithm smbus_algorithm = {
598 .smbus_xfer = i801_access,
599 .functionality = i801_func,
602 static const struct pci_device_id i801_ids[] = {
603 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
604 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
605 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
606 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
607 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
608 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
609 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
610 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
611 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
612 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
613 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
614 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
615 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
616 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
617 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
618 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
619 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
620 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
621 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
622 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
623 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
627 MODULE_DEVICE_TABLE(pci, i801_ids);
629 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
630 static unsigned char apanel_addr;
632 /* Scan the system ROM for the signature "FJKEYINF" */
633 static __init const void __iomem *bios_signature(const void __iomem *bios)
636 const unsigned char signature[] = "FJKEYINF";
638 for (offset = 0; offset < 0x10000; offset += 0x10) {
639 if (check_signature(bios + offset, signature,
640 sizeof(signature)-1))
641 return bios + offset;
646 static void __init input_apanel_init(void)
649 const void __iomem *p;
651 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
652 p = bios_signature(bios);
654 /* just use the first address */
655 apanel_addr = readb(p + 8 + 3) >> 1;
660 static void __init input_apanel_init(void) {}
663 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
664 struct dmi_onboard_device_info {
667 unsigned short i2c_addr;
668 const char *i2c_type;
671 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
672 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
673 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
674 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
677 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
678 struct i2c_adapter *adap)
681 struct i2c_board_info info;
683 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
684 /* & ~0x80, ignore enabled/disabled bit */
685 if ((type & ~0x80) != dmi_devices[i].type)
687 if (strcasecmp(name, dmi_devices[i].name))
690 memset(&info, 0, sizeof(struct i2c_board_info));
691 info.addr = dmi_devices[i].i2c_addr;
692 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
693 i2c_new_device(adap, &info);
698 /* We use our own function to check for onboard devices instead of
699 dmi_find_device() as some buggy BIOS's have the devices we are interested
700 in marked as disabled */
701 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
709 count = (dm->length - sizeof(struct dmi_header)) / 2;
710 for (i = 0; i < count; i++) {
711 const u8 *d = (char *)(dm + 1) + (i * 2);
712 const char *name = ((char *) dm) + dm->length;
719 while (s > 0 && name[0]) {
720 name += strlen(name) + 1;
723 if (name[0] == 0) /* Bogus string reference */
726 dmi_check_onboard_device(type, name, adap);
731 static int __devinit i801_probe(struct pci_dev *dev,
732 const struct pci_device_id *id)
736 struct i801_priv *priv;
738 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
742 i2c_set_adapdata(&priv->adapter, priv);
743 priv->adapter.owner = THIS_MODULE;
744 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
745 priv->adapter.algo = &smbus_algorithm;
748 switch (dev->device) {
750 priv->features |= FEATURE_I2C_BLOCK_READ;
752 case PCI_DEVICE_ID_INTEL_82801DB_3:
753 priv->features |= FEATURE_SMBUS_PEC;
754 priv->features |= FEATURE_BLOCK_BUFFER;
756 case PCI_DEVICE_ID_INTEL_82801CA_3:
757 case PCI_DEVICE_ID_INTEL_82801BA_2:
758 case PCI_DEVICE_ID_INTEL_82801AB_3:
759 case PCI_DEVICE_ID_INTEL_82801AA_3:
763 /* Disable features on user request */
764 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
765 if (priv->features & disable_features & (1 << i))
766 dev_notice(&dev->dev, "%s disabled by user\n",
767 i801_feature_names[i]);
769 priv->features &= ~disable_features;
771 err = pci_enable_device(dev);
773 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
778 /* Determine the address of the SMBus area */
779 priv->smba = pci_resource_start(dev, SMBBAR);
781 dev_err(&dev->dev, "SMBus base address uninitialized, "
787 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
793 err = pci_request_region(dev, SMBBAR, i801_driver.name);
795 dev_err(&dev->dev, "Failed to request SMBus region "
796 "0x%lx-0x%Lx\n", priv->smba,
797 (unsigned long long)pci_resource_end(dev, SMBBAR));
801 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
802 priv->original_hstcfg = temp;
803 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
804 if (!(temp & SMBHSTCFG_HST_EN)) {
805 dev_info(&dev->dev, "Enabling SMBus device\n");
806 temp |= SMBHSTCFG_HST_EN;
808 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
810 if (temp & SMBHSTCFG_SMB_SMI_EN)
811 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
813 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
815 /* Clear special mode bits */
816 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
817 outb_p(inb_p(SMBAUXCTL(priv)) &
818 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
820 /* set up the sysfs linkage to our parent device */
821 priv->adapter.dev.parent = &dev->dev;
823 /* Retry up to 3 times on lost arbitration */
824 priv->adapter.retries = 3;
826 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
827 "SMBus I801 adapter at %04lx", priv->smba);
828 err = i2c_add_adapter(&priv->adapter);
830 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
834 /* Register optional slaves */
835 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
837 struct i2c_board_info info;
839 memset(&info, 0, sizeof(struct i2c_board_info));
840 info.addr = apanel_addr;
841 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
842 i2c_new_device(&priv->adapter, &info);
845 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
846 if (dmi_name_in_vendors("FUJITSU"))
847 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
850 pci_set_drvdata(dev, priv);
854 pci_release_region(dev, SMBBAR);
860 static void __devexit i801_remove(struct pci_dev *dev)
862 struct i801_priv *priv = pci_get_drvdata(dev);
864 i2c_del_adapter(&priv->adapter);
865 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
866 pci_release_region(dev, SMBBAR);
867 pci_set_drvdata(dev, NULL);
870 * do not call pci_disable_device(dev) since it can cause hard hangs on
871 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
876 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
878 struct i801_priv *priv = pci_get_drvdata(dev);
881 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
882 pci_set_power_state(dev, pci_choose_state(dev, mesg));
886 static int i801_resume(struct pci_dev *dev)
888 pci_set_power_state(dev, PCI_D0);
889 pci_restore_state(dev);
890 return pci_enable_device(dev);
893 #define i801_suspend NULL
894 #define i801_resume NULL
897 static struct pci_driver i801_driver = {
898 .name = "i801_smbus",
899 .id_table = i801_ids,
901 .remove = __devexit_p(i801_remove),
902 .suspend = i801_suspend,
903 .resume = i801_resume,
906 static int __init i2c_i801_init(void)
909 return pci_register_driver(&i801_driver);
912 static void __exit i2c_i801_exit(void)
914 pci_unregister_driver(&i801_driver);
917 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
918 "Jean Delvare <khali@linux-fr.org>");
919 MODULE_DESCRIPTION("I801 SMBus driver");
920 MODULE_LICENSE("GPL");
922 module_init(i2c_i801_init);
923 module_exit(i2c_i801_exit);