drivers/i2c/busses/i2c-designware-master.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Synopsys DesignWare I2C adapter driver (master only).
   4  *
   5  * Based on the TI DAVINCI I2C adapter driver.
   6  *
   7  * Copyright (C) 2006 Texas Instruments.
   8  * Copyright (C) 2007 MontaVista Software Inc.
   9  * Copyright (C) 2009 Provigent Ltd.
  10  */
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/export.h>
  15 #include <linux/gpio/consumer.h>
  16 #include <linux/i2c.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/reset.h>
  22
  23 #include "i2c-designware-core.h"
  24
  25 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
  26 {
  27         /* Configure Tx/Rx FIFO threshold levels */
  28         dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
  29         dw_writel(dev, 0, DW_IC_RX_TL);
  30
  31         /* Configure the I2C master */
  32         dw_writel(dev, dev->master_cfg, DW_IC_CON);
  33 }
  34
  35 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
  36 {
  37         u32 ic_clk = i2c_dw_clk_rate(dev);
  38         const char *mode_str, *fp_str = "";
  39         u32 comp_param1;
  40         u32 sda_falling_time, scl_falling_time;
  41         struct i2c_timings *t = &dev->timings;
  42         int ret;
  43
  44         ret = i2c_dw_acquire_lock(dev);
  45         if (ret)
  46                 return ret;
  47         comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
  48         i2c_dw_release_lock(dev);
  49
  50         /* Set standard and fast speed dividers for high/low periods */
  51         sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
  52         scl_falling_time = t->scl_fall_ns ?: 300; /* ns */
  53
  54         /* Calculate SCL timing parameters for standard mode if not set */
  55         if (!dev->ss_hcnt || !dev->ss_lcnt) {
  56                 dev->ss_hcnt =
  57                         i2c_dw_scl_hcnt(ic_clk,
  58                                         4000,   /* tHD;STA = tHIGH = 4.0 us */
  59                                         sda_falling_time,
  60                                         0,      /* 0: DW default, 1: Ideal */
  61                                         0);     /* No offset */
  62                 dev->ss_lcnt =
  63                         i2c_dw_scl_lcnt(ic_clk,
  64                                         4700,   /* tLOW = 4.7 us */
  65                                         scl_falling_time,
  66                                         0);     /* No offset */
  67         }
  68         dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
  69                 dev->ss_hcnt, dev->ss_lcnt);
  70
  71         /*
  72          * Set SCL timing parameters for fast mode or fast mode plus. Only
  73          * difference is the timing parameter values since the registers are
  74          * the same.
  75          */
  76         if (t->bus_freq_hz == 1000000) {
  77                 /*
  78                  * Check are fast mode plus parameters available and use
  79                  * fast mode if not.
  80                  */
  81                 if (dev->fp_hcnt && dev->fp_lcnt) {
  82                         dev->fs_hcnt = dev->fp_hcnt;
  83                         dev->fs_lcnt = dev->fp_lcnt;
  84                         fp_str = " Plus";
  85                 }
  86         }
  87         /*
  88          * Calculate SCL timing parameters for fast mode if not set. They are
  89          * needed also in high speed mode.
  90          */
  91         if (!dev->fs_hcnt || !dev->fs_lcnt) {
  92                 dev->fs_hcnt =
  93                         i2c_dw_scl_hcnt(ic_clk,
  94                                         600,    /* tHD;STA = tHIGH = 0.6 us */
  95                                         sda_falling_time,
  96                                         0,      /* 0: DW default, 1: Ideal */
  97                                         0);     /* No offset */
  98                 dev->fs_lcnt =
  99                         i2c_dw_scl_lcnt(ic_clk,
 100                                         1300,   /* tLOW = 1.3 us */
 101                                         scl_falling_time,
 102                                         0);     /* No offset */
 103         }
 104         dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
 105                 fp_str, dev->fs_hcnt, dev->fs_lcnt);
 106
 107         /* Check is high speed possible and fall back to fast mode if not */
 108         if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
 109                 DW_IC_CON_SPEED_HIGH) {
 110                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 111                         != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
 112                         dev_err(dev->dev, "High Speed not supported!\n");
 113                         dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
 114                         dev->master_cfg |= DW_IC_CON_SPEED_FAST;
 115                         dev->hs_hcnt = 0;
 116                         dev->hs_lcnt = 0;
 117                 } else if (dev->hs_hcnt && dev->hs_lcnt) {
 118                         dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
 119                                 dev->hs_hcnt, dev->hs_lcnt);
 120                 }
 121         }
 122
 123         ret = i2c_dw_set_sda_hold(dev);
 124         if (ret)
 125                 goto out;
 126
 127         switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) {
 128         case DW_IC_CON_SPEED_STD:
 129                 mode_str = "Standard Mode";
 130                 break;
 131         case DW_IC_CON_SPEED_HIGH:
 132                 mode_str = "High Speed Mode";
 133                 break;
 134         default:
 135                 mode_str = "Fast Mode";
 136         }
 137         dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str);
 138
 139 out:
 140         return ret;
 141 }
 142
 143 /**
 144  * i2c_dw_init() - Initialize the designware I2C master hardware
 145  * @dev: device private data
 146  *
 147  * This functions configures and enables the I2C master.
 148  * This function is called during I2C init function, and in case of timeout at
 149  * run time.
 150  */
 151 static int i2c_dw_init_master(struct dw_i2c_dev *dev)
 152 {
 153         int ret;
 154
 155         ret = i2c_dw_acquire_lock(dev);
 156         if (ret)
 157                 return ret;
 158
 159         /* Disable the adapter */
 160         __i2c_dw_disable(dev);
 161
 162         /* Write standard speed timing parameters */
 163         dw_writel(dev, dev->ss_hcnt, DW_IC_SS_SCL_HCNT);
 164         dw_writel(dev, dev->ss_lcnt, DW_IC_SS_SCL_LCNT);
 165
 166         /* Write fast mode/fast mode plus timing parameters */
 167         dw_writel(dev, dev->fs_hcnt, DW_IC_FS_SCL_HCNT);
 168         dw_writel(dev, dev->fs_lcnt, DW_IC_FS_SCL_LCNT);
 169
 170         /* Write high speed timing parameters if supported */
 171         if (dev->hs_hcnt && dev->hs_lcnt) {
 172                 dw_writel(dev, dev->hs_hcnt, DW_IC_HS_SCL_HCNT);
 173                 dw_writel(dev, dev->hs_lcnt, DW_IC_HS_SCL_LCNT);
 174         }
 175
 176         /* Write SDA hold time if supported */
 177         if (dev->sda_hold_time)
 178                 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
 179
 180         i2c_dw_configure_fifo_master(dev);
 181         i2c_dw_release_lock(dev);
 182
 183         return 0;
 184 }
 185
 186 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 187 {
 188         struct i2c_msg *msgs = dev->msgs;
 189         u32 ic_con, ic_tar = 0;
 190
 191         /* Disable the adapter */
 192         __i2c_dw_disable(dev);
 193
 194         /* If the slave address is ten bit address, enable 10BITADDR */
 195         ic_con = dw_readl(dev, DW_IC_CON);
 196         if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
 197                 ic_con |= DW_IC_CON_10BITADDR_MASTER;
 198                 /*
 199                  * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
 200                  * mode has to be enabled via bit 12 of IC_TAR register.
 201                  * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
 202                  * detected from registers.
 203                  */
 204                 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
 205         } else {
 206                 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
 207         }
 208
 209         dw_writel(dev, ic_con, DW_IC_CON);
 210
 211         /*
 212          * Set the slave (target) address and enable 10-bit addressing mode
 213          * if applicable.
 214          */
 215         dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
 216
 217         /* Enforce disabled interrupts (due to HW issues) */
 218         i2c_dw_disable_int(dev);
 219
 220         /* Enable the adapter */
 221         __i2c_dw_enable(dev);
 222
 223         /* Dummy read to avoid the register getting stuck on Bay Trail */
 224         dw_readl(dev, DW_IC_ENABLE_STATUS);
 225
 226         /* Clear and enable interrupts */
 227         dw_readl(dev, DW_IC_CLR_INTR);
 228         dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK);
 229 }
 230
 231 /*
 232  * Initiate (and continue) low level master read/write transaction.
 233  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 234  * messages into the tx buffer.  Even if the size of i2c_msg data is
 235  * longer than the size of the tx buffer, it handles everything.
 236  */
 237 static void
 238 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 239 {
 240         struct i2c_msg *msgs = dev->msgs;
 241         u32 intr_mask;
 242         int tx_limit, rx_limit;
 243         u32 addr = msgs[dev->msg_write_idx].addr;
 244         u32 buf_len = dev->tx_buf_len;
 245         u8 *buf = dev->tx_buf;
 246         bool need_restart = false;
 247
 248         intr_mask = DW_IC_INTR_MASTER_MASK;
 249
 250         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 251                 u32 flags = msgs[dev->msg_write_idx].flags;
 252
 253                 /*
 254                  * If target address has changed, we need to
 255                  * reprogram the target address in the I2C
 256                  * adapter when we are done with this transfer.
 257                  */
 258                 if (msgs[dev->msg_write_idx].addr != addr) {
 259                         dev_err(dev->dev,
 260                                 "%s: invalid target address\n", __func__);
 261                         dev->msg_err = -EINVAL;
 262                         break;
 263                 }
 264
 265                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 266                         /* new i2c_msg */
 267                         buf = msgs[dev->msg_write_idx].buf;
 268                         buf_len = msgs[dev->msg_write_idx].len;
 269
 270                         /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
 271                          * IC_RESTART_EN are set, we must manually
 272                          * set restart bit between messages.
 273                          */
 274                         if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
 275                                         (dev->msg_write_idx > 0))
 276                                 need_restart = true;
 277                 }
 278
 279                 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
 280                 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
 281
 282                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 283                         u32 cmd = 0;
 284
 285                         /*
 286                          * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
 287                          * manually set the stop bit. However, it cannot be
 288                          * detected from the registers so we set it always
 289                          * when writing/reading the last byte.
 290                          */
 291
 292                         /*
 293                          * i2c-core always sets the buffer length of
 294                          * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
 295                          * be adjusted when receiving the first byte.
 296                          * Thus we can't stop the transaction here.
 297                          */
 298                         if (dev->msg_write_idx == dev->msgs_num - 1 &&
 299                             buf_len == 1 && !(flags & I2C_M_RECV_LEN))
 300                                 cmd |= BIT(9);
 301
 302                         if (need_restart) {
 303                                 cmd |= BIT(10);
 304                                 need_restart = false;
 305                         }
 306
 307                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 308
 309                                 /* Avoid rx buffer overrun */
 310                                 if (dev->rx_outstanding >= dev->rx_fifo_depth)
 311                                         break;
 312
 313                                 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
 314                                 rx_limit--;
 315                                 dev->rx_outstanding++;
 316                         } else
 317                                 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
 318                         tx_limit--; buf_len--;
 319                 }
 320
 321                 dev->tx_buf = buf;
 322                 dev->tx_buf_len = buf_len;
 323
 324                 /*
 325                  * Because we don't know the buffer length in the
 326                  * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
 327                  * the transaction here.
 328                  */
 329                 if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
 330                         /* more bytes to be written */
 331                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 332                         break;
 333                 } else
 334                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 335         }
 336
 337         /*
 338          * If i2c_msg index search is completed, we don't need TX_EMPTY
 339          * interrupt any more.
 340          */
 341         if (dev->msg_write_idx == dev->msgs_num)
 342                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 343
 344         if (dev->msg_err)
 345                 intr_mask = 0;
 346
 347         dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
 348 }
 349
 350 static u8
 351 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
 352 {
 353         struct i2c_msg *msgs = dev->msgs;
 354         u32 flags = msgs[dev->msg_read_idx].flags;
 355
 356         /*
 357          * Adjust the buffer length and mask the flag
 358          * after receiving the first byte.
 359          */
 360         len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
 361         dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
 362         msgs[dev->msg_read_idx].len = len;
 363         msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
 364
 365         return len;
 366 }
 367
 368 static void
 369 i2c_dw_read(struct dw_i2c_dev *dev)
 370 {
 371         struct i2c_msg *msgs = dev->msgs;
 372         int rx_valid;
 373
 374         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 375                 u32 len;
 376                 u8 *buf;
 377
 378                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 379                         continue;
 380
 381                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 382                         len = msgs[dev->msg_read_idx].len;
 383                         buf = msgs[dev->msg_read_idx].buf;
 384                 } else {
 385                         len = dev->rx_buf_len;
 386                         buf = dev->rx_buf;
 387                 }
 388
 389                 rx_valid = dw_readl(dev, DW_IC_RXFLR);
 390
 391                 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
 392                         u32 flags = msgs[dev->msg_read_idx].flags;
 393
 394                         *buf = dw_readl(dev, DW_IC_DATA_CMD);
 395                         /* Ensure length byte is a valid value */
 396                         if (flags & I2C_M_RECV_LEN &&
 397                                 *buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) {
 398                                 len = i2c_dw_recv_len(dev, *buf);
 399                         }
 400                         buf++;
 401                         dev->rx_outstanding--;
 402                 }
 403
 404                 if (len > 0) {
 405                         dev->status |= STATUS_READ_IN_PROGRESS;
 406                         dev->rx_buf_len = len;
 407                         dev->rx_buf = buf;
 408                         return;
 409                 } else
 410                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 411         }
 412 }
 413
 414 /*
 415  * Prepare controller for a transaction and call i2c_dw_xfer_msg.
 416  */
 417 static int
 418 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 419 {
 420         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 421         int ret;
 422
 423         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 424
 425         pm_runtime_get_sync(dev->dev);
 426
 427         reinit_completion(&dev->cmd_complete);
 428         dev->msgs = msgs;
 429         dev->msgs_num = num;
 430         dev->cmd_err = 0;
 431         dev->msg_write_idx = 0;
 432         dev->msg_read_idx = 0;
 433         dev->msg_err = 0;
 434         dev->status = STATUS_IDLE;
 435         dev->abort_source = 0;
 436         dev->rx_outstanding = 0;
 437
 438         ret = i2c_dw_acquire_lock(dev);
 439         if (ret)
 440                 goto done_nolock;
 441
 442         ret = i2c_dw_wait_bus_not_busy(dev);
 443         if (ret < 0)
 444                 goto done;
 445
 446         /* Start the transfers */
 447         i2c_dw_xfer_init(dev);
 448
 449         /* Wait for tx to complete */
 450         if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
 451                 dev_err(dev->dev, "controller timed out\n");
 452                 /* i2c_dw_init implicitly disables the adapter */
 453                 i2c_recover_bus(&dev->adapter);
 454                 i2c_dw_init_master(dev);
 455                 ret = -ETIMEDOUT;
 456                 goto done;
 457         }
 458
 459         /*
 460          * We must disable the adapter before returning and signaling the end
 461          * of the current transfer. Otherwise the hardware might continue
 462          * generating interrupts which in turn causes a race condition with
 463          * the following transfer.  Needs some more investigation if the
 464          * additional interrupts are a hardware bug or this driver doesn't
 465          * handle them correctly yet.
 466          */
 467         __i2c_dw_disable_nowait(dev);
 468
 469         if (dev->msg_err) {
 470                 ret = dev->msg_err;
 471                 goto done;
 472         }
 473
 474         /* No error */
 475         if (likely(!dev->cmd_err && !dev->status)) {
 476                 ret = num;
 477                 goto done;
 478         }
 479
 480         /* We have an error */
 481         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 482                 ret = i2c_dw_handle_tx_abort(dev);
 483                 goto done;
 484         }
 485
 486         if (dev->status)
 487                 dev_err(dev->dev,
 488                         "transfer terminated early - interrupt latency too high?\n");
 489
 490         ret = -EIO;
 491
 492 done:
 493         i2c_dw_release_lock(dev);
 494
 495 done_nolock:
 496         pm_runtime_mark_last_busy(dev->dev);
 497         pm_runtime_put_autosuspend(dev->dev);
 498
 499         return ret;
 500 }
 501
 502 static const struct i2c_algorithm i2c_dw_algo = {
 503         .master_xfer = i2c_dw_xfer,
 504         .functionality = i2c_dw_func,
 505 };
 506
 507 static const struct i2c_adapter_quirks i2c_dw_quirks = {
 508         .flags = I2C_AQ_NO_ZERO_LEN,
 509 };
 510
 511 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 512 {
 513         u32 stat;
 514
 515         /*
 516          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 517          * Ths unmasked raw version of interrupt status bits are available
 518          * in the IC_RAW_INTR_STAT register.
 519          *
 520          * That is,
 521          *   stat = dw_readl(IC_INTR_STAT);
 522          * equals to,
 523          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 524          *
 525          * The raw version might be useful for debugging purposes.
 526          */
 527         stat = dw_readl(dev, DW_IC_INTR_STAT);
 528
 529         /*
 530          * Do not use the IC_CLR_INTR register to clear interrupts, or
 531          * you'll miss some interrupts, triggered during the period from
 532          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 533          *
 534          * Instead, use the separately-prepared IC_CLR_* registers.
 535          */
 536         if (stat & DW_IC_INTR_RX_UNDER)
 537                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 538         if (stat & DW_IC_INTR_RX_OVER)
 539                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 540         if (stat & DW_IC_INTR_TX_OVER)
 541                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 542         if (stat & DW_IC_INTR_RD_REQ)
 543                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 544         if (stat & DW_IC_INTR_TX_ABRT) {
 545                 /*
 546                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 547                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 548                  */
 549                 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
 550                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 551         }
 552         if (stat & DW_IC_INTR_RX_DONE)
 553                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 554         if (stat & DW_IC_INTR_ACTIVITY)
 555                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 556         if (stat & DW_IC_INTR_STOP_DET)
 557                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 558         if (stat & DW_IC_INTR_START_DET)
 559                 dw_readl(dev, DW_IC_CLR_START_DET);
 560         if (stat & DW_IC_INTR_GEN_CALL)
 561                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 562
 563         return stat;
 564 }
 565
 566 /*
 567  * Interrupt service routine. This gets called whenever an I2C master interrupt
 568  * occurs.
 569  */
 570 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
 571 {
 572         u32 stat;
 573
 574         stat = i2c_dw_read_clear_intrbits(dev);
 575         if (stat & DW_IC_INTR_TX_ABRT) {
 576                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 577                 dev->status = STATUS_IDLE;
 578
 579                 /*
 580                  * Anytime TX_ABRT is set, the contents of the tx/rx
 581                  * buffers are flushed. Make sure to skip them.
 582                  */
 583                 dw_writel(dev, 0, DW_IC_INTR_MASK);
 584                 goto tx_aborted;
 585         }
 586
 587         if (stat & DW_IC_INTR_RX_FULL)
 588                 i2c_dw_read(dev);
 589
 590         if (stat & DW_IC_INTR_TX_EMPTY)
 591                 i2c_dw_xfer_msg(dev);
 592
 593         /*
 594          * No need to modify or disable the interrupt mask here.
 595          * i2c_dw_xfer_msg() will take care of it according to
 596          * the current transmit status.
 597          */
 598
 599 tx_aborted:
 600         if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
 601                 complete(&dev->cmd_complete);
 602         else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
 603                 /* Workaround to trigger pending interrupt */
 604                 stat = dw_readl(dev, DW_IC_INTR_MASK);
 605                 i2c_dw_disable_int(dev);
 606                 dw_writel(dev, stat, DW_IC_INTR_MASK);
 607         }
 608
 609         return 0;
 610 }
 611
 612 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 613 {
 614         struct dw_i2c_dev *dev = dev_id;
 615         u32 stat, enabled;
 616
 617         enabled = dw_readl(dev, DW_IC_ENABLE);
 618         stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 619         dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
 620         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 621                 return IRQ_NONE;
 622
 623         i2c_dw_irq_handler_master(dev);
 624
 625         return IRQ_HANDLED;
 626 }
 627
 628 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
 629 {
 630         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 631
 632         i2c_dw_disable(dev);
 633         reset_control_assert(dev->rst);
 634         i2c_dw_prepare_clk(dev, false);
 635 }
 636
 637 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
 638 {
 639         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 640
 641         i2c_dw_prepare_clk(dev, true);
 642         reset_control_deassert(dev->rst);
 643         i2c_dw_init_master(dev);
 644 }
 645
 646 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
 647 {
 648         struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
 649         struct i2c_adapter *adap = &dev->adapter;
 650         struct gpio_desc *gpio;
 651         int r;
 652
 653         gpio = devm_gpiod_get(dev->dev, "scl", GPIOD_OUT_HIGH);
 654         if (IS_ERR(gpio)) {
 655                 r = PTR_ERR(gpio);
 656                 if (r == -ENOENT || r == -ENOSYS)
 657                         return 0;
 658                 return r;
 659         }
 660         rinfo->scl_gpiod = gpio;
 661
 662         gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
 663         if (IS_ERR(gpio))
 664                 return PTR_ERR(gpio);
 665         rinfo->sda_gpiod = gpio;
 666
 667         rinfo->recover_bus = i2c_generic_scl_recovery;
 668         rinfo->prepare_recovery = i2c_dw_prepare_recovery;
 669         rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
 670         adap->bus_recovery_info = rinfo;
 671
 672         dev_info(dev->dev, "running with gpio recovery mode! scl%s",
 673                  rinfo->sda_gpiod ? ",sda" : "");
 674
 675         return 0;
 676 }
 677
 678 int i2c_dw_probe(struct dw_i2c_dev *dev)
 679 {
 680         struct i2c_adapter *adap = &dev->adapter;
 681         unsigned long irq_flags;
 682         int ret;
 683
 684         init_completion(&dev->cmd_complete);
 685
 686         dev->init = i2c_dw_init_master;
 687         dev->disable = i2c_dw_disable;
 688         dev->disable_int = i2c_dw_disable_int;
 689
 690         ret = i2c_dw_set_reg_access(dev);
 691         if (ret)
 692                 return ret;
 693
 694         ret = i2c_dw_set_timings_master(dev);
 695         if (ret)
 696                 return ret;
 697
 698         ret = dev->init(dev);
 699         if (ret)
 700                 return ret;
 701
 702         snprintf(adap->name, sizeof(adap->name),
 703                  "Synopsys DesignWare I2C adapter");
 704         adap->retries = 3;
 705         adap->algo = &i2c_dw_algo;
 706         adap->quirks = &i2c_dw_quirks;
 707         adap->dev.parent = dev->dev;
 708         i2c_set_adapdata(adap, dev);
 709
 710         if (dev->pm_disabled) {
 711                 dev_pm_syscore_device(dev->dev, true);
 712                 irq_flags = IRQF_NO_SUSPEND;
 713         } else {
 714                 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
 715         }
 716
 717         i2c_dw_disable_int(dev);
 718         ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
 719                                dev_name(dev->dev), dev);
 720         if (ret) {
 721                 dev_err(dev->dev, "failure requesting irq %i: %d\n",
 722                         dev->irq, ret);
 723                 return ret;
 724         }
 725
 726         ret = i2c_dw_init_recovery_info(dev);
 727         if (ret)
 728                 return ret;
 729
 730         /*
 731          * Increment PM usage count during adapter registration in order to
 732          * avoid possible spurious runtime suspend when adapter device is
 733          * registered to the device core and immediate resume in case bus has
 734          * registered I2C slaves that do I2C transfers in their probe.
 735          */
 736         pm_runtime_get_noresume(dev->dev);
 737         ret = i2c_add_numbered_adapter(adap);
 738         if (ret)
 739                 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
 740         pm_runtime_put_noidle(dev->dev);
 741
 742         return ret;
 743 }
 744 EXPORT_SYMBOL_GPL(i2c_dw_probe);
 745
 746 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
 747 MODULE_LICENSE("GPL");