2 * Synopsys DesignWare I2C adapter driver (master only).
4 * Based on the TI DAVINCI I2C adapter driver.
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
10 * ----------------------------------------------------------------------------
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 * ----------------------------------------------------------------------------
24 #include <linux/export.h>
25 #include <linux/errno.h>
26 #include <linux/err.h>
27 #include <linux/i2c.h>
28 #include <linux/interrupt.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/delay.h>
32 #include <linux/module.h>
33 #include "i2c-designware-core.h"
40 #define DW_IC_DATA_CMD 0x10
41 #define DW_IC_SS_SCL_HCNT 0x14
42 #define DW_IC_SS_SCL_LCNT 0x18
43 #define DW_IC_FS_SCL_HCNT 0x1c
44 #define DW_IC_FS_SCL_LCNT 0x20
45 #define DW_IC_HS_SCL_HCNT 0x24
46 #define DW_IC_HS_SCL_LCNT 0x28
47 #define DW_IC_INTR_STAT 0x2c
48 #define DW_IC_INTR_MASK 0x30
49 #define DW_IC_RAW_INTR_STAT 0x34
50 #define DW_IC_RX_TL 0x38
51 #define DW_IC_TX_TL 0x3c
52 #define DW_IC_CLR_INTR 0x40
53 #define DW_IC_CLR_RX_UNDER 0x44
54 #define DW_IC_CLR_RX_OVER 0x48
55 #define DW_IC_CLR_TX_OVER 0x4c
56 #define DW_IC_CLR_RD_REQ 0x50
57 #define DW_IC_CLR_TX_ABRT 0x54
58 #define DW_IC_CLR_RX_DONE 0x58
59 #define DW_IC_CLR_ACTIVITY 0x5c
60 #define DW_IC_CLR_STOP_DET 0x60
61 #define DW_IC_CLR_START_DET 0x64
62 #define DW_IC_CLR_GEN_CALL 0x68
63 #define DW_IC_ENABLE 0x6c
64 #define DW_IC_STATUS 0x70
65 #define DW_IC_TXFLR 0x74
66 #define DW_IC_RXFLR 0x78
67 #define DW_IC_SDA_HOLD 0x7c
68 #define DW_IC_TX_ABRT_SOURCE 0x80
69 #define DW_IC_ENABLE_STATUS 0x9c
70 #define DW_IC_COMP_PARAM_1 0xf4
71 #define DW_IC_COMP_VERSION 0xf8
72 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
73 #define DW_IC_COMP_TYPE 0xfc
74 #define DW_IC_COMP_TYPE_VALUE 0x44570140
76 #define DW_IC_INTR_RX_UNDER 0x001
77 #define DW_IC_INTR_RX_OVER 0x002
78 #define DW_IC_INTR_RX_FULL 0x004
79 #define DW_IC_INTR_TX_OVER 0x008
80 #define DW_IC_INTR_TX_EMPTY 0x010
81 #define DW_IC_INTR_RD_REQ 0x020
82 #define DW_IC_INTR_TX_ABRT 0x040
83 #define DW_IC_INTR_RX_DONE 0x080
84 #define DW_IC_INTR_ACTIVITY 0x100
85 #define DW_IC_INTR_STOP_DET 0x200
86 #define DW_IC_INTR_START_DET 0x400
87 #define DW_IC_INTR_GEN_CALL 0x800
89 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
90 DW_IC_INTR_TX_EMPTY | \
91 DW_IC_INTR_TX_ABRT | \
94 #define DW_IC_STATUS_ACTIVITY 0x1
95 #define DW_IC_STATUS_TFE BIT(2)
96 #define DW_IC_STATUS_MST_ACTIVITY BIT(5)
98 #define DW_IC_ERR_TX_ABRT 0x1
100 #define DW_IC_TAR_10BITADDR_MASTER BIT(12)
102 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
103 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2)
108 #define STATUS_IDLE 0x0
109 #define STATUS_WRITE_IN_PROGRESS 0x1
110 #define STATUS_READ_IN_PROGRESS 0x2
112 #define TIMEOUT 20 /* ms */
115 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
117 * only expected abort codes are listed here
118 * refer to the datasheet for the full list
120 #define ABRT_7B_ADDR_NOACK 0
121 #define ABRT_10ADDR1_NOACK 1
122 #define ABRT_10ADDR2_NOACK 2
123 #define ABRT_TXDATA_NOACK 3
124 #define ABRT_GCALL_NOACK 4
125 #define ABRT_GCALL_READ 5
126 #define ABRT_SBYTE_ACKDET 7
127 #define ABRT_SBYTE_NORSTRT 9
128 #define ABRT_10B_RD_NORSTRT 10
129 #define ABRT_MASTER_DIS 11
132 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
133 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
134 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
135 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
136 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
137 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
138 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
139 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
140 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
141 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
142 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
144 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
145 DW_IC_TX_ABRT_10ADDR1_NOACK | \
146 DW_IC_TX_ABRT_10ADDR2_NOACK | \
147 DW_IC_TX_ABRT_TXDATA_NOACK | \
148 DW_IC_TX_ABRT_GCALL_NOACK)
150 static char *abort_sources[] = {
151 [ABRT_7B_ADDR_NOACK] =
152 "slave address not acknowledged (7bit mode)",
153 [ABRT_10ADDR1_NOACK] =
154 "first address byte not acknowledged (10bit mode)",
155 [ABRT_10ADDR2_NOACK] =
156 "second address byte not acknowledged (10bit mode)",
157 [ABRT_TXDATA_NOACK] =
158 "data not acknowledged",
160 "no acknowledgement for a general call",
162 "read after general call",
163 [ABRT_SBYTE_ACKDET] =
164 "start byte acknowledged",
165 [ABRT_SBYTE_NORSTRT] =
166 "trying to send start byte when restart is disabled",
167 [ABRT_10B_RD_NORSTRT] =
168 "trying to read when restart is disabled (10bit mode)",
170 "trying to use disabled adapter",
175 static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
179 if (dev->accessor_flags & ACCESS_16BIT)
180 value = readw_relaxed(dev->base + offset) |
181 (readw_relaxed(dev->base + offset + 2) << 16);
183 value = readl_relaxed(dev->base + offset);
185 if (dev->accessor_flags & ACCESS_SWAP)
186 return swab32(value);
191 static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
193 if (dev->accessor_flags & ACCESS_SWAP)
196 if (dev->accessor_flags & ACCESS_16BIT) {
197 writew_relaxed((u16)b, dev->base + offset);
198 writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
200 writel_relaxed(b, dev->base + offset);
205 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
208 * DesignWare I2C core doesn't seem to have solid strategy to meet
209 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
210 * will result in violation of the tHD;STA spec.
214 * Conditional expression:
216 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
218 * This is based on the DW manuals, and represents an ideal
219 * configuration. The resulting I2C bus speed will be
220 * faster than any of the others.
222 * If your hardware is free from tHD;STA issue, try this one.
224 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
227 * Conditional expression:
229 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
231 * This is just experimental rule; the tHD;STA period turned
232 * out to be proportinal to (_HCNT + 3). With this setting,
233 * we could meet both tHIGH and tHD;STA timing specs.
235 * If unsure, you'd better to take this alternative.
237 * The reason why we need to take into account "tf" here,
238 * is the same as described in i2c_dw_scl_lcnt().
240 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
244 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
247 * Conditional expression:
249 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
251 * DW I2C core starts counting the SCL CNTs for the LOW period
252 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
253 * In order to meet the tLOW timing spec, we need to take into
254 * account the fall time of SCL signal (tf). Default tf value
255 * should be 0.3 us, for safety.
257 return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
260 static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
262 dw_writel(dev, enable, DW_IC_ENABLE);
265 static void __i2c_dw_enable_and_wait(struct dw_i2c_dev *dev, bool enable)
270 __i2c_dw_enable(dev, enable);
271 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
275 * Wait 10 times the signaling period of the highest I2C
276 * transfer supported by the driver (for 400KHz this is
277 * 25us) as described in the DesignWare I2C databook.
279 usleep_range(25, 250);
282 dev_warn(dev->dev, "timeout in %sabling adapter\n",
283 enable ? "en" : "dis");
286 static unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
289 * Clock is not necessary if we got LCNT/HCNT values directly from
292 if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
294 return dev->get_clk_rate_khz(dev);
297 static int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
301 if (!dev->acquire_lock)
304 ret = dev->acquire_lock(dev);
308 dev_err(dev->dev, "couldn't acquire bus ownership\n");
313 static void i2c_dw_release_lock(struct dw_i2c_dev *dev)
315 if (dev->release_lock)
316 dev->release_lock(dev);
320 * i2c_dw_init() - initialize the designware i2c master hardware
321 * @dev: device private data
323 * This functions configures and enables the I2C master.
324 * This function is called during I2C init function, and in case of timeout at
327 int i2c_dw_init(struct dw_i2c_dev *dev)
330 u32 reg, comp_param1;
331 u32 sda_falling_time, scl_falling_time;
334 ret = i2c_dw_acquire_lock(dev);
338 reg = dw_readl(dev, DW_IC_COMP_TYPE);
339 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
340 /* Configure register endianess access */
341 dev->accessor_flags |= ACCESS_SWAP;
342 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
343 /* Configure register access mode 16bit */
344 dev->accessor_flags |= ACCESS_16BIT;
345 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
346 dev_err(dev->dev, "Unknown Synopsys component type: "
348 i2c_dw_release_lock(dev);
352 comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
354 /* Disable the adapter */
355 __i2c_dw_enable_and_wait(dev, false);
357 /* set standard and fast speed deviders for high/low periods */
359 sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
360 scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
362 /* Set SCL timing parameters for standard-mode */
363 if (dev->ss_hcnt && dev->ss_lcnt) {
367 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
368 4000, /* tHD;STA = tHIGH = 4.0 us */
370 0, /* 0: DW default, 1: Ideal */
372 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
373 4700, /* tLOW = 4.7 us */
377 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
378 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
379 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
381 /* Set SCL timing parameters for fast-mode or fast-mode plus */
382 if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {
385 } else if (dev->fs_hcnt && dev->fs_lcnt) {
389 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
390 600, /* tHD;STA = tHIGH = 0.6 us */
392 0, /* 0: DW default, 1: Ideal */
394 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
395 1300, /* tLOW = 1.3 us */
399 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
400 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
401 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
403 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
404 DW_IC_CON_SPEED_HIGH) {
405 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
406 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
407 dev_err(dev->dev, "High Speed not supported!\n");
408 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
409 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
410 } else if (dev->hs_hcnt && dev->hs_lcnt) {
413 dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);
414 dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);
415 dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
420 /* Configure SDA Hold Time if required */
421 if (dev->sda_hold_time) {
422 reg = dw_readl(dev, DW_IC_COMP_VERSION);
423 if (reg >= DW_IC_SDA_HOLD_MIN_VERS)
424 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
427 "Hardware too old to adjust SDA hold time.");
430 /* Configure Tx/Rx FIFO threshold levels */
431 dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
432 dw_writel(dev, 0, DW_IC_RX_TL);
434 /* configure the i2c master */
435 dw_writel(dev, dev->master_cfg , DW_IC_CON);
437 i2c_dw_release_lock(dev);
441 EXPORT_SYMBOL_GPL(i2c_dw_init);
444 * Waiting for bus not busy
446 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
448 int timeout = TIMEOUT;
450 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
452 dev_warn(dev->dev, "timeout waiting for bus ready\n");
456 usleep_range(1000, 1100);
462 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
464 struct i2c_msg *msgs = dev->msgs;
468 enabled = dw_readl(dev, DW_IC_ENABLE_STATUS) & 1;
474 * Only disable adapter if ic_tar and ic_con can't be
475 * dynamically updated
477 ic_status = dw_readl(dev, DW_IC_STATUS);
478 if (!dev->dynamic_tar_update_enabled ||
479 (ic_status & DW_IC_STATUS_MST_ACTIVITY) ||
480 !(ic_status & DW_IC_STATUS_TFE)) {
481 __i2c_dw_enable_and_wait(dev, false);
486 /* if the slave address is ten bit address, enable 10BITADDR */
487 if (dev->dynamic_tar_update_enabled) {
489 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
490 * mode has to be enabled via bit 12 of IC_TAR register,
491 * otherwise bit 4 of IC_CON is used.
493 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
494 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
496 u32 ic_con = dw_readl(dev, DW_IC_CON);
498 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
499 ic_con |= DW_IC_CON_10BITADDR_MASTER;
501 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
502 dw_writel(dev, ic_con, DW_IC_CON);
506 * Set the slave (target) address and enable 10-bit addressing mode
509 dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
511 /* enforce disabled interrupts (due to HW issues) */
512 i2c_dw_disable_int(dev);
515 __i2c_dw_enable(dev, true);
517 /* Clear and enable interrupts */
518 dw_readl(dev, DW_IC_CLR_INTR);
519 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
523 * Initiate (and continue) low level master read/write transaction.
524 * This function is only called from i2c_dw_isr, and pumping i2c_msg
525 * messages into the tx buffer. Even if the size of i2c_msg data is
526 * longer than the size of the tx buffer, it handles everything.
529 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
531 struct i2c_msg *msgs = dev->msgs;
533 int tx_limit, rx_limit;
534 u32 addr = msgs[dev->msg_write_idx].addr;
535 u32 buf_len = dev->tx_buf_len;
536 u8 *buf = dev->tx_buf;
537 bool need_restart = false;
539 intr_mask = DW_IC_INTR_DEFAULT_MASK;
541 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
543 * if target address has changed, we need to
544 * reprogram the target address in the i2c
545 * adapter when we are done with this transfer
547 if (msgs[dev->msg_write_idx].addr != addr) {
549 "%s: invalid target address\n", __func__);
550 dev->msg_err = -EINVAL;
554 if (msgs[dev->msg_write_idx].len == 0) {
556 "%s: invalid message length\n", __func__);
557 dev->msg_err = -EINVAL;
561 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
563 buf = msgs[dev->msg_write_idx].buf;
564 buf_len = msgs[dev->msg_write_idx].len;
566 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
567 * IC_RESTART_EN are set, we must manually
568 * set restart bit between messages.
570 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
571 (dev->msg_write_idx > 0))
575 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
576 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
578 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
582 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
583 * manually set the stop bit. However, it cannot be
584 * detected from the registers so we set it always
585 * when writing/reading the last byte.
587 if (dev->msg_write_idx == dev->msgs_num - 1 &&
593 need_restart = false;
596 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
598 /* avoid rx buffer overrun */
599 if (rx_limit - dev->rx_outstanding <= 0)
602 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
604 dev->rx_outstanding++;
606 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
607 tx_limit--; buf_len--;
611 dev->tx_buf_len = buf_len;
614 /* more bytes to be written */
615 dev->status |= STATUS_WRITE_IN_PROGRESS;
618 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
622 * If i2c_msg index search is completed, we don't need TX_EMPTY
623 * interrupt any more.
625 if (dev->msg_write_idx == dev->msgs_num)
626 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
631 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
635 i2c_dw_read(struct dw_i2c_dev *dev)
637 struct i2c_msg *msgs = dev->msgs;
640 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
644 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
647 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
648 len = msgs[dev->msg_read_idx].len;
649 buf = msgs[dev->msg_read_idx].buf;
651 len = dev->rx_buf_len;
655 rx_valid = dw_readl(dev, DW_IC_RXFLR);
657 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
658 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
659 dev->rx_outstanding--;
663 dev->status |= STATUS_READ_IN_PROGRESS;
664 dev->rx_buf_len = len;
668 dev->status &= ~STATUS_READ_IN_PROGRESS;
672 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
674 unsigned long abort_source = dev->abort_source;
677 if (abort_source & DW_IC_TX_ABRT_NOACK) {
678 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
680 "%s: %s\n", __func__, abort_sources[i]);
684 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
685 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
687 if (abort_source & DW_IC_TX_ARB_LOST)
689 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
690 return -EINVAL; /* wrong msgs[] data */
696 * Prepare controller for a transaction and start transfer by calling
700 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
702 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
705 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
707 pm_runtime_get_sync(dev->dev);
709 reinit_completion(&dev->cmd_complete);
713 dev->msg_write_idx = 0;
714 dev->msg_read_idx = 0;
716 dev->status = STATUS_IDLE;
717 dev->abort_source = 0;
718 dev->rx_outstanding = 0;
720 ret = i2c_dw_acquire_lock(dev);
724 ret = i2c_dw_wait_bus_not_busy(dev);
728 /* start the transfers */
729 i2c_dw_xfer_init(dev);
731 /* wait for tx to complete */
732 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
733 dev_err(dev->dev, "controller timed out\n");
734 /* i2c_dw_init implicitly disables the adapter */
746 if (likely(!dev->cmd_err)) {
751 /* We have an error */
752 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
753 ret = i2c_dw_handle_tx_abort(dev);
759 i2c_dw_release_lock(dev);
762 pm_runtime_mark_last_busy(dev->dev);
763 pm_runtime_put_autosuspend(dev->dev);
768 static u32 i2c_dw_func(struct i2c_adapter *adap)
770 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
771 return dev->functionality;
774 static struct i2c_algorithm i2c_dw_algo = {
775 .master_xfer = i2c_dw_xfer,
776 .functionality = i2c_dw_func,
779 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
784 * The IC_INTR_STAT register just indicates "enabled" interrupts.
785 * Ths unmasked raw version of interrupt status bits are available
786 * in the IC_RAW_INTR_STAT register.
789 * stat = dw_readl(IC_INTR_STAT);
791 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
793 * The raw version might be useful for debugging purposes.
795 stat = dw_readl(dev, DW_IC_INTR_STAT);
798 * Do not use the IC_CLR_INTR register to clear interrupts, or
799 * you'll miss some interrupts, triggered during the period from
800 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
802 * Instead, use the separately-prepared IC_CLR_* registers.
804 if (stat & DW_IC_INTR_RX_UNDER)
805 dw_readl(dev, DW_IC_CLR_RX_UNDER);
806 if (stat & DW_IC_INTR_RX_OVER)
807 dw_readl(dev, DW_IC_CLR_RX_OVER);
808 if (stat & DW_IC_INTR_TX_OVER)
809 dw_readl(dev, DW_IC_CLR_TX_OVER);
810 if (stat & DW_IC_INTR_RD_REQ)
811 dw_readl(dev, DW_IC_CLR_RD_REQ);
812 if (stat & DW_IC_INTR_TX_ABRT) {
814 * The IC_TX_ABRT_SOURCE register is cleared whenever
815 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
817 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
818 dw_readl(dev, DW_IC_CLR_TX_ABRT);
820 if (stat & DW_IC_INTR_RX_DONE)
821 dw_readl(dev, DW_IC_CLR_RX_DONE);
822 if (stat & DW_IC_INTR_ACTIVITY)
823 dw_readl(dev, DW_IC_CLR_ACTIVITY);
824 if (stat & DW_IC_INTR_STOP_DET)
825 dw_readl(dev, DW_IC_CLR_STOP_DET);
826 if (stat & DW_IC_INTR_START_DET)
827 dw_readl(dev, DW_IC_CLR_START_DET);
828 if (stat & DW_IC_INTR_GEN_CALL)
829 dw_readl(dev, DW_IC_CLR_GEN_CALL);
835 * Interrupt service routine. This gets called whenever an I2C interrupt
838 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
840 struct dw_i2c_dev *dev = dev_id;
843 enabled = dw_readl(dev, DW_IC_ENABLE);
844 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
845 dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat);
846 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
849 stat = i2c_dw_read_clear_intrbits(dev);
851 if (stat & DW_IC_INTR_TX_ABRT) {
852 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
853 dev->status = STATUS_IDLE;
856 * Anytime TX_ABRT is set, the contents of the tx/rx
857 * buffers are flushed. Make sure to skip them.
859 dw_writel(dev, 0, DW_IC_INTR_MASK);
863 if (stat & DW_IC_INTR_RX_FULL)
866 if (stat & DW_IC_INTR_TX_EMPTY)
867 i2c_dw_xfer_msg(dev);
870 * No need to modify or disable the interrupt mask here.
871 * i2c_dw_xfer_msg() will take care of it according to
872 * the current transmit status.
876 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET))
879 * We must disable interruts before returning and signaling
880 * the end of the current transfer. Otherwise the hardware
881 * might continue generating interrupts for non-existent
884 i2c_dw_disable_int(dev);
885 dw_readl(dev, DW_IC_CLR_INTR);
887 complete(&dev->cmd_complete);
888 } else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) {
889 /* workaround to trigger pending interrupt */
890 stat = dw_readl(dev, DW_IC_INTR_MASK);
891 i2c_dw_disable_int(dev);
892 dw_writel(dev, stat, DW_IC_INTR_MASK);
898 void i2c_dw_disable(struct dw_i2c_dev *dev)
900 /* Disable controller */
901 __i2c_dw_enable_and_wait(dev, false);
903 /* Disable all interupts */
904 dw_writel(dev, 0, DW_IC_INTR_MASK);
905 dw_readl(dev, DW_IC_CLR_INTR);
907 EXPORT_SYMBOL_GPL(i2c_dw_disable);
909 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
911 dw_writel(dev, 0, DW_IC_INTR_MASK);
913 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
915 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
917 return dw_readl(dev, DW_IC_COMP_PARAM_1);
919 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
921 int i2c_dw_probe(struct dw_i2c_dev *dev)
923 struct i2c_adapter *adap = &dev->adapter;
927 init_completion(&dev->cmd_complete);
929 r = i2c_dw_init(dev);
933 r = i2c_dw_acquire_lock(dev);
938 * Test if dynamic TAR update is enabled in this controller by writing
939 * to IC_10BITADDR_MASTER field in IC_CON: when it is enabled this
940 * field is read-only so it should not succeed
942 reg = dw_readl(dev, DW_IC_CON);
943 dw_writel(dev, reg ^ DW_IC_CON_10BITADDR_MASTER, DW_IC_CON);
945 if ((dw_readl(dev, DW_IC_CON) & DW_IC_CON_10BITADDR_MASTER) ==
946 (reg & DW_IC_CON_10BITADDR_MASTER)) {
947 dev->dynamic_tar_update_enabled = true;
948 dev_dbg(dev->dev, "Dynamic TAR update enabled");
951 i2c_dw_release_lock(dev);
953 snprintf(adap->name, sizeof(adap->name),
954 "Synopsys DesignWare I2C adapter");
956 adap->algo = &i2c_dw_algo;
957 adap->dev.parent = dev->dev;
958 i2c_set_adapdata(adap, dev);
960 i2c_dw_disable_int(dev);
961 r = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr,
962 IRQF_SHARED | IRQF_COND_SUSPEND,
963 dev_name(dev->dev), dev);
965 dev_err(dev->dev, "failure requesting irq %i: %d\n",
971 * Increment PM usage count during adapter registration in order to
972 * avoid possible spurious runtime suspend when adapter device is
973 * registered to the device core and immediate resume in case bus has
974 * registered I2C slaves that do I2C transfers in their probe.
976 pm_runtime_get_noresume(dev->dev);
977 r = i2c_add_numbered_adapter(adap);
979 dev_err(dev->dev, "failure adding adapter: %d\n", r);
980 pm_runtime_put_noidle(dev->dev);
984 EXPORT_SYMBOL_GPL(i2c_dw_probe);
986 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
987 MODULE_LICENSE("GPL");