1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * I2C bus driver for the Cadence I2C controller.
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
9 #include <linux/delay.h>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/reset.h>
21 /* Register offsets for the I2C device. */
22 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */
23 #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */
24 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
25 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
26 #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */
27 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */
28 #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */
29 #define CDNS_I2C_IMR_OFFSET 0x20 /* IRQ Mask Register, RO */
30 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */
31 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */
33 /* Control Register Bit mask definitions */
34 #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */
35 #define CDNS_I2C_CR_ACK_EN BIT(3)
36 #define CDNS_I2C_CR_NEA BIT(2)
37 #define CDNS_I2C_CR_MS BIT(1)
38 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
39 #define CDNS_I2C_CR_RW BIT(0)
40 /* 1 = Auto init FIFO to zeroes */
41 #define CDNS_I2C_CR_CLR_FIFO BIT(6)
42 #define CDNS_I2C_CR_DIVA_SHIFT 14
43 #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT)
44 #define CDNS_I2C_CR_DIVB_SHIFT 8
45 #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
47 #define CDNS_I2C_CR_MASTER_EN_MASK (CDNS_I2C_CR_NEA | \
48 CDNS_I2C_CR_ACK_EN | \
51 #define CDNS_I2C_CR_SLAVE_EN_MASK ~CDNS_I2C_CR_MASTER_EN_MASK
53 /* Status Register Bit mask definitions */
54 #define CDNS_I2C_SR_BA BIT(8)
55 #define CDNS_I2C_SR_TXDV BIT(6)
56 #define CDNS_I2C_SR_RXDV BIT(5)
57 #define CDNS_I2C_SR_RXRW BIT(3)
60 * I2C Address Register Bit mask definitions
61 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
62 * bits. A write access to this register always initiates a transfer if the I2C
65 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
68 * I2C Interrupt Registers Bit mask definitions
69 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
72 #define CDNS_I2C_IXR_ARB_LOST BIT(9)
73 #define CDNS_I2C_IXR_RX_UNF BIT(7)
74 #define CDNS_I2C_IXR_TX_OVF BIT(6)
75 #define CDNS_I2C_IXR_RX_OVF BIT(5)
76 #define CDNS_I2C_IXR_SLV_RDY BIT(4)
77 #define CDNS_I2C_IXR_TO BIT(3)
78 #define CDNS_I2C_IXR_NACK BIT(2)
79 #define CDNS_I2C_IXR_DATA BIT(1)
80 #define CDNS_I2C_IXR_COMP BIT(0)
82 #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
83 CDNS_I2C_IXR_RX_UNF | \
84 CDNS_I2C_IXR_TX_OVF | \
85 CDNS_I2C_IXR_RX_OVF | \
86 CDNS_I2C_IXR_SLV_RDY | \
92 #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
93 CDNS_I2C_IXR_RX_UNF | \
94 CDNS_I2C_IXR_TX_OVF | \
95 CDNS_I2C_IXR_RX_OVF | \
98 #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
99 CDNS_I2C_IXR_RX_UNF | \
100 CDNS_I2C_IXR_TX_OVF | \
101 CDNS_I2C_IXR_RX_OVF | \
102 CDNS_I2C_IXR_NACK | \
103 CDNS_I2C_IXR_DATA | \
106 #define CDNS_I2C_IXR_SLAVE_INTR_MASK (CDNS_I2C_IXR_RX_UNF | \
107 CDNS_I2C_IXR_TX_OVF | \
108 CDNS_I2C_IXR_RX_OVF | \
110 CDNS_I2C_IXR_NACK | \
111 CDNS_I2C_IXR_DATA | \
114 #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000)
115 /* timeout for pm runtime autosuspend */
116 #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */
118 #define CDNS_I2C_FIFO_DEPTH_DEFAULT 16
119 #define CDNS_I2C_MAX_TRANSFER_SIZE 255
120 /* Transfer size in multiples of data interrupt depth */
121 #define CDNS_I2C_TRANSFER_SIZE(max) ((max) - 3)
123 #define DRIVER_NAME "cdns-i2c"
125 #define CDNS_I2C_DIVA_MAX 4
126 #define CDNS_I2C_DIVB_MAX 64
128 #define CDNS_I2C_TIMEOUT_MAX 0xFF
130 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
131 #define CDNS_I2C_POLL_US 100000
132 #define CDNS_I2C_TIMEOUT_US 500000
134 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
135 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
137 #if IS_ENABLED(CONFIG_I2C_SLAVE)
139 * enum cdns_i2c_mode - I2C Controller current operating mode
141 * @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode
142 * @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode
146 CDNS_I2C_MODE_MASTER,
150 * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode
152 * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle
153 * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master
154 * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master
156 enum cdns_i2c_slave_state {
157 CDNS_I2C_SLAVE_STATE_IDLE,
158 CDNS_I2C_SLAVE_STATE_SEND,
159 CDNS_I2C_SLAVE_STATE_RECV,
164 * struct cdns_i2c - I2C device private data structure
166 * @dev: Pointer to device structure
167 * @membase: Base address of the I2C device
168 * @adap: I2C adapter instance
169 * @p_msg: Message pointer
170 * @err_status: Error status in Interrupt Status Register
171 * @xfer_done: Transfer complete status
172 * @p_send_buf: Pointer to transmit buffer
173 * @p_recv_buf: Pointer to receive buffer
174 * @send_count: Number of bytes still expected to send
175 * @recv_count: Number of bytes still expected to receive
176 * @curr_recv_count: Number of bytes to be received in current transfer
177 * @input_clk: Input clock to I2C controller
178 * @i2c_clk: Maximum I2C clock speed
179 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit
180 * @clk: Pointer to struct clk
181 * @clk_rate_change_nb: Notifier block for clock rate changes
182 * @reset: Reset control for the device
183 * @quirks: flag for broken hold bit usage in r1p10
184 * @ctrl_reg: Cached value of the control register.
185 * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register
186 * @slave: Registered slave instance.
187 * @dev_mode: I2C operating role(master/slave).
188 * @slave_state: I2C Slave state(idle/read/write).
189 * @fifo_depth: The depth of the transfer FIFO
190 * @transfer_size: The maximum number of bytes in one transfer
194 void __iomem *membase;
195 struct i2c_adapter adap;
196 struct i2c_msg *p_msg;
198 struct completion xfer_done;
199 unsigned char *p_send_buf;
200 unsigned char *p_recv_buf;
201 unsigned int send_count;
202 unsigned int recv_count;
203 unsigned int curr_recv_count;
204 unsigned long input_clk;
205 unsigned int i2c_clk;
206 unsigned int bus_hold_flag;
208 struct notifier_block clk_rate_change_nb;
209 struct reset_control *reset;
212 struct i2c_bus_recovery_info rinfo;
213 #if IS_ENABLED(CONFIG_I2C_SLAVE)
214 u16 ctrl_reg_diva_divb;
215 struct i2c_client *slave;
216 enum cdns_i2c_mode dev_mode;
217 enum cdns_i2c_slave_state slave_state;
220 unsigned int transfer_size;
223 struct cdns_platform_data {
227 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \
231 * cdns_i2c_clear_bus_hold - Clear bus hold bit
232 * @id: Pointer to driver data struct
234 * Helper to clear the controller's bus hold bit.
236 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
238 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
239 if (reg & CDNS_I2C_CR_HOLD)
240 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
243 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
245 return (hold_wrkaround &&
246 (id->curr_recv_count == id->fifo_depth + 1));
249 #if IS_ENABLED(CONFIG_I2C_SLAVE)
250 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id)
252 /* Disable all interrupts */
253 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
255 /* Clear FIFO and transfer size */
256 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
258 /* Update device mode and state */
260 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
263 case CDNS_I2C_MODE_MASTER:
264 /* Enable i2c master */
265 cdns_i2c_writereg(id->ctrl_reg_diva_divb |
266 CDNS_I2C_CR_MASTER_EN_MASK,
269 * This delay is needed to give the IP some time to switch to
270 * the master mode. With lower values(like 110 us) i2cdetect
271 * will not detect any slave and without this delay, the IP will
272 * trigger a timeout interrupt.
274 usleep_range(115, 125);
276 case CDNS_I2C_MODE_SLAVE:
277 /* Enable i2c slave */
278 cdns_i2c_writereg(id->ctrl_reg_diva_divb &
279 CDNS_I2C_CR_SLAVE_EN_MASK,
282 /* Setting slave address */
283 cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK,
284 CDNS_I2C_ADDR_OFFSET);
286 /* Enable slave send/receive interrupts */
287 cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK,
288 CDNS_I2C_IER_OFFSET);
293 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id)
298 /* Prepare backend for data reception */
299 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
300 id->slave_state = CDNS_I2C_SLAVE_STATE_RECV;
301 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL);
304 /* Fetch number of bytes to receive */
305 bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
307 /* Read data and send to backend */
309 data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
310 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data);
314 static void cdns_i2c_slave_send_data(struct cdns_i2c *id)
318 /* Prepare backend for data transmission */
319 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
320 id->slave_state = CDNS_I2C_SLAVE_STATE_SEND;
321 i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data);
323 i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data);
326 /* Send data over bus */
327 cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET);
331 * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role
332 * @ptr: Pointer to I2C device private data
334 * This function handles the data interrupt and transfer complete interrupt of
335 * the I2C device in slave role.
337 * Return: IRQ_HANDLED always
339 static irqreturn_t cdns_i2c_slave_isr(void *ptr)
341 struct cdns_i2c *id = ptr;
342 unsigned int isr_status, i2c_status;
344 /* Fetch the interrupt status */
345 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
346 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
348 /* Ignore masked interrupts */
349 isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET);
351 /* Fetch transfer mode (send/receive) */
352 i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
354 /* Handle data send/receive */
355 if (i2c_status & CDNS_I2C_SR_RXRW) {
356 /* Send data to master */
357 if (isr_status & CDNS_I2C_IXR_DATA)
358 cdns_i2c_slave_send_data(id);
360 if (isr_status & CDNS_I2C_IXR_COMP) {
361 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
362 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
365 /* Receive data from master */
366 if (isr_status & CDNS_I2C_IXR_DATA)
367 cdns_i2c_slave_rcv_data(id);
369 if (isr_status & CDNS_I2C_IXR_COMP) {
370 cdns_i2c_slave_rcv_data(id);
371 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
372 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
376 /* Master indicated xfer stop or fifo underflow/overflow */
377 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF |
378 CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) {
379 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
380 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
381 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
389 * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role
390 * @ptr: Pointer to I2C device private data
392 * This function handles the data interrupt, transfer complete interrupt and
393 * the error interrupts of the I2C device in master role.
395 * Return: IRQ_HANDLED always
397 static irqreturn_t cdns_i2c_master_isr(void *ptr)
399 unsigned int isr_status, avail_bytes;
400 unsigned int bytes_to_send;
402 struct cdns_i2c *id = ptr;
403 /* Signal completion only after everything is updated */
405 irqreturn_t status = IRQ_NONE;
407 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
408 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
411 /* Handling nack and arbitration lost interrupt */
412 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
414 status = IRQ_HANDLED;
418 * Check if transfer size register needs to be updated again for a
419 * large data receive operation.
421 updatetx = id->recv_count > id->curr_recv_count;
423 /* When receiving, handle data interrupt and completion interrupt */
424 if (id->p_recv_buf &&
425 ((isr_status & CDNS_I2C_IXR_COMP) ||
426 (isr_status & CDNS_I2C_IXR_DATA))) {
427 /* Read data if receive data valid is set */
428 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
430 if (id->recv_count > 0) {
431 *(id->p_recv_buf)++ =
432 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
434 id->curr_recv_count--;
437 * Clear hold bit that was set for FIFO control
438 * if RX data left is less than or equal to
439 * FIFO DEPTH unless repeated start is selected
441 if (id->recv_count <= id->fifo_depth &&
443 cdns_i2c_clear_bus_hold(id);
446 dev_err(id->adap.dev.parent,
447 "xfer_size reg rollover. xfer aborted!\n");
448 id->err_status |= CDNS_I2C_IXR_TO;
452 if (cdns_is_holdquirk(id, updatetx))
457 * The controller sends NACK to the slave when transfer size
458 * register reaches zero without considering the HOLD bit.
459 * This workaround is implemented for large data transfers to
460 * maintain transfer size non-zero while performing a large
463 if (cdns_is_holdquirk(id, updatetx)) {
464 /* wait while fifo is full */
465 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
466 (id->curr_recv_count - id->fifo_depth))
470 * Check number of bytes to be received against maximum
471 * transfer size and update register accordingly.
473 if (((int)(id->recv_count) - id->fifo_depth) >
475 cdns_i2c_writereg(id->transfer_size,
476 CDNS_I2C_XFER_SIZE_OFFSET);
477 id->curr_recv_count = id->transfer_size +
480 cdns_i2c_writereg(id->recv_count -
482 CDNS_I2C_XFER_SIZE_OFFSET);
483 id->curr_recv_count = id->recv_count;
487 /* Clear hold (if not repeated start) and signal completion */
488 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
489 if (!id->bus_hold_flag)
490 cdns_i2c_clear_bus_hold(id);
494 status = IRQ_HANDLED;
497 /* When sending, handle transfer complete interrupt */
498 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
500 * If there is more data to be sent, calculate the
501 * space available in FIFO and fill with that many bytes.
503 if (id->send_count) {
504 avail_bytes = id->fifo_depth -
505 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
506 if (id->send_count > avail_bytes)
507 bytes_to_send = avail_bytes;
509 bytes_to_send = id->send_count;
511 while (bytes_to_send--) {
513 (*(id->p_send_buf)++),
514 CDNS_I2C_DATA_OFFSET);
519 * Signal the completion of transaction and
520 * clear the hold bus bit if there are no
521 * further messages to be processed.
525 if (!id->send_count && !id->bus_hold_flag)
526 cdns_i2c_clear_bus_hold(id);
528 status = IRQ_HANDLED;
531 /* Update the status for errors */
532 id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
534 status = IRQ_HANDLED;
537 complete(&id->xfer_done);
543 * cdns_i2c_isr - Interrupt handler for the I2C device
544 * @irq: irq number for the I2C device
545 * @ptr: void pointer to cdns_i2c structure
547 * This function passes the control to slave/master based on current role of
550 * Return: IRQ_HANDLED always
552 static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
554 #if IS_ENABLED(CONFIG_I2C_SLAVE)
555 struct cdns_i2c *id = ptr;
557 if (id->dev_mode == CDNS_I2C_MODE_SLAVE)
558 return cdns_i2c_slave_isr(ptr);
560 return cdns_i2c_master_isr(ptr);
564 * cdns_i2c_mrecv - Prepare and start a master receive operation
565 * @id: pointer to the i2c device structure
567 static void cdns_i2c_mrecv(struct cdns_i2c *id)
569 unsigned int ctrl_reg;
570 unsigned int isr_status;
572 bool hold_clear = false;
573 bool irq_save = false;
577 id->p_recv_buf = id->p_msg->buf;
578 id->recv_count = id->p_msg->len;
580 /* Put the controller in master receive mode and clear the FIFO */
581 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
582 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
585 * Receive up to I2C_SMBUS_BLOCK_MAX data bytes, plus one message length
586 * byte, plus one checksum byte if PEC is enabled. p_msg->len will be 2 if
587 * PEC is enabled, otherwise 1.
589 if (id->p_msg->flags & I2C_M_RECV_LEN)
590 id->recv_count = I2C_SMBUS_BLOCK_MAX + id->p_msg->len;
592 id->curr_recv_count = id->recv_count;
595 * Check for the message size against FIFO depth and set the
596 * 'hold bus' bit if it is greater than FIFO depth.
598 if (id->recv_count > id->fifo_depth)
599 ctrl_reg |= CDNS_I2C_CR_HOLD;
601 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
603 /* Clear the interrupts in interrupt status register */
604 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
605 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
608 * The no. of bytes to receive is checked against the limit of
609 * max transfer size. Set transfer size register with no of bytes
610 * receive if it is less than transfer size and transfer size if
611 * it is more. Enable the interrupts.
613 if (id->recv_count > id->transfer_size) {
614 cdns_i2c_writereg(id->transfer_size,
615 CDNS_I2C_XFER_SIZE_OFFSET);
616 id->curr_recv_count = id->transfer_size;
618 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
621 /* Determine hold_clear based on number of bytes to receive and hold flag */
622 if (!id->bus_hold_flag && id->recv_count <= id->fifo_depth) {
623 if (ctrl_reg & CDNS_I2C_CR_HOLD) {
625 if (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT)
630 addr = id->p_msg->addr;
631 addr &= CDNS_I2C_ADDR_MASK;
634 ctrl_reg &= ~CDNS_I2C_CR_HOLD;
636 * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size
637 * register reaches '0'. This is an IP bug which causes transfer size
638 * register overflow to 0xFF. To satisfy this timing requirement,
639 * disable the interrupts on current processor core between register
640 * writes to slave address register and control register.
643 local_irq_save(flags);
645 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET);
646 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
647 /* Read it back to avoid bufferring and make sure write happens */
648 cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
651 local_irq_restore(flags);
653 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET);
656 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
660 * cdns_i2c_msend - Prepare and start a master send operation
661 * @id: pointer to the i2c device
663 static void cdns_i2c_msend(struct cdns_i2c *id)
665 unsigned int avail_bytes;
666 unsigned int bytes_to_send;
667 unsigned int ctrl_reg;
668 unsigned int isr_status;
670 id->p_recv_buf = NULL;
671 id->p_send_buf = id->p_msg->buf;
672 id->send_count = id->p_msg->len;
674 /* Set the controller in Master transmit mode and clear the FIFO. */
675 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
676 ctrl_reg &= ~CDNS_I2C_CR_RW;
677 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
680 * Check for the message size against FIFO depth and set the
681 * 'hold bus' bit if it is greater than FIFO depth.
683 if (id->send_count > id->fifo_depth)
684 ctrl_reg |= CDNS_I2C_CR_HOLD;
685 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
687 /* Clear the interrupts in interrupt status register. */
688 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
689 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
692 * Calculate the space available in FIFO. Check the message length
693 * against the space available, and fill the FIFO accordingly.
694 * Enable the interrupts.
696 avail_bytes = id->fifo_depth -
697 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
699 if (id->send_count > avail_bytes)
700 bytes_to_send = avail_bytes;
702 bytes_to_send = id->send_count;
704 while (bytes_to_send--) {
705 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
710 * Clear the bus hold flag if there is no more data
711 * and if it is the last message.
713 if (!id->bus_hold_flag && !id->send_count)
714 cdns_i2c_clear_bus_hold(id);
715 /* Set the slave address in address register - triggers operation. */
716 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
717 CDNS_I2C_ADDR_OFFSET);
719 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
723 * cdns_i2c_master_reset - Reset the interface
724 * @adap: pointer to the i2c adapter driver instance
726 * This function cleanup the fifos, clear the hold bit and status
727 * and disable the interrupts.
729 static void cdns_i2c_master_reset(struct i2c_adapter *adap)
731 struct cdns_i2c *id = adap->algo_data;
734 /* Disable the interrupts */
735 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
736 /* Clear the hold bit and fifos */
737 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
738 regval &= ~CDNS_I2C_CR_HOLD;
739 regval |= CDNS_I2C_CR_CLR_FIFO;
740 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
741 /* Update the transfercount register to zero */
742 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
743 /* Clear the interrupt status register */
744 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
745 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
746 /* Clear the status register */
747 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
748 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
751 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
752 struct i2c_adapter *adap)
754 unsigned long time_left, msg_timeout;
759 reinit_completion(&id->xfer_done);
761 /* Check for the TEN Bit mode on each msg */
762 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
763 if (msg->flags & I2C_M_TEN) {
764 if (reg & CDNS_I2C_CR_NEA)
765 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
768 if (!(reg & CDNS_I2C_CR_NEA))
769 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
773 /* Check for the R/W flag on each msg */
774 if (msg->flags & I2C_M_RD)
779 /* Minimal time to execute this message */
780 msg_timeout = msecs_to_jiffies((1000 * msg->len * BITS_PER_BYTE) / id->i2c_clk);
781 /* Plus some wiggle room */
782 msg_timeout += msecs_to_jiffies(500);
784 if (msg_timeout < adap->timeout)
785 msg_timeout = adap->timeout;
787 /* Wait for the signal of completion */
788 time_left = wait_for_completion_timeout(&id->xfer_done, msg_timeout);
789 if (time_left == 0) {
790 cdns_i2c_master_reset(adap);
791 dev_err(id->adap.dev.parent,
792 "timeout waiting on completion\n");
796 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
797 CDNS_I2C_IDR_OFFSET);
799 /* If it is bus arbitration error, try again */
800 if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
803 if (msg->flags & I2C_M_RECV_LEN)
804 msg->len += min_t(unsigned int, msg->buf[0], I2C_SMBUS_BLOCK_MAX);
810 * cdns_i2c_master_xfer - The main i2c transfer function
811 * @adap: pointer to the i2c adapter driver instance
812 * @msgs: pointer to the i2c message structure
813 * @num: the number of messages to transfer
815 * Initiates the send/recv activity based on the transfer message received.
817 * Return: number of msgs processed on success, negative error otherwise
819 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
824 struct cdns_i2c *id = adap->algo_data;
826 #if IS_ENABLED(CONFIG_I2C_SLAVE)
827 bool change_role = false;
830 ret = pm_runtime_resume_and_get(id->dev);
834 #if IS_ENABLED(CONFIG_I2C_SLAVE)
835 /* Check i2c operating mode and switch if possible */
836 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) {
837 if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE) {
842 /* Set mode to master */
843 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
845 /* Mark flag to change role once xfer is completed */
850 /* Check if the bus is free */
852 ret = readl_relaxed_poll_timeout(id->membase + CDNS_I2C_SR_OFFSET,
854 !(reg & CDNS_I2C_SR_BA),
855 CDNS_I2C_POLL_US, CDNS_I2C_TIMEOUT_US);
858 if (id->adap.bus_recovery_info)
859 i2c_recover_bus(adap);
863 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
865 * Set the flag to one when multiple messages are to be
866 * processed with a repeated start.
870 * This controller does not give completion interrupt after a
871 * master receive message if HOLD bit is set (repeated start),
872 * resulting in SW timeout. Hence, if a receive message is
873 * followed by any other message, an error is returned
874 * indicating that this sequence is not supported.
876 for (count = 0; (count < num - 1 && hold_quirk); count++) {
877 if (msgs[count].flags & I2C_M_RD) {
878 dev_warn(adap->dev.parent,
879 "Can't do repeated start after a receive message\n");
884 id->bus_hold_flag = 1;
885 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
886 reg |= CDNS_I2C_CR_HOLD;
887 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
889 id->bus_hold_flag = 0;
892 /* Process the msg one by one */
893 for (count = 0; count < num; count++, msgs++) {
894 if (count == (num - 1))
895 id->bus_hold_flag = 0;
897 ret = cdns_i2c_process_msg(id, msgs, adap);
901 /* Report the other error interrupts to application */
902 if (id->err_status) {
903 cdns_i2c_master_reset(adap);
905 if (id->err_status & CDNS_I2C_IXR_NACK) {
918 #if IS_ENABLED(CONFIG_I2C_SLAVE)
919 /* Switch i2c mode to slave */
921 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
924 pm_runtime_mark_last_busy(id->dev);
925 pm_runtime_put_autosuspend(id->dev);
930 * cdns_i2c_func - Returns the supported features of the I2C driver
931 * @adap: pointer to the i2c adapter structure
933 * Return: 32 bit value, each bit corresponding to a feature
935 static u32 cdns_i2c_func(struct i2c_adapter *adap)
937 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
938 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
939 I2C_FUNC_SMBUS_BLOCK_DATA;
941 #if IS_ENABLED(CONFIG_I2C_SLAVE)
942 func |= I2C_FUNC_SLAVE;
948 #if IS_ENABLED(CONFIG_I2C_SLAVE)
949 static int cdns_reg_slave(struct i2c_client *slave)
952 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
958 if (slave->flags & I2C_CLIENT_TEN)
959 return -EAFNOSUPPORT;
961 ret = pm_runtime_resume_and_get(id->dev);
965 /* Store slave information */
968 /* Enable I2C slave */
969 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
974 static int cdns_unreg_slave(struct i2c_client *slave)
976 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
979 pm_runtime_put(id->dev);
981 /* Remove slave information */
984 /* Enable I2C master */
985 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
991 static const struct i2c_algorithm cdns_i2c_algo = {
992 .master_xfer = cdns_i2c_master_xfer,
993 .functionality = cdns_i2c_func,
994 #if IS_ENABLED(CONFIG_I2C_SLAVE)
995 .reg_slave = cdns_reg_slave,
996 .unreg_slave = cdns_unreg_slave,
1001 * cdns_i2c_calc_divs - Calculate clock dividers
1002 * @f: I2C clock frequency
1003 * @input_clk: Input clock frequency
1004 * @a: First divider (return value)
1005 * @b: Second divider (return value)
1007 * f is used as input and output variable. As input it is used as target I2C
1008 * frequency. On function exit f holds the actually resulting I2C frequency.
1010 * Return: 0 on success, negative errno otherwise.
1012 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
1013 unsigned int *a, unsigned int *b)
1015 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
1016 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
1017 unsigned int last_error, current_error;
1019 /* calculate (divisor_a+1) x (divisor_b+1) */
1020 temp = input_clk / (22 * fscl);
1023 * If the calculated value is negative or 0, the fscl input is out of
1024 * range. Return error.
1026 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
1030 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
1031 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
1033 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
1037 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
1039 if (actual_fscl > fscl)
1042 current_error = fscl - actual_fscl;
1044 if (last_error > current_error) {
1047 best_fscl = actual_fscl;
1048 last_error = current_error;
1060 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
1061 * @clk_in: I2C clock input frequency in Hz
1062 * @id: Pointer to the I2C device structure
1064 * The device must be idle rather than busy transferring data before setting
1065 * these device options.
1066 * The data rate is set by values in the control register.
1067 * The formula for determining the correct register values is
1068 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
1069 * See the hardware data sheet for a full explanation of setting the serial
1070 * clock rate. The clock can not be faster than the input clock divide by 22.
1071 * The two most common clock rates are 100KHz and 400KHz.
1073 * Return: 0 on success, negative error otherwise
1075 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
1077 unsigned int div_a, div_b;
1078 unsigned int ctrl_reg;
1080 unsigned long fscl = id->i2c_clk;
1082 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
1086 ctrl_reg = id->ctrl_reg;
1087 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
1088 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
1089 (div_b << CDNS_I2C_CR_DIVB_SHIFT));
1090 id->ctrl_reg = ctrl_reg;
1091 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
1092 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1093 id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK |
1094 CDNS_I2C_CR_DIVB_MASK);
1100 * cdns_i2c_clk_notifier_cb - Clock rate change callback
1101 * @nb: Pointer to notifier block
1102 * @event: Notification reason
1103 * @data: Pointer to notification data object
1105 * This function is called when the cdns_i2c input clock frequency changes.
1106 * The callback checks whether a valid bus frequency can be generated after the
1107 * change. If so, the change is acknowledged, otherwise the change is aborted.
1108 * New dividers are written to the HW in the pre- or post change notification
1109 * depending on the scaling direction.
1111 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
1112 * to acknowledge the change, NOTIFY_DONE if the notification is
1113 * considered irrelevant.
1115 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
1118 struct clk_notifier_data *ndata = data;
1119 struct cdns_i2c *id = to_cdns_i2c(nb);
1121 if (pm_runtime_suspended(id->dev))
1125 case PRE_RATE_CHANGE:
1127 unsigned long input_clk = ndata->new_rate;
1128 unsigned long fscl = id->i2c_clk;
1129 unsigned int div_a, div_b;
1132 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
1134 dev_warn(id->adap.dev.parent,
1135 "clock rate change rejected\n");
1140 if (ndata->new_rate > ndata->old_rate)
1141 cdns_i2c_setclk(ndata->new_rate, id);
1145 case POST_RATE_CHANGE:
1146 id->input_clk = ndata->new_rate;
1148 if (ndata->new_rate < ndata->old_rate)
1149 cdns_i2c_setclk(ndata->new_rate, id);
1151 case ABORT_RATE_CHANGE:
1153 if (ndata->new_rate > ndata->old_rate)
1154 cdns_i2c_setclk(ndata->old_rate, id);
1162 * cdns_i2c_runtime_suspend - Runtime suspend method for the driver
1163 * @dev: Address of the platform_device structure
1165 * Put the driver into low power mode.
1169 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
1171 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1173 clk_disable(xi2c->clk);
1179 * cdns_i2c_init - Controller initialisation
1180 * @id: Device private data structure
1182 * Initialise the i2c controller.
1185 static void cdns_i2c_init(struct cdns_i2c *id)
1187 cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET);
1189 * Cadence I2C controller has a bug wherein it generates
1190 * invalid read transaction after HW timeout in master receiver mode.
1191 * HW timeout is not used by this driver and the interrupt is disabled.
1192 * But the feature itself cannot be disabled. Hence maximum value
1193 * is written to this register to reduce the chances of error.
1195 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
1199 * cdns_i2c_runtime_resume - Runtime resume
1200 * @dev: Address of the platform_device structure
1202 * Runtime resume callback.
1204 * Return: 0 on success and error value on error
1206 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
1208 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1211 ret = clk_enable(xi2c->clk);
1213 dev_err(dev, "Cannot enable clock.\n");
1216 cdns_i2c_init(xi2c);
1221 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = {
1222 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend,
1223 cdns_i2c_runtime_resume, NULL)
1226 static const struct cdns_platform_data r1p10_i2c_def = {
1227 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
1230 static const struct of_device_id cdns_i2c_of_match[] = {
1231 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
1232 { .compatible = "cdns,i2c-r1p14",},
1233 { /* end of table */ }
1235 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
1238 * cdns_i2c_detect_transfer_size - Detect the maximum transfer size supported
1239 * @id: Device private data structure
1241 * Detect the maximum transfer size that is supported by this instance of the
1242 * Cadence I2C controller.
1244 static void cdns_i2c_detect_transfer_size(struct cdns_i2c *id)
1249 * Writing to the transfer size register is only possible if these two bits
1250 * are set in the control register.
1252 cdns_i2c_writereg(CDNS_I2C_CR_MS | CDNS_I2C_CR_RW, CDNS_I2C_CR_OFFSET);
1255 * The number of writable bits of the transfer size register can be between
1256 * 4 and 8. This is a controlled through a synthesis parameter of the IP
1257 * core and can vary from instance to instance. The unused MSBs always read
1258 * back as 0. Writing 0xff and then reading the value back will report the
1259 * maximum supported transfer size.
1261 cdns_i2c_writereg(CDNS_I2C_MAX_TRANSFER_SIZE, CDNS_I2C_XFER_SIZE_OFFSET);
1262 val = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
1263 id->transfer_size = CDNS_I2C_TRANSFER_SIZE(val);
1264 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
1265 cdns_i2c_writereg(0, CDNS_I2C_CR_OFFSET);
1269 * cdns_i2c_probe - Platform registration call
1270 * @pdev: Handle to the platform device structure
1272 * This function does all the memory allocation and registration for the i2c
1273 * device. User can modify the address mode to 10 bit address mode using the
1274 * ioctl call with option I2C_TENBIT.
1276 * Return: 0 on success, negative error otherwise
1278 static int cdns_i2c_probe(struct platform_device *pdev)
1280 struct resource *r_mem;
1281 struct cdns_i2c *id;
1283 const struct of_device_id *match;
1285 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
1289 id->dev = &pdev->dev;
1290 platform_set_drvdata(pdev, id);
1292 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
1293 if (match && match->data) {
1294 const struct cdns_platform_data *data = match->data;
1295 id->quirks = data->quirks;
1298 id->rinfo.pinctrl = devm_pinctrl_get(&pdev->dev);
1299 if (IS_ERR(id->rinfo.pinctrl)) {
1300 int err = PTR_ERR(id->rinfo.pinctrl);
1302 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1306 id->adap.bus_recovery_info = &id->rinfo;
1309 id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem);
1310 if (IS_ERR(id->membase))
1311 return PTR_ERR(id->membase);
1313 irq = platform_get_irq(pdev, 0);
1317 id->adap.owner = THIS_MODULE;
1318 id->adap.dev.of_node = pdev->dev.of_node;
1319 id->adap.algo = &cdns_i2c_algo;
1320 id->adap.timeout = CDNS_I2C_TIMEOUT;
1321 id->adap.retries = 3; /* Default retry value. */
1322 id->adap.algo_data = id;
1323 id->adap.dev.parent = &pdev->dev;
1324 init_completion(&id->xfer_done);
1325 snprintf(id->adap.name, sizeof(id->adap.name),
1326 "Cadence I2C at %08lx", (unsigned long)r_mem->start);
1328 id->clk = devm_clk_get(&pdev->dev, NULL);
1329 if (IS_ERR(id->clk))
1330 return dev_err_probe(&pdev->dev, PTR_ERR(id->clk),
1331 "input clock not found.\n");
1333 id->reset = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
1334 if (IS_ERR(id->reset))
1335 return dev_err_probe(&pdev->dev, PTR_ERR(id->reset),
1336 "Failed to request reset.\n");
1338 ret = clk_prepare_enable(id->clk);
1340 dev_err(&pdev->dev, "Unable to enable clock.\n");
1342 ret = reset_control_deassert(id->reset);
1344 dev_err_probe(&pdev->dev, ret,
1345 "Failed to de-assert reset.\n");
1349 pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT);
1350 pm_runtime_use_autosuspend(id->dev);
1351 pm_runtime_set_active(id->dev);
1352 pm_runtime_enable(id->dev);
1354 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
1355 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
1356 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1357 id->input_clk = clk_get_rate(id->clk);
1359 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1361 if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ))
1362 id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ;
1364 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1365 /* Set initial mode to master */
1366 id->dev_mode = CDNS_I2C_MODE_MASTER;
1367 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
1369 id->ctrl_reg = CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS;
1371 id->fifo_depth = CDNS_I2C_FIFO_DEPTH_DEFAULT;
1372 of_property_read_u32(pdev->dev.of_node, "fifo-depth", &id->fifo_depth);
1374 cdns_i2c_detect_transfer_size(id);
1376 ret = cdns_i2c_setclk(id->input_clk, id);
1378 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
1380 goto err_clk_notifier_unregister;
1383 ret = devm_request_irq(&pdev->dev, irq, cdns_i2c_isr, 0,
1386 dev_err(&pdev->dev, "cannot get irq %d\n", irq);
1387 goto err_clk_notifier_unregister;
1391 ret = i2c_add_adapter(&id->adap);
1393 goto err_clk_notifier_unregister;
1395 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
1396 id->i2c_clk / 1000, (unsigned long)r_mem->start, irq);
1400 err_clk_notifier_unregister:
1401 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1402 reset_control_assert(id->reset);
1404 clk_disable_unprepare(id->clk);
1405 pm_runtime_disable(&pdev->dev);
1406 pm_runtime_set_suspended(&pdev->dev);
1411 * cdns_i2c_remove - Unregister the device after releasing the resources
1412 * @pdev: Handle to the platform device structure
1414 * This function frees all the resources allocated to the device.
1418 static void cdns_i2c_remove(struct platform_device *pdev)
1420 struct cdns_i2c *id = platform_get_drvdata(pdev);
1422 pm_runtime_disable(&pdev->dev);
1423 pm_runtime_set_suspended(&pdev->dev);
1424 pm_runtime_dont_use_autosuspend(&pdev->dev);
1426 i2c_del_adapter(&id->adap);
1427 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1428 reset_control_assert(id->reset);
1429 clk_disable_unprepare(id->clk);
1432 static struct platform_driver cdns_i2c_drv = {
1434 .name = DRIVER_NAME,
1435 .of_match_table = cdns_i2c_of_match,
1436 .pm = &cdns_i2c_dev_pm_ops,
1438 .probe = cdns_i2c_probe,
1439 .remove_new = cdns_i2c_remove,
1442 module_platform_driver(cdns_i2c_drv);
1444 MODULE_AUTHOR("Xilinx Inc.");
1445 MODULE_DESCRIPTION("Cadence I2C bus driver");
1446 MODULE_LICENSE("GPL");