1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
4 * Description: CoreSight Trace Memory Controller driver
7 #include <linux/kernel.h>
8 #include <linux/init.h>
9 #include <linux/types.h>
10 #include <linux/device.h>
11 #include <linux/idr.h>
13 #include <linux/err.h>
15 #include <linux/miscdevice.h>
16 #include <linux/mutex.h>
17 #include <linux/property.h>
18 #include <linux/uaccess.h>
19 #include <linux/slab.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/spinlock.h>
22 #include <linux/pm_runtime.h>
24 #include <linux/coresight.h>
25 #include <linux/amba/bus.h>
27 #include "coresight-priv.h"
28 #include "coresight-tmc.h"
30 DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb");
31 DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf");
32 DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr");
34 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
36 /* Ensure formatter, unformatter and hardware fifo are empty */
37 if (coresight_timeout(drvdata->base,
38 TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
39 dev_err(&drvdata->csdev->dev,
40 "timeout while waiting for TMC to be Ready\n");
44 void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
48 ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
49 ffcr |= TMC_FFCR_STOP_ON_FLUSH;
50 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
51 ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
52 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
53 /* Ensure flush completes */
54 if (coresight_timeout(drvdata->base,
55 TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
56 dev_err(&drvdata->csdev->dev,
57 "timeout while waiting for completion of Manual Flush\n");
60 tmc_wait_for_tmcready(drvdata);
63 void tmc_enable_hw(struct tmc_drvdata *drvdata)
65 writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
68 void tmc_disable_hw(struct tmc_drvdata *drvdata)
70 writel_relaxed(0x0, drvdata->base + TMC_CTL);
73 static int tmc_read_prepare(struct tmc_drvdata *drvdata)
77 switch (drvdata->config_type) {
78 case TMC_CONFIG_TYPE_ETB:
79 case TMC_CONFIG_TYPE_ETF:
80 ret = tmc_read_prepare_etb(drvdata);
82 case TMC_CONFIG_TYPE_ETR:
83 ret = tmc_read_prepare_etr(drvdata);
90 dev_dbg(&drvdata->csdev->dev, "TMC read start\n");
95 static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
99 switch (drvdata->config_type) {
100 case TMC_CONFIG_TYPE_ETB:
101 case TMC_CONFIG_TYPE_ETF:
102 ret = tmc_read_unprepare_etb(drvdata);
104 case TMC_CONFIG_TYPE_ETR:
105 ret = tmc_read_unprepare_etr(drvdata);
112 dev_dbg(&drvdata->csdev->dev, "TMC read end\n");
117 static int tmc_open(struct inode *inode, struct file *file)
120 struct tmc_drvdata *drvdata = container_of(file->private_data,
121 struct tmc_drvdata, miscdev);
123 ret = tmc_read_prepare(drvdata);
127 nonseekable_open(inode, file);
129 dev_dbg(&drvdata->csdev->dev, "%s: successfully opened\n", __func__);
133 static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata,
134 loff_t pos, size_t len, char **bufpp)
136 switch (drvdata->config_type) {
137 case TMC_CONFIG_TYPE_ETB:
138 case TMC_CONFIG_TYPE_ETF:
139 return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp);
140 case TMC_CONFIG_TYPE_ETR:
141 return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
147 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
152 struct tmc_drvdata *drvdata = container_of(file->private_data,
153 struct tmc_drvdata, miscdev);
154 actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp);
158 if (copy_to_user(data, bufp, actual)) {
159 dev_dbg(&drvdata->csdev->dev,
160 "%s: copy_to_user failed\n", __func__);
165 dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual);
170 static int tmc_release(struct inode *inode, struct file *file)
173 struct tmc_drvdata *drvdata = container_of(file->private_data,
174 struct tmc_drvdata, miscdev);
176 ret = tmc_read_unprepare(drvdata);
180 dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__);
184 static const struct file_operations tmc_fops = {
185 .owner = THIS_MODULE,
188 .release = tmc_release,
192 static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
194 enum tmc_mem_intf_width memwidth;
197 * Excerpt from the TRM:
199 * DEVID::MEMWIDTH[10:8]
200 * 0x2 Memory interface databus is 32 bits wide.
201 * 0x3 Memory interface databus is 64 bits wide.
202 * 0x4 Memory interface databus is 128 bits wide.
203 * 0x5 Memory interface databus is 256 bits wide.
205 switch (BMVAL(devid, 8, 10)) {
207 memwidth = TMC_MEM_INTF_WIDTH_32BITS;
210 memwidth = TMC_MEM_INTF_WIDTH_64BITS;
213 memwidth = TMC_MEM_INTF_WIDTH_128BITS;
216 memwidth = TMC_MEM_INTF_WIDTH_256BITS;
225 #define coresight_tmc_reg(name, offset) \
226 coresight_simple_reg32(struct tmc_drvdata, name, offset)
227 #define coresight_tmc_reg64(name, lo_off, hi_off) \
228 coresight_simple_reg64(struct tmc_drvdata, name, lo_off, hi_off)
230 coresight_tmc_reg(rsz, TMC_RSZ);
231 coresight_tmc_reg(sts, TMC_STS);
232 coresight_tmc_reg(trg, TMC_TRG);
233 coresight_tmc_reg(ctl, TMC_CTL);
234 coresight_tmc_reg(ffsr, TMC_FFSR);
235 coresight_tmc_reg(ffcr, TMC_FFCR);
236 coresight_tmc_reg(mode, TMC_MODE);
237 coresight_tmc_reg(pscr, TMC_PSCR);
238 coresight_tmc_reg(axictl, TMC_AXICTL);
239 coresight_tmc_reg(devid, CORESIGHT_DEVID);
240 coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI);
241 coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI);
242 coresight_tmc_reg64(dba, TMC_DBALO, TMC_DBAHI);
244 static struct attribute *coresight_tmc_mgmt_attrs[] = {
255 &dev_attr_devid.attr,
257 &dev_attr_axictl.attr,
261 static ssize_t trigger_cntr_show(struct device *dev,
262 struct device_attribute *attr, char *buf)
264 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
265 unsigned long val = drvdata->trigger_cntr;
267 return sprintf(buf, "%#lx\n", val);
270 static ssize_t trigger_cntr_store(struct device *dev,
271 struct device_attribute *attr,
272 const char *buf, size_t size)
276 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
278 ret = kstrtoul(buf, 16, &val);
282 drvdata->trigger_cntr = val;
285 static DEVICE_ATTR_RW(trigger_cntr);
287 static ssize_t buffer_size_show(struct device *dev,
288 struct device_attribute *attr, char *buf)
290 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
292 return sprintf(buf, "%#x\n", drvdata->size);
295 static ssize_t buffer_size_store(struct device *dev,
296 struct device_attribute *attr,
297 const char *buf, size_t size)
301 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
303 /* Only permitted for TMC-ETRs */
304 if (drvdata->config_type != TMC_CONFIG_TYPE_ETR)
307 ret = kstrtoul(buf, 0, &val);
310 /* The buffer size should be page aligned */
311 if (val & (PAGE_SIZE - 1))
317 static DEVICE_ATTR_RW(buffer_size);
319 static struct attribute *coresight_tmc_attrs[] = {
320 &dev_attr_trigger_cntr.attr,
321 &dev_attr_buffer_size.attr,
325 static const struct attribute_group coresight_tmc_group = {
326 .attrs = coresight_tmc_attrs,
329 static const struct attribute_group coresight_tmc_mgmt_group = {
330 .attrs = coresight_tmc_mgmt_attrs,
334 const struct attribute_group *coresight_tmc_groups[] = {
335 &coresight_tmc_group,
336 &coresight_tmc_mgmt_group,
340 static inline bool tmc_etr_can_use_sg(struct device *dev)
342 return fwnode_property_present(dev->fwnode, "arm,scatter-gather");
345 /* Detect and initialise the capabilities of a TMC ETR */
346 static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps)
350 struct tmc_drvdata *drvdata = dev_get_drvdata(parent);
352 /* Set the unadvertised capabilities */
353 tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
355 if (!(devid & TMC_DEVID_NOSCAT) && tmc_etr_can_use_sg(parent))
356 tmc_etr_set_cap(drvdata, TMC_ETR_SG);
358 /* Check if the AXI address width is available */
359 if (devid & TMC_DEVID_AXIAW_VALID)
360 dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) &
361 TMC_DEVID_AXIAW_MASK);
364 * Unless specified in the device configuration, ETR uses a 40-bit
365 * AXI master in place of the embedded SRAM of ETB/ETF.
373 dev_info(parent, "Detected dma mask %dbits\n", dma_mask);
379 rc = dma_set_mask_and_coherent(parent, DMA_BIT_MASK(dma_mask));
381 dev_err(parent, "Failed to setup DMA mask: %d\n", rc);
385 static u32 tmc_etr_get_default_buffer_size(struct device *dev)
389 if (fwnode_property_read_u32(dev->fwnode, "arm,buffer-size", &size))
394 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
399 struct device *dev = &adev->dev;
400 struct coresight_platform_data *pdata = NULL;
401 struct tmc_drvdata *drvdata;
402 struct resource *res = &adev->res;
403 struct coresight_desc desc = { 0 };
404 struct coresight_dev_list *dev_list = NULL;
407 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
411 dev_set_drvdata(dev, drvdata);
413 /* Validity for the resource is already checked by the AMBA core */
414 base = devm_ioremap_resource(dev, res);
420 drvdata->base = base;
422 spin_lock_init(&drvdata->spinlock);
424 devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
425 drvdata->config_type = BMVAL(devid, 6, 7);
426 drvdata->memwidth = tmc_get_memwidth(devid);
427 /* This device is not associated with a session */
430 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
431 drvdata->size = tmc_etr_get_default_buffer_size(dev);
433 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
436 desc.groups = coresight_tmc_groups;
438 switch (drvdata->config_type) {
439 case TMC_CONFIG_TYPE_ETB:
440 desc.type = CORESIGHT_DEV_TYPE_SINK;
441 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
442 desc.ops = &tmc_etb_cs_ops;
443 dev_list = &etb_devs;
445 case TMC_CONFIG_TYPE_ETR:
446 desc.type = CORESIGHT_DEV_TYPE_SINK;
447 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
448 desc.ops = &tmc_etr_cs_ops;
449 ret = tmc_etr_setup_caps(dev, devid,
450 coresight_get_uci_data(id));
453 idr_init(&drvdata->idr);
454 mutex_init(&drvdata->idr_mutex);
455 dev_list = &etr_devs;
457 case TMC_CONFIG_TYPE_ETF:
458 desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
459 desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
460 desc.ops = &tmc_etf_cs_ops;
461 dev_list = &etf_devs;
464 pr_err("%s: Unsupported TMC config\n", desc.name);
469 desc.name = coresight_alloc_device_name(dev_list, dev);
475 pdata = coresight_get_platform_data(dev);
477 ret = PTR_ERR(pdata);
480 adev->dev.platform_data = pdata;
483 drvdata->csdev = coresight_register(&desc);
484 if (IS_ERR(drvdata->csdev)) {
485 ret = PTR_ERR(drvdata->csdev);
489 drvdata->miscdev.name = desc.name;
490 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
491 drvdata->miscdev.fops = &tmc_fops;
492 ret = misc_register(&drvdata->miscdev);
494 coresight_unregister(drvdata->csdev);
496 pm_runtime_put(&adev->dev);
501 static const struct amba_id tmc_ids[] = {
502 CS_AMBA_ID(0x000bb961),
503 /* Coresight SoC 600 TMC-ETR/ETS */
504 CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS),
505 /* Coresight SoC 600 TMC-ETB */
506 CS_AMBA_ID(0x000bb9e9),
507 /* Coresight SoC 600 TMC-ETF */
508 CS_AMBA_ID(0x000bb9ea),
512 static struct amba_driver tmc_driver = {
514 .name = "coresight-tmc",
515 .owner = THIS_MODULE,
516 .suppress_bind_attrs = true,
521 builtin_amba_driver(tmc_driver);