1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
4 * Description: CoreSight Trace Memory Controller driver
7 #include <linux/kernel.h>
8 #include <linux/init.h>
9 #include <linux/types.h>
10 #include <linux/device.h>
11 #include <linux/idr.h>
13 #include <linux/err.h>
15 #include <linux/miscdevice.h>
16 #include <linux/mutex.h>
17 #include <linux/property.h>
18 #include <linux/uaccess.h>
19 #include <linux/slab.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/spinlock.h>
22 #include <linux/pm_runtime.h>
24 #include <linux/coresight.h>
25 #include <linux/amba/bus.h>
27 #include "coresight-priv.h"
28 #include "coresight-tmc.h"
30 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
32 /* Ensure formatter, unformatter and hardware fifo are empty */
33 if (coresight_timeout(drvdata->base,
34 TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
35 dev_err(&drvdata->csdev->dev,
36 "timeout while waiting for TMC to be Ready\n");
40 void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
44 ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
45 ffcr |= TMC_FFCR_STOP_ON_FLUSH;
46 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
47 ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
48 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
49 /* Ensure flush completes */
50 if (coresight_timeout(drvdata->base,
51 TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
52 dev_err(&drvdata->csdev->dev,
53 "timeout while waiting for completion of Manual Flush\n");
56 tmc_wait_for_tmcready(drvdata);
59 void tmc_enable_hw(struct tmc_drvdata *drvdata)
61 writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
64 void tmc_disable_hw(struct tmc_drvdata *drvdata)
66 writel_relaxed(0x0, drvdata->base + TMC_CTL);
69 static int tmc_read_prepare(struct tmc_drvdata *drvdata)
73 switch (drvdata->config_type) {
74 case TMC_CONFIG_TYPE_ETB:
75 case TMC_CONFIG_TYPE_ETF:
76 ret = tmc_read_prepare_etb(drvdata);
78 case TMC_CONFIG_TYPE_ETR:
79 ret = tmc_read_prepare_etr(drvdata);
86 dev_dbg(&drvdata->csdev->dev, "TMC read start\n");
91 static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
95 switch (drvdata->config_type) {
96 case TMC_CONFIG_TYPE_ETB:
97 case TMC_CONFIG_TYPE_ETF:
98 ret = tmc_read_unprepare_etb(drvdata);
100 case TMC_CONFIG_TYPE_ETR:
101 ret = tmc_read_unprepare_etr(drvdata);
108 dev_dbg(&drvdata->csdev->dev, "TMC read end\n");
113 static int tmc_open(struct inode *inode, struct file *file)
116 struct tmc_drvdata *drvdata = container_of(file->private_data,
117 struct tmc_drvdata, miscdev);
119 ret = tmc_read_prepare(drvdata);
123 nonseekable_open(inode, file);
125 dev_dbg(&drvdata->csdev->dev, "%s: successfully opened\n", __func__);
129 static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata,
130 loff_t pos, size_t len, char **bufpp)
132 switch (drvdata->config_type) {
133 case TMC_CONFIG_TYPE_ETB:
134 case TMC_CONFIG_TYPE_ETF:
135 return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp);
136 case TMC_CONFIG_TYPE_ETR:
137 return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
143 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
148 struct tmc_drvdata *drvdata = container_of(file->private_data,
149 struct tmc_drvdata, miscdev);
150 actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp);
154 if (copy_to_user(data, bufp, actual)) {
155 dev_dbg(&drvdata->csdev->dev,
156 "%s: copy_to_user failed\n", __func__);
161 dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual);
166 static int tmc_release(struct inode *inode, struct file *file)
169 struct tmc_drvdata *drvdata = container_of(file->private_data,
170 struct tmc_drvdata, miscdev);
172 ret = tmc_read_unprepare(drvdata);
176 dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__);
180 static const struct file_operations tmc_fops = {
181 .owner = THIS_MODULE,
184 .release = tmc_release,
188 static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
190 enum tmc_mem_intf_width memwidth;
193 * Excerpt from the TRM:
195 * DEVID::MEMWIDTH[10:8]
196 * 0x2 Memory interface databus is 32 bits wide.
197 * 0x3 Memory interface databus is 64 bits wide.
198 * 0x4 Memory interface databus is 128 bits wide.
199 * 0x5 Memory interface databus is 256 bits wide.
201 switch (BMVAL(devid, 8, 10)) {
203 memwidth = TMC_MEM_INTF_WIDTH_32BITS;
206 memwidth = TMC_MEM_INTF_WIDTH_64BITS;
209 memwidth = TMC_MEM_INTF_WIDTH_128BITS;
212 memwidth = TMC_MEM_INTF_WIDTH_256BITS;
221 #define coresight_tmc_reg(name, offset) \
222 coresight_simple_reg32(struct tmc_drvdata, name, offset)
223 #define coresight_tmc_reg64(name, lo_off, hi_off) \
224 coresight_simple_reg64(struct tmc_drvdata, name, lo_off, hi_off)
226 coresight_tmc_reg(rsz, TMC_RSZ);
227 coresight_tmc_reg(sts, TMC_STS);
228 coresight_tmc_reg(trg, TMC_TRG);
229 coresight_tmc_reg(ctl, TMC_CTL);
230 coresight_tmc_reg(ffsr, TMC_FFSR);
231 coresight_tmc_reg(ffcr, TMC_FFCR);
232 coresight_tmc_reg(mode, TMC_MODE);
233 coresight_tmc_reg(pscr, TMC_PSCR);
234 coresight_tmc_reg(axictl, TMC_AXICTL);
235 coresight_tmc_reg(devid, CORESIGHT_DEVID);
236 coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI);
237 coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI);
238 coresight_tmc_reg64(dba, TMC_DBALO, TMC_DBAHI);
240 static struct attribute *coresight_tmc_mgmt_attrs[] = {
251 &dev_attr_devid.attr,
253 &dev_attr_axictl.attr,
257 static ssize_t trigger_cntr_show(struct device *dev,
258 struct device_attribute *attr, char *buf)
260 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
261 unsigned long val = drvdata->trigger_cntr;
263 return sprintf(buf, "%#lx\n", val);
266 static ssize_t trigger_cntr_store(struct device *dev,
267 struct device_attribute *attr,
268 const char *buf, size_t size)
272 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
274 ret = kstrtoul(buf, 16, &val);
278 drvdata->trigger_cntr = val;
281 static DEVICE_ATTR_RW(trigger_cntr);
283 static ssize_t buffer_size_show(struct device *dev,
284 struct device_attribute *attr, char *buf)
286 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
288 return sprintf(buf, "%#x\n", drvdata->size);
291 static ssize_t buffer_size_store(struct device *dev,
292 struct device_attribute *attr,
293 const char *buf, size_t size)
297 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
299 /* Only permitted for TMC-ETRs */
300 if (drvdata->config_type != TMC_CONFIG_TYPE_ETR)
303 ret = kstrtoul(buf, 0, &val);
306 /* The buffer size should be page aligned */
307 if (val & (PAGE_SIZE - 1))
313 static DEVICE_ATTR_RW(buffer_size);
315 static struct attribute *coresight_tmc_attrs[] = {
316 &dev_attr_trigger_cntr.attr,
317 &dev_attr_buffer_size.attr,
321 static const struct attribute_group coresight_tmc_group = {
322 .attrs = coresight_tmc_attrs,
325 static const struct attribute_group coresight_tmc_mgmt_group = {
326 .attrs = coresight_tmc_mgmt_attrs,
330 const struct attribute_group *coresight_tmc_groups[] = {
331 &coresight_tmc_group,
332 &coresight_tmc_mgmt_group,
336 static inline bool tmc_etr_can_use_sg(struct device *dev)
338 return fwnode_property_present(dev->fwnode, "arm,scatter-gather");
341 /* Detect and initialise the capabilities of a TMC ETR */
342 static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps)
346 struct tmc_drvdata *drvdata = dev_get_drvdata(parent);
348 /* Set the unadvertised capabilities */
349 tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
351 if (!(devid & TMC_DEVID_NOSCAT) && tmc_etr_can_use_sg(parent))
352 tmc_etr_set_cap(drvdata, TMC_ETR_SG);
354 /* Check if the AXI address width is available */
355 if (devid & TMC_DEVID_AXIAW_VALID)
356 dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) &
357 TMC_DEVID_AXIAW_MASK);
360 * Unless specified in the device configuration, ETR uses a 40-bit
361 * AXI master in place of the embedded SRAM of ETB/ETF.
369 dev_info(parent, "Detected dma mask %dbits\n", dma_mask);
375 rc = dma_set_mask_and_coherent(parent, DMA_BIT_MASK(dma_mask));
377 dev_err(parent, "Failed to setup DMA mask: %d\n", rc);
381 static u32 tmc_etr_get_default_buffer_size(struct device *dev)
385 if (fwnode_property_read_u32(dev->fwnode, "arm,buffer-size", &size))
390 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
395 struct device *dev = &adev->dev;
396 struct coresight_platform_data *pdata = NULL;
397 struct tmc_drvdata *drvdata;
398 struct resource *res = &adev->res;
399 struct coresight_desc desc = { 0 };
401 pdata = coresight_get_platform_data(dev);
403 ret = PTR_ERR(pdata);
406 adev->dev.platform_data = pdata;
409 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
413 dev_set_drvdata(dev, drvdata);
415 /* Validity for the resource is already checked by the AMBA core */
416 base = devm_ioremap_resource(dev, res);
422 drvdata->base = base;
424 spin_lock_init(&drvdata->spinlock);
426 devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
427 drvdata->config_type = BMVAL(devid, 6, 7);
428 drvdata->memwidth = tmc_get_memwidth(devid);
429 /* This device is not associated with a session */
432 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
433 drvdata->size = tmc_etr_get_default_buffer_size(dev);
435 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
439 desc.groups = coresight_tmc_groups;
440 desc.name = dev_name(dev);
442 switch (drvdata->config_type) {
443 case TMC_CONFIG_TYPE_ETB:
444 desc.type = CORESIGHT_DEV_TYPE_SINK;
445 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
446 desc.ops = &tmc_etb_cs_ops;
448 case TMC_CONFIG_TYPE_ETR:
449 desc.type = CORESIGHT_DEV_TYPE_SINK;
450 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
451 desc.ops = &tmc_etr_cs_ops;
452 ret = tmc_etr_setup_caps(dev, devid,
453 coresight_get_uci_data(id));
456 idr_init(&drvdata->idr);
457 mutex_init(&drvdata->idr_mutex);
459 case TMC_CONFIG_TYPE_ETF:
460 desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
461 desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
462 desc.ops = &tmc_etf_cs_ops;
465 pr_err("%s: Unsupported TMC config\n", desc.name);
470 drvdata->csdev = coresight_register(&desc);
471 if (IS_ERR(drvdata->csdev)) {
472 ret = PTR_ERR(drvdata->csdev);
476 drvdata->miscdev.name = desc.name;
477 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
478 drvdata->miscdev.fops = &tmc_fops;
479 ret = misc_register(&drvdata->miscdev);
481 coresight_unregister(drvdata->csdev);
483 pm_runtime_put(&adev->dev);
488 static const struct amba_id tmc_ids[] = {
489 CS_AMBA_ID(0x000bb961),
490 /* Coresight SoC 600 TMC-ETR/ETS */
491 CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS),
492 /* Coresight SoC 600 TMC-ETB */
493 CS_AMBA_ID(0x000bb9e9),
494 /* Coresight SoC 600 TMC-ETF */
495 CS_AMBA_ID(0x000bb9ea),
499 static struct amba_driver tmc_driver = {
501 .name = "coresight-tmc",
502 .owner = THIS_MODULE,
503 .suppress_bind_attrs = true,
508 builtin_amba_driver(tmc_driver);