drivers/hwtracing/coresight/coresight-tmc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
   3  *
   4  * Description: CoreSight Trace Memory Controller driver
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/init.h>
   9 #include <linux/types.h>
  10 #include <linux/device.h>
  11 #include <linux/idr.h>
  12 #include <linux/io.h>
  13 #include <linux/err.h>
  14 #include <linux/fs.h>
  15 #include <linux/miscdevice.h>
  16 #include <linux/mutex.h>
  17 #include <linux/property.h>
  18 #include <linux/uaccess.h>
  19 #include <linux/slab.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/of.h>
  24 #include <linux/coresight.h>
  25 #include <linux/amba/bus.h>
  26
  27 #include "coresight-priv.h"
  28 #include "coresight-tmc.h"
  29
  30 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
  31 {
  32         /* Ensure formatter, unformatter and hardware fifo are empty */
  33         if (coresight_timeout(drvdata->base,
  34                               TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
  35                 dev_err(&drvdata->csdev->dev,
  36                         "timeout while waiting for TMC to be Ready\n");
  37         }
  38 }
  39
  40 void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
  41 {
  42         u32 ffcr;
  43
  44         ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
  45         ffcr |= TMC_FFCR_STOP_ON_FLUSH;
  46         writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
  47         ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
  48         writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
  49         /* Ensure flush completes */
  50         if (coresight_timeout(drvdata->base,
  51                               TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
  52                 dev_err(&drvdata->csdev->dev,
  53                 "timeout while waiting for completion of Manual Flush\n");
  54         }
  55
  56         tmc_wait_for_tmcready(drvdata);
  57 }
  58
  59 void tmc_enable_hw(struct tmc_drvdata *drvdata)
  60 {
  61         writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
  62 }
  63
  64 void tmc_disable_hw(struct tmc_drvdata *drvdata)
  65 {
  66         writel_relaxed(0x0, drvdata->base + TMC_CTL);
  67 }
  68
  69 static int tmc_read_prepare(struct tmc_drvdata *drvdata)
  70 {
  71         int ret = 0;
  72
  73         switch (drvdata->config_type) {
  74         case TMC_CONFIG_TYPE_ETB:
  75         case TMC_CONFIG_TYPE_ETF:
  76                 ret = tmc_read_prepare_etb(drvdata);
  77                 break;
  78         case TMC_CONFIG_TYPE_ETR:
  79                 ret = tmc_read_prepare_etr(drvdata);
  80                 break;
  81         default:
  82                 ret = -EINVAL;
  83         }
  84
  85         if (!ret)
  86                 dev_dbg(&drvdata->csdev->dev, "TMC read start\n");
  87
  88         return ret;
  89 }
  90
  91 static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
  92 {
  93         int ret = 0;
  94
  95         switch (drvdata->config_type) {
  96         case TMC_CONFIG_TYPE_ETB:
  97         case TMC_CONFIG_TYPE_ETF:
  98                 ret = tmc_read_unprepare_etb(drvdata);
  99                 break;
 100         case TMC_CONFIG_TYPE_ETR:
 101                 ret = tmc_read_unprepare_etr(drvdata);
 102                 break;
 103         default:
 104                 ret = -EINVAL;
 105         }
 106
 107         if (!ret)
 108                 dev_dbg(&drvdata->csdev->dev, "TMC read end\n");
 109
 110         return ret;
 111 }
 112
 113 static int tmc_open(struct inode *inode, struct file *file)
 114 {
 115         int ret;
 116         struct tmc_drvdata *drvdata = container_of(file->private_data,
 117                                                    struct tmc_drvdata, miscdev);
 118
 119         ret = tmc_read_prepare(drvdata);
 120         if (ret)
 121                 return ret;
 122
 123         nonseekable_open(inode, file);
 124
 125         dev_dbg(&drvdata->csdev->dev, "%s: successfully opened\n", __func__);
 126         return 0;
 127 }
 128
 129 static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata,
 130                                           loff_t pos, size_t len, char **bufpp)
 131 {
 132         switch (drvdata->config_type) {
 133         case TMC_CONFIG_TYPE_ETB:
 134         case TMC_CONFIG_TYPE_ETF:
 135                 return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp);
 136         case TMC_CONFIG_TYPE_ETR:
 137                 return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
 138         }
 139
 140         return -EINVAL;
 141 }
 142
 143 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
 144                         loff_t *ppos)
 145 {
 146         char *bufp;
 147         ssize_t actual;
 148         struct tmc_drvdata *drvdata = container_of(file->private_data,
 149                                                    struct tmc_drvdata, miscdev);
 150         actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp);
 151         if (actual <= 0)
 152                 return 0;
 153
 154         if (copy_to_user(data, bufp, actual)) {
 155                 dev_dbg(&drvdata->csdev->dev,
 156                         "%s: copy_to_user failed\n", __func__);
 157                 return -EFAULT;
 158         }
 159
 160         *ppos += actual;
 161         dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual);
 162
 163         return actual;
 164 }
 165
 166 static int tmc_release(struct inode *inode, struct file *file)
 167 {
 168         int ret;
 169         struct tmc_drvdata *drvdata = container_of(file->private_data,
 170                                                    struct tmc_drvdata, miscdev);
 171
 172         ret = tmc_read_unprepare(drvdata);
 173         if (ret)
 174                 return ret;
 175
 176         dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__);
 177         return 0;
 178 }
 179
 180 static const struct file_operations tmc_fops = {
 181         .owner          = THIS_MODULE,
 182         .open           = tmc_open,
 183         .read           = tmc_read,
 184         .release        = tmc_release,
 185         .llseek         = no_llseek,
 186 };
 187
 188 static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
 189 {
 190         enum tmc_mem_intf_width memwidth;
 191
 192         /*
 193          * Excerpt from the TRM:
 194          *
 195          * DEVID::MEMWIDTH[10:8]
 196          * 0x2 Memory interface databus is 32 bits wide.
 197          * 0x3 Memory interface databus is 64 bits wide.
 198          * 0x4 Memory interface databus is 128 bits wide.
 199          * 0x5 Memory interface databus is 256 bits wide.
 200          */
 201         switch (BMVAL(devid, 8, 10)) {
 202         case 0x2:
 203                 memwidth = TMC_MEM_INTF_WIDTH_32BITS;
 204                 break;
 205         case 0x3:
 206                 memwidth = TMC_MEM_INTF_WIDTH_64BITS;
 207                 break;
 208         case 0x4:
 209                 memwidth = TMC_MEM_INTF_WIDTH_128BITS;
 210                 break;
 211         case 0x5:
 212                 memwidth = TMC_MEM_INTF_WIDTH_256BITS;
 213                 break;
 214         default:
 215                 memwidth = 0;
 216         }
 217
 218         return memwidth;
 219 }
 220
 221 #define coresight_tmc_reg(name, offset)                 \
 222         coresight_simple_reg32(struct tmc_drvdata, name, offset)
 223 #define coresight_tmc_reg64(name, lo_off, hi_off)       \
 224         coresight_simple_reg64(struct tmc_drvdata, name, lo_off, hi_off)
 225
 226 coresight_tmc_reg(rsz, TMC_RSZ);
 227 coresight_tmc_reg(sts, TMC_STS);
 228 coresight_tmc_reg(trg, TMC_TRG);
 229 coresight_tmc_reg(ctl, TMC_CTL);
 230 coresight_tmc_reg(ffsr, TMC_FFSR);
 231 coresight_tmc_reg(ffcr, TMC_FFCR);
 232 coresight_tmc_reg(mode, TMC_MODE);
 233 coresight_tmc_reg(pscr, TMC_PSCR);
 234 coresight_tmc_reg(axictl, TMC_AXICTL);
 235 coresight_tmc_reg(devid, CORESIGHT_DEVID);
 236 coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI);
 237 coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI);
 238 coresight_tmc_reg64(dba, TMC_DBALO, TMC_DBAHI);
 239
 240 static struct attribute *coresight_tmc_mgmt_attrs[] = {
 241         &dev_attr_rsz.attr,
 242         &dev_attr_sts.attr,
 243         &dev_attr_rrp.attr,
 244         &dev_attr_rwp.attr,
 245         &dev_attr_trg.attr,
 246         &dev_attr_ctl.attr,
 247         &dev_attr_ffsr.attr,
 248         &dev_attr_ffcr.attr,
 249         &dev_attr_mode.attr,
 250         &dev_attr_pscr.attr,
 251         &dev_attr_devid.attr,
 252         &dev_attr_dba.attr,
 253         &dev_attr_axictl.attr,
 254         NULL,
 255 };
 256
 257 static ssize_t trigger_cntr_show(struct device *dev,
 258                                  struct device_attribute *attr, char *buf)
 259 {
 260         struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 261         unsigned long val = drvdata->trigger_cntr;
 262
 263         return sprintf(buf, "%#lx\n", val);
 264 }
 265
 266 static ssize_t trigger_cntr_store(struct device *dev,
 267                              struct device_attribute *attr,
 268                              const char *buf, size_t size)
 269 {
 270         int ret;
 271         unsigned long val;
 272         struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 273
 274         ret = kstrtoul(buf, 16, &val);
 275         if (ret)
 276                 return ret;
 277
 278         drvdata->trigger_cntr = val;
 279         return size;
 280 }
 281 static DEVICE_ATTR_RW(trigger_cntr);
 282
 283 static ssize_t buffer_size_show(struct device *dev,
 284                                 struct device_attribute *attr, char *buf)
 285 {
 286         struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 287
 288         return sprintf(buf, "%#x\n", drvdata->size);
 289 }
 290
 291 static ssize_t buffer_size_store(struct device *dev,
 292                                  struct device_attribute *attr,
 293                                  const char *buf, size_t size)
 294 {
 295         int ret;
 296         unsigned long val;
 297         struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 298
 299         /* Only permitted for TMC-ETRs */
 300         if (drvdata->config_type != TMC_CONFIG_TYPE_ETR)
 301                 return -EPERM;
 302
 303         ret = kstrtoul(buf, 0, &val);
 304         if (ret)
 305                 return ret;
 306         /* The buffer size should be page aligned */
 307         if (val & (PAGE_SIZE - 1))
 308                 return -EINVAL;
 309         drvdata->size = val;
 310         return size;
 311 }
 312
 313 static DEVICE_ATTR_RW(buffer_size);
 314
 315 static struct attribute *coresight_tmc_attrs[] = {
 316         &dev_attr_trigger_cntr.attr,
 317         &dev_attr_buffer_size.attr,
 318         NULL,
 319 };
 320
 321 static const struct attribute_group coresight_tmc_group = {
 322         .attrs = coresight_tmc_attrs,
 323 };
 324
 325 static const struct attribute_group coresight_tmc_mgmt_group = {
 326         .attrs = coresight_tmc_mgmt_attrs,
 327         .name = "mgmt",
 328 };
 329
 330 const struct attribute_group *coresight_tmc_groups[] = {
 331         &coresight_tmc_group,
 332         &coresight_tmc_mgmt_group,
 333         NULL,
 334 };
 335
 336 static inline bool tmc_etr_can_use_sg(struct device *dev)
 337 {
 338         return fwnode_property_present(dev->fwnode, "arm,scatter-gather");
 339 }
 340
 341 /* Detect and initialise the capabilities of a TMC ETR */
 342 static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps)
 343 {
 344         int rc;
 345         u32 dma_mask = 0;
 346         struct tmc_drvdata *drvdata = dev_get_drvdata(parent);
 347
 348         /* Set the unadvertised capabilities */
 349         tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
 350
 351         if (!(devid & TMC_DEVID_NOSCAT) && tmc_etr_can_use_sg(parent))
 352                 tmc_etr_set_cap(drvdata, TMC_ETR_SG);
 353
 354         /* Check if the AXI address width is available */
 355         if (devid & TMC_DEVID_AXIAW_VALID)
 356                 dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) &
 357                                 TMC_DEVID_AXIAW_MASK);
 358
 359         /*
 360          * Unless specified in the device configuration, ETR uses a 40-bit
 361          * AXI master in place of the embedded SRAM of ETB/ETF.
 362          */
 363         switch (dma_mask) {
 364         case 32:
 365         case 40:
 366         case 44:
 367         case 48:
 368         case 52:
 369                 dev_info(parent, "Detected dma mask %dbits\n", dma_mask);
 370                 break;
 371         default:
 372                 dma_mask = 40;
 373         }
 374
 375         rc = dma_set_mask_and_coherent(parent, DMA_BIT_MASK(dma_mask));
 376         if (rc)
 377                 dev_err(parent, "Failed to setup DMA mask: %d\n", rc);
 378         return rc;
 379 }
 380
 381 static u32 tmc_etr_get_default_buffer_size(struct device *dev)
 382 {
 383         u32 size;
 384
 385         if (fwnode_property_read_u32(dev->fwnode, "arm,buffer-size", &size))
 386                 size = SZ_1M;
 387         return size;
 388 }
 389
 390 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 391 {
 392         int ret = 0;
 393         u32 devid;
 394         void __iomem *base;
 395         struct device *dev = &adev->dev;
 396         struct coresight_platform_data *pdata = NULL;
 397         struct tmc_drvdata *drvdata;
 398         struct resource *res = &adev->res;
 399         struct coresight_desc desc = { 0 };
 400
 401         pdata = coresight_get_platform_data(dev);
 402         if (IS_ERR(pdata)) {
 403                 ret = PTR_ERR(pdata);
 404                 goto out;
 405         }
 406         adev->dev.platform_data = pdata;
 407
 408         ret = -ENOMEM;
 409         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 410         if (!drvdata)
 411                 goto out;
 412
 413         dev_set_drvdata(dev, drvdata);
 414
 415         /* Validity for the resource is already checked by the AMBA core */
 416         base = devm_ioremap_resource(dev, res);
 417         if (IS_ERR(base)) {
 418                 ret = PTR_ERR(base);
 419                 goto out;
 420         }
 421
 422         drvdata->base = base;
 423
 424         spin_lock_init(&drvdata->spinlock);
 425
 426         devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
 427         drvdata->config_type = BMVAL(devid, 6, 7);
 428         drvdata->memwidth = tmc_get_memwidth(devid);
 429         /* This device is not associated with a session */
 430         drvdata->pid = -1;
 431
 432         if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
 433                 drvdata->size = tmc_etr_get_default_buffer_size(dev);
 434         else
 435                 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
 436
 437         desc.pdata = pdata;
 438         desc.dev = dev;
 439         desc.groups = coresight_tmc_groups;
 440         desc.name = dev_name(dev);
 441
 442         switch (drvdata->config_type) {
 443         case TMC_CONFIG_TYPE_ETB:
 444                 desc.type = CORESIGHT_DEV_TYPE_SINK;
 445                 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 446                 desc.ops = &tmc_etb_cs_ops;
 447                 break;
 448         case TMC_CONFIG_TYPE_ETR:
 449                 desc.type = CORESIGHT_DEV_TYPE_SINK;
 450                 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 451                 desc.ops = &tmc_etr_cs_ops;
 452                 ret = tmc_etr_setup_caps(dev, devid,
 453                                          coresight_get_uci_data(id));
 454                 if (ret)
 455                         goto out;
 456                 idr_init(&drvdata->idr);
 457                 mutex_init(&drvdata->idr_mutex);
 458                 break;
 459         case TMC_CONFIG_TYPE_ETF:
 460                 desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
 461                 desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
 462                 desc.ops = &tmc_etf_cs_ops;
 463                 break;
 464         default:
 465                 pr_err("%s: Unsupported TMC config\n", desc.name);
 466                 ret = -EINVAL;
 467                 goto out;
 468         }
 469
 470         drvdata->csdev = coresight_register(&desc);
 471         if (IS_ERR(drvdata->csdev)) {
 472                 ret = PTR_ERR(drvdata->csdev);
 473                 goto out;
 474         }
 475
 476         drvdata->miscdev.name = desc.name;
 477         drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
 478         drvdata->miscdev.fops = &tmc_fops;
 479         ret = misc_register(&drvdata->miscdev);
 480         if (ret)
 481                 coresight_unregister(drvdata->csdev);
 482         else
 483                 pm_runtime_put(&adev->dev);
 484 out:
 485         return ret;
 486 }
 487
 488 static const struct amba_id tmc_ids[] = {
 489         CS_AMBA_ID(0x000bb961),
 490         /* Coresight SoC 600 TMC-ETR/ETS */
 491         CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS),
 492         /* Coresight SoC 600 TMC-ETB */
 493         CS_AMBA_ID(0x000bb9e9),
 494         /* Coresight SoC 600 TMC-ETF */
 495         CS_AMBA_ID(0x000bb9ea),
 496         { 0, 0},
 497 };
 498
 499 static struct amba_driver tmc_driver = {
 500         .drv = {
 501                 .name   = "coresight-tmc",
 502                 .owner  = THIS_MODULE,
 503                 .suppress_bind_attrs = true,
 504         },
 505         .probe          = tmc_probe,
 506         .id_table       = tmc_ids,
 507 };
 508 builtin_amba_driver(tmc_driver);