2 # Coresight configuration
5 bool "CoreSight Tracing Support"
9 This framework provides a kernel interface for the CoreSight debug
10 and trace drivers to register themselves with. It's intended to build
11 a topological view of the CoreSight components based on a DT
12 specification and configure the right series of components when a
13 trace source gets enabled.
16 config CORESIGHT_LINKS_AND_SINKS
17 bool "CoreSight Link and Sink drivers"
19 This enables support for CoreSight link and sink drivers that are
20 responsible for transporting and collecting the trace data
21 respectively. Link and sinks are dynamically aggregated with a trace
22 entity at run time to form a complete trace path.
24 config CORESIGHT_LINK_AND_SINK_TMC
25 bool "Coresight generic TMC driver"
26 depends on CORESIGHT_LINKS_AND_SINKS
28 This enables support for the Trace Memory Controller driver.
29 Depending on its configuration the device can act as a link (embedded
30 trace router - ETR) or sink (embedded trace FIFO). The driver
31 complies with the generic implementation of the component without
32 special enhancement or added features.
35 bool "Coresight Address Translation Unit (CATU) driver"
36 depends on CORESIGHT_LINK_AND_SINK_TMC
38 Enable support for the Coresight Address Translation Unit (CATU).
39 CATU supports a scatter gather table of 4K pages, with forward/backward
40 lookup. CATU helps TMC ETR to use a large physically non-contiguous trace
41 buffer by translating the addresses used by ETR to the physical address
42 by looking up the provided table. CATU can also be used in pass-through
43 mode where the address is not translated.
45 config CORESIGHT_SINK_TPIU
46 bool "Coresight generic TPIU driver"
47 depends on CORESIGHT_LINKS_AND_SINKS
49 This enables support for the Trace Port Interface Unit driver,
50 responsible for bridging the gap between the on-chip coresight
51 components and a trace for bridging the gap between the on-chip
52 coresight components and a trace port collection engine, typically
53 connected to an external host for use case capturing more traces than
54 the on-board coresight memory can handle.
56 config CORESIGHT_SINK_ETBV10
57 bool "Coresight ETBv1.0 driver"
58 depends on CORESIGHT_LINKS_AND_SINKS
60 This enables support for the Embedded Trace Buffer version 1.0 driver
61 that complies with the generic implementation of the component without
62 special enhancement or added features.
64 config CORESIGHT_SOURCE_ETM3X
65 bool "CoreSight Embedded Trace Macrocell 3.x driver"
67 select CORESIGHT_LINKS_AND_SINKS
69 This driver provides support for processor ETM3.x and PTM1.x modules,
70 which allows tracing the instructions that a processor is executing
71 This is primarily useful for instruction level tracing. Depending
72 the ETM version data tracing may also be available.
74 config CORESIGHT_SOURCE_ETM4X
75 bool "CoreSight Embedded Trace Macrocell 4.x driver"
77 select CORESIGHT_LINKS_AND_SINKS
78 select PID_IN_CONTEXTIDR
80 This driver provides support for the ETM4.x tracer module, tracing the
81 instructions that a processor is executing. This is primarily useful
82 for instruction level tracing. Depending on the implemented version
83 data tracing may also be available.
86 bool "CoreSight System Trace Macrocell driver"
87 depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64
88 select CORESIGHT_LINKS_AND_SINKS
91 This driver provides support for hardware assisted software
92 instrumentation based tracing. This is primarily used for
93 logging useful software events or data coming from various entities
94 in the system, possibly running different OSs
96 config CORESIGHT_CPU_DEBUG
97 tristate "CoreSight CPU Debug driver"
98 depends on ARM || ARM64
101 This driver provides support for coresight debugging module. This
102 is primarily used to dump sample-based profiling registers when
103 system triggers panic, the driver will parse context registers so
104 can quickly get to know program counter (PC), secure state,
105 exception level, etc. Before use debugging functionality, platform
106 needs to ensure the clock domain and power domain are enabled
107 properly, please refer Documentation/trace/coresight-cpu-debug.txt
108 for detailed description and the example for usage.